drivers/pinctrl/pinctrl-rza1.c

   1 /*
   2  * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
   3  *
   4  * Copyright (C) 2017 Jacopo Mondi
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2. This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 /*
  12  * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
  13  * family.
  14  * This includes SoCs which are sub- or super- sets of this particular line,
  15  * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).
  16  */
  17
  18 #include <linux/bitops.h>
  19 #include <linux/err.h>
  20 #include <linux/gpio/driver.h>
  21 #include <linux/init.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pinctrl/pinconf-generic.h>
  28 #include <linux/pinctrl/pinctrl.h>
  29 #include <linux/pinctrl/pinmux.h>
  30 #include <linux/slab.h>
  31
  32 #include "core.h"
  33 #include "devicetree.h"
  34 #include "pinconf.h"
  35 #include "pinmux.h"
  36
  37 #define DRIVER_NAME                     "pinctrl-rza1"
  38
  39 #define RZA1_P_REG                      0x0000
  40 #define RZA1_PPR_REG                    0x0200
  41 #define RZA1_PM_REG                     0x0300
  42 #define RZA1_PMC_REG                    0x0400
  43 #define RZA1_PFC_REG                    0x0500
  44 #define RZA1_PFCE_REG                   0x0600
  45 #define RZA1_PFCEA_REG                  0x0a00
  46 #define RZA1_PIBC_REG                   0x4000
  47 #define RZA1_PBDC_REG                   0x4100
  48 #define RZA1_PIPC_REG                   0x4200
  49
  50 #define RZA1_ADDR(mem, reg, port)       ((mem) + (reg) + ((port) * 4))
  51
  52 #define RZA1_NPORTS                     12
  53 #define RZA1_PINS_PER_PORT              16
  54 #define RZA1_NPINS                      (RZA1_PINS_PER_PORT * RZA1_NPORTS)
  55 #define RZA1_PIN_ID_TO_PORT(id)         ((id) / RZA1_PINS_PER_PORT)
  56 #define RZA1_PIN_ID_TO_PIN(id)          ((id) % RZA1_PINS_PER_PORT)
  57
  58 /*
  59  * Use 16 lower bits [15:0] for pin identifier
  60  * Use 16 higher bits [31:16] for pin mux function
  61  */
  62 #define MUX_PIN_ID_MASK                 GENMASK(15, 0)
  63 #define MUX_FUNC_MASK                   GENMASK(31, 16)
  64
  65 #define MUX_FUNC_OFFS                   16
  66 #define MUX_FUNC(pinconf)               \
  67         ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
  68 #define MUX_FUNC_PFC_MASK               BIT(0)
  69 #define MUX_FUNC_PFCE_MASK              BIT(1)
  70 #define MUX_FUNC_PFCEA_MASK             BIT(2)
  71
  72 /* Pin mux flags */
  73 #define MUX_FLAGS_BIDIR                 BIT(0)
  74 #define MUX_FLAGS_SWIO_INPUT            BIT(1)
  75 #define MUX_FLAGS_SWIO_OUTPUT           BIT(2)
  76
  77 /* ----------------------------------------------------------------------------
  78  * RZ/A1 pinmux flags
  79  */
  80
  81 /**
  82  * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
  83  */
  84 struct rza1_bidir_pin {
  85         u8 pin: 4;
  86         u8 func: 4;
  87 };
  88
  89 /**
  90  * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
  91  *                    Each struct rza1_bidir_entry describes a port.
  92  */
  93 struct rza1_bidir_entry {
  94         const unsigned int npins;
  95         const struct rza1_bidir_pin *pins;
  96 };
  97
  98 /**
  99  * rza1_swio_pin - describe a single pin that needs bidir flag applied.
 100  */
 101 struct rza1_swio_pin {
 102         u16 pin: 4;
 103         u16 port: 4;
 104         u16 func: 4;
 105         u16 input: 1;
 106 };
 107
 108 /**
 109  * rza1_swio_entry - describe a list of pins that needs swio flag applied
 110  */
 111 struct rza1_swio_entry {
 112         const unsigned int npins;
 113         const struct rza1_swio_pin *pins;
 114 };
 115
 116 /**
 117  * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
 118  */
 119 struct rza1_pinmux_conf {
 120         const struct rza1_bidir_entry *bidir_entries;
 121         const struct rza1_swio_entry *swio_entries;
 122 };
 123
 124 /* ----------------------------------------------------------------------------
 125  * RZ/A1H (r7s72100) pinmux flags
 126  */
 127
 128 static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {
 129         { .pin = 0, .func = 1 },
 130         { .pin = 1, .func = 1 },
 131         { .pin = 2, .func = 1 },
 132         { .pin = 3, .func = 1 },
 133         { .pin = 4, .func = 1 },
 134         { .pin = 5, .func = 1 },
 135         { .pin = 6, .func = 1 },
 136         { .pin = 7, .func = 1 },
 137 };
 138
 139 static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {
 140         { .pin = 0, .func = 1 },
 141         { .pin = 1, .func = 1 },
 142         { .pin = 2, .func = 1 },
 143         { .pin = 3, .func = 1 },
 144         { .pin = 4, .func = 1 },
 145         { .pin = 0, .func = 4 },
 146         { .pin = 1, .func = 4 },
 147         { .pin = 2, .func = 4 },
 148         { .pin = 3, .func = 4 },
 149         { .pin = 5, .func = 1 },
 150         { .pin = 6, .func = 1 },
 151         { .pin = 7, .func = 1 },
 152         { .pin = 8, .func = 1 },
 153         { .pin = 9, .func = 1 },
 154         { .pin = 10, .func = 1 },
 155         { .pin = 11, .func = 1 },
 156         { .pin = 12, .func = 1 },
 157         { .pin = 13, .func = 1 },
 158         { .pin = 14, .func = 1 },
 159         { .pin = 15, .func = 1 },
 160         { .pin = 12, .func = 4 },
 161         { .pin = 13, .func = 4 },
 162         { .pin = 14, .func = 4 },
 163         { .pin = 15, .func = 4 },
 164 };
 165
 166 static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {
 167         { .pin = 3, .func = 2 },
 168         { .pin = 10, .func = 7 },
 169         { .pin = 11, .func = 7 },
 170         { .pin = 13, .func = 7 },
 171         { .pin = 14, .func = 7 },
 172         { .pin = 15, .func = 7 },
 173         { .pin = 10, .func = 8 },
 174         { .pin = 11, .func = 8 },
 175         { .pin = 13, .func = 8 },
 176         { .pin = 14, .func = 8 },
 177         { .pin = 15, .func = 8 },
 178 };
 179
 180 static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {
 181         { .pin = 0, .func = 8 },
 182         { .pin = 1, .func = 8 },
 183         { .pin = 2, .func = 8 },
 184         { .pin = 3, .func = 8 },
 185         { .pin = 10, .func = 3 },
 186         { .pin = 11, .func = 3 },
 187         { .pin = 13, .func = 3 },
 188         { .pin = 14, .func = 3 },
 189         { .pin = 15, .func = 3 },
 190         { .pin = 10, .func = 4 },
 191         { .pin = 11, .func = 4 },
 192         { .pin = 13, .func = 4 },
 193         { .pin = 14, .func = 4 },
 194         { .pin = 15, .func = 4 },
 195         { .pin = 12, .func = 5 },
 196         { .pin = 13, .func = 5 },
 197         { .pin = 14, .func = 5 },
 198         { .pin = 15, .func = 5 },
 199 };
 200
 201 static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {
 202         { .pin = 0, .func = 1 },
 203         { .pin = 1, .func = 1 },
 204         { .pin = 2, .func = 1 },
 205         { .pin = 3, .func = 1 },
 206         { .pin = 4, .func = 1 },
 207         { .pin = 5, .func = 1 },
 208         { .pin = 6, .func = 1 },
 209         { .pin = 7, .func = 1 },
 210         { .pin = 8, .func = 1 },
 211         { .pin = 9, .func = 1 },
 212         { .pin = 10, .func = 1 },
 213         { .pin = 11, .func = 1 },
 214         { .pin = 12, .func = 1 },
 215         { .pin = 13, .func = 1 },
 216         { .pin = 14, .func = 1 },
 217         { .pin = 15, .func = 1 },
 218 };
 219
 220 static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {
 221         { .pin = 13, .func = 3 },
 222 };
 223
 224 static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {
 225         { .pin = 8, .func = 3 },
 226         { .pin = 9, .func = 3 },
 227         { .pin = 10, .func = 3 },
 228         { .pin = 11, .func = 3 },
 229         { .pin = 14, .func = 2 },
 230         { .pin = 15, .func = 2 },
 231         { .pin = 14, .func = 3 },
 232         { .pin = 15, .func = 3 },
 233 };
 234
 235 static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {
 236         { .pin = 0, .func = 2 },
 237         { .pin = 1, .func = 2 },
 238         { .pin = 4, .func = 2 },
 239         { .pin = 5, .func = 2 },
 240         { .pin = 6, .func = 2 },
 241         { .pin = 7, .func = 2 },
 242 };
 243
 244 static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {
 245         { .pin = 6, .func = 2 },
 246         { .pin = 7, .func = 2 },
 247         { .pin = 9, .func = 2 },
 248         { .pin = 6, .func = 4 },
 249         { .pin = 7, .func = 4 },
 250         { .pin = 9, .func = 4 },
 251         { .pin = 10, .func = 2 },
 252         { .pin = 11, .func = 2 },
 253         { .pin = 10, .func = 4 },
 254         { .pin = 11, .func = 4 },
 255         { .pin = 12, .func = 4 },
 256         { .pin = 13, .func = 4 },
 257         { .pin = 14, .func = 4 },
 258         { .pin = 15, .func = 4 },
 259 };
 260
 261 static const struct rza1_swio_pin rza1h_swio_pins[] = {
 262         { .port = 2, .pin = 7, .func = 4, .input = 0 },
 263         { .port = 2, .pin = 11, .func = 4, .input = 0 },
 264         { .port = 3, .pin = 7, .func = 3, .input = 0 },
 265         { .port = 3, .pin = 7, .func = 8, .input = 0 },
 266         { .port = 4, .pin = 7, .func = 5, .input = 0 },
 267         { .port = 4, .pin = 7, .func = 11, .input = 0 },
 268         { .port = 4, .pin = 15, .func = 6, .input = 0 },
 269         { .port = 5, .pin = 0, .func = 1, .input = 1 },
 270         { .port = 5, .pin = 1, .func = 1, .input = 1 },
 271         { .port = 5, .pin = 2, .func = 1, .input = 1 },
 272         { .port = 5, .pin = 3, .func = 1, .input = 1 },
 273         { .port = 5, .pin = 4, .func = 1, .input = 1 },
 274         { .port = 5, .pin = 5, .func = 1, .input = 1 },
 275         { .port = 5, .pin = 6, .func = 1, .input = 1 },
 276         { .port = 5, .pin = 7, .func = 1, .input = 1 },
 277         { .port = 7, .pin = 4, .func = 6, .input = 0 },
 278         { .port = 7, .pin = 11, .func = 2, .input = 0 },
 279         { .port = 8, .pin = 10, .func = 8, .input = 0 },
 280         { .port = 10, .pin = 15, .func = 2, .input = 0 },
 281 };
 282
 283 static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {
 284         [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },
 285         [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },
 286         [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
 287         [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },
 288         [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },
 289         [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },
 290         [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },
 291         [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },
 292         [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },
 293 };
 294
 295 static const struct rza1_swio_entry rza1h_swio_entries[] = {
 296         [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
 297 };
 298
 299 /* RZ/A1H (r7s72100x) pinmux flags table */
 300 static const struct rza1_pinmux_conf rza1h_pmx_conf = {
 301         .bidir_entries  = rza1h_bidir_entries,
 302         .swio_entries   = rza1h_swio_entries,
 303 };
 304
 305 /* ----------------------------------------------------------------------------
 306  * RZ/A1 types
 307  */
 308 /**
 309  * rza1_mux_conf - describes a pin multiplexing operation
 310  *
 311  * @id: the pin identifier from 0 to RZA1_NPINS
 312  * @port: the port where pin sits on
 313  * @pin: pin id
 314  * @mux_func: alternate function id number
 315  * @mux_flags: alternate function flags
 316  * @value: output value to set the pin to
 317  */
 318 struct rza1_mux_conf {
 319         u16 id;
 320         u8 port;
 321         u8 pin;
 322         u8 mux_func;
 323         u8 mux_flags;
 324         u8 value;
 325 };
 326
 327 /**
 328  * rza1_port - describes a pin port
 329  *
 330  * This is mostly useful to lock register writes per-bank and not globally.
 331  *
 332  * @lock: protect access to HW registers
 333  * @id: port number
 334  * @base: logical address base
 335  * @pins: pins sitting on this port
 336  */
 337 struct rza1_port {
 338         spinlock_t lock;
 339         unsigned int id;
 340         void __iomem *base;
 341         struct pinctrl_pin_desc *pins;
 342 };
 343
 344 /**
 345  * rza1_pinctrl - RZ pincontroller device
 346  *
 347  * @dev: parent device structure
 348  * @mutex: protect [pinctrl|pinmux]_generic functions
 349  * @base: logical address base
 350  * @nports: number of pin controller ports
 351  * @ports: pin controller banks
 352  * @pins: pin array for pinctrl core
 353  * @desc: pincontroller desc for pinctrl core
 354  * @pctl: pinctrl device
 355  * @data: device specific data
 356  */
 357 struct rza1_pinctrl {
 358         struct device *dev;
 359
 360         struct mutex mutex;
 361
 362         void __iomem *base;
 363
 364         unsigned int nport;
 365         struct rza1_port *ports;
 366
 367         struct pinctrl_pin_desc *pins;
 368         struct pinctrl_desc desc;
 369         struct pinctrl_dev *pctl;
 370
 371         const void *data;
 372 };
 373
 374 /* ----------------------------------------------------------------------------
 375  * RZ/A1 pinmux flags
 376  */
 377 static inline bool rza1_pinmux_get_bidir(unsigned int port,
 378                                          unsigned int pin,
 379                                          unsigned int func,
 380                                          const struct rza1_bidir_entry *table)
 381 {
 382         const struct rza1_bidir_entry *entry = &table[port];
 383         const struct rza1_bidir_pin *bidir_pin;
 384         unsigned int i;
 385
 386         for (i = 0; i < entry->npins; ++i) {
 387                 bidir_pin = &entry->pins[i];
 388                 if (bidir_pin->pin == pin && bidir_pin->func == func)
 389                         return true;
 390         }
 391
 392         return false;
 393 }
 394
 395 static inline int rza1_pinmux_get_swio(unsigned int port,
 396                                        unsigned int pin,
 397                                        unsigned int func,
 398                                        const struct rza1_swio_entry *table)
 399 {
 400         const struct rza1_swio_pin *swio_pin;
 401         unsigned int i;
 402
 403
 404         for (i = 0; i < table->npins; ++i) {
 405                 swio_pin = &table->pins[i];
 406                 if (swio_pin->port == port && swio_pin->pin == pin &&
 407                     swio_pin->func == func)
 408                         return swio_pin->input;
 409         }
 410
 411         return -ENOENT;
 412 }
 413
 414 /**
 415  * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
 416  */
 417 static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
 418                                           unsigned int func,
 419                                           struct rza1_pinctrl *rza1_pctl)
 420
 421 {
 422         const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;
 423         const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;
 424         const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;
 425         unsigned int pmx_flags = 0;
 426         int ret;
 427
 428         if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))
 429                 pmx_flags |= MUX_FLAGS_BIDIR;
 430
 431         ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);
 432         if (ret == 0)
 433                 pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;
 434         else if (ret > 0)
 435                 pmx_flags |= MUX_FLAGS_SWIO_INPUT;
 436
 437         return pmx_flags;
 438 }
 439
 440 /* ----------------------------------------------------------------------------
 441  * RZ/A1 SoC operations
 442  */
 443
 444 /**
 445  * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
 446  *                  registers
 447  */
 448 static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
 449                                 unsigned int bit, bool set)
 450 {
 451         void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
 452         u16 val = ioread16(mem);
 453
 454         if (set)
 455                 val |= BIT(bit);
 456         else
 457                 val &= ~BIT(bit);
 458
 459         iowrite16(val, mem);
 460 }
 461
 462 static inline unsigned int rza1_get_bit(struct rza1_port *port,
 463                                         unsigned int reg, unsigned int bit)
 464 {
 465         void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
 466
 467         return ioread16(mem) & BIT(bit);
 468 }
 469
 470 /**
 471  * rza1_pin_reset() - reset a pin to default initial state
 472  *
 473  * Reset pin state disabling input buffer and bi-directional control,
 474  * and configure it as input port.
 475  * Note that pin is now configured with direction as input but with input
 476  * buffer disabled. This implies the pin value cannot be read in this state.
 477  *
 478  * @port: port where pin sits on
 479  * @pin: pin offset
 480  */
 481 static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
 482 {
 483         unsigned long irqflags;
 484
 485         spin_lock_irqsave(&port->lock, irqflags);
 486         rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);
 487         rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
 488
 489         rza1_set_bit(port, RZA1_PM_REG, pin, 1);
 490         rza1_set_bit(port, RZA1_PMC_REG, pin, 0);
 491         rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);
 492         spin_unlock_irqrestore(&port->lock, irqflags);
 493 }
 494
 495 static inline int rza1_pin_get_direction(struct rza1_port *port,
 496                                          unsigned int pin)
 497 {
 498         unsigned long irqflags;
 499         int input;
 500
 501         spin_lock_irqsave(&port->lock, irqflags);
 502         input = rza1_get_bit(port, RZA1_PM_REG, pin);
 503         spin_unlock_irqrestore(&port->lock, irqflags);
 504
 505         return !!input;
 506 }
 507
 508 /**
 509  * rza1_pin_set_direction() - set I/O direction on a pin in port mode
 510  *
 511  * When running in output port mode keep PBDC enabled to allow reading the
 512  * pin value from PPR.
 513  *
 514  * @port: port where pin sits on
 515  * @pin: pin offset
 516  * @input: input enable/disable flag
 517  */
 518 static inline void rza1_pin_set_direction(struct rza1_port *port,
 519                                           unsigned int pin, bool input)
 520 {
 521         unsigned long irqflags;
 522
 523         spin_lock_irqsave(&port->lock, irqflags);
 524
 525         rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);
 526         if (input) {
 527                 rza1_set_bit(port, RZA1_PM_REG, pin, 1);
 528                 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
 529         } else {
 530                 rza1_set_bit(port, RZA1_PM_REG, pin, 0);
 531                 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
 532         }
 533
 534         spin_unlock_irqrestore(&port->lock, irqflags);
 535 }
 536
 537 static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
 538                                 unsigned int value)
 539 {
 540         unsigned long irqflags;
 541
 542         spin_lock_irqsave(&port->lock, irqflags);
 543         rza1_set_bit(port, RZA1_P_REG, pin, !!value);
 544         spin_unlock_irqrestore(&port->lock, irqflags);
 545 }
 546
 547 static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
 548 {
 549         unsigned long irqflags;
 550         int val;
 551
 552         spin_lock_irqsave(&port->lock, irqflags);
 553         val = rza1_get_bit(port, RZA1_PPR_REG, pin);
 554         spin_unlock_irqrestore(&port->lock, irqflags);
 555
 556         return val;
 557 }
 558
 559 /**
 560  * rza1_pin_mux_single() - configure pin multiplexing on a single pin
 561  *
 562  * @pinctrl: RZ/A1 pin controller device
 563  * @mux_conf: pin multiplexing descriptor
 564  */
 565 static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
 566                                struct rza1_mux_conf *mux_conf)
 567 {
 568         struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
 569         unsigned int pin = mux_conf->pin;
 570         u8 mux_func = mux_conf->mux_func;
 571         u8 mux_flags = mux_conf->mux_flags;
 572         u8 mux_flags_from_table;
 573
 574         rza1_pin_reset(port, pin);
 575
 576         /* SWIO pinmux flags coming from DT are high precedence */
 577         mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,
 578                                                      rza1_pctl);
 579         if (mux_flags)
 580                 mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);
 581         else
 582                 mux_flags = mux_flags_from_table;
 583
 584         if (mux_flags & MUX_FLAGS_BIDIR)
 585                 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
 586
 587         /*
 588          * Enable alternate function mode and select it.
 589          *
 590          * Be careful here: the pin mux sub-nodes in device tree
 591          * enumerate alternate functions from 1 to 8;
 592          * subtract 1 before using macros to match registers configuration
 593          * which expects numbers from 0 to 7 instead.
 594          *
 595          * ----------------------------------------------------
 596          * Alternate mode selection table:
 597          *
 598          * PMC  PFC     PFCE    PFCAE   (mux_func - 1)
 599          * 1    0       0       0       0
 600          * 1    1       0       0       1
 601          * 1    0       1       0       2
 602          * 1    1       1       0       3
 603          * 1    0       0       1       4
 604          * 1    1       0       1       5
 605          * 1    0       1       1       6
 606          * 1    1       1       1       7
 607          * ----------------------------------------------------
 608          */
 609         mux_func -= 1;
 610         rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);
 611         rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);
 612         rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);
 613
 614         /*
 615          * All alternate functions except a few need PIPCn = 1.
 616          * If PIPCn has to stay disabled (SW IO mode), configure PMn according
 617          * to I/O direction specified by pin configuration -after- PMC has been
 618          * set to one.
 619          */
 620         if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))
 621                 rza1_set_bit(port, RZA1_PM_REG, pin,
 622                              mux_flags & MUX_FLAGS_SWIO_INPUT);
 623         else
 624                 rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);
 625
 626         rza1_set_bit(port, RZA1_PMC_REG, pin, 1);
 627
 628         return 0;
 629 }
 630
 631 /* ----------------------------------------------------------------------------
 632  * gpio operations
 633  */
 634
 635 /**
 636  * rza1_gpio_request() - configure pin in port mode
 637  *
 638  * Configure a pin as gpio (port mode).
 639  * After reset, the pin is in input mode with input buffer disabled.
 640  * To use the pin as input or output, set_direction shall be called first
 641  *
 642  * @chip: gpio chip where the gpio sits on
 643  * @gpio: gpio offset
 644  */
 645 static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
 646 {
 647         struct rza1_port *port = gpiochip_get_data(chip);
 648
 649         rza1_pin_reset(port, gpio);
 650
 651         return 0;
 652 }
 653
 654 /**
 655  * rza1_gpio_disable_free() - reset a pin
 656  *
 657  * Surprisingly, disable_free a gpio, is equivalent to request it.
 658  * Reset pin to port mode, with input buffer disabled. This overwrites all
 659  * port direction settings applied with set_direction
 660  *
 661  * @chip: gpio chip where the gpio sits on
 662  * @gpio: gpio offset
 663  */
 664 static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
 665 {
 666         struct rza1_port *port = gpiochip_get_data(chip);
 667
 668         rza1_pin_reset(port, gpio);
 669 }
 670
 671 static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
 672 {
 673         struct rza1_port *port = gpiochip_get_data(chip);
 674
 675         return rza1_pin_get_direction(port, gpio);
 676 }
 677
 678 static int rza1_gpio_direction_input(struct gpio_chip *chip,
 679                                      unsigned int gpio)
 680 {
 681         struct rza1_port *port = gpiochip_get_data(chip);
 682
 683         rza1_pin_set_direction(port, gpio, true);
 684
 685         return 0;
 686 }
 687
 688 static int rza1_gpio_direction_output(struct gpio_chip *chip,
 689                                       unsigned int gpio,
 690                                       int value)
 691 {
 692         struct rza1_port *port = gpiochip_get_data(chip);
 693
 694         /* Set value before driving pin direction */
 695         rza1_pin_set(port, gpio, value);
 696         rza1_pin_set_direction(port, gpio, false);
 697
 698         return 0;
 699 }
 700
 701 /**
 702  * rza1_gpio_get() - read a gpio pin value
 703  *
 704  * Read gpio pin value through PPR register.
 705  * Requires bi-directional mode to work when reading the value of a pin
 706  * in output mode
 707  *
 708  * @chip: gpio chip where the gpio sits on
 709  * @gpio: gpio offset
 710  */
 711 static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
 712 {
 713         struct rza1_port *port = gpiochip_get_data(chip);
 714
 715         return rza1_pin_get(port, gpio);
 716 }
 717
 718 static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
 719                           int value)
 720 {
 721         struct rza1_port *port = gpiochip_get_data(chip);
 722
 723         rza1_pin_set(port, gpio, value);
 724 }
 725
 726 static const struct gpio_chip rza1_gpiochip_template = {
 727         .request                = rza1_gpio_request,
 728         .free                   = rza1_gpio_free,
 729         .get_direction          = rza1_gpio_get_direction,
 730         .direction_input        = rza1_gpio_direction_input,
 731         .direction_output       = rza1_gpio_direction_output,
 732         .get                    = rza1_gpio_get,
 733         .set                    = rza1_gpio_set,
 734 };
 735 /* ----------------------------------------------------------------------------
 736  * pinctrl operations
 737  */
 738
 739 /**
 740  * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
 741  *                            children sub-nodes
 742  *
 743  * @np: device tree node to parse
 744  */
 745 static int rza1_dt_node_pin_count(struct device_node *np)
 746 {
 747         struct device_node *child;
 748         struct property *of_pins;
 749         unsigned int npins;
 750
 751         of_pins = of_find_property(np, "pinmux", NULL);
 752         if (of_pins)
 753                 return of_pins->length / sizeof(u32);
 754
 755         npins = 0;
 756         for_each_child_of_node(np, child) {
 757                 of_pins = of_find_property(child, "pinmux", NULL);
 758                 if (!of_pins)
 759                         return -EINVAL;
 760
 761                 npins += of_pins->length / sizeof(u32);
 762         }
 763
 764         return npins;
 765 }
 766
 767 /**
 768  * rza1_parse_pmx_function() - parse a pin mux sub-node
 769  *
 770  * @rza1_pctl: RZ/A1 pin controller device
 771  * @np: of pmx sub-node
 772  * @mux_confs: array of pin mux configurations to fill with parsed info
 773  * @grpins: array of pin ids to mux
 774  */
 775 static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
 776                                   struct device_node *np,
 777                                   struct rza1_mux_conf *mux_confs,
 778                                   unsigned int *grpins)
 779 {
 780         struct pinctrl_dev *pctldev = rza1_pctl->pctl;
 781         char const *prop_name = "pinmux";
 782         unsigned long *pin_configs;
 783         unsigned int npin_configs;
 784         struct property *of_pins;
 785         unsigned int npins;
 786         u8 pinmux_flags;
 787         unsigned int i;
 788         int ret;
 789
 790         of_pins = of_find_property(np, prop_name, NULL);
 791         if (!of_pins) {
 792                 dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);
 793                 return -ENOENT;
 794         }
 795         npins = of_pins->length / sizeof(u32);
 796
 797         /*
 798          * Collect pin configuration properties: they apply to all pins in
 799          * this sub-node
 800          */
 801         ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,
 802                                               &npin_configs);
 803         if (ret) {
 804                 dev_err(rza1_pctl->dev,
 805                         "Unable to parse pin configuration options for %s\n",
 806                         np->name);
 807                 return ret;
 808         }
 809
 810         /*
 811          * Create a mask with pinmux flags from pin configuration;
 812          * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction
 813          * specified in device tree.
 814          */
 815         pinmux_flags = 0;
 816         for (i = 0; i < npin_configs && pinmux_flags == 0; i++)
 817                 switch (pinconf_to_config_param(pin_configs[i])) {
 818                 case PIN_CONFIG_INPUT_ENABLE:
 819                         pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
 820                         break;
 821                 case PIN_CONFIG_OUTPUT:
 822                         pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
 823                 default:
 824                         break;
 825
 826                 }
 827
 828         kfree(pin_configs);
 829
 830         /* Collect pin positions and their mux settings. */
 831         for (i = 0; i < npins; ++i) {
 832                 u32 of_pinconf;
 833                 struct rza1_mux_conf *mux_conf = &mux_confs[i];
 834
 835                 ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);
 836                 if (ret)
 837                         return ret;
 838
 839                 mux_conf->id            = of_pinconf & MUX_PIN_ID_MASK;
 840                 mux_conf->port          = RZA1_PIN_ID_TO_PORT(mux_conf->id);
 841                 mux_conf->pin           = RZA1_PIN_ID_TO_PIN(mux_conf->id);
 842                 mux_conf->mux_func      = MUX_FUNC(of_pinconf);
 843                 mux_conf->mux_flags     = pinmux_flags;
 844
 845                 if (mux_conf->port >= RZA1_NPORTS ||
 846                     mux_conf->pin >= RZA1_PINS_PER_PORT) {
 847                         dev_err(rza1_pctl->dev,
 848                                 "Wrong port %u pin %u for %s property\n",
 849                                 mux_conf->port, mux_conf->pin, prop_name);
 850                         return -EINVAL;
 851                 }
 852
 853                 grpins[i] = mux_conf->id;
 854         }
 855
 856         return npins;
 857 }
 858
 859 /**
 860  * rza1_dt_node_to_map() - map a pin mux node to a function/group
 861  *
 862  * Parse and register a pin mux function.
 863  *
 864  * @pctldev: pin controller device
 865  * @np: device tree node to parse
 866  * @map: pointer to pin map (output)
 867  * @num_maps: number of collected maps (output)
 868  */
 869 static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
 870                                struct device_node *np,
 871                                struct pinctrl_map **map,
 872                                unsigned int *num_maps)
 873 {
 874         struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
 875         struct rza1_mux_conf *mux_confs, *mux_conf;
 876         unsigned int *grpins, *grpin;
 877         struct device_node *child;
 878         const char *grpname;
 879         const char **fngrps;
 880         int ret, npins;
 881
 882         npins = rza1_dt_node_pin_count(np);
 883         if (npins < 0) {
 884                 dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");
 885                 return -EINVAL;
 886         }
 887
 888         /*
 889          * Functions are made of 1 group only;
 890          * in fact, functions and groups are identical for this pin controller
 891          * except that functions carry an array of per-pin mux configuration
 892          * settings.
 893          */
 894         mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),
 895                                  GFP_KERNEL);
 896         grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),
 897                               GFP_KERNEL);
 898         fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
 899
 900         if (!mux_confs || !grpins || !fngrps)
 901                 return -ENOMEM;
 902
 903         /*
 904          * Parse the pinmux node.
 905          * If the node does not contain "pinmux" property (-ENOENT)
 906          * that property shall be specified in all its children sub-nodes.
 907          */
 908         mux_conf = &mux_confs[0];
 909         grpin = &grpins[0];
 910
 911         ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
 912         if (ret == -ENOENT)
 913                 for_each_child_of_node(np, child) {
 914                         ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
 915                                                      grpin);
 916                         if (ret < 0)
 917                                 return ret;
 918
 919                         grpin += ret;
 920                         mux_conf += ret;
 921                 }
 922         else if (ret < 0)
 923                 return ret;
 924
 925         /* Register pin group and function name to pinctrl_generic */
 926         grpname = np->name;
 927         fngrps[0] = grpname;
 928
 929         mutex_lock(&rza1_pctl->mutex);
 930         ret = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
 931                                         NULL);
 932         if (ret) {
 933                 mutex_unlock(&rza1_pctl->mutex);
 934                 return ret;
 935         }
 936
 937         ret = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
 938                                           mux_confs);
 939         if (ret)
 940                 goto remove_group;
 941         mutex_unlock(&rza1_pctl->mutex);
 942
 943         dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
 944                                  grpname, npins);
 945
 946         /* Create map where to retrieve function and mux settings from */
 947         *num_maps = 0;
 948         *map = kzalloc(sizeof(**map), GFP_KERNEL);
 949         if (!*map) {
 950                 ret = -ENOMEM;
 951                 goto remove_function;
 952         }
 953
 954         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
 955         (*map)->data.mux.group = np->name;
 956         (*map)->data.mux.function = np->name;
 957         *num_maps = 1;
 958
 959         return 0;
 960
 961 remove_function:
 962         mutex_lock(&rza1_pctl->mutex);
 963         pinmux_generic_remove_last_function(pctldev);
 964
 965 remove_group:
 966         pinctrl_generic_remove_last_group(pctldev);
 967         mutex_unlock(&rza1_pctl->mutex);
 968
 969         dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
 970                                  grpname);
 971
 972         return ret;
 973 }
 974
 975 static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
 976                              struct pinctrl_map *map, unsigned int num_maps)
 977 {
 978         kfree(map);
 979 }
 980
 981 static const struct pinctrl_ops rza1_pinctrl_ops = {
 982         .get_groups_count       = pinctrl_generic_get_group_count,
 983         .get_group_name         = pinctrl_generic_get_group_name,
 984         .get_group_pins         = pinctrl_generic_get_group_pins,
 985         .dt_node_to_map         = rza1_dt_node_to_map,
 986         .dt_free_map            = rza1_dt_free_map,
 987 };
 988
 989 /* ----------------------------------------------------------------------------
 990  * pinmux operations
 991  */
 992
 993 /**
 994  * rza1_set_mux() - retrieve pins from a group and apply their mux settings
 995  *
 996  * @pctldev: pin controller device
 997  * @selector: function selector
 998  * @group: group selector
 999  */
1000 static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1001                            unsigned int group)
1002 {
1003         struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
1004         struct rza1_mux_conf *mux_confs;
1005         struct function_desc *func;
1006         struct group_desc *grp;
1007         int i;
1008
1009         grp = pinctrl_generic_get_group(pctldev, group);
1010         if (!grp)
1011                 return -EINVAL;
1012
1013         func = pinmux_generic_get_function(pctldev, selector);
1014         if (!func)
1015                 return -EINVAL;
1016
1017         mux_confs = (struct rza1_mux_conf *)func->data;
1018         for (i = 0; i < grp->num_pins; ++i) {
1019                 int ret;
1020
1021                 ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
1022                 if (ret)
1023                         return ret;
1024         }
1025
1026         return 0;
1027 }
1028
1029 static const struct pinmux_ops rza1_pinmux_ops = {
1030         .get_functions_count    = pinmux_generic_get_function_count,
1031         .get_function_name      = pinmux_generic_get_function_name,
1032         .get_function_groups    = pinmux_generic_get_function_groups,
1033         .set_mux                = rza1_set_mux,
1034         .strict                 = true,
1035 };
1036
1037 /* ----------------------------------------------------------------------------
1038  * RZ/A1 pin controller driver operations
1039  */
1040
1041 static unsigned int rza1_count_gpio_chips(struct device_node *np)
1042 {
1043         struct device_node *child;
1044         unsigned int count = 0;
1045
1046         for_each_child_of_node(np, child) {
1047                 if (!of_property_read_bool(child, "gpio-controller"))
1048                         continue;
1049
1050                 count++;
1051         }
1052
1053         return count;
1054 }
1055
1056 /**
1057  * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
1058  *
1059  * The gpio controller subnode shall provide a "gpio-ranges" list property as
1060  * defined by gpio device tree binding documentation.
1061  *
1062  * @rza1_pctl: RZ/A1 pin controller device
1063  * @np: of gpio-controller node
1064  * @chip: gpio chip to register to gpiolib
1065  * @range: pin range to register to pinctrl core
1066  */
1067 static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
1068                                struct device_node *np,
1069                                struct gpio_chip *chip,
1070                                struct pinctrl_gpio_range *range)
1071 {
1072         const char *list_name = "gpio-ranges";
1073         struct of_phandle_args of_args;
1074         unsigned int gpioport;
1075         u32 pinctrl_base;
1076         int ret;
1077
1078         ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args);
1079         if (ret) {
1080                 dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
1081                         list_name);
1082                 return ret;
1083         }
1084
1085         /*
1086          * Find out on which port this gpio-chip maps to by inspecting the
1087          * second argument of the "gpio-ranges" property.
1088          */
1089         pinctrl_base = of_args.args[1];
1090         gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
1091         if (gpioport >= RZA1_NPORTS) {
1092                 dev_err(rza1_pctl->dev,
1093                         "Invalid values in property %s\n", list_name);
1094                 return -EINVAL;
1095         }
1096
1097         *chip           = rza1_gpiochip_template;
1098         chip->base      = -1;
1099         chip->label     = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%s",
1100                                          np->name);
1101         chip->ngpio     = of_args.args[2];
1102         chip->of_node   = np;
1103         chip->parent    = rza1_pctl->dev;
1104
1105         range->id       = gpioport;
1106         range->name     = chip->label;
1107         range->pin_base = range->base = pinctrl_base;
1108         range->npins    = of_args.args[2];
1109         range->gc       = chip;
1110
1111         ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
1112                                      &rza1_pctl->ports[gpioport]);
1113         if (ret)
1114                 return ret;
1115
1116         pinctrl_add_gpio_range(rza1_pctl->pctl, range);
1117
1118         dev_info(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
1119                  chip->label, chip->ngpio);
1120
1121         return 0;
1122 }
1123
1124 /**
1125  * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
1126  *
1127  * @rza1_pctl: RZ/A1 pin controller device
1128  */
1129 static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
1130 {
1131         struct device_node *np = rza1_pctl->dev->of_node;
1132         struct pinctrl_gpio_range *gpio_ranges;
1133         struct gpio_chip *gpio_chips;
1134         struct device_node *child;
1135         unsigned int ngpiochips;
1136         unsigned int i;
1137         int ret;
1138
1139         ngpiochips = rza1_count_gpio_chips(np);
1140         if (ngpiochips == 0) {
1141                 dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
1142                 return 0;
1143         }
1144
1145         gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1146                                   sizeof(*gpio_chips), GFP_KERNEL);
1147         gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1148                                    sizeof(*gpio_ranges), GFP_KERNEL);
1149         if (!gpio_chips || !gpio_ranges)
1150                 return -ENOMEM;
1151
1152         i = 0;
1153         for_each_child_of_node(np, child) {
1154                 if (!of_property_read_bool(child, "gpio-controller"))
1155                         continue;
1156
1157                 ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
1158                                           &gpio_ranges[i]);
1159                 if (ret)
1160                         goto gpiochip_remove;
1161
1162                 ++i;
1163         }
1164
1165         dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);
1166
1167         return 0;
1168
1169 gpiochip_remove:
1170         for (; i > 0; i--)
1171                 devm_gpiochip_remove(rza1_pctl->dev, &gpio_chips[i - 1]);
1172
1173         return ret;
1174 }
1175
1176 /**
1177  * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
1178  *                           them to pinctrl and gpio cores.
1179  *
1180  * @rza1_pctl: RZ/A1 pin controller device
1181  */
1182 static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
1183 {
1184         struct pinctrl_pin_desc *pins;
1185         struct rza1_port *ports;
1186         unsigned int i;
1187         int ret;
1188
1189         pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
1190                             GFP_KERNEL);
1191         ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
1192                              GFP_KERNEL);
1193         if (!pins || !ports)
1194                 return -ENOMEM;
1195
1196         rza1_pctl->pins         = pins;
1197         rza1_pctl->desc.pins    = pins;
1198         rza1_pctl->desc.npins   = RZA1_NPINS;
1199         rza1_pctl->ports        = ports;
1200
1201         for (i = 0; i < RZA1_NPINS; ++i) {
1202                 unsigned int pin = RZA1_PIN_ID_TO_PIN(i);
1203                 unsigned int port = RZA1_PIN_ID_TO_PORT(i);
1204
1205                 pins[i].number = i;
1206                 pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
1207                                               "P%u-%u", port, pin);
1208
1209                 if (i % RZA1_PINS_PER_PORT == 0) {
1210                         /*
1211                          * Setup ports;
1212                          * they provide per-port lock and logical base address.
1213                          */
1214                         unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);
1215
1216                         ports[port_id].id       = port_id;
1217                         ports[port_id].base     = rza1_pctl->base;
1218                         ports[port_id].pins     = &pins[i];
1219                         spin_lock_init(&ports[port_id].lock);
1220                 }
1221         }
1222
1223         ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
1224                                              rza1_pctl, &rza1_pctl->pctl);
1225         if (ret) {
1226                 dev_err(rza1_pctl->dev,
1227                         "RZ/A1 pin controller registration failed\n");
1228                 return ret;
1229         }
1230
1231         ret = pinctrl_enable(rza1_pctl->pctl);
1232         if (ret) {
1233                 dev_err(rza1_pctl->dev,
1234                         "RZ/A1 pin controller failed to start\n");
1235                 return ret;
1236         }
1237
1238         ret = rza1_gpio_register(rza1_pctl);
1239         if (ret) {
1240                 dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");
1241                 return ret;
1242         }
1243
1244         return 0;
1245 }
1246
1247 static int rza1_pinctrl_probe(struct platform_device *pdev)
1248 {
1249         struct rza1_pinctrl *rza1_pctl;
1250         struct resource *res;
1251         int ret;
1252
1253         rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
1254         if (!rza1_pctl)
1255                 return -ENOMEM;
1256
1257         rza1_pctl->dev = &pdev->dev;
1258
1259         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1260         rza1_pctl->base = devm_ioremap_resource(&pdev->dev, res);
1261         if (IS_ERR(rza1_pctl->base))
1262                 return PTR_ERR(rza1_pctl->base);
1263
1264         mutex_init(&rza1_pctl->mutex);
1265
1266         platform_set_drvdata(pdev, rza1_pctl);
1267
1268         rza1_pctl->desc.name    = DRIVER_NAME;
1269         rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
1270         rza1_pctl->desc.pmxops  = &rza1_pinmux_ops;
1271         rza1_pctl->desc.owner   = THIS_MODULE;
1272         rza1_pctl->data         = of_device_get_match_data(&pdev->dev);
1273
1274         ret = rza1_pinctrl_register(rza1_pctl);
1275         if (ret)
1276                 return ret;
1277
1278         dev_info(&pdev->dev,
1279                  "RZ/A1 pin controller and gpio successfully registered\n");
1280
1281         return 0;
1282 }
1283
1284 static const struct of_device_id rza1_pinctrl_of_match[] = {
1285         {
1286                 .compatible     = "renesas,r7s72100-ports",
1287                 .data           = &rza1h_pmx_conf,
1288         },
1289         { }
1290 };
1291
1292 static struct platform_driver rza1_pinctrl_driver = {
1293         .driver = {
1294                 .name = DRIVER_NAME,
1295                 .of_match_table = rza1_pinctrl_of_match,
1296         },
1297         .probe = rza1_pinctrl_probe,
1298 };
1299
1300 static int __init rza1_pinctrl_init(void)
1301 {
1302         return platform_driver_register(&rza1_pinctrl_driver);
1303 }
1304 core_initcall(rza1_pinctrl_init);
1305
1306 MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");
1307 MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
1308 MODULE_LICENSE("GPL v2");