drivers/watchdog/dw_wdt.c

   1 /*
   2  * Copyright 2010-2011 Picochip Ltd., Jamie Iles
   3  * http://www.picochip.com
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  *
  10  * This file implements a driver for the Synopsys DesignWare watchdog device
  11  * in the many subsystems. The watchdog has 16 different timeout periods
  12  * and these are a function of the input clock frequency.
  13  *
  14  * The DesignWare watchdog cannot be stopped once it has been started so we
  15  * do not implement a stop function. The watchdog core will continue to send
  16  * heartbeat requests after the watchdog device has been closed.
  17  */
  18
  19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  20
  21 #include <linux/bitops.h>
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/of.h>
  30 #include <linux/pm.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/reset.h>
  33 #include <linux/watchdog.h>
  34
  35 #define WDOG_CONTROL_REG_OFFSET             0x00
  36 #define WDOG_CONTROL_REG_WDT_EN_MASK        0x01
  37 #define WDOG_CONTROL_REG_RESP_MODE_MASK     0x02
  38 #define WDOG_TIMEOUT_RANGE_REG_OFFSET       0x04
  39 #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT    4
  40 #define WDOG_CURRENT_COUNT_REG_OFFSET       0x08
  41 #define WDOG_COUNTER_RESTART_REG_OFFSET     0x0c
  42 #define WDOG_COUNTER_RESTART_KICK_VALUE     0x76
  43
  44 /* The maximum TOP (timeout period) value that can be set in the watchdog. */
  45 #define DW_WDT_MAX_TOP          15
  46
  47 #define DW_WDT_DEFAULT_SECONDS  30
  48
  49 static bool nowayout = WATCHDOG_NOWAYOUT;
  50 module_param(nowayout, bool, 0);
  51 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  52                  "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  53
  54 struct dw_wdt {
  55         void __iomem            *regs;
  56         struct clk              *clk;
  57         unsigned long           rate;
  58         struct watchdog_device  wdd;
  59         struct reset_control    *rst;
  60 };
  61
  62 #define to_dw_wdt(wdd)  container_of(wdd, struct dw_wdt, wdd)
  63
  64 static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
  65 {
  66         return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
  67                 WDOG_CONTROL_REG_WDT_EN_MASK;
  68 }
  69
  70 static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top)
  71 {
  72         /*
  73          * There are 16 possible timeout values in 0..15 where the number of
  74          * cycles is 2 ^ (16 + i) and the watchdog counts down.
  75          */
  76         return (1U << (16 + top)) / dw_wdt->rate;
  77 }
  78
  79 static int dw_wdt_get_top(struct dw_wdt *dw_wdt)
  80 {
  81         int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
  82
  83         return dw_wdt_top_in_seconds(dw_wdt, top);
  84 }
  85
  86 static int dw_wdt_ping(struct watchdog_device *wdd)
  87 {
  88         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  89
  90         writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
  91                WDOG_COUNTER_RESTART_REG_OFFSET);
  92
  93         return 0;
  94 }
  95
  96 static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
  97 {
  98         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  99         int i, top_val = DW_WDT_MAX_TOP;
 100
 101         /*
 102          * Iterate over the timeout values until we find the closest match. We
 103          * always look for >=.
 104          */
 105         for (i = 0; i <= DW_WDT_MAX_TOP; ++i)
 106                 if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) {
 107                         top_val = i;
 108                         break;
 109                 }
 110
 111         /*
 112          * Set the new value in the watchdog.  Some versions of dw_wdt
 113          * have have TOPINIT in the TIMEOUT_RANGE register (as per
 114          * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1).  On those we
 115          * effectively get a pat of the watchdog right here.
 116          */
 117         writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
 118                dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
 119
 120         wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val);
 121
 122         return 0;
 123 }
 124
 125 static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
 126 {
 127         u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
 128
 129         /* Disable interrupt mode; always perform system reset. */
 130         val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
 131         /* Enable watchdog. */
 132         val |= WDOG_CONTROL_REG_WDT_EN_MASK;
 133         writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
 134 }
 135
 136 static int dw_wdt_start(struct watchdog_device *wdd)
 137 {
 138         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
 139
 140         dw_wdt_set_timeout(wdd, wdd->timeout);
 141         dw_wdt_arm_system_reset(dw_wdt);
 142
 143         return 0;
 144 }
 145
 146 static int dw_wdt_stop(struct watchdog_device *wdd)
 147 {
 148         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
 149
 150         if (!dw_wdt->rst) {
 151                 set_bit(WDOG_HW_RUNNING, &wdd->status);
 152                 return 0;
 153         }
 154
 155         reset_control_assert(dw_wdt->rst);
 156         reset_control_deassert(dw_wdt->rst);
 157
 158         return 0;
 159 }
 160
 161 static int dw_wdt_restart(struct watchdog_device *wdd,
 162                           unsigned long action, void *data)
 163 {
 164         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
 165
 166         writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
 167         if (dw_wdt_is_enabled(dw_wdt))
 168                 writel(WDOG_COUNTER_RESTART_KICK_VALUE,
 169                        dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
 170         else
 171                 dw_wdt_arm_system_reset(dw_wdt);
 172
 173         /* wait for reset to assert... */
 174         mdelay(500);
 175
 176         return 0;
 177 }
 178
 179 static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
 180 {
 181         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
 182
 183         return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) /
 184                 dw_wdt->rate;
 185 }
 186
 187 static const struct watchdog_info dw_wdt_ident = {
 188         .options        = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
 189                           WDIOF_MAGICCLOSE,
 190         .identity       = "Synopsys DesignWare Watchdog",
 191 };
 192
 193 static const struct watchdog_ops dw_wdt_ops = {
 194         .owner          = THIS_MODULE,
 195         .start          = dw_wdt_start,
 196         .stop           = dw_wdt_stop,
 197         .ping           = dw_wdt_ping,
 198         .set_timeout    = dw_wdt_set_timeout,
 199         .get_timeleft   = dw_wdt_get_timeleft,
 200         .restart        = dw_wdt_restart,
 201 };
 202
 203 #ifdef CONFIG_PM_SLEEP
 204 static int dw_wdt_suspend(struct device *dev)
 205 {
 206         struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
 207
 208         clk_disable_unprepare(dw_wdt->clk);
 209
 210         return 0;
 211 }
 212
 213 static int dw_wdt_resume(struct device *dev)
 214 {
 215         struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
 216         int err = clk_prepare_enable(dw_wdt->clk);
 217
 218         if (err)
 219                 return err;
 220
 221         dw_wdt_ping(&dw_wdt->wdd);
 222
 223         return 0;
 224 }
 225 #endif /* CONFIG_PM_SLEEP */
 226
 227 static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
 228
 229 static int dw_wdt_drv_probe(struct platform_device *pdev)
 230 {
 231         struct device *dev = &pdev->dev;
 232         struct watchdog_device *wdd;
 233         struct dw_wdt *dw_wdt;
 234         struct resource *mem;
 235         int ret;
 236
 237         dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
 238         if (!dw_wdt)
 239                 return -ENOMEM;
 240
 241         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 242         dw_wdt->regs = devm_ioremap_resource(dev, mem);
 243         if (IS_ERR(dw_wdt->regs))
 244                 return PTR_ERR(dw_wdt->regs);
 245
 246         dw_wdt->clk = devm_clk_get(dev, NULL);
 247         if (IS_ERR(dw_wdt->clk))
 248                 return PTR_ERR(dw_wdt->clk);
 249
 250         ret = clk_prepare_enable(dw_wdt->clk);
 251         if (ret)
 252                 return ret;
 253
 254         dw_wdt->rate = clk_get_rate(dw_wdt->clk);
 255         if (dw_wdt->rate == 0) {
 256                 ret = -EINVAL;
 257                 goto out_disable_clk;
 258         }
 259
 260         dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
 261         if (IS_ERR(dw_wdt->rst)) {
 262                 ret = PTR_ERR(dw_wdt->rst);
 263                 goto out_disable_clk;
 264         }
 265
 266         reset_control_deassert(dw_wdt->rst);
 267
 268         wdd = &dw_wdt->wdd;
 269         wdd->info = &dw_wdt_ident;
 270         wdd->ops = &dw_wdt_ops;
 271         wdd->min_timeout = 1;
 272         wdd->max_hw_heartbeat_ms =
 273                 dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000;
 274         wdd->parent = dev;
 275
 276         watchdog_set_drvdata(wdd, dw_wdt);
 277         watchdog_set_nowayout(wdd, nowayout);
 278         watchdog_init_timeout(wdd, 0, dev);
 279
 280         /*
 281          * If the watchdog is already running, use its already configured
 282          * timeout. Otherwise use the default or the value provided through
 283          * devicetree.
 284          */
 285         if (dw_wdt_is_enabled(dw_wdt)) {
 286                 wdd->timeout = dw_wdt_get_top(dw_wdt);
 287                 set_bit(WDOG_HW_RUNNING, &wdd->status);
 288         } else {
 289                 wdd->timeout = DW_WDT_DEFAULT_SECONDS;
 290                 watchdog_init_timeout(wdd, 0, dev);
 291         }
 292
 293         platform_set_drvdata(pdev, dw_wdt);
 294
 295         watchdog_set_restart_priority(wdd, 128);
 296
 297         ret = watchdog_register_device(wdd);
 298         if (ret)
 299                 goto out_disable_clk;
 300
 301         return 0;
 302
 303 out_disable_clk:
 304         clk_disable_unprepare(dw_wdt->clk);
 305         return ret;
 306 }
 307
 308 static int dw_wdt_drv_remove(struct platform_device *pdev)
 309 {
 310         struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
 311
 312         watchdog_unregister_device(&dw_wdt->wdd);
 313         reset_control_assert(dw_wdt->rst);
 314         clk_disable_unprepare(dw_wdt->clk);
 315
 316         return 0;
 317 }
 318
 319 #ifdef CONFIG_OF
 320 static const struct of_device_id dw_wdt_of_match[] = {
 321         { .compatible = "snps,dw-wdt", },
 322         { /* sentinel */ }
 323 };
 324 MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
 325 #endif
 326
 327 static struct platform_driver dw_wdt_driver = {
 328         .probe          = dw_wdt_drv_probe,
 329         .remove         = dw_wdt_drv_remove,
 330         .driver         = {
 331                 .name   = "dw_wdt",
 332                 .of_match_table = of_match_ptr(dw_wdt_of_match),
 333                 .pm     = &dw_wdt_pm_ops,
 334         },
 335 };
 336
 337 module_platform_driver(dw_wdt_driver);
 338
 339 MODULE_AUTHOR("Jamie Iles");
 340 MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
 341 MODULE_LICENSE("GPL");