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mtd: rawnand: denali: do not pass zero maxchips to nand_scan()
[linux/fpc-iii.git] / drivers / parport / parport_serial.c
blob461fd8a24278030fb97736736f6258428d49c776
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Support for common PCI multi-I/O cards (which is most of them)
4 *
5 * Copyright (C) 2001 Tim Waugh <twaugh@redhat.com>
6 *
7 * Multi-function PCI cards are supposed to present separate logical
8 * devices on the bus. A common thing to do seems to be to just use
9 * one logical device with lots of base address registers for both
10 * parallel ports and serial ports. This driver is for dealing with
11 * that.
12 */
13
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/parport.h>
17 #include <linux/parport_pc.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21
22 #include <linux/8250_pci.h>
23
24 enum parport_pc_pci_cards {
25 titan_110l = 0,
26 titan_210l,
27 netmos_9xx5_combo,
28 netmos_9855,
29 netmos_9855_2p,
30 netmos_9900,
31 netmos_9900_2p,
32 netmos_99xx_1p,
33 avlab_1s1p,
34 avlab_1s2p,
35 avlab_2s1p,
36 siig_1s1p_10x,
37 siig_2s1p_10x,
38 siig_2p1s_20x,
39 siig_1s1p_20x,
40 siig_2s1p_20x,
41 timedia_4078a,
42 timedia_4079h,
43 timedia_4085h,
44 timedia_4088a,
45 timedia_4089a,
46 timedia_4095a,
47 timedia_4096a,
48 timedia_4078u,
49 timedia_4079a,
50 timedia_4085u,
51 timedia_4079r,
52 timedia_4079s,
53 timedia_4079d,
54 timedia_4079e,
55 timedia_4079f,
56 timedia_9079a,
57 timedia_9079b,
58 timedia_9079c,
59 wch_ch353_1s1p,
60 wch_ch353_2s1p,
61 wch_ch382_0s1p,
62 wch_ch382_2s1p,
63 brainboxes_5s1p,
64 sunix_2s1p,
65 };
66
67 /* each element directly indexed from enum list, above */
68 struct parport_pc_pci {
69 int numports;
70 struct { /* BAR (base address registers) numbers in the config
71 space header */
72 int lo;
73 int hi; /* -1 if not there, >6 for offset-method (max
74 BAR is 6) */
75 } addr[4];
76
77 /* If set, this is called immediately after pci_enable_device.
78 * If it returns non-zero, no probing will take place and the
79 * ports will not be used. */
80 int (*preinit_hook) (struct pci_dev *pdev, struct parport_pc_pci *card,
81 int autoirq, int autodma);
82
83 /* If set, this is called after probing for ports. If 'failed'
84 * is non-zero we couldn't use any of the ports. */
85 void (*postinit_hook) (struct pci_dev *pdev,
86 struct parport_pc_pci *card, int failed);
87 };
88
89 static int netmos_parallel_init(struct pci_dev *dev, struct parport_pc_pci *par,
90 int autoirq, int autodma)
91 {
92 /* the rule described below doesn't hold for this device */
93 if (dev->device == PCI_DEVICE_ID_NETMOS_9835 &&
94 dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
95 dev->subsystem_device == 0x0299)
96 return -ENODEV;
97
98 if (dev->device == PCI_DEVICE_ID_NETMOS_9912) {
99 par->numports = 1;
100 } else {
101 /*
102 * Netmos uses the subdevice ID to indicate the number of parallel
103 * and serial ports. The form is 0x00PS, where <P> is the number of
104 * parallel ports and <S> is the number of serial ports.
105 */
106 par->numports = (dev->subsystem_device & 0xf0) >> 4;
107 if (par->numports > ARRAY_SIZE(par->addr))
108 par->numports = ARRAY_SIZE(par->addr);
109 }
110
111 return 0;
112 }
113
114 static struct parport_pc_pci cards[] = {
115 /* titan_110l */ { 1, { { 3, -1 }, } },
116 /* titan_210l */ { 1, { { 3, -1 }, } },
117 /* netmos_9xx5_combo */ { 1, { { 2, -1 }, }, netmos_parallel_init },
118 /* netmos_9855 */ { 1, { { 0, -1 }, }, netmos_parallel_init },
119 /* netmos_9855_2p */ { 2, { { 0, -1 }, { 2, -1 }, } },
120 /* netmos_9900 */ {1, { { 3, 4 }, }, netmos_parallel_init },
121 /* netmos_9900_2p */ {2, { { 0, 1 }, { 3, 4 }, } },
122 /* netmos_99xx_1p */ {1, { { 0, 1 }, } },
123 /* avlab_1s1p */ { 1, { { 1, 2}, } },
124 /* avlab_1s2p */ { 2, { { 1, 2}, { 3, 4 },} },
125 /* avlab_2s1p */ { 1, { { 2, 3}, } },
126 /* siig_1s1p_10x */ { 1, { { 3, 4 }, } },
127 /* siig_2s1p_10x */ { 1, { { 4, 5 }, } },
128 /* siig_2p1s_20x */ { 2, { { 1, 2 }, { 3, 4 }, } },
129 /* siig_1s1p_20x */ { 1, { { 1, 2 }, } },
130 /* siig_2s1p_20x */ { 1, { { 2, 3 }, } },
131 /* timedia_4078a */ { 1, { { 2, -1 }, } },
132 /* timedia_4079h */ { 1, { { 2, 3 }, } },
133 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
134 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
135 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
136 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
137 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
138 /* timedia_4078u */ { 1, { { 2, -1 }, } },
139 /* timedia_4079a */ { 1, { { 2, 3 }, } },
140 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
141 /* timedia_4079r */ { 1, { { 2, 3 }, } },
142 /* timedia_4079s */ { 1, { { 2, 3 }, } },
143 /* timedia_4079d */ { 1, { { 2, 3 }, } },
144 /* timedia_4079e */ { 1, { { 2, 3 }, } },
145 /* timedia_4079f */ { 1, { { 2, 3 }, } },
146 /* timedia_9079a */ { 1, { { 2, 3 }, } },
147 /* timedia_9079b */ { 1, { { 2, 3 }, } },
148 /* timedia_9079c */ { 1, { { 2, 3 }, } },
149 /* wch_ch353_1s1p*/ { 1, { { 1, -1}, } },
150 /* wch_ch353_2s1p*/ { 1, { { 2, -1}, } },
151 /* wch_ch382_0s1p*/ { 1, { { 2, -1}, } },
152 /* wch_ch382_2s1p*/ { 1, { { 2, -1}, } },
153 /* brainboxes_5s1p */ { 1, { { 3, -1 }, } },
154 /* sunix_2s1p */ { 1, { { 3, -1 }, } },
155 };
156
157 static struct pci_device_id parport_serial_pci_tbl[] = {
158 /* PCI cards */
159 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_110L,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_110l },
161 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_210L,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_210l },
163 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9735,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
165 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9745,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
167 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
169 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9845,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
171 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
172 0x1000, 0x0020, 0, 0, netmos_9855_2p },
173 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
174 0x1000, 0x0022, 0, 0, netmos_9855_2p },
175 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
177 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
178 0xA000, 0x3011, 0, 0, netmos_9900 },
179 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
180 0xA000, 0x3012, 0, 0, netmos_9900 },
181 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
182 0xA000, 0x3020, 0, 0, netmos_9900_2p },
183 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
184 0xA000, 0x2000, 0, 0, netmos_99xx_1p },
185 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
186 { PCI_VENDOR_ID_AFAVLAB, 0x2110,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
188 { PCI_VENDOR_ID_AFAVLAB, 0x2111,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
190 { PCI_VENDOR_ID_AFAVLAB, 0x2112,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
192 { PCI_VENDOR_ID_AFAVLAB, 0x2140,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
194 { PCI_VENDOR_ID_AFAVLAB, 0x2141,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
196 { PCI_VENDOR_ID_AFAVLAB, 0x2142,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
198 { PCI_VENDOR_ID_AFAVLAB, 0x2160,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
200 { PCI_VENDOR_ID_AFAVLAB, 0x2161,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
202 { PCI_VENDOR_ID_AFAVLAB, 0x2162,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
204 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_550,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
206 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_650,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
208 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_850,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
210 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_550,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
212 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_650,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
214 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_850,
215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
216 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_550,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
218 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_650,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
220 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_850,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
222 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_550,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
224 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_650,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
226 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_850,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
228 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_550,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
230 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_650,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
232 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_850,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
234 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
235 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
236 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
237 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
238 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
239 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
240 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
241 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
242 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
243 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
244 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
245 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
246 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
247 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
248 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
249 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
250 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
251 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
252 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
253
254 /* WCH CARDS */
255 { 0x4348, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, wch_ch353_1s1p},
256 { 0x4348, 0x7053, 0x4348, 0x3253, 0, 0, wch_ch353_2s1p},
257 { 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382_0s1p},
258 { 0x1c00, 0x3250, 0x1c00, 0x3250, 0, 0, wch_ch382_2s1p},
259
260 /* BrainBoxes PX272/PX306 MIO card */
261 { PCI_VENDOR_ID_INTASHIELD, 0x4100,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_5s1p },
263
264 /*
265 * More SUNIX variations. At least one of these has part number
266 * '5079A but subdevice 0x102. That board reports 0x0708 as
267 * its PCI Class.
268 */
269 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
270 0x0102, 0, 0, sunix_2s1p },
271
272 { 0, } /* terminate list */
273 };
274 MODULE_DEVICE_TABLE(pci,parport_serial_pci_tbl);
275
276 /*
277 * This table describes the serial "geometry" of these boards. Any
278 * quirks for these can be found in drivers/serial/8250_pci.c
279 *
280 * Cards not tested are marked n/t
281 * If you have one of these cards and it works for you, please tell me..
282 */
283 static struct pciserial_board pci_parport_serial_boards[] = {
284 [titan_110l] = {
285 .flags = FL_BASE1 | FL_BASE_BARS,
286 .num_ports = 1,
287 .base_baud = 921600,
288 .uart_offset = 8,
289 },
290 [titan_210l] = {
291 .flags = FL_BASE1 | FL_BASE_BARS,
292 .num_ports = 2,
293 .base_baud = 921600,
294 .uart_offset = 8,
295 },
296 [netmos_9xx5_combo] = {
297 .flags = FL_BASE0 | FL_BASE_BARS,
298 .num_ports = 1,
299 .base_baud = 115200,
300 .uart_offset = 8,
301 },
302 [netmos_9855] = {
303 .flags = FL_BASE2 | FL_BASE_BARS,
304 .num_ports = 1,
305 .base_baud = 115200,
306 .uart_offset = 8,
307 },
308 [netmos_9855_2p] = {
309 .flags = FL_BASE4 | FL_BASE_BARS,
310 .num_ports = 1,
311 .base_baud = 115200,
312 .uart_offset = 8,
313 },
314 [netmos_9900] = { /* n/t */
315 .flags = FL_BASE0 | FL_BASE_BARS,
316 .num_ports = 1,
317 .base_baud = 115200,
318 .uart_offset = 8,
319 },
320 [netmos_9900_2p] = { /* parallel only */ /* n/t */
321 .flags = FL_BASE0,
322 .num_ports = 0,
323 .base_baud = 115200,
324 .uart_offset = 8,
325 },
326 [netmos_99xx_1p] = { /* parallel only */ /* n/t */
327 .flags = FL_BASE0,
328 .num_ports = 0,
329 .base_baud = 115200,
330 .uart_offset = 8,
331 },
332 [avlab_1s1p] = { /* n/t */
333 .flags = FL_BASE0 | FL_BASE_BARS,
334 .num_ports = 1,
335 .base_baud = 115200,
336 .uart_offset = 8,
337 },
338 [avlab_1s2p] = { /* n/t */
339 .flags = FL_BASE0 | FL_BASE_BARS,
340 .num_ports = 1,
341 .base_baud = 115200,
342 .uart_offset = 8,
343 },
344 [avlab_2s1p] = { /* n/t */
345 .flags = FL_BASE0 | FL_BASE_BARS,
346 .num_ports = 2,
347 .base_baud = 115200,
348 .uart_offset = 8,
349 },
350 [siig_1s1p_10x] = {
351 .flags = FL_BASE2,
352 .num_ports = 1,
353 .base_baud = 460800,
354 .uart_offset = 8,
355 },
356 [siig_2s1p_10x] = {
357 .flags = FL_BASE2,
358 .num_ports = 1,
359 .base_baud = 921600,
360 .uart_offset = 8,
361 },
362 [siig_2p1s_20x] = {
363 .flags = FL_BASE0,
364 .num_ports = 1,
365 .base_baud = 921600,
366 .uart_offset = 8,
367 },
368 [siig_1s1p_20x] = {
369 .flags = FL_BASE0,
370 .num_ports = 1,
371 .base_baud = 921600,
372 .uart_offset = 8,
373 },
374 [siig_2s1p_20x] = {
375 .flags = FL_BASE0,
376 .num_ports = 1,
377 .base_baud = 921600,
378 .uart_offset = 8,
379 },
380 [timedia_4078a] = {
381 .flags = FL_BASE0|FL_BASE_BARS,
382 .num_ports = 1,
383 .base_baud = 921600,
384 .uart_offset = 8,
385 },
386 [timedia_4079h] = {
387 .flags = FL_BASE0|FL_BASE_BARS,
388 .num_ports = 1,
389 .base_baud = 921600,
390 .uart_offset = 8,
391 },
392 [timedia_4085h] = {
393 .flags = FL_BASE0|FL_BASE_BARS,
394 .num_ports = 1,
395 .base_baud = 921600,
396 .uart_offset = 8,
397 },
398 [timedia_4088a] = {
399 .flags = FL_BASE0|FL_BASE_BARS,
400 .num_ports = 1,
401 .base_baud = 921600,
402 .uart_offset = 8,
403 },
404 [timedia_4089a] = {
405 .flags = FL_BASE0|FL_BASE_BARS,
406 .num_ports = 1,
407 .base_baud = 921600,
408 .uart_offset = 8,
409 },
410 [timedia_4095a] = {
411 .flags = FL_BASE0|FL_BASE_BARS,
412 .num_ports = 1,
413 .base_baud = 921600,
414 .uart_offset = 8,
415 },
416 [timedia_4096a] = {
417 .flags = FL_BASE0|FL_BASE_BARS,
418 .num_ports = 1,
419 .base_baud = 921600,
420 .uart_offset = 8,
421 },
422 [timedia_4078u] = {
423 .flags = FL_BASE0|FL_BASE_BARS,
424 .num_ports = 1,
425 .base_baud = 921600,
426 .uart_offset = 8,
427 },
428 [timedia_4079a] = {
429 .flags = FL_BASE0|FL_BASE_BARS,
430 .num_ports = 1,
431 .base_baud = 921600,
432 .uart_offset = 8,
433 },
434 [timedia_4085u] = {
435 .flags = FL_BASE0|FL_BASE_BARS,
436 .num_ports = 1,
437 .base_baud = 921600,
438 .uart_offset = 8,
439 },
440 [timedia_4079r] = {
441 .flags = FL_BASE0|FL_BASE_BARS,
442 .num_ports = 1,
443 .base_baud = 921600,
444 .uart_offset = 8,
445 },
446 [timedia_4079s] = {
447 .flags = FL_BASE0|FL_BASE_BARS,
448 .num_ports = 1,
449 .base_baud = 921600,
450 .uart_offset = 8,
451 },
452 [timedia_4079d] = {
453 .flags = FL_BASE0|FL_BASE_BARS,
454 .num_ports = 1,
455 .base_baud = 921600,
456 .uart_offset = 8,
457 },
458 [timedia_4079e] = {
459 .flags = FL_BASE0|FL_BASE_BARS,
460 .num_ports = 1,
461 .base_baud = 921600,
462 .uart_offset = 8,
463 },
464 [timedia_4079f] = {
465 .flags = FL_BASE0|FL_BASE_BARS,
466 .num_ports = 1,
467 .base_baud = 921600,
468 .uart_offset = 8,
469 },
470 [timedia_9079a] = {
471 .flags = FL_BASE0|FL_BASE_BARS,
472 .num_ports = 1,
473 .base_baud = 921600,
474 .uart_offset = 8,
475 },
476 [timedia_9079b] = {
477 .flags = FL_BASE0|FL_BASE_BARS,
478 .num_ports = 1,
479 .base_baud = 921600,
480 .uart_offset = 8,
481 },
482 [timedia_9079c] = {
483 .flags = FL_BASE0|FL_BASE_BARS,
484 .num_ports = 1,
485 .base_baud = 921600,
486 .uart_offset = 8,
487 },
488 [wch_ch353_1s1p] = {
489 .flags = FL_BASE0|FL_BASE_BARS,
490 .num_ports = 1,
491 .base_baud = 115200,
492 .uart_offset = 8,
493 },
494 [wch_ch353_2s1p] = {
495 .flags = FL_BASE0|FL_BASE_BARS,
496 .num_ports = 2,
497 .base_baud = 115200,
498 .uart_offset = 8,
499 },
500 [wch_ch382_0s1p] = {
501 .flags = FL_BASE0,
502 .num_ports = 0,
503 .base_baud = 115200,
504 .uart_offset = 8,
505 },
506 [wch_ch382_2s1p] = {
507 .flags = FL_BASE0,
508 .num_ports = 2,
509 .base_baud = 115200,
510 .uart_offset = 8,
511 .first_offset = 0xC0,
512 },
513 [brainboxes_5s1p] = {
514 .flags = FL_BASE2,
515 .num_ports = 5,
516 .base_baud = 921600,
517 .uart_offset = 8,
518 },
519 [sunix_2s1p] = {
520 .flags = FL_BASE0|FL_BASE_BARS,
521 .num_ports = 2,
522 .base_baud = 921600,
523 .uart_offset = 8,
524 },
525 };
526
527 struct parport_serial_private {
528 struct serial_private *serial;
529 int num_par;
530 struct parport *port[PARPORT_MAX];
531 struct parport_pc_pci par;
532 };
533
534 /* Register the serial port(s) of a PCI card. */
535 static int serial_register(struct pci_dev *dev, const struct pci_device_id *id)
536 {
537 struct parport_serial_private *priv = pci_get_drvdata (dev);
538 struct pciserial_board *board;
539 struct serial_private *serial;
540
541 board = &pci_parport_serial_boards[id->driver_data];
542 if (board->num_ports == 0)
543 return 0;
544
545 serial = pciserial_init_ports(dev, board);
546 if (IS_ERR(serial))
547 return PTR_ERR(serial);
548
549 priv->serial = serial;
550 return 0;
551 }
552
553 /* Register the parallel port(s) of a PCI card. */
554 static int parport_register(struct pci_dev *dev, const struct pci_device_id *id)
555 {
556 struct parport_pc_pci *card;
557 struct parport_serial_private *priv = pci_get_drvdata (dev);
558 int n, success = 0;
559
560 priv->par = cards[id->driver_data];
561 card = &priv->par;
562 if (card->preinit_hook &&
563 card->preinit_hook (dev, card, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
564 return -ENODEV;
565
566 for (n = 0; n < card->numports; n++) {
567 struct parport *port;
568 int lo = card->addr[n].lo;
569 int hi = card->addr[n].hi;
570 unsigned long io_lo, io_hi;
571 int irq;
572
573 if (priv->num_par == ARRAY_SIZE (priv->port)) {
574 dev_warn(&dev->dev,
575 "only %zu parallel ports supported (%d reported)\n",
576 ARRAY_SIZE(priv->port), card->numports);
577 break;
578 }
579
580 io_lo = pci_resource_start (dev, lo);
581 io_hi = 0;
582 if ((hi >= 0) && (hi <= 6))
583 io_hi = pci_resource_start (dev, hi);
584 else if (hi > 6)
585 io_lo += hi; /* Reinterpret the meaning of
586 "hi" as an offset (see SYBA
587 def.) */
588 /* TODO: test if sharing interrupts works */
589 irq = dev->irq;
590 if (irq == IRQ_NONE) {
591 dev_dbg(&dev->dev,
592 "PCI parallel port detected: I/O at %#lx(%#lx)\n",
593 io_lo, io_hi);
594 irq = PARPORT_IRQ_NONE;
595 } else {
596 dev_dbg(&dev->dev,
597 "PCI parallel port detected: I/O at %#lx(%#lx), IRQ %d\n",
598 io_lo, io_hi, irq);
599 }
600 port = parport_pc_probe_port (io_lo, io_hi, irq,
601 PARPORT_DMA_NONE, &dev->dev, IRQF_SHARED);
602 if (port) {
603 priv->port[priv->num_par++] = port;
604 success = 1;
605 }
606 }
607
608 if (card->postinit_hook)
609 card->postinit_hook (dev, card, !success);
610
611 return 0;
612 }
613
614 static int parport_serial_pci_probe(struct pci_dev *dev,
615 const struct pci_device_id *id)
616 {
617 struct parport_serial_private *priv;
618 int err;
619
620 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
621 if (!priv)
622 return -ENOMEM;
623
624 pci_set_drvdata (dev, priv);
625
626 err = pcim_enable_device(dev);
627 if (err)
628 return err;
629
630 err = parport_register(dev, id);
631 if (err)
632 return err;
633
634 err = serial_register(dev, id);
635 if (err) {
636 int i;
637 for (i = 0; i < priv->num_par; i++)
638 parport_pc_unregister_port (priv->port[i]);
639 return err;
640 }
641
642 return 0;
643 }
644
645 static void parport_serial_pci_remove(struct pci_dev *dev)
646 {
647 struct parport_serial_private *priv = pci_get_drvdata (dev);
648 int i;
649
650 // Serial ports
651 if (priv->serial)
652 pciserial_remove_ports(priv->serial);
653
654 // Parallel ports
655 for (i = 0; i < priv->num_par; i++)
656 parport_pc_unregister_port (priv->port[i]);
657
658 return;
659 }
660
661 static int __maybe_unused parport_serial_pci_suspend(struct device *dev)
662 {
663 struct pci_dev *pdev = to_pci_dev(dev);
664 struct parport_serial_private *priv = pci_get_drvdata(pdev);
665
666 if (priv->serial)
667 pciserial_suspend_ports(priv->serial);
668
669 /* FIXME: What about parport? */
670 return 0;
671 }
672
673 static int __maybe_unused parport_serial_pci_resume(struct device *dev)
674 {
675 struct pci_dev *pdev = to_pci_dev(dev);
676 struct parport_serial_private *priv = pci_get_drvdata(pdev);
677
678 if (priv->serial)
679 pciserial_resume_ports(priv->serial);
680
681 /* FIXME: What about parport? */
682 return 0;
683 }
684
685 static SIMPLE_DEV_PM_OPS(parport_serial_pm_ops,
686 parport_serial_pci_suspend, parport_serial_pci_resume);
687
688 static struct pci_driver parport_serial_pci_driver = {
689 .name = "parport_serial",
690 .id_table = parport_serial_pci_tbl,
691 .probe = parport_serial_pci_probe,
692 .remove = parport_serial_pci_remove,
693 .driver = {
694 .pm = &parport_serial_pm_ops,
695 },
696 };
697 module_pci_driver(parport_serial_pci_driver);
698
699 MODULE_AUTHOR("Tim Waugh <twaugh@redhat.com>");
700 MODULE_DESCRIPTION("Driver for common parallel+serial multi-I/O PCI cards");
701 MODULE_LICENSE("GPL");
Linux with added FPC-III support