drivers/mmc/host/dw_mmc.h

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #ifndef _DW_MMC_H_
  15 #define _DW_MMC_H_
  16
  17 #define DW_MMC_240A             0x240a
  18
  19 #define SDMMC_CTRL              0x000
  20 #define SDMMC_PWREN             0x004
  21 #define SDMMC_CLKDIV            0x008
  22 #define SDMMC_CLKSRC            0x00c
  23 #define SDMMC_CLKENA            0x010
  24 #define SDMMC_TMOUT             0x014
  25 #define SDMMC_CTYPE             0x018
  26 #define SDMMC_BLKSIZ            0x01c
  27 #define SDMMC_BYTCNT            0x020
  28 #define SDMMC_INTMASK           0x024
  29 #define SDMMC_CMDARG            0x028
  30 #define SDMMC_CMD               0x02c
  31 #define SDMMC_RESP0             0x030
  32 #define SDMMC_RESP1             0x034
  33 #define SDMMC_RESP2             0x038
  34 #define SDMMC_RESP3             0x03c
  35 #define SDMMC_MINTSTS           0x040
  36 #define SDMMC_RINTSTS           0x044
  37 #define SDMMC_STATUS            0x048
  38 #define SDMMC_FIFOTH            0x04c
  39 #define SDMMC_CDETECT           0x050
  40 #define SDMMC_WRTPRT            0x054
  41 #define SDMMC_GPIO              0x058
  42 #define SDMMC_TCBCNT            0x05c
  43 #define SDMMC_TBBCNT            0x060
  44 #define SDMMC_DEBNCE            0x064
  45 #define SDMMC_USRID             0x068
  46 #define SDMMC_VERID             0x06c
  47 #define SDMMC_HCON              0x070
  48 #define SDMMC_UHS_REG           0x074
  49 #define SDMMC_BMOD              0x080
  50 #define SDMMC_PLDMND            0x084
  51 #define SDMMC_DBADDR            0x088
  52 #define SDMMC_IDSTS             0x08c
  53 #define SDMMC_IDINTEN           0x090
  54 #define SDMMC_DSCADDR           0x094
  55 #define SDMMC_BUFADDR           0x098
  56 #define SDMMC_DATA(x)           (x)
  57
  58 /*
  59  * Data offset is difference according to Version
  60  * Lower than 2.40a : data register offest is 0x100
  61  */
  62 #define DATA_OFFSET             0x100
  63 #define DATA_240A_OFFSET        0x200
  64
  65 /* shift bit field */
  66 #define _SBF(f, v)              ((v) << (f))
  67
  68 /* Control register defines */
  69 #define SDMMC_CTRL_USE_IDMAC            BIT(25)
  70 #define SDMMC_CTRL_CEATA_INT_EN         BIT(11)
  71 #define SDMMC_CTRL_SEND_AS_CCSD         BIT(10)
  72 #define SDMMC_CTRL_SEND_CCSD            BIT(9)
  73 #define SDMMC_CTRL_ABRT_READ_DATA       BIT(8)
  74 #define SDMMC_CTRL_SEND_IRQ_RESP        BIT(7)
  75 #define SDMMC_CTRL_READ_WAIT            BIT(6)
  76 #define SDMMC_CTRL_DMA_ENABLE           BIT(5)
  77 #define SDMMC_CTRL_INT_ENABLE           BIT(4)
  78 #define SDMMC_CTRL_DMA_RESET            BIT(2)
  79 #define SDMMC_CTRL_FIFO_RESET           BIT(1)
  80 #define SDMMC_CTRL_RESET                BIT(0)
  81 /* Clock Enable register defines */
  82 #define SDMMC_CLKEN_LOW_PWR             BIT(16)
  83 #define SDMMC_CLKEN_ENABLE              BIT(0)
  84 /* time-out register defines */
  85 #define SDMMC_TMOUT_DATA(n)             _SBF(8, (n))
  86 #define SDMMC_TMOUT_DATA_MSK            0xFFFFFF00
  87 #define SDMMC_TMOUT_RESP(n)             ((n) & 0xFF)
  88 #define SDMMC_TMOUT_RESP_MSK            0xFF
  89 /* card-type register defines */
  90 #define SDMMC_CTYPE_8BIT                BIT(16)
  91 #define SDMMC_CTYPE_4BIT                BIT(0)
  92 #define SDMMC_CTYPE_1BIT                0
  93 /* Interrupt status & mask register defines */
  94 #define SDMMC_INT_SDIO(n)               BIT(16 + (n))
  95 #define SDMMC_INT_EBE                   BIT(15)
  96 #define SDMMC_INT_ACD                   BIT(14)
  97 #define SDMMC_INT_SBE                   BIT(13)
  98 #define SDMMC_INT_HLE                   BIT(12)
  99 #define SDMMC_INT_FRUN                  BIT(11)
 100 #define SDMMC_INT_HTO                   BIT(10)
 101 #define SDMMC_INT_DTO                   BIT(9)
 102 #define SDMMC_INT_RTO                   BIT(8)
 103 #define SDMMC_INT_DCRC                  BIT(7)
 104 #define SDMMC_INT_RCRC                  BIT(6)
 105 #define SDMMC_INT_RXDR                  BIT(5)
 106 #define SDMMC_INT_TXDR                  BIT(4)
 107 #define SDMMC_INT_DATA_OVER             BIT(3)
 108 #define SDMMC_INT_CMD_DONE              BIT(2)
 109 #define SDMMC_INT_RESP_ERR              BIT(1)
 110 #define SDMMC_INT_CD                    BIT(0)
 111 #define SDMMC_INT_ERROR                 0xbfc2
 112 /* Command register defines */
 113 #define SDMMC_CMD_START                 BIT(31)
 114 #define SDMMC_CMD_CCS_EXP               BIT(23)
 115 #define SDMMC_CMD_CEATA_RD              BIT(22)
 116 #define SDMMC_CMD_UPD_CLK               BIT(21)
 117 #define SDMMC_CMD_INIT                  BIT(15)
 118 #define SDMMC_CMD_STOP                  BIT(14)
 119 #define SDMMC_CMD_PRV_DAT_WAIT          BIT(13)
 120 #define SDMMC_CMD_SEND_STOP             BIT(12)
 121 #define SDMMC_CMD_STRM_MODE             BIT(11)
 122 #define SDMMC_CMD_DAT_WR                BIT(10)
 123 #define SDMMC_CMD_DAT_EXP               BIT(9)
 124 #define SDMMC_CMD_RESP_CRC              BIT(8)
 125 #define SDMMC_CMD_RESP_LONG             BIT(7)
 126 #define SDMMC_CMD_RESP_EXP              BIT(6)
 127 #define SDMMC_CMD_INDX(n)               ((n) & 0x1F)
 128 /* Status register defines */
 129 #define SDMMC_GET_FCNT(x)               (((x)>>17) & 0x1FFF)
 130 /* Internal DMAC interrupt defines */
 131 #define SDMMC_IDMAC_INT_AI              BIT(9)
 132 #define SDMMC_IDMAC_INT_NI              BIT(8)
 133 #define SDMMC_IDMAC_INT_CES             BIT(5)
 134 #define SDMMC_IDMAC_INT_DU              BIT(4)
 135 #define SDMMC_IDMAC_INT_FBE             BIT(2)
 136 #define SDMMC_IDMAC_INT_RI              BIT(1)
 137 #define SDMMC_IDMAC_INT_TI              BIT(0)
 138 /* Internal DMAC bus mode bits */
 139 #define SDMMC_IDMAC_ENABLE              BIT(7)
 140 #define SDMMC_IDMAC_FB                  BIT(1)
 141 #define SDMMC_IDMAC_SWRESET             BIT(0)
 142 /* Version ID register define */
 143 #define SDMMC_GET_VERID(x)              ((x) & 0xFFFF)
 144
 145 /* Register access macros */
 146 #define mci_readl(dev, reg)                     \
 147         __raw_readl((dev)->regs + SDMMC_##reg)
 148 #define mci_writel(dev, reg, value)                     \
 149         __raw_writel((value), (dev)->regs + SDMMC_##reg)
 150
 151 /* 16-bit FIFO access macros */
 152 #define mci_readw(dev, reg)                     \
 153         __raw_readw((dev)->regs + SDMMC_##reg)
 154 #define mci_writew(dev, reg, value)                     \
 155         __raw_writew((value), (dev)->regs + SDMMC_##reg)
 156
 157 /* 64-bit FIFO access macros */
 158 #ifdef readq
 159 #define mci_readq(dev, reg)                     \
 160         __raw_readq((dev)->regs + SDMMC_##reg)
 161 #define mci_writeq(dev, reg, value)                     \
 162         __raw_writeq((value), (dev)->regs + SDMMC_##reg)
 163 #else
 164 /*
 165  * Dummy readq implementation for architectures that don't define it.
 166  *
 167  * We would assume that none of these architectures would configure
 168  * the IP block with a 64bit FIFO width, so this code will never be
 169  * executed on those machines. Defining these macros here keeps the
 170  * rest of the code free from ifdefs.
 171  */
 172 #define mci_readq(dev, reg)                     \
 173         (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
 174 #define mci_writeq(dev, reg, value)                     \
 175         (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
 176 #endif
 177
 178 extern int dw_mci_probe(struct dw_mci *host);
 179 extern void dw_mci_remove(struct dw_mci *host);
 180 #ifdef CONFIG_PM
 181 extern int dw_mci_suspend(struct dw_mci *host);
 182 extern int dw_mci_resume(struct dw_mci *host);
 183 #endif
 184
 185 /**
 186  * dw_mci driver data - dw-mshc implementation specific driver data.
 187  * @caps: mmc subsystem specified capabilities of the controller(s).
 188  * @init: early implementation specific initialization.
 189  * @setup_clock: implementation specific clock configuration.
 190  * @prepare_command: handle CMD register extensions.
 191  * @set_ios: handle bus specific extensions.
 192  * @parse_dt: parse implementation specific device tree properties.
 193  * @setup_bus: initialize io-interface
 194  *
 195  * Provide controller implementation specific extensions. The usage of this
 196  * data structure is fully optional and usage of each member in this structure
 197  * is optional as well.
 198  */
 199 struct dw_mci_drv_data {
 200         unsigned long   *caps;
 201         int             (*init)(struct dw_mci *host);
 202         int             (*setup_clock)(struct dw_mci *host);
 203         void            (*prepare_command)(struct dw_mci *host, u32 *cmdr);
 204         void            (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
 205         int             (*parse_dt)(struct dw_mci *host);
 206         int             (*setup_bus)(struct dw_mci *host,
 207                                 struct device_node *slot_np, u8 bus_width);
 208 };
 209 #endif /* _DW_MMC_H_ */