drivers/mmc/host/sdhci-tegra.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_gpio.h>
  24 #include <linux/gpio.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/mmc/host.h>
  27
  28 #include <asm/gpio.h>
  29
  30 #include <linux/platform_data/mmc-sdhci-tegra.h>
  31
  32 #include "sdhci-pltfm.h"
  33
  34 /* Tegra SDHOST controller vendor register definitions */
  35 #define SDHCI_TEGRA_VENDOR_MISC_CTRL            0x120
  36 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300   0x20
  37
  38 #define NVQUIRK_FORCE_SDHCI_SPEC_200    BIT(0)
  39 #define NVQUIRK_ENABLE_BLOCK_GAP_DET    BIT(1)
  40 #define NVQUIRK_ENABLE_SDHCI_SPEC_300   BIT(2)
  41
  42 struct sdhci_tegra_soc_data {
  43         struct sdhci_pltfm_data *pdata;
  44         u32 nvquirks;
  45 };
  46
  47 struct sdhci_tegra {
  48         const struct tegra_sdhci_platform_data *plat;
  49         const struct sdhci_tegra_soc_data *soc_data;
  50 };
  51
  52 static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
  53 {
  54         u32 val;
  55
  56         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
  57                 /* Use wp_gpio here instead? */
  58                 val = readl(host->ioaddr + reg);
  59                 return val | SDHCI_WRITE_PROTECT;
  60         }
  61
  62         return readl(host->ioaddr + reg);
  63 }
  64
  65 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
  66 {
  67         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  68         struct sdhci_tegra *tegra_host = pltfm_host->priv;
  69         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  70
  71         if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
  72                         (reg == SDHCI_HOST_VERSION))) {
  73                 /* Erratum: Version register is invalid in HW. */
  74                 return SDHCI_SPEC_200;
  75         }
  76
  77         return readw(host->ioaddr + reg);
  78 }
  79
  80 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  81 {
  82         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  83         struct sdhci_tegra *tegra_host = pltfm_host->priv;
  84         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  85
  86         /* Seems like we're getting spurious timeout and crc errors, so
  87          * disable signalling of them. In case of real errors software
  88          * timers should take care of eventually detecting them.
  89          */
  90         if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
  91                 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
  92
  93         writel(val, host->ioaddr + reg);
  94
  95         if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
  96                         (reg == SDHCI_INT_ENABLE))) {
  97                 /* Erratum: Must enable block gap interrupt detection */
  98                 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  99                 if (val & SDHCI_INT_CARD_INT)
 100                         gap_ctrl |= 0x8;
 101                 else
 102                         gap_ctrl &= ~0x8;
 103                 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
 104         }
 105 }
 106
 107 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
 108 {
 109         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 110         struct sdhci_tegra *tegra_host = pltfm_host->priv;
 111         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
 112
 113         if (!gpio_is_valid(plat->wp_gpio))
 114                 return -1;
 115
 116         return gpio_get_value(plat->wp_gpio);
 117 }
 118
 119 static irqreturn_t carddetect_irq(int irq, void *data)
 120 {
 121         struct sdhci_host *sdhost = (struct sdhci_host *)data;
 122
 123         tasklet_schedule(&sdhost->card_tasklet);
 124         return IRQ_HANDLED;
 125 };
 126
 127 static void tegra_sdhci_reset_exit(struct sdhci_host *host, u8 mask)
 128 {
 129         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 130         struct sdhci_tegra *tegra_host = pltfm_host->priv;
 131         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 132
 133         if (!(mask & SDHCI_RESET_ALL))
 134                 return;
 135
 136         /* Erratum: Enable SDHCI spec v3.00 support */
 137         if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) {
 138                 u32 misc_ctrl;
 139
 140                 misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
 141                 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
 142                 sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
 143         }
 144 }
 145
 146 static int tegra_sdhci_8bit(struct sdhci_host *host, int bus_width)
 147 {
 148         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 149         struct sdhci_tegra *tegra_host = pltfm_host->priv;
 150         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
 151         u32 ctrl;
 152
 153         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 154         if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
 155                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 156                 ctrl |= SDHCI_CTRL_8BITBUS;
 157         } else {
 158                 ctrl &= ~SDHCI_CTRL_8BITBUS;
 159                 if (bus_width == MMC_BUS_WIDTH_4)
 160                         ctrl |= SDHCI_CTRL_4BITBUS;
 161                 else
 162                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 163         }
 164         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 165         return 0;
 166 }
 167
 168 static struct sdhci_ops tegra_sdhci_ops = {
 169         .get_ro     = tegra_sdhci_get_ro,
 170         .read_l     = tegra_sdhci_readl,
 171         .read_w     = tegra_sdhci_readw,
 172         .write_l    = tegra_sdhci_writel,
 173         .platform_8bit_width = tegra_sdhci_8bit,
 174         .platform_reset_exit = tegra_sdhci_reset_exit,
 175 };
 176
 177 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 178 static struct sdhci_pltfm_data sdhci_tegra20_pdata = {
 179         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 180                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
 181                   SDHCI_QUIRK_NO_HISPD_BIT |
 182                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
 183         .ops  = &tegra_sdhci_ops,
 184 };
 185
 186 static struct sdhci_tegra_soc_data soc_data_tegra20 = {
 187         .pdata = &sdhci_tegra20_pdata,
 188         .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
 189                     NVQUIRK_ENABLE_BLOCK_GAP_DET,
 190 };
 191 #endif
 192
 193 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 194 static struct sdhci_pltfm_data sdhci_tegra30_pdata = {
 195         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 196                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 197                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
 198                   SDHCI_QUIRK_NO_HISPD_BIT |
 199                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
 200         .ops  = &tegra_sdhci_ops,
 201 };
 202
 203 static struct sdhci_tegra_soc_data soc_data_tegra30 = {
 204         .pdata = &sdhci_tegra30_pdata,
 205         .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300,
 206 };
 207 #endif
 208
 209 static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = {
 210 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 211         { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
 212 #endif
 213 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 214         { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
 215 #endif
 216         {}
 217 };
 218 MODULE_DEVICE_TABLE(of, sdhci_dt_ids);
 219
 220 static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata(
 221                                                 struct platform_device *pdev)
 222 {
 223         struct tegra_sdhci_platform_data *plat;
 224         struct device_node *np = pdev->dev.of_node;
 225         u32 bus_width;
 226
 227         if (!np)
 228                 return NULL;
 229
 230         plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
 231         if (!plat) {
 232                 dev_err(&pdev->dev, "Can't allocate platform data\n");
 233                 return NULL;
 234         }
 235
 236         plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
 237         plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
 238         plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
 239
 240         if (of_property_read_u32(np, "bus-width", &bus_width) == 0 &&
 241             bus_width == 8)
 242                 plat->is_8bit = 1;
 243
 244         return plat;
 245 }
 246
 247 static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
 248 {
 249         const struct of_device_id *match;
 250         const struct sdhci_tegra_soc_data *soc_data;
 251         struct sdhci_host *host;
 252         struct sdhci_pltfm_host *pltfm_host;
 253         struct tegra_sdhci_platform_data *plat;
 254         struct sdhci_tegra *tegra_host;
 255         struct clk *clk;
 256         int rc;
 257
 258         match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
 259         if (!match)
 260                 return -EINVAL;
 261         soc_data = match->data;
 262
 263         host = sdhci_pltfm_init(pdev, soc_data->pdata);
 264         if (IS_ERR(host))
 265                 return PTR_ERR(host);
 266
 267         pltfm_host = sdhci_priv(host);
 268
 269         plat = pdev->dev.platform_data;
 270
 271         if (plat == NULL)
 272                 plat = sdhci_tegra_dt_parse_pdata(pdev);
 273
 274         if (plat == NULL) {
 275                 dev_err(mmc_dev(host->mmc), "missing platform data\n");
 276                 rc = -ENXIO;
 277                 goto err_no_plat;
 278         }
 279
 280         tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
 281         if (!tegra_host) {
 282                 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
 283                 rc = -ENOMEM;
 284                 goto err_no_plat;
 285         }
 286
 287         tegra_host->plat = plat;
 288         tegra_host->soc_data = soc_data;
 289
 290         pltfm_host->priv = tegra_host;
 291
 292         if (gpio_is_valid(plat->power_gpio)) {
 293                 rc = gpio_request(plat->power_gpio, "sdhci_power");
 294                 if (rc) {
 295                         dev_err(mmc_dev(host->mmc),
 296                                 "failed to allocate power gpio\n");
 297                         goto err_power_req;
 298                 }
 299                 gpio_direction_output(plat->power_gpio, 1);
 300         }
 301
 302         if (gpio_is_valid(plat->cd_gpio)) {
 303                 rc = gpio_request(plat->cd_gpio, "sdhci_cd");
 304                 if (rc) {
 305                         dev_err(mmc_dev(host->mmc),
 306                                 "failed to allocate cd gpio\n");
 307                         goto err_cd_req;
 308                 }
 309                 gpio_direction_input(plat->cd_gpio);
 310
 311                 rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
 312                                  IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
 313                                  mmc_hostname(host->mmc), host);
 314
 315                 if (rc) {
 316                         dev_err(mmc_dev(host->mmc), "request irq error\n");
 317                         goto err_cd_irq_req;
 318                 }
 319
 320         }
 321
 322         if (gpio_is_valid(plat->wp_gpio)) {
 323                 rc = gpio_request(plat->wp_gpio, "sdhci_wp");
 324                 if (rc) {
 325                         dev_err(mmc_dev(host->mmc),
 326                                 "failed to allocate wp gpio\n");
 327                         goto err_wp_req;
 328                 }
 329                 gpio_direction_input(plat->wp_gpio);
 330         }
 331
 332         clk = clk_get(mmc_dev(host->mmc), NULL);
 333         if (IS_ERR(clk)) {
 334                 dev_err(mmc_dev(host->mmc), "clk err\n");
 335                 rc = PTR_ERR(clk);
 336                 goto err_clk_get;
 337         }
 338         clk_prepare_enable(clk);
 339         pltfm_host->clk = clk;
 340
 341         host->mmc->pm_caps = plat->pm_flags;
 342
 343         if (plat->is_8bit)
 344                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 345
 346         rc = sdhci_add_host(host);
 347         if (rc)
 348                 goto err_add_host;
 349
 350         return 0;
 351
 352 err_add_host:
 353         clk_disable_unprepare(pltfm_host->clk);
 354         clk_put(pltfm_host->clk);
 355 err_clk_get:
 356         if (gpio_is_valid(plat->wp_gpio))
 357                 gpio_free(plat->wp_gpio);
 358 err_wp_req:
 359         if (gpio_is_valid(plat->cd_gpio))
 360                 free_irq(gpio_to_irq(plat->cd_gpio), host);
 361 err_cd_irq_req:
 362         if (gpio_is_valid(plat->cd_gpio))
 363                 gpio_free(plat->cd_gpio);
 364 err_cd_req:
 365         if (gpio_is_valid(plat->power_gpio))
 366                 gpio_free(plat->power_gpio);
 367 err_power_req:
 368 err_no_plat:
 369         sdhci_pltfm_free(pdev);
 370         return rc;
 371 }
 372
 373 static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
 374 {
 375         struct sdhci_host *host = platform_get_drvdata(pdev);
 376         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 377         struct sdhci_tegra *tegra_host = pltfm_host->priv;
 378         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
 379         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
 380
 381         sdhci_remove_host(host, dead);
 382
 383         if (gpio_is_valid(plat->wp_gpio))
 384                 gpio_free(plat->wp_gpio);
 385
 386         if (gpio_is_valid(plat->cd_gpio)) {
 387                 free_irq(gpio_to_irq(plat->cd_gpio), host);
 388                 gpio_free(plat->cd_gpio);
 389         }
 390
 391         if (gpio_is_valid(plat->power_gpio))
 392                 gpio_free(plat->power_gpio);
 393
 394         clk_disable_unprepare(pltfm_host->clk);
 395         clk_put(pltfm_host->clk);
 396
 397         sdhci_pltfm_free(pdev);
 398
 399         return 0;
 400 }
 401
 402 static struct platform_driver sdhci_tegra_driver = {
 403         .driver         = {
 404                 .name   = "sdhci-tegra",
 405                 .owner  = THIS_MODULE,
 406                 .of_match_table = sdhci_tegra_dt_match,
 407                 .pm     = SDHCI_PLTFM_PMOPS,
 408         },
 409         .probe          = sdhci_tegra_probe,
 410         .remove         = __devexit_p(sdhci_tegra_remove),
 411 };
 412
 413 module_platform_driver(sdhci_tegra_driver);
 414
 415 MODULE_DESCRIPTION("SDHCI driver for Tegra");
 416 MODULE_AUTHOR("Google, Inc.");
 417 MODULE_LICENSE("GPL v2");