sound/soc/codecs/tlv320aic3x.h

   1 /*
   2  * ALSA SoC TLV320AIC3X codec driver
   3  *
   4  * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
   5  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #ifndef _AIC3X_H
  13 #define _AIC3X_H
  14
  15 /* AIC3X register space */
  16 #define AIC3X_CACHEREGNUM               103
  17
  18 /* Page select register */
  19 #define AIC3X_PAGE_SELECT               0
  20 /* Software reset register */
  21 #define AIC3X_RESET                     1
  22 /* Codec Sample rate select register */
  23 #define AIC3X_SAMPLE_RATE_SEL_REG       2
  24 /* PLL progrramming register A */
  25 #define AIC3X_PLL_PROGA_REG             3
  26 /* PLL progrramming register B */
  27 #define AIC3X_PLL_PROGB_REG             4
  28 /* PLL progrramming register C */
  29 #define AIC3X_PLL_PROGC_REG             5
  30 /* PLL progrramming register D */
  31 #define AIC3X_PLL_PROGD_REG             6
  32 /* Codec datapath setup register */
  33 #define AIC3X_CODEC_DATAPATH_REG        7
  34 /* Audio serial data interface control register A */
  35 #define AIC3X_ASD_INTF_CTRLA            8
  36 /* Audio serial data interface control register B */
  37 #define AIC3X_ASD_INTF_CTRLB            9
  38 /* Audio serial data interface control register C */
  39 #define AIC3X_ASD_INTF_CTRLC            10
  40 /* Audio overflow status and PLL R value programming register */
  41 #define AIC3X_OVRF_STATUS_AND_PLLR_REG  11
  42 /* Audio codec digital filter control register */
  43 #define AIC3X_CODEC_DFILT_CTRL          12
  44 /* Headset/button press detection register */
  45 #define AIC3X_HEADSET_DETECT_CTRL_A     13
  46 #define AIC3X_HEADSET_DETECT_CTRL_B     14
  47 /* ADC PGA Gain control registers */
  48 #define LADC_VOL                        15
  49 #define RADC_VOL                        16
  50 /* MIC3 control registers */
  51 #define MIC3LR_2_LADC_CTRL              17
  52 #define MIC3LR_2_RADC_CTRL              18
  53 /* Line1 Input control registers */
  54 #define LINE1L_2_LADC_CTRL              19
  55 #define LINE1R_2_LADC_CTRL              21
  56 #define LINE1R_2_RADC_CTRL              22
  57 #define LINE1L_2_RADC_CTRL              24
  58 /* Line2 Input control registers */
  59 #define LINE2L_2_LADC_CTRL              20
  60 #define LINE2R_2_RADC_CTRL              23
  61 /* MICBIAS Control Register */
  62 #define MICBIAS_CTRL                    25
  63
  64 /* AGC Control Registers A, B, C */
  65 #define LAGC_CTRL_A                     26
  66 #define LAGC_CTRL_B                     27
  67 #define LAGC_CTRL_C                     28
  68 #define RAGC_CTRL_A                     29
  69 #define RAGC_CTRL_B                     30
  70 #define RAGC_CTRL_C                     31
  71
  72 /* DAC Power and Left High Power Output control registers */
  73 #define DAC_PWR                         37
  74 #define HPLCOM_CFG                      37
  75 /* Right High Power Output control registers */
  76 #define HPRCOM_CFG                      38
  77 /* DAC Output Switching control registers */
  78 #define DAC_LINE_MUX                    41
  79 /* High Power Output Driver Pop Reduction registers */
  80 #define HPOUT_POP_REDUCTION             42
  81 /* DAC Digital control registers */
  82 #define LDAC_VOL                        43
  83 #define RDAC_VOL                        44
  84 /* Left High Power Output control registers */
  85 #define LINE2L_2_HPLOUT_VOL             45
  86 #define PGAL_2_HPLOUT_VOL               46
  87 #define DACL1_2_HPLOUT_VOL              47
  88 #define LINE2R_2_HPLOUT_VOL             48
  89 #define PGAR_2_HPLOUT_VOL               49
  90 #define DACR1_2_HPLOUT_VOL              50
  91 #define HPLOUT_CTRL                     51
  92 /* Left High Power COM control registers */
  93 #define LINE2L_2_HPLCOM_VOL             52
  94 #define PGAL_2_HPLCOM_VOL               53
  95 #define DACL1_2_HPLCOM_VOL              54
  96 #define LINE2R_2_HPLCOM_VOL             55
  97 #define PGAR_2_HPLCOM_VOL               56
  98 #define DACR1_2_HPLCOM_VOL              57
  99 #define HPLCOM_CTRL                     58
 100 /* Right High Power Output control registers */
 101 #define LINE2L_2_HPROUT_VOL             59
 102 #define PGAL_2_HPROUT_VOL               60
 103 #define DACL1_2_HPROUT_VOL              61
 104 #define LINE2R_2_HPROUT_VOL             62
 105 #define PGAR_2_HPROUT_VOL               63
 106 #define DACR1_2_HPROUT_VOL              64
 107 #define HPROUT_CTRL                     65
 108 /* Right High Power COM control registers */
 109 #define LINE2L_2_HPRCOM_VOL             66
 110 #define PGAL_2_HPRCOM_VOL               67
 111 #define DACL1_2_HPRCOM_VOL              68
 112 #define LINE2R_2_HPRCOM_VOL             69
 113 #define PGAR_2_HPRCOM_VOL               70
 114 #define DACR1_2_HPRCOM_VOL              71
 115 #define HPRCOM_CTRL                     72
 116 /* Mono Line Output Plus/Minus control registers */
 117 #define LINE2L_2_MONOLOPM_VOL           73
 118 #define PGAL_2_MONOLOPM_VOL             74
 119 #define DACL1_2_MONOLOPM_VOL            75
 120 #define LINE2R_2_MONOLOPM_VOL           76
 121 #define PGAR_2_MONOLOPM_VOL             77
 122 #define DACR1_2_MONOLOPM_VOL            78
 123 #define MONOLOPM_CTRL                   79
 124 /* Class-D speaker driver on tlv320aic3007 */
 125 #define CLASSD_CTRL                     73
 126 /* Left Line Output Plus/Minus control registers */
 127 #define LINE2L_2_LLOPM_VOL              80
 128 #define PGAL_2_LLOPM_VOL                81
 129 #define DACL1_2_LLOPM_VOL               82
 130 #define LINE2R_2_LLOPM_VOL              83
 131 #define PGAR_2_LLOPM_VOL                84
 132 #define DACR1_2_LLOPM_VOL               85
 133 #define LLOPM_CTRL                      86
 134 /* Right Line Output Plus/Minus control registers */
 135 #define LINE2L_2_RLOPM_VOL              87
 136 #define PGAL_2_RLOPM_VOL                88
 137 #define DACL1_2_RLOPM_VOL               89
 138 #define LINE2R_2_RLOPM_VOL              90
 139 #define PGAR_2_RLOPM_VOL                91
 140 #define DACR1_2_RLOPM_VOL               92
 141 #define RLOPM_CTRL                      93
 142 /* GPIO/IRQ registers */
 143 #define AIC3X_STICKY_IRQ_FLAGS_REG      96
 144 #define AIC3X_RT_IRQ_FLAGS_REG          97
 145 #define AIC3X_GPIO1_REG                 98
 146 #define AIC3X_GPIO2_REG                 99
 147 #define AIC3X_GPIOA_REG                 100
 148 #define AIC3X_GPIOB_REG                 101
 149 /* Clock generation control register */
 150 #define AIC3X_CLKGEN_CTRL_REG           102
 151
 152 /* Page select register bits */
 153 #define PAGE0_SELECT            0
 154 #define PAGE1_SELECT            1
 155
 156 /* Audio serial data interface control register A bits */
 157 #define BIT_CLK_MASTER          0x80
 158 #define WORD_CLK_MASTER         0x40
 159
 160 /* Codec Datapath setup register 7 */
 161 #define FSREF_44100             (1 << 7)
 162 #define FSREF_48000             (0 << 7)
 163 #define DUAL_RATE_MODE          ((1 << 5) | (1 << 6))
 164 #define LDAC2LCH                (0x1 << 3)
 165 #define RDAC2RCH                (0x1 << 1)
 166
 167 /* PLL registers bitfields */
 168 #define PLLP_SHIFT              0
 169 #define PLLQ_SHIFT              3
 170 #define PLLR_SHIFT              0
 171 #define PLLJ_SHIFT              2
 172 #define PLLD_MSB_SHIFT          0
 173 #define PLLD_LSB_SHIFT          2
 174
 175 /* Clock generation register bits */
 176 #define CODEC_CLKIN_PLLDIV      0
 177 #define CODEC_CLKIN_CLKDIV      1
 178 #define PLL_CLKIN_SHIFT         4
 179 #define MCLK_SOURCE             0x0
 180 #define PLL_CLKDIV_SHIFT        0
 181
 182 /* Software reset register bits */
 183 #define SOFT_RESET              0x80
 184
 185 /* PLL progrramming register A bits */
 186 #define PLL_ENABLE              0x80
 187
 188 /* Route bits */
 189 #define ROUTE_ON                0x80
 190
 191 /* Mute bits */
 192 #define UNMUTE                  0x08
 193 #define MUTE_ON                 0x80
 194
 195 /* Power bits */
 196 #define LADC_PWR_ON             0x04
 197 #define RADC_PWR_ON             0x04
 198 #define LDAC_PWR_ON             0x80
 199 #define RDAC_PWR_ON             0x40
 200 #define HPLOUT_PWR_ON           0x01
 201 #define HPROUT_PWR_ON           0x01
 202 #define HPLCOM_PWR_ON           0x01
 203 #define HPRCOM_PWR_ON           0x01
 204 #define MONOLOPM_PWR_ON         0x01
 205 #define LLOPM_PWR_ON            0x01
 206 #define RLOPM_PWR_ON    0x01
 207
 208 #define INVERT_VOL(val)   (0x7f - val)
 209
 210 /* Default output volume (inverted) */
 211 #define DEFAULT_VOL     INVERT_VOL(0x50)
 212 /* Default input volume */
 213 #define DEFAULT_GAIN    0x20
 214
 215 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
 216 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
 217
 218 /* headset detection / button API */
 219
 220 /* The AIC3x supports detection of stereo headsets (GND + left + right signal)
 221  * and cellular headsets (GND + speaker output + microphone input).
 222  * It is recommended to enable MIC bias for this function to work properly.
 223  * For more information, please refer to the datasheet. */
 224 enum {
 225         AIC3X_HEADSET_DETECT_OFF        = 0,
 226         AIC3X_HEADSET_DETECT_STEREO     = 1,
 227         AIC3X_HEADSET_DETECT_CELLULAR   = 2,
 228         AIC3X_HEADSET_DETECT_BOTH       = 3
 229 };
 230
 231 enum {
 232         AIC3X_HEADSET_DEBOUNCE_16MS     = 0,
 233         AIC3X_HEADSET_DEBOUNCE_32MS     = 1,
 234         AIC3X_HEADSET_DEBOUNCE_64MS     = 2,
 235         AIC3X_HEADSET_DEBOUNCE_128MS    = 3,
 236         AIC3X_HEADSET_DEBOUNCE_256MS    = 4,
 237         AIC3X_HEADSET_DEBOUNCE_512MS    = 5
 238 };
 239
 240 enum {
 241         AIC3X_BUTTON_DEBOUNCE_0MS       = 0,
 242         AIC3X_BUTTON_DEBOUNCE_8MS       = 1,
 243         AIC3X_BUTTON_DEBOUNCE_16MS      = 2,
 244         AIC3X_BUTTON_DEBOUNCE_32MS      = 3
 245 };
 246
 247 #define AIC3X_HEADSET_DETECT_ENABLED    0x80
 248 #define AIC3X_HEADSET_DETECT_SHIFT      5
 249 #define AIC3X_HEADSET_DETECT_MASK       3
 250 #define AIC3X_HEADSET_DEBOUNCE_SHIFT    2
 251 #define AIC3X_HEADSET_DEBOUNCE_MASK     7
 252 #define AIC3X_BUTTON_DEBOUNCE_SHIFT     0
 253 #define AIC3X_BUTTON_DEBOUNCE_MASK      3
 254
 255 /* see the enums above for valid parameters to this function */
 256 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
 257                                  int headset_debounce, int button_debounce);
 258 int aic3x_headset_detected(struct snd_soc_codec *codec);
 259 int aic3x_button_pressed(struct snd_soc_codec *codec);
 260
 261 #endif /* _AIC3X_H */