arch/powerpc/include/asm/nohash/32/pte-fsl-booke.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H
   3 #define _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H
   4 #ifdef __KERNEL__
   5
   6 /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
   7  * processors
   8  *
   9    MMU Assist Register 3:
  10
  11    32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
  12    RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
  13
  14    - PRESENT *must* be in the bottom three bits because swap cache
  15      entries use the top 29 bits.
  16
  17 */
  18
  19 /* Definitions for FSL Book-E Cores */
  20 #define _PAGE_PRESENT   0x00001 /* S: PTE contains a translation */
  21 #define _PAGE_USER      0x00002 /* S: User page (maps to UR) */
  22 #define _PAGE_RW        0x00004 /* S: Write permission (SW) */
  23 #define _PAGE_DIRTY     0x00008 /* S: Page dirty */
  24 #define _PAGE_EXEC      0x00010 /* H: SX permission */
  25 #define _PAGE_ACCESSED  0x00020 /* S: Page referenced */
  26
  27 #define _PAGE_ENDIAN    0x00040 /* H: E bit */
  28 #define _PAGE_GUARDED   0x00080 /* H: G bit */
  29 #define _PAGE_COHERENT  0x00100 /* H: M bit */
  30 #define _PAGE_NO_CACHE  0x00200 /* H: I bit */
  31 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
  32 #define _PAGE_SPECIAL   0x00800 /* S: Special page */
  33
  34 #define _PAGE_KERNEL_RO         0
  35 #define _PAGE_KERNEL_ROX        _PAGE_EXEC
  36 #define _PAGE_KERNEL_RW         (_PAGE_DIRTY | _PAGE_RW)
  37 #define _PAGE_KERNEL_RWX        (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
  38
  39 /* No page size encoding in the linux PTE */
  40 #define _PAGE_PSIZE             0
  41
  42 #define _PMD_PRESENT    0
  43 #define _PMD_PRESENT_MASK (PAGE_MASK)
  44 #define _PMD_BAD        (~PAGE_MASK)
  45 #define _PMD_USER       0
  46
  47 #define _PTE_NONE_MASK  0
  48
  49 #define PTE_WIMGE_SHIFT (6)
  50
  51 /*
  52  * We define 2 sets of base prot bits, one for basic pages (ie,
  53  * cacheable kernel and user pages) and one for non cacheable
  54  * pages. We always set _PAGE_COHERENT when SMP is enabled or
  55  * the processor might need it for DMA coherency.
  56  */
  57 #define _PAGE_BASE_NC   (_PAGE_PRESENT | _PAGE_ACCESSED)
  58 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
  59 #define _PAGE_BASE      (_PAGE_BASE_NC | _PAGE_COHERENT)
  60 #else
  61 #define _PAGE_BASE      (_PAGE_BASE_NC)
  62 #endif
  63
  64 /* Permission masks used to generate the __P and __S table */
  65 #define PAGE_NONE       __pgprot(_PAGE_BASE)
  66 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
  67 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
  68 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
  69 #define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
  70 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
  71 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
  72
  73 #endif /* __KERNEL__ */
  74 #endif /*  _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H */