drivers/clk/renesas/r8a7796-cpg-mssr.c

   1 /*
   2  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
   3  *
   4  * Copyright (C) 2016 Glider bvba
   5  *
   6  * Based on r8a7795-cpg-mssr.c
   7  *
   8  * Copyright (C) 2015 Glider bvba
   9  * Copyright (C) 2015 Renesas Electronics Corp.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; version 2 of the License.
  14  */
  15
  16 #include <linux/device.h>
  17 #include <linux/init.h>
  18 #include <linux/kernel.h>
  19
  20 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
  21
  22 #include "renesas-cpg-mssr.h"
  23 #include "rcar-gen3-cpg.h"
  24
  25 enum clk_ids {
  26         /* Core Clock Outputs exported to DT */
  27         LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
  28
  29         /* External Input Clocks */
  30         CLK_EXTAL,
  31         CLK_EXTALR,
  32
  33         /* Internal Core Clocks */
  34         CLK_MAIN,
  35         CLK_PLL0,
  36         CLK_PLL1,
  37         CLK_PLL2,
  38         CLK_PLL3,
  39         CLK_PLL4,
  40         CLK_PLL1_DIV2,
  41         CLK_PLL1_DIV4,
  42         CLK_S0,
  43         CLK_S1,
  44         CLK_S2,
  45         CLK_S3,
  46         CLK_SDSRC,
  47         CLK_SSPSRC,
  48         CLK_RINT,
  49
  50         /* Module Clocks */
  51         MOD_CLK_BASE
  52 };
  53
  54 static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
  55         /* External Clock Inputs */
  56         DEF_INPUT("extal",  CLK_EXTAL),
  57         DEF_INPUT("extalr", CLK_EXTALR),
  58
  59         /* Internal Core Clocks */
  60         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  61         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
  62         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  63         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
  64         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  65         DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
  66
  67         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
  68         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
  69         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
  70         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
  71         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
  72         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
  73         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
  74
  75         /* Core Clock Outputs */
  76         DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
  77         DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
  78         DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
  79         DEF_FIXED("zx",         R8A7796_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
  80         DEF_FIXED("s0d1",       R8A7796_CLK_S0D1,  CLK_S0,         1, 1),
  81         DEF_FIXED("s0d2",       R8A7796_CLK_S0D2,  CLK_S0,         2, 1),
  82         DEF_FIXED("s0d3",       R8A7796_CLK_S0D3,  CLK_S0,         3, 1),
  83         DEF_FIXED("s0d4",       R8A7796_CLK_S0D4,  CLK_S0,         4, 1),
  84         DEF_FIXED("s0d6",       R8A7796_CLK_S0D6,  CLK_S0,         6, 1),
  85         DEF_FIXED("s0d8",       R8A7796_CLK_S0D8,  CLK_S0,         8, 1),
  86         DEF_FIXED("s0d12",      R8A7796_CLK_S0D12, CLK_S0,        12, 1),
  87         DEF_FIXED("s1d1",       R8A7796_CLK_S1D1,  CLK_S1,         1, 1),
  88         DEF_FIXED("s1d2",       R8A7796_CLK_S1D2,  CLK_S1,         2, 1),
  89         DEF_FIXED("s1d4",       R8A7796_CLK_S1D4,  CLK_S1,         4, 1),
  90         DEF_FIXED("s2d1",       R8A7796_CLK_S2D1,  CLK_S2,         1, 1),
  91         DEF_FIXED("s2d2",       R8A7796_CLK_S2D2,  CLK_S2,         2, 1),
  92         DEF_FIXED("s2d4",       R8A7796_CLK_S2D4,  CLK_S2,         4, 1),
  93         DEF_FIXED("s3d1",       R8A7796_CLK_S3D1,  CLK_S3,         1, 1),
  94         DEF_FIXED("s3d2",       R8A7796_CLK_S3D2,  CLK_S3,         2, 1),
  95         DEF_FIXED("s3d4",       R8A7796_CLK_S3D4,  CLK_S3,         4, 1),
  96
  97         DEF_GEN3_SD("sd0",      R8A7796_CLK_SD0,   CLK_SDSRC,    0x0074),
  98         DEF_GEN3_SD("sd1",      R8A7796_CLK_SD1,   CLK_SDSRC,    0x0078),
  99         DEF_GEN3_SD("sd2",      R8A7796_CLK_SD2,   CLK_SDSRC,    0x0268),
 100         DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,    0x026c),
 101
 102         DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 103         DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),
 104
 105         DEF_DIV6_RO("osc",      R8A7796_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
 106         DEF_DIV6_RO("r_int",    CLK_RINT,          CLK_EXTAL, CPG_RCKCR, 32),
 107
 108         DEF_BASE("r",           R8A7796_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 109 };
 110
 111 static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
 112         DEF_MOD("cmt3",                  300,   R8A7796_CLK_R),
 113         DEF_MOD("cmt2",                  301,   R8A7796_CLK_R),
 114         DEF_MOD("cmt1",                  302,   R8A7796_CLK_R),
 115         DEF_MOD("cmt0",                  303,   R8A7796_CLK_R),
 116         DEF_MOD("scif2",                 310,   R8A7796_CLK_S3D4),
 117         DEF_MOD("sdif3",                 311,   R8A7796_CLK_SD3),
 118         DEF_MOD("sdif2",                 312,   R8A7796_CLK_SD2),
 119         DEF_MOD("sdif1",                 313,   R8A7796_CLK_SD1),
 120         DEF_MOD("sdif0",                 314,   R8A7796_CLK_SD0),
 121         DEF_MOD("rwdt0",                 402,   R8A7796_CLK_R),
 122         DEF_MOD("intc-ap",               408,   R8A7796_CLK_S3D1),
 123         DEF_MOD("thermal",               522,   R8A7796_CLK_CP),
 124         DEF_MOD("etheravb",              812,   R8A7796_CLK_S0D6),
 125         DEF_MOD("gpio7",                 905,   R8A7796_CLK_S3D4),
 126         DEF_MOD("gpio6",                 906,   R8A7796_CLK_S3D4),
 127         DEF_MOD("gpio5",                 907,   R8A7796_CLK_S3D4),
 128         DEF_MOD("gpio4",                 908,   R8A7796_CLK_S3D4),
 129         DEF_MOD("gpio3",                 909,   R8A7796_CLK_S3D4),
 130         DEF_MOD("gpio2",                 910,   R8A7796_CLK_S3D4),
 131         DEF_MOD("gpio1",                 911,   R8A7796_CLK_S3D4),
 132         DEF_MOD("gpio0",                 912,   R8A7796_CLK_S3D4),
 133 };
 134
 135 static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
 136         MOD_CLK_ID(408),        /* INTC-AP (GIC) */
 137 };
 138
 139
 140 /*
 141  * CPG Clock Data
 142  */
 143
 144 /*
 145  *   MD         EXTAL           PLL0    PLL1    PLL2    PLL3    PLL4
 146  * 14 13 19 17  (MHz)
 147  *-------------------------------------------------------------------
 148  * 0  0  0  0   16.66 x 1       x180    x192    x144    x192    x144
 149  * 0  0  0  1   16.66 x 1       x180    x192    x144    x128    x144
 150  * 0  0  1  0   Prohibited setting
 151  * 0  0  1  1   16.66 x 1       x180    x192    x144    x192    x144
 152  * 0  1  0  0   20    x 1       x150    x160    x120    x160    x120
 153  * 0  1  0  1   20    x 1       x150    x160    x120    x106    x120
 154  * 0  1  1  0   Prohibited setting
 155  * 0  1  1  1   20    x 1       x150    x160    x120    x160    x120
 156  * 1  0  0  0   25    x 1       x120    x128    x96     x128    x96
 157  * 1  0  0  1   25    x 1       x120    x128    x96     x84     x96
 158  * 1  0  1  0   Prohibited setting
 159  * 1  0  1  1   25    x 1       x120    x128    x96     x128    x96
 160  * 1  1  0  0   33.33 / 2       x180    x192    x144    x192    x144
 161  * 1  1  0  1   33.33 / 2       x180    x192    x144    x128    x144
 162  * 1  1  1  0   Prohibited setting
 163  * 1  1  1  1   33.33 / 2       x180    x192    x144    x192    x144
 164  */
 165 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 11) | \
 166                                          (((md) & BIT(13)) >> 11) | \
 167                                          (((md) & BIT(19)) >> 18) | \
 168                                          (((md) & BIT(17)) >> 17))
 169
 170 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
 171         /* EXTAL div    PLL1 mult       PLL3 mult */
 172         { 1,            192,            192,    },
 173         { 1,            192,            128,    },
 174         { 0, /* Prohibited setting */           },
 175         { 1,            192,            192,    },
 176         { 1,            160,            160,    },
 177         { 1,            160,            106,    },
 178         { 0, /* Prohibited setting */           },
 179         { 1,            160,            160,    },
 180         { 1,            128,            128,    },
 181         { 1,            128,            84,     },
 182         { 0, /* Prohibited setting */           },
 183         { 1,            128,            128,    },
 184         { 2,            192,            192,    },
 185         { 2,            192,            128,    },
 186         { 0, /* Prohibited setting */           },
 187         { 2,            192,            192,    },
 188 };
 189
 190 static int __init r8a7796_cpg_mssr_init(struct device *dev)
 191 {
 192         const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
 193         u32 cpg_mode = rcar_gen3_read_mode_pins();
 194
 195         cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 196         if (!cpg_pll_config->extal_div) {
 197                 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
 198                 return -EINVAL;
 199         }
 200
 201         return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR);
 202 }
 203
 204 const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = {
 205         /* Core Clocks */
 206         .core_clks = r8a7796_core_clks,
 207         .num_core_clks = ARRAY_SIZE(r8a7796_core_clks),
 208         .last_dt_core_clk = LAST_DT_CORE_CLK,
 209         .num_total_core_clks = MOD_CLK_BASE,
 210
 211         /* Module Clocks */
 212         .mod_clks = r8a7796_mod_clks,
 213         .num_mod_clks = ARRAY_SIZE(r8a7796_mod_clks),
 214         .num_hw_mod_clks = 12 * 32,
 215
 216         /* Critical Module Clocks */
 217         .crit_mod_clks = r8a7796_crit_mod_clks,
 218         .num_crit_mod_clks = ARRAY_SIZE(r8a7796_crit_mod_clks),
 219
 220         /* Callbacks */
 221         .init = r8a7796_cpg_mssr_init,
 222         .cpg_clk_register = rcar_gen3_cpg_clk_register,
 223 };