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perf bench futex: Cache align the worker struct
[linux/fpc-iii.git] / drivers / clk / tegra / clk-tegra114.c
blob933b5dd698b8cc86ddc924fd65aee483b53a2aec
1 /*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/io.h>
18 #include <linux/clk-provider.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/clk/tegra.h>
24 #include <dt-bindings/clock/tegra114-car.h>
25
26 #include "clk.h"
27 #include "clk-id.h"
28
29 #define RST_DFLL_DVCO 0x2F4
30 #define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */
31 #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
32 #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
33
34 /* RST_DFLL_DVCO bitfields */
35 #define DVFS_DFLL_RESET_SHIFT 0
36
37 /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
38 #define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */
39 #define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */
40 #define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */
41 #define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */
42 #define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */
43 #define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */
44
45 /* CPU_FINETRIM_R bitfields */
46 #define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */
47 #define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
48 #define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */
49 #define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
50 #define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */
51 #define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
52 #define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */
53 #define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
54 #define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */
55 #define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
56 #define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */
57 #define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
58
59 #define TEGRA114_CLK_PERIPH_BANKS 5
60
61 #define PLLC_BASE 0x80
62 #define PLLC_MISC2 0x88
63 #define PLLC_MISC 0x8c
64 #define PLLC2_BASE 0x4e8
65 #define PLLC2_MISC 0x4ec
66 #define PLLC3_BASE 0x4fc
67 #define PLLC3_MISC 0x500
68 #define PLLM_BASE 0x90
69 #define PLLM_MISC 0x9c
70 #define PLLP_BASE 0xa0
71 #define PLLP_MISC 0xac
72 #define PLLX_BASE 0xe0
73 #define PLLX_MISC 0xe4
74 #define PLLX_MISC2 0x514
75 #define PLLX_MISC3 0x518
76 #define PLLD_BASE 0xd0
77 #define PLLD_MISC 0xdc
78 #define PLLD2_BASE 0x4b8
79 #define PLLD2_MISC 0x4bc
80 #define PLLE_BASE 0xe8
81 #define PLLE_MISC 0xec
82 #define PLLA_BASE 0xb0
83 #define PLLA_MISC 0xbc
84 #define PLLU_BASE 0xc0
85 #define PLLU_MISC 0xcc
86 #define PLLRE_BASE 0x4c4
87 #define PLLRE_MISC 0x4c8
88
89 #define PLL_MISC_LOCK_ENABLE 18
90 #define PLLC_MISC_LOCK_ENABLE 24
91 #define PLLDU_MISC_LOCK_ENABLE 22
92 #define PLLE_MISC_LOCK_ENABLE 9
93 #define PLLRE_MISC_LOCK_ENABLE 30
94
95 #define PLLC_IDDQ_BIT 26
96 #define PLLX_IDDQ_BIT 3
97 #define PLLRE_IDDQ_BIT 16
98
99 #define PLL_BASE_LOCK BIT(27)
100 #define PLLE_MISC_LOCK BIT(11)
101 #define PLLRE_MISC_LOCK BIT(24)
102 #define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
103
104 #define PLLE_AUX 0x48c
105 #define PLLC_OUT 0x84
106 #define PLLM_OUT 0x94
107
108 #define OSC_CTRL 0x50
109 #define OSC_CTRL_OSC_FREQ_SHIFT 28
110 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
111
112 #define PLLXC_SW_MAX_P 6
113
114 #define CCLKG_BURST_POLICY 0x368
115
116 #define CLK_SOURCE_CSITE 0x1d4
117 #define CLK_SOURCE_EMC 0x19c
118
119 /* PLLM override registers */
120 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
121 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
122
123 /* Tegra CPU clock and reset control regs */
124 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
125
126 #define MUX8(_name, _parents, _offset, \
127 _clk_num, _gate_flags, _clk_id) \
128 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
129 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
130 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
131 NULL)
132
133 #ifdef CONFIG_PM_SLEEP
134 static struct cpu_clk_suspend_context {
135 u32 clk_csite_src;
136 u32 cclkg_burst;
137 u32 cclkg_divider;
138 } tegra114_cpu_clk_sctx;
139 #endif
140
141 static void __iomem *clk_base;
142 static void __iomem *pmc_base;
143
144 static DEFINE_SPINLOCK(pll_d_lock);
145 static DEFINE_SPINLOCK(pll_d2_lock);
146 static DEFINE_SPINLOCK(pll_u_lock);
147 static DEFINE_SPINLOCK(pll_re_lock);
148 static DEFINE_SPINLOCK(emc_lock);
149
150 static struct div_nmp pllxc_nmp = {
151 .divm_shift = 0,
152 .divm_width = 8,
153 .divn_shift = 8,
154 .divn_width = 8,
155 .divp_shift = 20,
156 .divp_width = 4,
157 };
158
159 static const struct pdiv_map pllxc_p[] = {
160 { .pdiv = 1, .hw_val = 0 },
161 { .pdiv = 2, .hw_val = 1 },
162 { .pdiv = 3, .hw_val = 2 },
163 { .pdiv = 4, .hw_val = 3 },
164 { .pdiv = 5, .hw_val = 4 },
165 { .pdiv = 6, .hw_val = 5 },
166 { .pdiv = 8, .hw_val = 6 },
167 { .pdiv = 10, .hw_val = 7 },
168 { .pdiv = 12, .hw_val = 8 },
169 { .pdiv = 16, .hw_val = 9 },
170 { .pdiv = 12, .hw_val = 10 },
171 { .pdiv = 16, .hw_val = 11 },
172 { .pdiv = 20, .hw_val = 12 },
173 { .pdiv = 24, .hw_val = 13 },
174 { .pdiv = 32, .hw_val = 14 },
175 { .pdiv = 0, .hw_val = 0 },
176 };
177
178 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
179 { 12000000, 624000000, 104, 1, 2, 0 },
180 { 12000000, 600000000, 100, 1, 2, 0 },
181 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
182 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
183 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
184 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
185 { 0, 0, 0, 0, 0, 0 },
186 };
187
188 static struct tegra_clk_pll_params pll_c_params = {
189 .input_min = 12000000,
190 .input_max = 800000000,
191 .cf_min = 12000000,
192 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
193 .vco_min = 600000000,
194 .vco_max = 1400000000,
195 .base_reg = PLLC_BASE,
196 .misc_reg = PLLC_MISC,
197 .lock_mask = PLL_BASE_LOCK,
198 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
199 .lock_delay = 300,
200 .iddq_reg = PLLC_MISC,
201 .iddq_bit_idx = PLLC_IDDQ_BIT,
202 .max_p = PLLXC_SW_MAX_P,
203 .dyn_ramp_reg = PLLC_MISC2,
204 .stepa_shift = 17,
205 .stepb_shift = 9,
206 .pdiv_tohw = pllxc_p,
207 .div_nmp = &pllxc_nmp,
208 .freq_table = pll_c_freq_table,
209 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
210 };
211
212 static struct div_nmp pllcx_nmp = {
213 .divm_shift = 0,
214 .divm_width = 2,
215 .divn_shift = 8,
216 .divn_width = 8,
217 .divp_shift = 20,
218 .divp_width = 3,
219 };
220
221 static const struct pdiv_map pllc_p[] = {
222 { .pdiv = 1, .hw_val = 0 },
223 { .pdiv = 2, .hw_val = 1 },
224 { .pdiv = 4, .hw_val = 3 },
225 { .pdiv = 8, .hw_val = 5 },
226 { .pdiv = 16, .hw_val = 7 },
227 { .pdiv = 0, .hw_val = 0 },
228 };
229
230 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
231 { 12000000, 600000000, 100, 1, 2, 0 },
232 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
233 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
234 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
235 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
236 { 0, 0, 0, 0, 0, 0 },
237 };
238
239 static struct tegra_clk_pll_params pll_c2_params = {
240 .input_min = 12000000,
241 .input_max = 48000000,
242 .cf_min = 12000000,
243 .cf_max = 19200000,
244 .vco_min = 600000000,
245 .vco_max = 1200000000,
246 .base_reg = PLLC2_BASE,
247 .misc_reg = PLLC2_MISC,
248 .lock_mask = PLL_BASE_LOCK,
249 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
250 .lock_delay = 300,
251 .pdiv_tohw = pllc_p,
252 .div_nmp = &pllcx_nmp,
253 .max_p = 7,
254 .ext_misc_reg[0] = 0x4f0,
255 .ext_misc_reg[1] = 0x4f4,
256 .ext_misc_reg[2] = 0x4f8,
257 .freq_table = pll_cx_freq_table,
258 .flags = TEGRA_PLL_USE_LOCK,
259 };
260
261 static struct tegra_clk_pll_params pll_c3_params = {
262 .input_min = 12000000,
263 .input_max = 48000000,
264 .cf_min = 12000000,
265 .cf_max = 19200000,
266 .vco_min = 600000000,
267 .vco_max = 1200000000,
268 .base_reg = PLLC3_BASE,
269 .misc_reg = PLLC3_MISC,
270 .lock_mask = PLL_BASE_LOCK,
271 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
272 .lock_delay = 300,
273 .pdiv_tohw = pllc_p,
274 .div_nmp = &pllcx_nmp,
275 .max_p = 7,
276 .ext_misc_reg[0] = 0x504,
277 .ext_misc_reg[1] = 0x508,
278 .ext_misc_reg[2] = 0x50c,
279 .freq_table = pll_cx_freq_table,
280 .flags = TEGRA_PLL_USE_LOCK,
281 };
282
283 static struct div_nmp pllm_nmp = {
284 .divm_shift = 0,
285 .divm_width = 8,
286 .override_divm_shift = 0,
287 .divn_shift = 8,
288 .divn_width = 8,
289 .override_divn_shift = 8,
290 .divp_shift = 20,
291 .divp_width = 1,
292 .override_divp_shift = 27,
293 };
294
295 static const struct pdiv_map pllm_p[] = {
296 { .pdiv = 1, .hw_val = 0 },
297 { .pdiv = 2, .hw_val = 1 },
298 { .pdiv = 0, .hw_val = 0 },
299 };
300
301 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
302 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
303 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
304 { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
305 { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
306 { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
307 { 0, 0, 0, 0, 0, 0 },
308 };
309
310 static struct tegra_clk_pll_params pll_m_params = {
311 .input_min = 12000000,
312 .input_max = 500000000,
313 .cf_min = 12000000,
314 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
315 .vco_min = 400000000,
316 .vco_max = 1066000000,
317 .base_reg = PLLM_BASE,
318 .misc_reg = PLLM_MISC,
319 .lock_mask = PLL_BASE_LOCK,
320 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
321 .lock_delay = 300,
322 .max_p = 2,
323 .pdiv_tohw = pllm_p,
324 .div_nmp = &pllm_nmp,
325 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
326 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
327 .freq_table = pll_m_freq_table,
328 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
329 TEGRA_PLL_FIXED,
330 };
331
332 static struct div_nmp pllp_nmp = {
333 .divm_shift = 0,
334 .divm_width = 5,
335 .divn_shift = 8,
336 .divn_width = 10,
337 .divp_shift = 20,
338 .divp_width = 3,
339 };
340
341 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
342 { 12000000, 216000000, 432, 12, 2, 8 },
343 { 13000000, 216000000, 432, 13, 2, 8 },
344 { 16800000, 216000000, 360, 14, 2, 8 },
345 { 19200000, 216000000, 360, 16, 2, 8 },
346 { 26000000, 216000000, 432, 26, 2, 8 },
347 { 0, 0, 0, 0, 0, 0 },
348 };
349
350 static struct tegra_clk_pll_params pll_p_params = {
351 .input_min = 2000000,
352 .input_max = 31000000,
353 .cf_min = 1000000,
354 .cf_max = 6000000,
355 .vco_min = 200000000,
356 .vco_max = 700000000,
357 .base_reg = PLLP_BASE,
358 .misc_reg = PLLP_MISC,
359 .lock_mask = PLL_BASE_LOCK,
360 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
361 .lock_delay = 300,
362 .div_nmp = &pllp_nmp,
363 .freq_table = pll_p_freq_table,
364 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
365 TEGRA_PLL_HAS_LOCK_ENABLE,
366 .fixed_rate = 408000000,
367 };
368
369 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
370 { 9600000, 282240000, 147, 5, 1, 4 },
371 { 9600000, 368640000, 192, 5, 1, 4 },
372 { 9600000, 240000000, 200, 8, 1, 8 },
373 { 28800000, 282240000, 245, 25, 1, 8 },
374 { 28800000, 368640000, 320, 25, 1, 8 },
375 { 28800000, 240000000, 200, 24, 1, 8 },
376 { 0, 0, 0, 0, 0, 0 },
377 };
378
379
380 static struct tegra_clk_pll_params pll_a_params = {
381 .input_min = 2000000,
382 .input_max = 31000000,
383 .cf_min = 1000000,
384 .cf_max = 6000000,
385 .vco_min = 200000000,
386 .vco_max = 700000000,
387 .base_reg = PLLA_BASE,
388 .misc_reg = PLLA_MISC,
389 .lock_mask = PLL_BASE_LOCK,
390 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
391 .lock_delay = 300,
392 .div_nmp = &pllp_nmp,
393 .freq_table = pll_a_freq_table,
394 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
395 TEGRA_PLL_HAS_LOCK_ENABLE,
396 };
397
398 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
399 { 12000000, 216000000, 864, 12, 4, 12 },
400 { 13000000, 216000000, 864, 13, 4, 12 },
401 { 16800000, 216000000, 720, 14, 4, 12 },
402 { 19200000, 216000000, 720, 16, 4, 12 },
403 { 26000000, 216000000, 864, 26, 4, 12 },
404 { 12000000, 594000000, 594, 12, 1, 12 },
405 { 13000000, 594000000, 594, 13, 1, 12 },
406 { 16800000, 594000000, 495, 14, 1, 12 },
407 { 19200000, 594000000, 495, 16, 1, 12 },
408 { 26000000, 594000000, 594, 26, 1, 12 },
409 { 12000000, 1000000000, 1000, 12, 1, 12 },
410 { 13000000, 1000000000, 1000, 13, 1, 12 },
411 { 19200000, 1000000000, 625, 12, 1, 12 },
412 { 26000000, 1000000000, 1000, 26, 1, 12 },
413 { 0, 0, 0, 0, 0, 0 },
414 };
415
416 static struct tegra_clk_pll_params pll_d_params = {
417 .input_min = 2000000,
418 .input_max = 40000000,
419 .cf_min = 1000000,
420 .cf_max = 6000000,
421 .vco_min = 500000000,
422 .vco_max = 1000000000,
423 .base_reg = PLLD_BASE,
424 .misc_reg = PLLD_MISC,
425 .lock_mask = PLL_BASE_LOCK,
426 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
427 .lock_delay = 1000,
428 .div_nmp = &pllp_nmp,
429 .freq_table = pll_d_freq_table,
430 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
431 TEGRA_PLL_HAS_LOCK_ENABLE,
432 };
433
434 static struct tegra_clk_pll_params pll_d2_params = {
435 .input_min = 2000000,
436 .input_max = 40000000,
437 .cf_min = 1000000,
438 .cf_max = 6000000,
439 .vco_min = 500000000,
440 .vco_max = 1000000000,
441 .base_reg = PLLD2_BASE,
442 .misc_reg = PLLD2_MISC,
443 .lock_mask = PLL_BASE_LOCK,
444 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
445 .lock_delay = 1000,
446 .div_nmp = &pllp_nmp,
447 .freq_table = pll_d_freq_table,
448 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
449 TEGRA_PLL_HAS_LOCK_ENABLE,
450 };
451
452 static const struct pdiv_map pllu_p[] = {
453 { .pdiv = 1, .hw_val = 1 },
454 { .pdiv = 2, .hw_val = 0 },
455 { .pdiv = 0, .hw_val = 0 },
456 };
457
458 static struct div_nmp pllu_nmp = {
459 .divm_shift = 0,
460 .divm_width = 5,
461 .divn_shift = 8,
462 .divn_width = 10,
463 .divp_shift = 20,
464 .divp_width = 1,
465 };
466
467 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
468 { 12000000, 480000000, 960, 12, 2, 12 },
469 { 13000000, 480000000, 960, 13, 2, 12 },
470 { 16800000, 480000000, 400, 7, 2, 5 },
471 { 19200000, 480000000, 200, 4, 2, 3 },
472 { 26000000, 480000000, 960, 26, 2, 12 },
473 { 0, 0, 0, 0, 0, 0 },
474 };
475
476 static struct tegra_clk_pll_params pll_u_params = {
477 .input_min = 2000000,
478 .input_max = 40000000,
479 .cf_min = 1000000,
480 .cf_max = 6000000,
481 .vco_min = 480000000,
482 .vco_max = 960000000,
483 .base_reg = PLLU_BASE,
484 .misc_reg = PLLU_MISC,
485 .lock_mask = PLL_BASE_LOCK,
486 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
487 .lock_delay = 1000,
488 .pdiv_tohw = pllu_p,
489 .div_nmp = &pllu_nmp,
490 .freq_table = pll_u_freq_table,
491 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
492 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
493 };
494
495 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
496 /* 1 GHz */
497 { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
498 { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
499 { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
500 { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
501 { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
502 { 0, 0, 0, 0, 0, 0 },
503 };
504
505 static struct tegra_clk_pll_params pll_x_params = {
506 .input_min = 12000000,
507 .input_max = 800000000,
508 .cf_min = 12000000,
509 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
510 .vco_min = 700000000,
511 .vco_max = 2400000000U,
512 .base_reg = PLLX_BASE,
513 .misc_reg = PLLX_MISC,
514 .lock_mask = PLL_BASE_LOCK,
515 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
516 .lock_delay = 300,
517 .iddq_reg = PLLX_MISC3,
518 .iddq_bit_idx = PLLX_IDDQ_BIT,
519 .max_p = PLLXC_SW_MAX_P,
520 .dyn_ramp_reg = PLLX_MISC2,
521 .stepa_shift = 16,
522 .stepb_shift = 24,
523 .pdiv_tohw = pllxc_p,
524 .div_nmp = &pllxc_nmp,
525 .freq_table = pll_x_freq_table,
526 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
527 };
528
529 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
530 /* PLLE special case: use cpcon field to store cml divider value */
531 { 336000000, 100000000, 100, 21, 16, 11 },
532 { 312000000, 100000000, 200, 26, 24, 13 },
533 { 12000000, 100000000, 200, 1, 24, 13 },
534 { 0, 0, 0, 0, 0, 0 },
535 };
536
537 static const struct pdiv_map plle_p[] = {
538 { .pdiv = 1, .hw_val = 0 },
539 { .pdiv = 2, .hw_val = 1 },
540 { .pdiv = 3, .hw_val = 2 },
541 { .pdiv = 4, .hw_val = 3 },
542 { .pdiv = 5, .hw_val = 4 },
543 { .pdiv = 6, .hw_val = 5 },
544 { .pdiv = 8, .hw_val = 6 },
545 { .pdiv = 10, .hw_val = 7 },
546 { .pdiv = 12, .hw_val = 8 },
547 { .pdiv = 16, .hw_val = 9 },
548 { .pdiv = 12, .hw_val = 10 },
549 { .pdiv = 16, .hw_val = 11 },
550 { .pdiv = 20, .hw_val = 12 },
551 { .pdiv = 24, .hw_val = 13 },
552 { .pdiv = 32, .hw_val = 14 },
553 { .pdiv = 0, .hw_val = 0 }
554 };
555
556 static struct div_nmp plle_nmp = {
557 .divm_shift = 0,
558 .divm_width = 8,
559 .divn_shift = 8,
560 .divn_width = 8,
561 .divp_shift = 24,
562 .divp_width = 4,
563 };
564
565 static struct tegra_clk_pll_params pll_e_params = {
566 .input_min = 12000000,
567 .input_max = 1000000000,
568 .cf_min = 12000000,
569 .cf_max = 75000000,
570 .vco_min = 1600000000,
571 .vco_max = 2400000000U,
572 .base_reg = PLLE_BASE,
573 .misc_reg = PLLE_MISC,
574 .aux_reg = PLLE_AUX,
575 .lock_mask = PLLE_MISC_LOCK,
576 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
577 .lock_delay = 300,
578 .pdiv_tohw = plle_p,
579 .div_nmp = &plle_nmp,
580 .freq_table = pll_e_freq_table,
581 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
582 .fixed_rate = 100000000,
583 };
584
585 static struct div_nmp pllre_nmp = {
586 .divm_shift = 0,
587 .divm_width = 8,
588 .divn_shift = 8,
589 .divn_width = 8,
590 .divp_shift = 16,
591 .divp_width = 4,
592 };
593
594 static struct tegra_clk_pll_params pll_re_vco_params = {
595 .input_min = 12000000,
596 .input_max = 1000000000,
597 .cf_min = 12000000,
598 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
599 .vco_min = 300000000,
600 .vco_max = 600000000,
601 .base_reg = PLLRE_BASE,
602 .misc_reg = PLLRE_MISC,
603 .lock_mask = PLLRE_MISC_LOCK,
604 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
605 .lock_delay = 300,
606 .iddq_reg = PLLRE_MISC,
607 .iddq_bit_idx = PLLRE_IDDQ_BIT,
608 .div_nmp = &pllre_nmp,
609 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
610 TEGRA_PLL_LOCK_MISC,
611 };
612
613 /* possible OSC frequencies in Hz */
614 static unsigned long tegra114_input_freq[] = {
615 [ 0] = 13000000,
616 [ 1] = 16800000,
617 [ 4] = 19200000,
618 [ 5] = 38400000,
619 [ 8] = 12000000,
620 [ 9] = 48000000,
621 [12] = 26000000,
622 };
623
624 #define MASK(x) (BIT(x) - 1)
625
626 /* peripheral mux definitions */
627
628 static const char *mux_plld_out0_plld2_out0[] = {
629 "pll_d_out0", "pll_d2_out0",
630 };
631 #define mux_plld_out0_plld2_out0_idx NULL
632
633 static const char *mux_pllmcp_clkm[] = {
634 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
635 };
636
637 static const struct clk_div_table pll_re_div_table[] = {
638 { .val = 0, .div = 1 },
639 { .val = 1, .div = 2 },
640 { .val = 2, .div = 3 },
641 { .val = 3, .div = 4 },
642 { .val = 4, .div = 5 },
643 { .val = 5, .div = 6 },
644 { .val = 0, .div = 0 },
645 };
646
647 static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
648 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
649 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
650 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
651 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
652 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
653 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
654 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
655 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
656 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
657 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
658 [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
659 [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
660 [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
661 [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
662 [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
663 [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
664 [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
665 [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
666 [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
667 [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
668 [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
669 [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
670 [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
671 [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
672 [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
673 [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
674 [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
675 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
676 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
677 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
678 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
679 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
680 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
681 [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
682 [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
683 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
684 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
685 [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
686 [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
687 [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
688 [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
689 [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
690 [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
691 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
692 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
693 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
694 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
695 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
696 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
697 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
698 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
699 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
700 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
701 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
702 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
703 [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
704 [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
705 [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
706 [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
707 [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
708 [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
709 [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
710 [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
711 [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
712 [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
713 [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
714 [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
715 [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
716 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
717 [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
718 [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
719 [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
720 [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
721 [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
722 [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
723 [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
724 [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
725 [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
726 [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
727 [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
728 [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
729 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
730 [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
731 [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
732 [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
733 [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
734 [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
735 [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
736 [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
737 [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
738 [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
739 [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
740 [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
741 [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
742 [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
743 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
744 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
745 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
746 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
747 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
748 [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
749 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
750 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
751 [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
752 [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
753 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
754 [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
755 [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
756 [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
757 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
758 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
759 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
760 [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
761 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
762 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
763 [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
764 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
765 [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
766 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
767 [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
768 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
769 [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
770 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
771 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
772 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
773 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
774 [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
775 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
776 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
777 [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
778 [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
779 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
780 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
781 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
782 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
783 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
784 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
785 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
786 [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
787 [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
788 [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
789 [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
790 [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
791 [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
792 [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
793 [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
794 [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
795 [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
796 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
797 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
798 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
799 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
800 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
801 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
802 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
803 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
804 [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
805 [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
806 [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
807 [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
808 [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
809 [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
810 [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
811 [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
812 [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
813 [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
814 [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
815 [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
816 [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
817 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
818 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
819 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
820 [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
821 [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
822 };
823
824 static struct tegra_devclk devclks[] __initdata = {
825 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
826 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
827 { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
828 { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
829 { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
830 { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
831 { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
832 { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
833 { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
834 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
835 { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
836 { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
837 { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
838 { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
839 { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
840 { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
841 { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
842 { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
843 { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
844 { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
845 { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
846 { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
847 { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
848 { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
849 { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
850 { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
851 { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
852 { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
853 { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
854 { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
855 { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
856 { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
857 { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
858 { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
859 { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
860 { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
861 { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
862 { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
863 { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
864 { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
865 { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
866 { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
867 { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
868 { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
869 { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
870 { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
871 { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
872 { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
873 { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
874 { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
875 { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
876 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
877 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
878 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
879 { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
880 { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
881 { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
882 { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
883 { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
884 { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
885 { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
886 { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
887 { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
888 };
889
890 static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
891 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
892 };
893 static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
894 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
895 };
896
897 static struct tegra_audio_clk_info tegra114_audio_plls[] = {
898 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
899 };
900
901 static struct clk **clks;
902
903 static unsigned long osc_freq;
904 static unsigned long pll_ref_freq;
905
906 static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
907 {
908 struct clk *clk;
909
910 /* clk_32k */
911 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
912 clks[TEGRA114_CLK_CLK_32K] = clk;
913
914 /* clk_m_div2 */
915 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
916 CLK_SET_RATE_PARENT, 1, 2);
917 clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
918
919 /* clk_m_div4 */
920 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
921 CLK_SET_RATE_PARENT, 1, 4);
922 clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
923
924 }
925
926 static void __init tegra114_pll_init(void __iomem *clk_base,
927 void __iomem *pmc)
928 {
929 struct clk *clk;
930
931 /* PLLC */
932 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
933 pmc, 0, &pll_c_params, NULL);
934 clks[TEGRA114_CLK_PLL_C] = clk;
935
936 /* PLLC_OUT1 */
937 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
938 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
939 8, 8, 1, NULL);
940 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
941 clk_base + PLLC_OUT, 1, 0,
942 CLK_SET_RATE_PARENT, 0, NULL);
943 clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
944
945 /* PLLC2 */
946 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
947 &pll_c2_params, NULL);
948 clks[TEGRA114_CLK_PLL_C2] = clk;
949
950 /* PLLC3 */
951 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
952 &pll_c3_params, NULL);
953 clks[TEGRA114_CLK_PLL_C3] = clk;
954
955 /* PLLM */
956 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
957 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
958 &pll_m_params, NULL);
959 clks[TEGRA114_CLK_PLL_M] = clk;
960
961 /* PLLM_OUT1 */
962 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
963 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
964 8, 8, 1, NULL);
965 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
966 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
967 CLK_SET_RATE_PARENT, 0, NULL);
968 clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
969
970 /* PLLM_UD */
971 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
972 CLK_SET_RATE_PARENT, 1, 1);
973
974 /* PLLU */
975 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
976 &pll_u_params, &pll_u_lock);
977 clks[TEGRA114_CLK_PLL_U] = clk;
978
979 /* PLLU_480M */
980 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
981 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
982 22, 0, &pll_u_lock);
983 clks[TEGRA114_CLK_PLL_U_480M] = clk;
984
985 /* PLLU_60M */
986 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
987 CLK_SET_RATE_PARENT, 1, 8);
988 clks[TEGRA114_CLK_PLL_U_60M] = clk;
989
990 /* PLLU_48M */
991 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
992 CLK_SET_RATE_PARENT, 1, 10);
993 clks[TEGRA114_CLK_PLL_U_48M] = clk;
994
995 /* PLLU_12M */
996 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
997 CLK_SET_RATE_PARENT, 1, 40);
998 clks[TEGRA114_CLK_PLL_U_12M] = clk;
999
1000 /* PLLD */
1001 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1002 &pll_d_params, &pll_d_lock);
1003 clks[TEGRA114_CLK_PLL_D] = clk;
1004
1005 /* PLLD_OUT0 */
1006 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1007 CLK_SET_RATE_PARENT, 1, 2);
1008 clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
1009
1010 /* PLLD2 */
1011 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
1012 &pll_d2_params, &pll_d2_lock);
1013 clks[TEGRA114_CLK_PLL_D2] = clk;
1014
1015 /* PLLD2_OUT0 */
1016 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1017 CLK_SET_RATE_PARENT, 1, 2);
1018 clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
1019
1020 /* PLLRE */
1021 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1022 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1023 clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
1024
1025 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1026 clk_base + PLLRE_BASE, 16, 4, 0,
1027 pll_re_div_table, &pll_re_lock);
1028 clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
1029
1030 /* PLLE */
1031 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
1032 clk_base, 0, &pll_e_params, NULL);
1033 clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1034 }
1035
1036 #define CLK_SOURCE_VI_SENSOR 0x1a8
1037
1038 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1039 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
1040 };
1041
1042 static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1043 void __iomem *pmc_base)
1044 {
1045 struct clk *clk;
1046 struct tegra_periph_init_data *data;
1047 unsigned int i;
1048
1049 /* xusb_ss_div2 */
1050 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1051 1, 2);
1052 clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
1053
1054 /* dsia mux */
1055 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1056 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1057 CLK_SET_RATE_NO_REPARENT,
1058 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1059 clks[TEGRA114_CLK_DSIA_MUX] = clk;
1060
1061 /* dsib mux */
1062 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1063 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1064 CLK_SET_RATE_NO_REPARENT,
1065 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1066 clks[TEGRA114_CLK_DSIB_MUX] = clk;
1067
1068 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1069 0, 48, periph_clk_enb_refcnt);
1070 clks[TEGRA114_CLK_DSIA] = clk;
1071
1072 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1073 0, 82, periph_clk_enb_refcnt);
1074 clks[TEGRA114_CLK_DSIB] = clk;
1075
1076 /* emc mux */
1077 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1078 ARRAY_SIZE(mux_pllmcp_clkm),
1079 CLK_SET_RATE_NO_REPARENT,
1080 clk_base + CLK_SOURCE_EMC,
1081 29, 3, 0, &emc_lock);
1082
1083 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1084 &emc_lock);
1085 clks[TEGRA114_CLK_MC] = clk;
1086
1087 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
1088 CLK_SET_RATE_PARENT, 56,
1089 periph_clk_enb_refcnt);
1090 clks[TEGRA114_CLK_MIPI_CAL] = clk;
1091
1092 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1093 data = &tegra_periph_clk_list[i];
1094 clk = tegra_clk_register_periph(data->name,
1095 data->p.parent_names, data->num_parents,
1096 &data->periph, clk_base, data->offset, data->flags);
1097 clks[data->clk_id] = clk;
1098 }
1099
1100 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
1101 &pll_p_params);
1102 }
1103
1104 /* Tegra114 CPU clock and reset control functions */
1105 static void tegra114_wait_cpu_in_reset(u32 cpu)
1106 {
1107 unsigned int reg;
1108
1109 do {
1110 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1111 cpu_relax();
1112 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1113 }
1114
1115 static void tegra114_disable_cpu_clock(u32 cpu)
1116 {
1117 /* flow controller would take care in the power sequence. */
1118 }
1119
1120 #ifdef CONFIG_PM_SLEEP
1121 static void tegra114_cpu_clock_suspend(void)
1122 {
1123 /* switch coresite to clk_m, save off original source */
1124 tegra114_cpu_clk_sctx.clk_csite_src =
1125 readl(clk_base + CLK_SOURCE_CSITE);
1126 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1127
1128 tegra114_cpu_clk_sctx.cclkg_burst =
1129 readl(clk_base + CCLKG_BURST_POLICY);
1130 tegra114_cpu_clk_sctx.cclkg_divider =
1131 readl(clk_base + CCLKG_BURST_POLICY + 4);
1132 }
1133
1134 static void tegra114_cpu_clock_resume(void)
1135 {
1136 writel(tegra114_cpu_clk_sctx.clk_csite_src,
1137 clk_base + CLK_SOURCE_CSITE);
1138
1139 writel(tegra114_cpu_clk_sctx.cclkg_burst,
1140 clk_base + CCLKG_BURST_POLICY);
1141 writel(tegra114_cpu_clk_sctx.cclkg_divider,
1142 clk_base + CCLKG_BURST_POLICY + 4);
1143 }
1144 #endif
1145
1146 static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
1147 .wait_for_reset = tegra114_wait_cpu_in_reset,
1148 .disable_clock = tegra114_disable_cpu_clock,
1149 #ifdef CONFIG_PM_SLEEP
1150 .suspend = tegra114_cpu_clock_suspend,
1151 .resume = tegra114_cpu_clock_resume,
1152 #endif
1153 };
1154
1155 static const struct of_device_id pmc_match[] __initconst = {
1156 { .compatible = "nvidia,tegra114-pmc" },
1157 { },
1158 };
1159
1160 /*
1161 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
1162 * breaks
1163 */
1164 static struct tegra_clk_init_table init_table[] __initdata = {
1165 { TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
1166 { TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
1167 { TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
1168 { TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
1169 { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
1170 { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
1171 { TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
1172 { TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
1173 { TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
1174 { TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1175 { TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1176 { TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1177 { TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1178 { TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1179 { TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
1180 { TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 },
1181 { TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 },
1182 { TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
1183 { TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
1184 { TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1185 { TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1186 { TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1187 { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1188 { TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
1189 { TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
1190 { TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
1191 { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
1192 { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
1193 { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
1194 /* must be the last entry */
1195 { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
1196 };
1197
1198 static void __init tegra114_clock_apply_init_table(void)
1199 {
1200 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
1201 }
1202
1203 /**
1204 * tegra114_car_barrier - wait for pending writes to the CAR to complete
1205 *
1206 * Wait for any outstanding writes to the CAR MMIO space from this CPU
1207 * to complete before continuing execution. No return value.
1208 */
1209 static void tegra114_car_barrier(void)
1210 {
1211 wmb(); /* probably unnecessary */
1212 readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
1213 }
1214
1215 /**
1216 * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
1217 *
1218 * When the CPU rail voltage is in the high-voltage range, use the
1219 * built-in hardwired clock propagation delays in the CPU clock
1220 * shaper. No return value.
1221 */
1222 void tegra114_clock_tune_cpu_trimmers_high(void)
1223 {
1224 u32 select = 0;
1225
1226 /* Use hardwired rise->rise & fall->fall clock propagation delays */
1227 select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1228 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1229 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1230 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1231
1232 tegra114_car_barrier();
1233 }
1234 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
1235
1236 /**
1237 * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
1238 *
1239 * When the CPU rail voltage is in the low-voltage range, use the
1240 * extended clock propagation delays set by
1241 * tegra114_clock_tune_cpu_trimmers_init(). The intention is to
1242 * maintain the input clock duty cycle that the FCPU subsystem
1243 * expects. No return value.
1244 */
1245 void tegra114_clock_tune_cpu_trimmers_low(void)
1246 {
1247 u32 select = 0;
1248
1249 /*
1250 * Use software-specified rise->rise & fall->fall clock
1251 * propagation delays (from
1252 * tegra114_clock_tune_cpu_trimmers_init()
1253 */
1254 select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1255 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1256 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1257 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1258
1259 tegra114_car_barrier();
1260 }
1261 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
1262
1263 /**
1264 * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
1265 *
1266 * Program extended clock propagation delays into the FCPU clock
1267 * shaper and enable them. XXX Define the purpose - peak current
1268 * reduction? No return value.
1269 */
1270 /* XXX Initial voltage rail state assumption issues? */
1271 void tegra114_clock_tune_cpu_trimmers_init(void)
1272 {
1273 u32 dr = 0, r = 0;
1274
1275 /* Increment the rise->rise clock delay by four steps */
1276 r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
1277 CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
1278 CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
1279 writel_relaxed(r, clk_base + CPU_FINETRIM_R);
1280
1281 /*
1282 * Use the rise->rise clock propagation delay specified in the
1283 * r field
1284 */
1285 dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1286 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1287 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1288 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
1289
1290 tegra114_clock_tune_cpu_trimmers_low();
1291 }
1292 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
1293
1294 /**
1295 * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1296 *
1297 * Assert the reset line of the DFLL's DVCO. No return value.
1298 */
1299 void tegra114_clock_assert_dfll_dvco_reset(void)
1300 {
1301 u32 v;
1302
1303 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1304 v |= (1 << DVFS_DFLL_RESET_SHIFT);
1305 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1306 tegra114_car_barrier();
1307 }
1308 EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
1309
1310 /**
1311 * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1312 *
1313 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1314 * operate. No return value.
1315 */
1316 void tegra114_clock_deassert_dfll_dvco_reset(void)
1317 {
1318 u32 v;
1319
1320 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1321 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1322 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1323 tegra114_car_barrier();
1324 }
1325 EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
1326
1327 static void __init tegra114_clock_init(struct device_node *np)
1328 {
1329 struct device_node *node;
1330
1331 clk_base = of_iomap(np, 0);
1332 if (!clk_base) {
1333 pr_err("ioremap tegra114 CAR failed\n");
1334 return;
1335 }
1336
1337 node = of_find_matching_node(NULL, pmc_match);
1338 if (!node) {
1339 pr_err("Failed to find pmc node\n");
1340 WARN_ON(1);
1341 return;
1342 }
1343
1344 pmc_base = of_iomap(node, 0);
1345 if (!pmc_base) {
1346 pr_err("Can't map pmc registers\n");
1347 WARN_ON(1);
1348 return;
1349 }
1350
1351 clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
1352 TEGRA114_CLK_PERIPH_BANKS);
1353 if (!clks)
1354 return;
1355
1356 if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,
1357 ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq,
1358 &pll_ref_freq) < 0)
1359 return;
1360
1361 tegra114_fixed_clk_init(clk_base);
1362 tegra114_pll_init(clk_base, pmc_base);
1363 tegra114_periph_clk_init(clk_base, pmc_base);
1364 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
1365 tegra114_audio_plls,
1366 ARRAY_SIZE(tegra114_audio_plls));
1367 tegra_pmc_clk_init(pmc_base, tegra114_clks);
1368 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1369 &pll_x_params);
1370
1371 tegra_add_of_provider(np);
1372 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1373
1374 tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
1375
1376 tegra_cpu_car_ops = &tegra114_cpu_car_ops;
1377 }
1378 CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);
Linux with added FPC-III support