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perf bench futex: Cache align the worker struct
[linux/fpc-iii.git] / drivers / iio / gyro / bmg160_core.c
blobf7fcfa886f72181e36b89b38daa327dbf8d17cd0
1 /*
2 * BMG160 Gyro Sensor driver
3 * Copyright (c) 2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/acpi.h>
20 #include <linux/pm.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/trigger.h>
26 #include <linux/iio/events.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/regmap.h>
30 #include "bmg160.h"
31
32 #define BMG160_IRQ_NAME "bmg160_event"
33
34 #define BMG160_REG_CHIP_ID 0x00
35 #define BMG160_CHIP_ID_VAL 0x0F
36
37 #define BMG160_REG_PMU_LPW 0x11
38 #define BMG160_MODE_NORMAL 0x00
39 #define BMG160_MODE_DEEP_SUSPEND 0x20
40 #define BMG160_MODE_SUSPEND 0x80
41
42 #define BMG160_REG_RANGE 0x0F
43
44 #define BMG160_RANGE_2000DPS 0
45 #define BMG160_RANGE_1000DPS 1
46 #define BMG160_RANGE_500DPS 2
47 #define BMG160_RANGE_250DPS 3
48 #define BMG160_RANGE_125DPS 4
49
50 #define BMG160_REG_PMU_BW 0x10
51 #define BMG160_NO_FILTER 0
52 #define BMG160_DEF_BW 100
53 #define BMG160_REG_PMU_BW_RES BIT(7)
54
55 #define BMG160_REG_INT_MAP_0 0x17
56 #define BMG160_INT_MAP_0_BIT_ANY BIT(1)
57
58 #define BMG160_REG_INT_MAP_1 0x18
59 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0)
60
61 #define BMG160_REG_INT_RST_LATCH 0x21
62 #define BMG160_INT_MODE_LATCH_RESET 0x80
63 #define BMG160_INT_MODE_LATCH_INT 0x0F
64 #define BMG160_INT_MODE_NON_LATCH_INT 0x00
65
66 #define BMG160_REG_INT_EN_0 0x15
67 #define BMG160_DATA_ENABLE_INT BIT(7)
68
69 #define BMG160_REG_INT_EN_1 0x16
70 #define BMG160_INT1_BIT_OD BIT(1)
71
72 #define BMG160_REG_XOUT_L 0x02
73 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2))
74
75 #define BMG160_REG_SLOPE_THRES 0x1B
76 #define BMG160_SLOPE_THRES_MASK 0x0F
77
78 #define BMG160_REG_MOTION_INTR 0x1C
79 #define BMG160_INT_MOTION_X BIT(0)
80 #define BMG160_INT_MOTION_Y BIT(1)
81 #define BMG160_INT_MOTION_Z BIT(2)
82 #define BMG160_ANY_DUR_MASK 0x30
83 #define BMG160_ANY_DUR_SHIFT 4
84
85 #define BMG160_REG_INT_STATUS_2 0x0B
86 #define BMG160_ANY_MOTION_MASK 0x07
87 #define BMG160_ANY_MOTION_BIT_X BIT(0)
88 #define BMG160_ANY_MOTION_BIT_Y BIT(1)
89 #define BMG160_ANY_MOTION_BIT_Z BIT(2)
90
91 #define BMG160_REG_TEMP 0x08
92 #define BMG160_TEMP_CENTER_VAL 23
93
94 #define BMG160_MAX_STARTUP_TIME_MS 80
95
96 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000
97
98 struct bmg160_data {
99 struct regmap *regmap;
100 struct iio_trigger *dready_trig;
101 struct iio_trigger *motion_trig;
102 struct mutex mutex;
103 s16 buffer[8];
104 u32 dps_range;
105 int ev_enable_state;
106 int slope_thres;
107 bool dready_trigger_on;
108 bool motion_trigger_on;
109 int irq;
110 };
111
112 enum bmg160_axis {
113 AXIS_X,
114 AXIS_Y,
115 AXIS_Z,
116 AXIS_MAX,
117 };
118
119 static const struct {
120 int odr;
121 int filter;
122 int bw_bits;
123 } bmg160_samp_freq_table[] = { {100, 32, 0x07},
124 {200, 64, 0x06},
125 {100, 12, 0x05},
126 {200, 23, 0x04},
127 {400, 47, 0x03},
128 {1000, 116, 0x02},
129 {2000, 230, 0x01} };
130
131 static const struct {
132 int scale;
133 int dps_range;
134 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS},
135 { 532, BMG160_RANGE_1000DPS},
136 { 266, BMG160_RANGE_500DPS},
137 { 133, BMG160_RANGE_250DPS},
138 { 66, BMG160_RANGE_125DPS} };
139
140 static int bmg160_set_mode(struct bmg160_data *data, u8 mode)
141 {
142 struct device *dev = regmap_get_device(data->regmap);
143 int ret;
144
145 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode);
146 if (ret < 0) {
147 dev_err(dev, "Error writing reg_pmu_lpw\n");
148 return ret;
149 }
150
151 return 0;
152 }
153
154 static int bmg160_convert_freq_to_bit(int val)
155 {
156 int i;
157
158 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
159 if (bmg160_samp_freq_table[i].odr == val)
160 return bmg160_samp_freq_table[i].bw_bits;
161 }
162
163 return -EINVAL;
164 }
165
166 static int bmg160_set_bw(struct bmg160_data *data, int val)
167 {
168 struct device *dev = regmap_get_device(data->regmap);
169 int ret;
170 int bw_bits;
171
172 bw_bits = bmg160_convert_freq_to_bit(val);
173 if (bw_bits < 0)
174 return bw_bits;
175
176 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits);
177 if (ret < 0) {
178 dev_err(dev, "Error writing reg_pmu_bw\n");
179 return ret;
180 }
181
182 return 0;
183 }
184
185 static int bmg160_get_filter(struct bmg160_data *data, int *val)
186 {
187 struct device *dev = regmap_get_device(data->regmap);
188 int ret;
189 int i;
190 unsigned int bw_bits;
191
192 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
193 if (ret < 0) {
194 dev_err(dev, "Error reading reg_pmu_bw\n");
195 return ret;
196 }
197
198 /* Ignore the readonly reserved bit. */
199 bw_bits &= ~BMG160_REG_PMU_BW_RES;
200
201 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
202 if (bmg160_samp_freq_table[i].bw_bits == bw_bits)
203 break;
204 }
205
206 *val = bmg160_samp_freq_table[i].filter;
207
208 return ret ? ret : IIO_VAL_INT;
209 }
210
211
212 static int bmg160_set_filter(struct bmg160_data *data, int val)
213 {
214 struct device *dev = regmap_get_device(data->regmap);
215 int ret;
216 int i;
217
218 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
219 if (bmg160_samp_freq_table[i].filter == val)
220 break;
221 }
222
223 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW,
224 bmg160_samp_freq_table[i].bw_bits);
225 if (ret < 0) {
226 dev_err(dev, "Error writing reg_pmu_bw\n");
227 return ret;
228 }
229
230 return 0;
231 }
232
233 static int bmg160_chip_init(struct bmg160_data *data)
234 {
235 struct device *dev = regmap_get_device(data->regmap);
236 int ret;
237 unsigned int val;
238
239 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val);
240 if (ret < 0) {
241 dev_err(dev, "Error reading reg_chip_id\n");
242 return ret;
243 }
244
245 dev_dbg(dev, "Chip Id %x\n", val);
246 if (val != BMG160_CHIP_ID_VAL) {
247 dev_err(dev, "invalid chip %x\n", val);
248 return -ENODEV;
249 }
250
251 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
252 if (ret < 0)
253 return ret;
254
255 /* Wait upto 500 ms to be ready after changing mode */
256 usleep_range(500, 1000);
257
258 /* Set Bandwidth */
259 ret = bmg160_set_bw(data, BMG160_DEF_BW);
260 if (ret < 0)
261 return ret;
262
263 /* Set Default Range */
264 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS);
265 if (ret < 0) {
266 dev_err(dev, "Error writing reg_range\n");
267 return ret;
268 }
269 data->dps_range = BMG160_RANGE_500DPS;
270
271 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val);
272 if (ret < 0) {
273 dev_err(dev, "Error reading reg_slope_thres\n");
274 return ret;
275 }
276 data->slope_thres = val;
277
278 /* Set default interrupt mode */
279 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1,
280 BMG160_INT1_BIT_OD, 0);
281 if (ret < 0) {
282 dev_err(dev, "Error updating bits in reg_int_en_1\n");
283 return ret;
284 }
285
286 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
287 BMG160_INT_MODE_LATCH_INT |
288 BMG160_INT_MODE_LATCH_RESET);
289 if (ret < 0) {
290 dev_err(dev,
291 "Error writing reg_motion_intr\n");
292 return ret;
293 }
294
295 return 0;
296 }
297
298 static int bmg160_set_power_state(struct bmg160_data *data, bool on)
299 {
300 #ifdef CONFIG_PM
301 struct device *dev = regmap_get_device(data->regmap);
302 int ret;
303
304 if (on)
305 ret = pm_runtime_get_sync(dev);
306 else {
307 pm_runtime_mark_last_busy(dev);
308 ret = pm_runtime_put_autosuspend(dev);
309 }
310
311 if (ret < 0) {
312 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on);
313
314 if (on)
315 pm_runtime_put_noidle(dev);
316
317 return ret;
318 }
319 #endif
320
321 return 0;
322 }
323
324 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data,
325 bool status)
326 {
327 struct device *dev = regmap_get_device(data->regmap);
328 int ret;
329
330 /* Enable/Disable INT_MAP0 mapping */
331 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0,
332 BMG160_INT_MAP_0_BIT_ANY,
333 (status ? BMG160_INT_MAP_0_BIT_ANY : 0));
334 if (ret < 0) {
335 dev_err(dev, "Error updating bits reg_int_map0\n");
336 return ret;
337 }
338
339 /* Enable/Disable slope interrupts */
340 if (status) {
341 /* Update slope thres */
342 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES,
343 data->slope_thres);
344 if (ret < 0) {
345 dev_err(dev, "Error writing reg_slope_thres\n");
346 return ret;
347 }
348
349 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR,
350 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y |
351 BMG160_INT_MOTION_Z);
352 if (ret < 0) {
353 dev_err(dev, "Error writing reg_motion_intr\n");
354 return ret;
355 }
356
357 /*
358 * New data interrupt is always non-latched,
359 * which will have higher priority, so no need
360 * to set latched mode, we will be flooded anyway with INTR
361 */
362 if (!data->dready_trigger_on) {
363 ret = regmap_write(data->regmap,
364 BMG160_REG_INT_RST_LATCH,
365 BMG160_INT_MODE_LATCH_INT |
366 BMG160_INT_MODE_LATCH_RESET);
367 if (ret < 0) {
368 dev_err(dev, "Error writing reg_rst_latch\n");
369 return ret;
370 }
371 }
372
373 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
374 BMG160_DATA_ENABLE_INT);
375
376 } else {
377 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
378 }
379
380 if (ret < 0) {
381 dev_err(dev, "Error writing reg_int_en0\n");
382 return ret;
383 }
384
385 return 0;
386 }
387
388 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data,
389 bool status)
390 {
391 struct device *dev = regmap_get_device(data->regmap);
392 int ret;
393
394 /* Enable/Disable INT_MAP1 mapping */
395 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1,
396 BMG160_INT_MAP_1_BIT_NEW_DATA,
397 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0));
398 if (ret < 0) {
399 dev_err(dev, "Error updating bits in reg_int_map1\n");
400 return ret;
401 }
402
403 if (status) {
404 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
405 BMG160_INT_MODE_NON_LATCH_INT |
406 BMG160_INT_MODE_LATCH_RESET);
407 if (ret < 0) {
408 dev_err(dev, "Error writing reg_rst_latch\n");
409 return ret;
410 }
411
412 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
413 BMG160_DATA_ENABLE_INT);
414
415 } else {
416 /* Restore interrupt mode */
417 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
418 BMG160_INT_MODE_LATCH_INT |
419 BMG160_INT_MODE_LATCH_RESET);
420 if (ret < 0) {
421 dev_err(dev, "Error writing reg_rst_latch\n");
422 return ret;
423 }
424
425 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
426 }
427
428 if (ret < 0) {
429 dev_err(dev, "Error writing reg_int_en0\n");
430 return ret;
431 }
432
433 return 0;
434 }
435
436 static int bmg160_get_bw(struct bmg160_data *data, int *val)
437 {
438 struct device *dev = regmap_get_device(data->regmap);
439 int i;
440 unsigned int bw_bits;
441 int ret;
442
443 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
444 if (ret < 0) {
445 dev_err(dev, "Error reading reg_pmu_bw\n");
446 return ret;
447 }
448
449 /* Ignore the readonly reserved bit. */
450 bw_bits &= ~BMG160_REG_PMU_BW_RES;
451
452 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
453 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) {
454 *val = bmg160_samp_freq_table[i].odr;
455 return IIO_VAL_INT;
456 }
457 }
458
459 return -EINVAL;
460 }
461
462 static int bmg160_set_scale(struct bmg160_data *data, int val)
463 {
464 struct device *dev = regmap_get_device(data->regmap);
465 int ret, i;
466
467 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
468 if (bmg160_scale_table[i].scale == val) {
469 ret = regmap_write(data->regmap, BMG160_REG_RANGE,
470 bmg160_scale_table[i].dps_range);
471 if (ret < 0) {
472 dev_err(dev, "Error writing reg_range\n");
473 return ret;
474 }
475 data->dps_range = bmg160_scale_table[i].dps_range;
476 return 0;
477 }
478 }
479
480 return -EINVAL;
481 }
482
483 static int bmg160_get_temp(struct bmg160_data *data, int *val)
484 {
485 struct device *dev = regmap_get_device(data->regmap);
486 int ret;
487 unsigned int raw_val;
488
489 mutex_lock(&data->mutex);
490 ret = bmg160_set_power_state(data, true);
491 if (ret < 0) {
492 mutex_unlock(&data->mutex);
493 return ret;
494 }
495
496 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val);
497 if (ret < 0) {
498 dev_err(dev, "Error reading reg_temp\n");
499 bmg160_set_power_state(data, false);
500 mutex_unlock(&data->mutex);
501 return ret;
502 }
503
504 *val = sign_extend32(raw_val, 7);
505 ret = bmg160_set_power_state(data, false);
506 mutex_unlock(&data->mutex);
507 if (ret < 0)
508 return ret;
509
510 return IIO_VAL_INT;
511 }
512
513 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val)
514 {
515 struct device *dev = regmap_get_device(data->regmap);
516 int ret;
517 __le16 raw_val;
518
519 mutex_lock(&data->mutex);
520 ret = bmg160_set_power_state(data, true);
521 if (ret < 0) {
522 mutex_unlock(&data->mutex);
523 return ret;
524 }
525
526 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val,
527 sizeof(raw_val));
528 if (ret < 0) {
529 dev_err(dev, "Error reading axis %d\n", axis);
530 bmg160_set_power_state(data, false);
531 mutex_unlock(&data->mutex);
532 return ret;
533 }
534
535 *val = sign_extend32(le16_to_cpu(raw_val), 15);
536 ret = bmg160_set_power_state(data, false);
537 mutex_unlock(&data->mutex);
538 if (ret < 0)
539 return ret;
540
541 return IIO_VAL_INT;
542 }
543
544 static int bmg160_read_raw(struct iio_dev *indio_dev,
545 struct iio_chan_spec const *chan,
546 int *val, int *val2, long mask)
547 {
548 struct bmg160_data *data = iio_priv(indio_dev);
549 int ret;
550
551 switch (mask) {
552 case IIO_CHAN_INFO_RAW:
553 switch (chan->type) {
554 case IIO_TEMP:
555 return bmg160_get_temp(data, val);
556 case IIO_ANGL_VEL:
557 if (iio_buffer_enabled(indio_dev))
558 return -EBUSY;
559 else
560 return bmg160_get_axis(data, chan->scan_index,
561 val);
562 default:
563 return -EINVAL;
564 }
565 case IIO_CHAN_INFO_OFFSET:
566 if (chan->type == IIO_TEMP) {
567 *val = BMG160_TEMP_CENTER_VAL;
568 return IIO_VAL_INT;
569 } else
570 return -EINVAL;
571 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
572 return bmg160_get_filter(data, val);
573 case IIO_CHAN_INFO_SCALE:
574 *val = 0;
575 switch (chan->type) {
576 case IIO_TEMP:
577 *val2 = 500000;
578 return IIO_VAL_INT_PLUS_MICRO;
579 case IIO_ANGL_VEL:
580 {
581 int i;
582
583 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
584 if (bmg160_scale_table[i].dps_range ==
585 data->dps_range) {
586 *val2 = bmg160_scale_table[i].scale;
587 return IIO_VAL_INT_PLUS_MICRO;
588 }
589 }
590 return -EINVAL;
591 }
592 default:
593 return -EINVAL;
594 }
595 case IIO_CHAN_INFO_SAMP_FREQ:
596 *val2 = 0;
597 mutex_lock(&data->mutex);
598 ret = bmg160_get_bw(data, val);
599 mutex_unlock(&data->mutex);
600 return ret;
601 default:
602 return -EINVAL;
603 }
604 }
605
606 static int bmg160_write_raw(struct iio_dev *indio_dev,
607 struct iio_chan_spec const *chan,
608 int val, int val2, long mask)
609 {
610 struct bmg160_data *data = iio_priv(indio_dev);
611 int ret;
612
613 switch (mask) {
614 case IIO_CHAN_INFO_SAMP_FREQ:
615 mutex_lock(&data->mutex);
616 /*
617 * Section 4.2 of spec
618 * In suspend mode, the only supported operations are reading
619 * registers as well as writing to the (0x14) softreset
620 * register. Since we will be in suspend mode by default, change
621 * mode to power on for other writes.
622 */
623 ret = bmg160_set_power_state(data, true);
624 if (ret < 0) {
625 mutex_unlock(&data->mutex);
626 return ret;
627 }
628 ret = bmg160_set_bw(data, val);
629 if (ret < 0) {
630 bmg160_set_power_state(data, false);
631 mutex_unlock(&data->mutex);
632 return ret;
633 }
634 ret = bmg160_set_power_state(data, false);
635 mutex_unlock(&data->mutex);
636 return ret;
637 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
638 if (val2)
639 return -EINVAL;
640
641 mutex_lock(&data->mutex);
642 ret = bmg160_set_power_state(data, true);
643 if (ret < 0) {
644 bmg160_set_power_state(data, false);
645 mutex_unlock(&data->mutex);
646 return ret;
647 }
648 ret = bmg160_set_filter(data, val);
649 if (ret < 0) {
650 bmg160_set_power_state(data, false);
651 mutex_unlock(&data->mutex);
652 return ret;
653 }
654 ret = bmg160_set_power_state(data, false);
655 mutex_unlock(&data->mutex);
656 return ret;
657 case IIO_CHAN_INFO_SCALE:
658 if (val)
659 return -EINVAL;
660
661 mutex_lock(&data->mutex);
662 /* Refer to comments above for the suspend mode ops */
663 ret = bmg160_set_power_state(data, true);
664 if (ret < 0) {
665 mutex_unlock(&data->mutex);
666 return ret;
667 }
668 ret = bmg160_set_scale(data, val2);
669 if (ret < 0) {
670 bmg160_set_power_state(data, false);
671 mutex_unlock(&data->mutex);
672 return ret;
673 }
674 ret = bmg160_set_power_state(data, false);
675 mutex_unlock(&data->mutex);
676 return ret;
677 default:
678 return -EINVAL;
679 }
680
681 return -EINVAL;
682 }
683
684 static int bmg160_read_event(struct iio_dev *indio_dev,
685 const struct iio_chan_spec *chan,
686 enum iio_event_type type,
687 enum iio_event_direction dir,
688 enum iio_event_info info,
689 int *val, int *val2)
690 {
691 struct bmg160_data *data = iio_priv(indio_dev);
692
693 *val2 = 0;
694 switch (info) {
695 case IIO_EV_INFO_VALUE:
696 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK;
697 break;
698 default:
699 return -EINVAL;
700 }
701
702 return IIO_VAL_INT;
703 }
704
705 static int bmg160_write_event(struct iio_dev *indio_dev,
706 const struct iio_chan_spec *chan,
707 enum iio_event_type type,
708 enum iio_event_direction dir,
709 enum iio_event_info info,
710 int val, int val2)
711 {
712 struct bmg160_data *data = iio_priv(indio_dev);
713
714 switch (info) {
715 case IIO_EV_INFO_VALUE:
716 if (data->ev_enable_state)
717 return -EBUSY;
718 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK;
719 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK);
720 break;
721 default:
722 return -EINVAL;
723 }
724
725 return 0;
726 }
727
728 static int bmg160_read_event_config(struct iio_dev *indio_dev,
729 const struct iio_chan_spec *chan,
730 enum iio_event_type type,
731 enum iio_event_direction dir)
732 {
733
734 struct bmg160_data *data = iio_priv(indio_dev);
735
736 return data->ev_enable_state;
737 }
738
739 static int bmg160_write_event_config(struct iio_dev *indio_dev,
740 const struct iio_chan_spec *chan,
741 enum iio_event_type type,
742 enum iio_event_direction dir,
743 int state)
744 {
745 struct bmg160_data *data = iio_priv(indio_dev);
746 int ret;
747
748 if (state && data->ev_enable_state)
749 return 0;
750
751 mutex_lock(&data->mutex);
752
753 if (!state && data->motion_trigger_on) {
754 data->ev_enable_state = 0;
755 mutex_unlock(&data->mutex);
756 return 0;
757 }
758 /*
759 * We will expect the enable and disable to do operation in
760 * in reverse order. This will happen here anyway as our
761 * resume operation uses sync mode runtime pm calls, the
762 * suspend operation will be delayed by autosuspend delay
763 * So the disable operation will still happen in reverse of
764 * enable operation. When runtime pm is disabled the mode
765 * is always on so sequence doesn't matter
766 */
767 ret = bmg160_set_power_state(data, state);
768 if (ret < 0) {
769 mutex_unlock(&data->mutex);
770 return ret;
771 }
772
773 ret = bmg160_setup_any_motion_interrupt(data, state);
774 if (ret < 0) {
775 bmg160_set_power_state(data, false);
776 mutex_unlock(&data->mutex);
777 return ret;
778 }
779
780 data->ev_enable_state = state;
781 mutex_unlock(&data->mutex);
782
783 return 0;
784 }
785
786 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000");
787
788 static IIO_CONST_ATTR(in_anglvel_scale_available,
789 "0.001065 0.000532 0.000266 0.000133 0.000066");
790
791 static struct attribute *bmg160_attributes[] = {
792 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
793 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
794 NULL,
795 };
796
797 static const struct attribute_group bmg160_attrs_group = {
798 .attrs = bmg160_attributes,
799 };
800
801 static const struct iio_event_spec bmg160_event = {
802 .type = IIO_EV_TYPE_ROC,
803 .dir = IIO_EV_DIR_EITHER,
804 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
805 BIT(IIO_EV_INFO_ENABLE)
806 };
807
808 #define BMG160_CHANNEL(_axis) { \
809 .type = IIO_ANGL_VEL, \
810 .modified = 1, \
811 .channel2 = IIO_MOD_##_axis, \
812 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
813 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
814 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
815 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
816 .scan_index = AXIS_##_axis, \
817 .scan_type = { \
818 .sign = 's', \
819 .realbits = 16, \
820 .storagebits = 16, \
821 .endianness = IIO_LE, \
822 }, \
823 .event_spec = &bmg160_event, \
824 .num_event_specs = 1 \
825 }
826
827 static const struct iio_chan_spec bmg160_channels[] = {
828 {
829 .type = IIO_TEMP,
830 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
831 BIT(IIO_CHAN_INFO_SCALE) |
832 BIT(IIO_CHAN_INFO_OFFSET),
833 .scan_index = -1,
834 },
835 BMG160_CHANNEL(X),
836 BMG160_CHANNEL(Y),
837 BMG160_CHANNEL(Z),
838 IIO_CHAN_SOFT_TIMESTAMP(3),
839 };
840
841 static const struct iio_info bmg160_info = {
842 .attrs = &bmg160_attrs_group,
843 .read_raw = bmg160_read_raw,
844 .write_raw = bmg160_write_raw,
845 .read_event_value = bmg160_read_event,
846 .write_event_value = bmg160_write_event,
847 .write_event_config = bmg160_write_event_config,
848 .read_event_config = bmg160_read_event_config,
849 .driver_module = THIS_MODULE,
850 };
851
852 static const unsigned long bmg160_accel_scan_masks[] = {
853 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
854 0};
855
856 static irqreturn_t bmg160_trigger_handler(int irq, void *p)
857 {
858 struct iio_poll_func *pf = p;
859 struct iio_dev *indio_dev = pf->indio_dev;
860 struct bmg160_data *data = iio_priv(indio_dev);
861 int ret;
862
863 mutex_lock(&data->mutex);
864 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L,
865 data->buffer, AXIS_MAX * 2);
866 mutex_unlock(&data->mutex);
867 if (ret < 0)
868 goto err;
869
870 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
871 pf->timestamp);
872 err:
873 iio_trigger_notify_done(indio_dev->trig);
874
875 return IRQ_HANDLED;
876 }
877
878 static int bmg160_trig_try_reen(struct iio_trigger *trig)
879 {
880 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
881 struct bmg160_data *data = iio_priv(indio_dev);
882 struct device *dev = regmap_get_device(data->regmap);
883 int ret;
884
885 /* new data interrupts don't need ack */
886 if (data->dready_trigger_on)
887 return 0;
888
889 /* Set latched mode interrupt and clear any latched interrupt */
890 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
891 BMG160_INT_MODE_LATCH_INT |
892 BMG160_INT_MODE_LATCH_RESET);
893 if (ret < 0) {
894 dev_err(dev, "Error writing reg_rst_latch\n");
895 return ret;
896 }
897
898 return 0;
899 }
900
901 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig,
902 bool state)
903 {
904 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
905 struct bmg160_data *data = iio_priv(indio_dev);
906 int ret;
907
908 mutex_lock(&data->mutex);
909
910 if (!state && data->ev_enable_state && data->motion_trigger_on) {
911 data->motion_trigger_on = false;
912 mutex_unlock(&data->mutex);
913 return 0;
914 }
915
916 /*
917 * Refer to comment in bmg160_write_event_config for
918 * enable/disable operation order
919 */
920 ret = bmg160_set_power_state(data, state);
921 if (ret < 0) {
922 mutex_unlock(&data->mutex);
923 return ret;
924 }
925 if (data->motion_trig == trig)
926 ret = bmg160_setup_any_motion_interrupt(data, state);
927 else
928 ret = bmg160_setup_new_data_interrupt(data, state);
929 if (ret < 0) {
930 bmg160_set_power_state(data, false);
931 mutex_unlock(&data->mutex);
932 return ret;
933 }
934 if (data->motion_trig == trig)
935 data->motion_trigger_on = state;
936 else
937 data->dready_trigger_on = state;
938
939 mutex_unlock(&data->mutex);
940
941 return 0;
942 }
943
944 static const struct iio_trigger_ops bmg160_trigger_ops = {
945 .set_trigger_state = bmg160_data_rdy_trigger_set_state,
946 .try_reenable = bmg160_trig_try_reen,
947 .owner = THIS_MODULE,
948 };
949
950 static irqreturn_t bmg160_event_handler(int irq, void *private)
951 {
952 struct iio_dev *indio_dev = private;
953 struct bmg160_data *data = iio_priv(indio_dev);
954 struct device *dev = regmap_get_device(data->regmap);
955 int ret;
956 int dir;
957 unsigned int val;
958
959 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val);
960 if (ret < 0) {
961 dev_err(dev, "Error reading reg_int_status2\n");
962 goto ack_intr_status;
963 }
964
965 if (val & 0x08)
966 dir = IIO_EV_DIR_RISING;
967 else
968 dir = IIO_EV_DIR_FALLING;
969
970 if (val & BMG160_ANY_MOTION_BIT_X)
971 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
972 0,
973 IIO_MOD_X,
974 IIO_EV_TYPE_ROC,
975 dir),
976 iio_get_time_ns(indio_dev));
977 if (val & BMG160_ANY_MOTION_BIT_Y)
978 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
979 0,
980 IIO_MOD_Y,
981 IIO_EV_TYPE_ROC,
982 dir),
983 iio_get_time_ns(indio_dev));
984 if (val & BMG160_ANY_MOTION_BIT_Z)
985 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
986 0,
987 IIO_MOD_Z,
988 IIO_EV_TYPE_ROC,
989 dir),
990 iio_get_time_ns(indio_dev));
991
992 ack_intr_status:
993 if (!data->dready_trigger_on) {
994 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
995 BMG160_INT_MODE_LATCH_INT |
996 BMG160_INT_MODE_LATCH_RESET);
997 if (ret < 0)
998 dev_err(dev, "Error writing reg_rst_latch\n");
999 }
1000
1001 return IRQ_HANDLED;
1002 }
1003
1004 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private)
1005 {
1006 struct iio_dev *indio_dev = private;
1007 struct bmg160_data *data = iio_priv(indio_dev);
1008
1009 if (data->dready_trigger_on)
1010 iio_trigger_poll(data->dready_trig);
1011 else if (data->motion_trigger_on)
1012 iio_trigger_poll(data->motion_trig);
1013
1014 if (data->ev_enable_state)
1015 return IRQ_WAKE_THREAD;
1016 else
1017 return IRQ_HANDLED;
1018
1019 }
1020
1021 static int bmg160_buffer_preenable(struct iio_dev *indio_dev)
1022 {
1023 struct bmg160_data *data = iio_priv(indio_dev);
1024
1025 return bmg160_set_power_state(data, true);
1026 }
1027
1028 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev)
1029 {
1030 struct bmg160_data *data = iio_priv(indio_dev);
1031
1032 return bmg160_set_power_state(data, false);
1033 }
1034
1035 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = {
1036 .preenable = bmg160_buffer_preenable,
1037 .postenable = iio_triggered_buffer_postenable,
1038 .predisable = iio_triggered_buffer_predisable,
1039 .postdisable = bmg160_buffer_postdisable,
1040 };
1041
1042 static const char *bmg160_match_acpi_device(struct device *dev)
1043 {
1044 const struct acpi_device_id *id;
1045
1046 id = acpi_match_device(dev->driver->acpi_match_table, dev);
1047 if (!id)
1048 return NULL;
1049
1050 return dev_name(dev);
1051 }
1052
1053 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq,
1054 const char *name)
1055 {
1056 struct bmg160_data *data;
1057 struct iio_dev *indio_dev;
1058 int ret;
1059
1060 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1061 if (!indio_dev)
1062 return -ENOMEM;
1063
1064 data = iio_priv(indio_dev);
1065 dev_set_drvdata(dev, indio_dev);
1066 data->irq = irq;
1067 data->regmap = regmap;
1068
1069 ret = bmg160_chip_init(data);
1070 if (ret < 0)
1071 return ret;
1072
1073 mutex_init(&data->mutex);
1074
1075 if (ACPI_HANDLE(dev))
1076 name = bmg160_match_acpi_device(dev);
1077
1078 indio_dev->dev.parent = dev;
1079 indio_dev->channels = bmg160_channels;
1080 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels);
1081 indio_dev->name = name;
1082 indio_dev->available_scan_masks = bmg160_accel_scan_masks;
1083 indio_dev->modes = INDIO_DIRECT_MODE;
1084 indio_dev->info = &bmg160_info;
1085
1086 if (data->irq > 0) {
1087 ret = devm_request_threaded_irq(dev,
1088 data->irq,
1089 bmg160_data_rdy_trig_poll,
1090 bmg160_event_handler,
1091 IRQF_TRIGGER_RISING,
1092 BMG160_IRQ_NAME,
1093 indio_dev);
1094 if (ret)
1095 return ret;
1096
1097 data->dready_trig = devm_iio_trigger_alloc(dev,
1098 "%s-dev%d",
1099 indio_dev->name,
1100 indio_dev->id);
1101 if (!data->dready_trig)
1102 return -ENOMEM;
1103
1104 data->motion_trig = devm_iio_trigger_alloc(dev,
1105 "%s-any-motion-dev%d",
1106 indio_dev->name,
1107 indio_dev->id);
1108 if (!data->motion_trig)
1109 return -ENOMEM;
1110
1111 data->dready_trig->dev.parent = dev;
1112 data->dready_trig->ops = &bmg160_trigger_ops;
1113 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
1114 ret = iio_trigger_register(data->dready_trig);
1115 if (ret)
1116 return ret;
1117
1118 data->motion_trig->dev.parent = dev;
1119 data->motion_trig->ops = &bmg160_trigger_ops;
1120 iio_trigger_set_drvdata(data->motion_trig, indio_dev);
1121 ret = iio_trigger_register(data->motion_trig);
1122 if (ret) {
1123 data->motion_trig = NULL;
1124 goto err_trigger_unregister;
1125 }
1126 }
1127
1128 ret = iio_triggered_buffer_setup(indio_dev,
1129 iio_pollfunc_store_time,
1130 bmg160_trigger_handler,
1131 &bmg160_buffer_setup_ops);
1132 if (ret < 0) {
1133 dev_err(dev,
1134 "iio triggered buffer setup failed\n");
1135 goto err_trigger_unregister;
1136 }
1137
1138 ret = pm_runtime_set_active(dev);
1139 if (ret)
1140 goto err_buffer_cleanup;
1141
1142 pm_runtime_enable(dev);
1143 pm_runtime_set_autosuspend_delay(dev,
1144 BMG160_AUTO_SUSPEND_DELAY_MS);
1145 pm_runtime_use_autosuspend(dev);
1146
1147 ret = iio_device_register(indio_dev);
1148 if (ret < 0) {
1149 dev_err(dev, "unable to register iio device\n");
1150 goto err_buffer_cleanup;
1151 }
1152
1153 return 0;
1154
1155 err_buffer_cleanup:
1156 iio_triggered_buffer_cleanup(indio_dev);
1157 err_trigger_unregister:
1158 if (data->dready_trig)
1159 iio_trigger_unregister(data->dready_trig);
1160 if (data->motion_trig)
1161 iio_trigger_unregister(data->motion_trig);
1162
1163 return ret;
1164 }
1165 EXPORT_SYMBOL_GPL(bmg160_core_probe);
1166
1167 void bmg160_core_remove(struct device *dev)
1168 {
1169 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1170 struct bmg160_data *data = iio_priv(indio_dev);
1171
1172 iio_device_unregister(indio_dev);
1173
1174 pm_runtime_disable(dev);
1175 pm_runtime_set_suspended(dev);
1176 pm_runtime_put_noidle(dev);
1177
1178 iio_triggered_buffer_cleanup(indio_dev);
1179
1180 if (data->dready_trig) {
1181 iio_trigger_unregister(data->dready_trig);
1182 iio_trigger_unregister(data->motion_trig);
1183 }
1184
1185 mutex_lock(&data->mutex);
1186 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND);
1187 mutex_unlock(&data->mutex);
1188 }
1189 EXPORT_SYMBOL_GPL(bmg160_core_remove);
1190
1191 #ifdef CONFIG_PM_SLEEP
1192 static int bmg160_suspend(struct device *dev)
1193 {
1194 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1195 struct bmg160_data *data = iio_priv(indio_dev);
1196
1197 mutex_lock(&data->mutex);
1198 bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1199 mutex_unlock(&data->mutex);
1200
1201 return 0;
1202 }
1203
1204 static int bmg160_resume(struct device *dev)
1205 {
1206 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1207 struct bmg160_data *data = iio_priv(indio_dev);
1208
1209 mutex_lock(&data->mutex);
1210 if (data->dready_trigger_on || data->motion_trigger_on ||
1211 data->ev_enable_state)
1212 bmg160_set_mode(data, BMG160_MODE_NORMAL);
1213 mutex_unlock(&data->mutex);
1214
1215 return 0;
1216 }
1217 #endif
1218
1219 #ifdef CONFIG_PM
1220 static int bmg160_runtime_suspend(struct device *dev)
1221 {
1222 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1223 struct bmg160_data *data = iio_priv(indio_dev);
1224 int ret;
1225
1226 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1227 if (ret < 0) {
1228 dev_err(dev, "set mode failed\n");
1229 return -EAGAIN;
1230 }
1231
1232 return 0;
1233 }
1234
1235 static int bmg160_runtime_resume(struct device *dev)
1236 {
1237 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1238 struct bmg160_data *data = iio_priv(indio_dev);
1239 int ret;
1240
1241 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
1242 if (ret < 0)
1243 return ret;
1244
1245 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS);
1246
1247 return 0;
1248 }
1249 #endif
1250
1251 const struct dev_pm_ops bmg160_pm_ops = {
1252 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume)
1253 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend,
1254 bmg160_runtime_resume, NULL)
1255 };
1256 EXPORT_SYMBOL_GPL(bmg160_pm_ops);
1257
1258 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1259 MODULE_LICENSE("GPL v2");
1260 MODULE_DESCRIPTION("BMG160 Gyro driver");
Linux with added FPC-III support