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perf bench futex: Cache align the worker struct
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-esdhc-imx.c
blob1f54fd8755c8e026fd8fb99f7fdb1cbc154acc87
1 /*
2 * Freescale eSDHC i.MX controller driver for the platform bus.
3 *
4 * derived from the OF-version.
5 *
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <kernel@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14 #include <linux/io.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_data/mmc-esdhc-imx.h>
30 #include <linux/pm_runtime.h>
31 #include "sdhci-pltfm.h"
32 #include "sdhci-esdhc.h"
33
34 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
35 #define ESDHC_CTRL_D3CD 0x08
36 #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
37 /* VENDOR SPEC register */
38 #define ESDHC_VENDOR_SPEC 0xc0
39 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
40 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
41 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
42 #define ESDHC_WTMK_LVL 0x44
43 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
44 #define ESDHC_MIX_CTRL 0x48
45 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
46 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
47 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
48 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
49 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
50 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
51 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
52 /* Bits 3 and 6 are not SDHCI standard definitions */
53 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
54 /* Tuning bits */
55 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
56
57 /* dll control register */
58 #define ESDHC_DLL_CTRL 0x60
59 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
60 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
61
62 /* tune control register */
63 #define ESDHC_TUNE_CTRL_STATUS 0x68
64 #define ESDHC_TUNE_CTRL_STEP 1
65 #define ESDHC_TUNE_CTRL_MIN 0
66 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
67
68 /* strobe dll register */
69 #define ESDHC_STROBE_DLL_CTRL 0x70
70 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
71 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
72 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
73
74 #define ESDHC_STROBE_DLL_STATUS 0x74
75 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
76 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
77
78 #define ESDHC_TUNING_CTRL 0xcc
79 #define ESDHC_STD_TUNING_EN (1 << 24)
80 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
81 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
82 #define ESDHC_TUNING_START_TAP_MASK 0xff
83 #define ESDHC_TUNING_STEP_MASK 0x00070000
84 #define ESDHC_TUNING_STEP_SHIFT 16
85
86 /* pinctrl state */
87 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
88 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
89
90 /*
91 * Our interpretation of the SDHCI_HOST_CONTROL register
92 */
93 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
94 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
95 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
96
97 /*
98 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
99 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
100 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
101 * Define this macro DMA error INT for fsl eSDHC
102 */
103 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
104
105 /*
106 * The CMDTYPE of the CMD register (offset 0xE) should be set to
107 * "11" when the STOP CMD12 is issued on imx53 to abort one
108 * open ended multi-blk IO. Otherwise the TC INT wouldn't
109 * be generated.
110 * In exact block transfer, the controller doesn't complete the
111 * operations automatically as required at the end of the
112 * transfer and remains on hold if the abort command is not sent.
113 * As a result, the TC flag is not asserted and SW received timeout
114 * exeception. Bit1 of Vendor Spec registor is used to fix it.
115 */
116 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
117 /*
118 * The flag enables the workaround for ESDHC errata ENGcm07207 which
119 * affects i.MX25 and i.MX35.
120 */
121 #define ESDHC_FLAG_ENGCM07207 BIT(2)
122 /*
123 * The flag tells that the ESDHC controller is an USDHC block that is
124 * integrated on the i.MX6 series.
125 */
126 #define ESDHC_FLAG_USDHC BIT(3)
127 /* The IP supports manual tuning process */
128 #define ESDHC_FLAG_MAN_TUNING BIT(4)
129 /* The IP supports standard tuning process */
130 #define ESDHC_FLAG_STD_TUNING BIT(5)
131 /* The IP has SDHCI_CAPABILITIES_1 register */
132 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
133 /*
134 * The IP has errata ERR004536
135 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
136 * when reading data from the card
137 */
138 #define ESDHC_FLAG_ERR004536 BIT(7)
139 /* The IP supports HS200 mode */
140 #define ESDHC_FLAG_HS200 BIT(8)
141 /* The IP supports HS400 mode */
142 #define ESDHC_FLAG_HS400 BIT(9)
143
144 /* A higher clock ferquency than this rate requires strobell dll control */
145 #define ESDHC_STROBE_DLL_CLK_FREQ 100000000
146
147 struct esdhc_soc_data {
148 u32 flags;
149 };
150
151 static struct esdhc_soc_data esdhc_imx25_data = {
152 .flags = ESDHC_FLAG_ENGCM07207,
153 };
154
155 static struct esdhc_soc_data esdhc_imx35_data = {
156 .flags = ESDHC_FLAG_ENGCM07207,
157 };
158
159 static struct esdhc_soc_data esdhc_imx51_data = {
160 .flags = 0,
161 };
162
163 static struct esdhc_soc_data esdhc_imx53_data = {
164 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
165 };
166
167 static struct esdhc_soc_data usdhc_imx6q_data = {
168 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
169 };
170
171 static struct esdhc_soc_data usdhc_imx6sl_data = {
172 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
173 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
174 | ESDHC_FLAG_HS200,
175 };
176
177 static struct esdhc_soc_data usdhc_imx6sx_data = {
178 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
179 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
180 };
181
182 static struct esdhc_soc_data usdhc_imx7d_data = {
183 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
184 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
185 | ESDHC_FLAG_HS400,
186 };
187
188 struct pltfm_imx_data {
189 u32 scratchpad;
190 struct pinctrl *pinctrl;
191 struct pinctrl_state *pins_default;
192 struct pinctrl_state *pins_100mhz;
193 struct pinctrl_state *pins_200mhz;
194 const struct esdhc_soc_data *socdata;
195 struct esdhc_platform_data boarddata;
196 struct clk *clk_ipg;
197 struct clk *clk_ahb;
198 struct clk *clk_per;
199 enum {
200 NO_CMD_PENDING, /* no multiblock command pending*/
201 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
202 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
203 } multiblock_status;
204 u32 is_ddr;
205 };
206
207 static const struct platform_device_id imx_esdhc_devtype[] = {
208 {
209 .name = "sdhci-esdhc-imx25",
210 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
211 }, {
212 .name = "sdhci-esdhc-imx35",
213 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
214 }, {
215 .name = "sdhci-esdhc-imx51",
216 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
217 }, {
218 /* sentinel */
219 }
220 };
221 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
222
223 static const struct of_device_id imx_esdhc_dt_ids[] = {
224 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
225 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
226 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
227 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
228 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
229 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
230 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
231 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
232 { /* sentinel */ }
233 };
234 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
235
236 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
237 {
238 return data->socdata == &esdhc_imx25_data;
239 }
240
241 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
242 {
243 return data->socdata == &esdhc_imx53_data;
244 }
245
246 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
247 {
248 return data->socdata == &usdhc_imx6q_data;
249 }
250
251 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
252 {
253 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
254 }
255
256 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
257 {
258 void __iomem *base = host->ioaddr + (reg & ~0x3);
259 u32 shift = (reg & 0x3) * 8;
260
261 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
262 }
263
264 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
265 {
266 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
267 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
268 u32 val = readl(host->ioaddr + reg);
269
270 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
271 u32 fsl_prss = val;
272 /* save the least 20 bits */
273 val = fsl_prss & 0x000FFFFF;
274 /* move dat[0-3] bits */
275 val |= (fsl_prss & 0x0F000000) >> 4;
276 /* move cmd line bit */
277 val |= (fsl_prss & 0x00800000) << 1;
278 }
279
280 if (unlikely(reg == SDHCI_CAPABILITIES)) {
281 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
282 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
283 val &= 0xffff0000;
284
285 /* In FSL esdhc IC module, only bit20 is used to indicate the
286 * ADMA2 capability of esdhc, but this bit is messed up on
287 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
288 * don't actually support ADMA2). So set the BROKEN_ADMA
289 * uirk on MX25/35 platforms.
290 */
291
292 if (val & SDHCI_CAN_DO_ADMA1) {
293 val &= ~SDHCI_CAN_DO_ADMA1;
294 val |= SDHCI_CAN_DO_ADMA2;
295 }
296 }
297
298 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
299 if (esdhc_is_usdhc(imx_data)) {
300 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
301 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
302 else
303 /* imx6q/dl does not have cap_1 register, fake one */
304 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
305 | SDHCI_SUPPORT_SDR50
306 | SDHCI_USE_SDR50_TUNING
307 | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
308
309 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
310 val |= SDHCI_SUPPORT_HS400;
311 }
312 }
313
314 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
315 val = 0;
316 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
317 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
318 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
319 }
320
321 if (unlikely(reg == SDHCI_INT_STATUS)) {
322 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
323 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
324 val |= SDHCI_INT_ADMA_ERROR;
325 }
326
327 /*
328 * mask off the interrupt we get in response to the manually
329 * sent CMD12
330 */
331 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
332 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
333 val &= ~SDHCI_INT_RESPONSE;
334 writel(SDHCI_INT_RESPONSE, host->ioaddr +
335 SDHCI_INT_STATUS);
336 imx_data->multiblock_status = NO_CMD_PENDING;
337 }
338 }
339
340 return val;
341 }
342
343 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
344 {
345 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
346 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
347 u32 data;
348
349 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
350 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
351 /*
352 * Clear and then set D3CD bit to avoid missing the
353 * card interrupt. This is a eSDHC controller problem
354 * so we need to apply the following workaround: clear
355 * and set D3CD bit will make eSDHC re-sample the card
356 * interrupt. In case a card interrupt was lost,
357 * re-sample it by the following steps.
358 */
359 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
360 data &= ~ESDHC_CTRL_D3CD;
361 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
362 data |= ESDHC_CTRL_D3CD;
363 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
364 }
365
366 if (val & SDHCI_INT_ADMA_ERROR) {
367 val &= ~SDHCI_INT_ADMA_ERROR;
368 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
369 }
370 }
371
372 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
373 && (reg == SDHCI_INT_STATUS)
374 && (val & SDHCI_INT_DATA_END))) {
375 u32 v;
376 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
377 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
378 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
379
380 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
381 {
382 /* send a manual CMD12 with RESPTYP=none */
383 data = MMC_STOP_TRANSMISSION << 24 |
384 SDHCI_CMD_ABORTCMD << 16;
385 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
386 imx_data->multiblock_status = WAIT_FOR_INT;
387 }
388 }
389
390 writel(val, host->ioaddr + reg);
391 }
392
393 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
394 {
395 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
396 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
397 u16 ret = 0;
398 u32 val;
399
400 if (unlikely(reg == SDHCI_HOST_VERSION)) {
401 reg ^= 2;
402 if (esdhc_is_usdhc(imx_data)) {
403 /*
404 * The usdhc register returns a wrong host version.
405 * Correct it here.
406 */
407 return SDHCI_SPEC_300;
408 }
409 }
410
411 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
412 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
413 if (val & ESDHC_VENDOR_SPEC_VSELECT)
414 ret |= SDHCI_CTRL_VDD_180;
415
416 if (esdhc_is_usdhc(imx_data)) {
417 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
418 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
419 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
420 /* the std tuning bits is in ACMD12_ERR for imx6sl */
421 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
422 }
423
424 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
425 ret |= SDHCI_CTRL_EXEC_TUNING;
426 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
427 ret |= SDHCI_CTRL_TUNED_CLK;
428
429 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
430
431 return ret;
432 }
433
434 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
435 if (esdhc_is_usdhc(imx_data)) {
436 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
437 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
438 /* Swap AC23 bit */
439 if (m & ESDHC_MIX_CTRL_AC23EN) {
440 ret &= ~ESDHC_MIX_CTRL_AC23EN;
441 ret |= SDHCI_TRNS_AUTO_CMD23;
442 }
443 } else {
444 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
445 }
446
447 return ret;
448 }
449
450 return readw(host->ioaddr + reg);
451 }
452
453 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
454 {
455 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
456 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
457 u32 new_val = 0;
458
459 switch (reg) {
460 case SDHCI_CLOCK_CONTROL:
461 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
462 if (val & SDHCI_CLOCK_CARD_EN)
463 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
464 else
465 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
466 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
467 return;
468 case SDHCI_HOST_CONTROL2:
469 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
470 if (val & SDHCI_CTRL_VDD_180)
471 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
472 else
473 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
474 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
475 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
476 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
477 if (val & SDHCI_CTRL_TUNED_CLK) {
478 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
479 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
480 } else {
481 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
482 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
483 }
484 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
485 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
486 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
487 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
488 if (val & SDHCI_CTRL_TUNED_CLK) {
489 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
490 } else {
491 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
492 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
493 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
494 }
495
496 if (val & SDHCI_CTRL_EXEC_TUNING) {
497 v |= ESDHC_MIX_CTRL_EXE_TUNE;
498 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
499 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
500 } else {
501 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
502 }
503
504 writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
505 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
506 }
507 return;
508 case SDHCI_TRANSFER_MODE:
509 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
510 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
511 && (host->cmd->data->blocks > 1)
512 && (host->cmd->data->flags & MMC_DATA_READ)) {
513 u32 v;
514 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
515 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
516 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
517 }
518
519 if (esdhc_is_usdhc(imx_data)) {
520 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
521 /* Swap AC23 bit */
522 if (val & SDHCI_TRNS_AUTO_CMD23) {
523 val &= ~SDHCI_TRNS_AUTO_CMD23;
524 val |= ESDHC_MIX_CTRL_AC23EN;
525 }
526 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
527 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
528 } else {
529 /*
530 * Postpone this write, we must do it together with a
531 * command write that is down below.
532 */
533 imx_data->scratchpad = val;
534 }
535 return;
536 case SDHCI_COMMAND:
537 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
538 val |= SDHCI_CMD_ABORTCMD;
539
540 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
541 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
542 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
543
544 if (esdhc_is_usdhc(imx_data))
545 writel(val << 16,
546 host->ioaddr + SDHCI_TRANSFER_MODE);
547 else
548 writel(val << 16 | imx_data->scratchpad,
549 host->ioaddr + SDHCI_TRANSFER_MODE);
550 return;
551 case SDHCI_BLOCK_SIZE:
552 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
553 break;
554 }
555 esdhc_clrset_le(host, 0xffff, val, reg);
556 }
557
558 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
559 {
560 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
561 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
562 u32 new_val;
563 u32 mask;
564
565 switch (reg) {
566 case SDHCI_POWER_CONTROL:
567 /*
568 * FSL put some DMA bits here
569 * If your board has a regulator, code should be here
570 */
571 return;
572 case SDHCI_HOST_CONTROL:
573 /* FSL messed up here, so we need to manually compose it. */
574 new_val = val & SDHCI_CTRL_LED;
575 /* ensure the endianness */
576 new_val |= ESDHC_HOST_CONTROL_LE;
577 /* bits 8&9 are reserved on mx25 */
578 if (!is_imx25_esdhc(imx_data)) {
579 /* DMA mode bits are shifted */
580 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
581 }
582
583 /*
584 * Do not touch buswidth bits here. This is done in
585 * esdhc_pltfm_bus_width.
586 * Do not touch the D3CD bit either which is used for the
587 * SDIO interrupt errata workaround.
588 */
589 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
590
591 esdhc_clrset_le(host, mask, new_val, reg);
592 return;
593 }
594 esdhc_clrset_le(host, 0xff, val, reg);
595
596 /*
597 * The esdhc has a design violation to SDHC spec which tells
598 * that software reset should not affect card detection circuit.
599 * But esdhc clears its SYSCTL register bits [0..2] during the
600 * software reset. This will stop those clocks that card detection
601 * circuit relies on. To work around it, we turn the clocks on back
602 * to keep card detection circuit functional.
603 */
604 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
605 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
606 /*
607 * The reset on usdhc fails to clear MIX_CTRL register.
608 * Do it manually here.
609 */
610 if (esdhc_is_usdhc(imx_data)) {
611 /* the tuning bits should be kept during reset */
612 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
613 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
614 host->ioaddr + ESDHC_MIX_CTRL);
615 imx_data->is_ddr = 0;
616 }
617 }
618 }
619
620 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
621 {
622 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
623
624 return pltfm_host->clock;
625 }
626
627 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
628 {
629 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
630
631 return pltfm_host->clock / 256 / 16;
632 }
633
634 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
635 unsigned int clock)
636 {
637 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
638 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
639 unsigned int host_clock = pltfm_host->clock;
640 int pre_div = 2;
641 int div = 1;
642 u32 temp, val;
643
644 if (clock == 0) {
645 host->mmc->actual_clock = 0;
646
647 if (esdhc_is_usdhc(imx_data)) {
648 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
649 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
650 host->ioaddr + ESDHC_VENDOR_SPEC);
651 }
652 return;
653 }
654
655 if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
656 pre_div = 1;
657
658 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
659 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
660 | ESDHC_CLOCK_MASK);
661 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
662
663 while (host_clock / pre_div / 16 > clock && pre_div < 256)
664 pre_div *= 2;
665
666 while (host_clock / pre_div / div > clock && div < 16)
667 div++;
668
669 host->mmc->actual_clock = host_clock / pre_div / div;
670 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
671 clock, host->mmc->actual_clock);
672
673 if (imx_data->is_ddr)
674 pre_div >>= 2;
675 else
676 pre_div >>= 1;
677 div--;
678
679 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
680 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
681 | (div << ESDHC_DIVIDER_SHIFT)
682 | (pre_div << ESDHC_PREDIV_SHIFT));
683 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
684
685 if (esdhc_is_usdhc(imx_data)) {
686 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
687 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
688 host->ioaddr + ESDHC_VENDOR_SPEC);
689 }
690
691 mdelay(1);
692 }
693
694 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
695 {
696 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
697 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
698 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
699
700 switch (boarddata->wp_type) {
701 case ESDHC_WP_GPIO:
702 return mmc_gpio_get_ro(host->mmc);
703 case ESDHC_WP_CONTROLLER:
704 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
705 SDHCI_WRITE_PROTECT);
706 case ESDHC_WP_NONE:
707 break;
708 }
709
710 return -ENOSYS;
711 }
712
713 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
714 {
715 u32 ctrl;
716
717 switch (width) {
718 case MMC_BUS_WIDTH_8:
719 ctrl = ESDHC_CTRL_8BITBUS;
720 break;
721 case MMC_BUS_WIDTH_4:
722 ctrl = ESDHC_CTRL_4BITBUS;
723 break;
724 default:
725 ctrl = 0;
726 break;
727 }
728
729 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
730 SDHCI_HOST_CONTROL);
731 }
732
733 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
734 {
735 u32 reg;
736
737 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
738 mdelay(1);
739
740 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
741 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
742 ESDHC_MIX_CTRL_FBCLK_SEL;
743 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
744 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
745 dev_dbg(mmc_dev(host->mmc),
746 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
747 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
748 }
749
750 static void esdhc_post_tuning(struct sdhci_host *host)
751 {
752 u32 reg;
753
754 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
755 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
756 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
757 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
758 }
759
760 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
761 {
762 int min, max, avg, ret;
763
764 /* find the mininum delay first which can pass tuning */
765 min = ESDHC_TUNE_CTRL_MIN;
766 while (min < ESDHC_TUNE_CTRL_MAX) {
767 esdhc_prepare_tuning(host, min);
768 if (!mmc_send_tuning(host->mmc, opcode, NULL))
769 break;
770 min += ESDHC_TUNE_CTRL_STEP;
771 }
772
773 /* find the maxinum delay which can not pass tuning */
774 max = min + ESDHC_TUNE_CTRL_STEP;
775 while (max < ESDHC_TUNE_CTRL_MAX) {
776 esdhc_prepare_tuning(host, max);
777 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
778 max -= ESDHC_TUNE_CTRL_STEP;
779 break;
780 }
781 max += ESDHC_TUNE_CTRL_STEP;
782 }
783
784 /* use average delay to get the best timing */
785 avg = (min + max) / 2;
786 esdhc_prepare_tuning(host, avg);
787 ret = mmc_send_tuning(host->mmc, opcode, NULL);
788 esdhc_post_tuning(host);
789
790 dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
791 ret ? "failed" : "passed", avg, ret);
792
793 return ret;
794 }
795
796 static int esdhc_change_pinstate(struct sdhci_host *host,
797 unsigned int uhs)
798 {
799 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
800 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
801 struct pinctrl_state *pinctrl;
802
803 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
804
805 if (IS_ERR(imx_data->pinctrl) ||
806 IS_ERR(imx_data->pins_default) ||
807 IS_ERR(imx_data->pins_100mhz) ||
808 IS_ERR(imx_data->pins_200mhz))
809 return -EINVAL;
810
811 switch (uhs) {
812 case MMC_TIMING_UHS_SDR50:
813 pinctrl = imx_data->pins_100mhz;
814 break;
815 case MMC_TIMING_UHS_SDR104:
816 case MMC_TIMING_MMC_HS200:
817 case MMC_TIMING_MMC_HS400:
818 pinctrl = imx_data->pins_200mhz;
819 break;
820 default:
821 /* back to default state for other legacy timing */
822 pinctrl = imx_data->pins_default;
823 }
824
825 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
826 }
827
828 /*
829 * For HS400 eMMC, there is a data_strobe line, this signal is generated
830 * by the device and used for data output and CRC status response output
831 * in HS400 mode. The frequency of this signal follows the frequency of
832 * CLK generated by host. Host receive the data which is aligned to the
833 * edge of data_strobe line. Due to the time delay between CLK line and
834 * data_strobe line, if the delay time is larger than one clock cycle,
835 * then CLK and data_strobe line will misaligned, read error shows up.
836 * So when the CLK is higher than 100MHz, each clock cycle is short enough,
837 * host should config the delay target.
838 */
839 static void esdhc_set_strobe_dll(struct sdhci_host *host)
840 {
841 u32 v;
842
843 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
844 /* disable clock before enabling strobe dll */
845 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
846 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
847 host->ioaddr + ESDHC_VENDOR_SPEC);
848
849 /* force a reset on strobe dll */
850 writel(ESDHC_STROBE_DLL_CTRL_RESET,
851 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
852 /*
853 * enable strobe dll ctrl and adjust the delay target
854 * for the uSDHC loopback read clock
855 */
856 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
857 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
858 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
859 /* wait 1us to make sure strobe dll status register stable */
860 udelay(1);
861 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
862 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
863 dev_warn(mmc_dev(host->mmc),
864 "warning! HS400 strobe DLL status REF not lock!\n");
865 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
866 dev_warn(mmc_dev(host->mmc),
867 "warning! HS400 strobe DLL status SLV not lock!\n");
868 }
869 }
870
871 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
872 {
873 u32 m;
874 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
875 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
876 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
877
878 /* disable ddr mode and disable HS400 mode */
879 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
880 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
881 imx_data->is_ddr = 0;
882
883 switch (timing) {
884 case MMC_TIMING_UHS_SDR12:
885 case MMC_TIMING_UHS_SDR25:
886 case MMC_TIMING_UHS_SDR50:
887 case MMC_TIMING_UHS_SDR104:
888 case MMC_TIMING_MMC_HS200:
889 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
890 break;
891 case MMC_TIMING_UHS_DDR50:
892 case MMC_TIMING_MMC_DDR52:
893 m |= ESDHC_MIX_CTRL_DDREN;
894 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
895 imx_data->is_ddr = 1;
896 if (boarddata->delay_line) {
897 u32 v;
898 v = boarddata->delay_line <<
899 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
900 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
901 if (is_imx53_esdhc(imx_data))
902 v <<= 1;
903 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
904 }
905 break;
906 case MMC_TIMING_MMC_HS400:
907 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
908 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
909 imx_data->is_ddr = 1;
910 /* update clock after enable DDR for strobe DLL lock */
911 host->ops->set_clock(host, host->clock);
912 esdhc_set_strobe_dll(host);
913 break;
914 }
915
916 esdhc_change_pinstate(host, timing);
917 }
918
919 static void esdhc_reset(struct sdhci_host *host, u8 mask)
920 {
921 sdhci_reset(host, mask);
922
923 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
924 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
925 }
926
927 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
928 {
929 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
930 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
931
932 /* Doc Errata: the uSDHC actual maximum timeout count is 1 << 29 */
933 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
934 }
935
936 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
937 {
938 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
939 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
940
941 /* use maximum timeout counter */
942 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
943 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
944 SDHCI_TIMEOUT_CONTROL);
945 }
946
947 static struct sdhci_ops sdhci_esdhc_ops = {
948 .read_l = esdhc_readl_le,
949 .read_w = esdhc_readw_le,
950 .write_l = esdhc_writel_le,
951 .write_w = esdhc_writew_le,
952 .write_b = esdhc_writeb_le,
953 .set_clock = esdhc_pltfm_set_clock,
954 .get_max_clock = esdhc_pltfm_get_max_clock,
955 .get_min_clock = esdhc_pltfm_get_min_clock,
956 .get_max_timeout_count = esdhc_get_max_timeout_count,
957 .get_ro = esdhc_pltfm_get_ro,
958 .set_timeout = esdhc_set_timeout,
959 .set_bus_width = esdhc_pltfm_set_bus_width,
960 .set_uhs_signaling = esdhc_set_uhs_signaling,
961 .reset = esdhc_reset,
962 };
963
964 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
965 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
966 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
967 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
968 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
969 .ops = &sdhci_esdhc_ops,
970 };
971
972 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
973 {
974 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
975 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
976 int tmp;
977
978 if (esdhc_is_usdhc(imx_data)) {
979 /*
980 * The imx6q ROM code will change the default watermark
981 * level setting to something insane. Change it back here.
982 */
983 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
984
985 /*
986 * ROM code will change the bit burst_length_enable setting
987 * to zero if this usdhc is choosed to boot system. Change
988 * it back here, otherwise it will impact the performance a
989 * lot. This bit is used to enable/disable the burst length
990 * for the external AHB2AXI bridge, it's usefully especially
991 * for INCR transfer because without burst length indicator,
992 * the AHB2AXI bridge does not know the burst length in
993 * advance. And without burst length indicator, AHB INCR
994 * transfer can only be converted to singles on the AXI side.
995 */
996 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
997 | ESDHC_BURST_LEN_EN_INCR,
998 host->ioaddr + SDHCI_HOST_CONTROL);
999 /*
1000 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1001 * TO1.1, it's harmless for MX6SL
1002 */
1003 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1004 host->ioaddr + 0x6c);
1005
1006 /* disable DLL_CTRL delay line settings */
1007 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1008
1009 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1010 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1011 tmp |= ESDHC_STD_TUNING_EN |
1012 ESDHC_TUNING_START_TAP_DEFAULT;
1013 if (imx_data->boarddata.tuning_start_tap) {
1014 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1015 tmp |= imx_data->boarddata.tuning_start_tap;
1016 }
1017
1018 if (imx_data->boarddata.tuning_step) {
1019 tmp &= ~ESDHC_TUNING_STEP_MASK;
1020 tmp |= imx_data->boarddata.tuning_step
1021 << ESDHC_TUNING_STEP_SHIFT;
1022 }
1023 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1024 }
1025 }
1026 }
1027
1028 #ifdef CONFIG_OF
1029 static int
1030 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1031 struct sdhci_host *host,
1032 struct pltfm_imx_data *imx_data)
1033 {
1034 struct device_node *np = pdev->dev.of_node;
1035 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1036 int ret;
1037
1038 if (of_get_property(np, "fsl,wp-controller", NULL))
1039 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1040
1041 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1042 if (gpio_is_valid(boarddata->wp_gpio))
1043 boarddata->wp_type = ESDHC_WP_GPIO;
1044
1045 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1046 of_property_read_u32(np, "fsl,tuning-start-tap",
1047 &boarddata->tuning_start_tap);
1048
1049 if (of_find_property(np, "no-1-8-v", NULL))
1050 boarddata->support_vsel = false;
1051 else
1052 boarddata->support_vsel = true;
1053
1054 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1055 boarddata->delay_line = 0;
1056
1057 mmc_of_parse_voltage(np, &host->ocr_mask);
1058
1059 /* sdr50 and sdr104 needs work on 1.8v signal voltage */
1060 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
1061 !IS_ERR(imx_data->pins_default)) {
1062 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1063 ESDHC_PINCTRL_STATE_100MHZ);
1064 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1065 ESDHC_PINCTRL_STATE_200MHZ);
1066 if (IS_ERR(imx_data->pins_100mhz) ||
1067 IS_ERR(imx_data->pins_200mhz)) {
1068 dev_warn(mmc_dev(host->mmc),
1069 "could not get ultra high speed state, work on normal mode\n");
1070 /*
1071 * fall back to not support uhs by specify no 1.8v quirk
1072 */
1073 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1074 }
1075 } else {
1076 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1077 }
1078
1079 /* call to generic mmc_of_parse to support additional capabilities */
1080 ret = mmc_of_parse(host->mmc);
1081 if (ret)
1082 return ret;
1083
1084 if (mmc_gpio_get_cd(host->mmc) >= 0)
1085 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1086
1087 return 0;
1088 }
1089 #else
1090 static inline int
1091 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1092 struct sdhci_host *host,
1093 struct pltfm_imx_data *imx_data)
1094 {
1095 return -ENODEV;
1096 }
1097 #endif
1098
1099 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1100 struct sdhci_host *host,
1101 struct pltfm_imx_data *imx_data)
1102 {
1103 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1104 int err;
1105
1106 if (!host->mmc->parent->platform_data) {
1107 dev_err(mmc_dev(host->mmc), "no board data!\n");
1108 return -EINVAL;
1109 }
1110
1111 imx_data->boarddata = *((struct esdhc_platform_data *)
1112 host->mmc->parent->platform_data);
1113 /* write_protect */
1114 if (boarddata->wp_type == ESDHC_WP_GPIO) {
1115 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1116 if (err) {
1117 dev_err(mmc_dev(host->mmc),
1118 "failed to request write-protect gpio!\n");
1119 return err;
1120 }
1121 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1122 }
1123
1124 /* card_detect */
1125 switch (boarddata->cd_type) {
1126 case ESDHC_CD_GPIO:
1127 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1128 if (err) {
1129 dev_err(mmc_dev(host->mmc),
1130 "failed to request card-detect gpio!\n");
1131 return err;
1132 }
1133 /* fall through */
1134
1135 case ESDHC_CD_CONTROLLER:
1136 /* we have a working card_detect back */
1137 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1138 break;
1139
1140 case ESDHC_CD_PERMANENT:
1141 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1142 break;
1143
1144 case ESDHC_CD_NONE:
1145 break;
1146 }
1147
1148 switch (boarddata->max_bus_width) {
1149 case 8:
1150 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1151 break;
1152 case 4:
1153 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1154 break;
1155 case 1:
1156 default:
1157 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1158 break;
1159 }
1160
1161 return 0;
1162 }
1163
1164 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1165 {
1166 const struct of_device_id *of_id =
1167 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1168 struct sdhci_pltfm_host *pltfm_host;
1169 struct sdhci_host *host;
1170 int err;
1171 struct pltfm_imx_data *imx_data;
1172
1173 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1174 sizeof(*imx_data));
1175 if (IS_ERR(host))
1176 return PTR_ERR(host);
1177
1178 pltfm_host = sdhci_priv(host);
1179
1180 imx_data = sdhci_pltfm_priv(pltfm_host);
1181
1182 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1183 pdev->id_entry->driver_data;
1184
1185 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1186 if (IS_ERR(imx_data->clk_ipg)) {
1187 err = PTR_ERR(imx_data->clk_ipg);
1188 goto free_sdhci;
1189 }
1190
1191 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1192 if (IS_ERR(imx_data->clk_ahb)) {
1193 err = PTR_ERR(imx_data->clk_ahb);
1194 goto free_sdhci;
1195 }
1196
1197 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1198 if (IS_ERR(imx_data->clk_per)) {
1199 err = PTR_ERR(imx_data->clk_per);
1200 goto free_sdhci;
1201 }
1202
1203 pltfm_host->clk = imx_data->clk_per;
1204 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1205 clk_prepare_enable(imx_data->clk_per);
1206 clk_prepare_enable(imx_data->clk_ipg);
1207 clk_prepare_enable(imx_data->clk_ahb);
1208
1209 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1210 if (IS_ERR(imx_data->pinctrl)) {
1211 err = PTR_ERR(imx_data->pinctrl);
1212 goto disable_clk;
1213 }
1214
1215 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1216 PINCTRL_STATE_DEFAULT);
1217 if (IS_ERR(imx_data->pins_default))
1218 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1219
1220 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1221 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1222 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1223 | SDHCI_QUIRK_BROKEN_ADMA;
1224
1225 if (esdhc_is_usdhc(imx_data)) {
1226 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1227 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1228 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1229 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1230
1231 /* clear tuning bits in case ROM has set it already */
1232 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1233 writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR);
1234 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1235 }
1236
1237 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1238 sdhci_esdhc_ops.platform_execute_tuning =
1239 esdhc_executing_tuning;
1240
1241 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1242 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1243
1244 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1245 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1246
1247 if (of_id)
1248 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1249 else
1250 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1251 if (err)
1252 goto disable_clk;
1253
1254 sdhci_esdhc_imx_hwinit(host);
1255
1256 err = sdhci_add_host(host);
1257 if (err)
1258 goto disable_clk;
1259
1260 pm_runtime_set_active(&pdev->dev);
1261 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1262 pm_runtime_use_autosuspend(&pdev->dev);
1263 pm_suspend_ignore_children(&pdev->dev, 1);
1264 pm_runtime_enable(&pdev->dev);
1265
1266 return 0;
1267
1268 disable_clk:
1269 clk_disable_unprepare(imx_data->clk_per);
1270 clk_disable_unprepare(imx_data->clk_ipg);
1271 clk_disable_unprepare(imx_data->clk_ahb);
1272 free_sdhci:
1273 sdhci_pltfm_free(pdev);
1274 return err;
1275 }
1276
1277 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1278 {
1279 struct sdhci_host *host = platform_get_drvdata(pdev);
1280 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1281 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1282 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1283
1284 pm_runtime_get_sync(&pdev->dev);
1285 pm_runtime_disable(&pdev->dev);
1286 pm_runtime_put_noidle(&pdev->dev);
1287
1288 sdhci_remove_host(host, dead);
1289
1290 clk_disable_unprepare(imx_data->clk_per);
1291 clk_disable_unprepare(imx_data->clk_ipg);
1292 clk_disable_unprepare(imx_data->clk_ahb);
1293
1294 sdhci_pltfm_free(pdev);
1295
1296 return 0;
1297 }
1298
1299 #ifdef CONFIG_PM_SLEEP
1300 static int sdhci_esdhc_suspend(struct device *dev)
1301 {
1302 struct sdhci_host *host = dev_get_drvdata(dev);
1303
1304 return sdhci_suspend_host(host);
1305 }
1306
1307 static int sdhci_esdhc_resume(struct device *dev)
1308 {
1309 struct sdhci_host *host = dev_get_drvdata(dev);
1310
1311 /* re-initialize hw state in case it's lost in low power mode */
1312 sdhci_esdhc_imx_hwinit(host);
1313
1314 return sdhci_resume_host(host);
1315 }
1316 #endif
1317
1318 #ifdef CONFIG_PM
1319 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1320 {
1321 struct sdhci_host *host = dev_get_drvdata(dev);
1322 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1323 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1324 int ret;
1325
1326 ret = sdhci_runtime_suspend_host(host);
1327
1328 if (!sdhci_sdio_irq_enabled(host)) {
1329 clk_disable_unprepare(imx_data->clk_per);
1330 clk_disable_unprepare(imx_data->clk_ipg);
1331 }
1332 clk_disable_unprepare(imx_data->clk_ahb);
1333
1334 return ret;
1335 }
1336
1337 static int sdhci_esdhc_runtime_resume(struct device *dev)
1338 {
1339 struct sdhci_host *host = dev_get_drvdata(dev);
1340 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1341 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1342
1343 if (!sdhci_sdio_irq_enabled(host)) {
1344 clk_prepare_enable(imx_data->clk_per);
1345 clk_prepare_enable(imx_data->clk_ipg);
1346 }
1347 clk_prepare_enable(imx_data->clk_ahb);
1348
1349 return sdhci_runtime_resume_host(host);
1350 }
1351 #endif
1352
1353 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1354 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1355 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1356 sdhci_esdhc_runtime_resume, NULL)
1357 };
1358
1359 static struct platform_driver sdhci_esdhc_imx_driver = {
1360 .driver = {
1361 .name = "sdhci-esdhc-imx",
1362 .of_match_table = imx_esdhc_dt_ids,
1363 .pm = &sdhci_esdhc_pmops,
1364 },
1365 .id_table = imx_esdhc_devtype,
1366 .probe = sdhci_esdhc_imx_probe,
1367 .remove = sdhci_esdhc_imx_remove,
1368 };
1369
1370 module_platform_driver(sdhci_esdhc_imx_driver);
1371
1372 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1373 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1374 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support