| blob | 838fe373cd6f73c61d98ceaab92bacc77af0d97a |
1 /*
2 * Broadcom Starfighter 2 switch register defines
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11 #ifndef __BCM_SF2_REGS_H
12 #define __BCM_SF2_REGS_H
14 /* Register set relative to 'REG' */
15 #define REG_SWITCH_CNTRL 0x00
16 #define MDIO_MASTER_SEL (1 << 0)
18 #define REG_SWITCH_STATUS 0x04
19 #define REG_DIR_DATA_WRITE 0x08
20 #define REG_DIR_DATA_READ 0x0C
22 #define REG_SWITCH_REVISION 0x18
23 #define SF2_REV_MASK 0xffff
24 #define SWITCH_TOP_REV_SHIFT 16
25 #define SWITCH_TOP_REV_MASK 0xffff
27 #define REG_PHY_REVISION 0x1C
28 #define PHY_REVISION_MASK 0xffff
30 #define REG_SPHY_CNTRL 0x2C
31 #define IDDQ_BIAS (1 << 0)
32 #define EXT_PWR_DOWN (1 << 1)
33 #define FORCE_DLL_EN (1 << 2)
34 #define IDDQ_GLOBAL_PWR (1 << 3)
35 #define CK25_DIS (1 << 4)
36 #define PHY_RESET (1 << 5)
37 #define PHY_PHYAD_SHIFT 8
38 #define PHY_PHYAD_MASK 0x1F
40 #define REG_RGMII_0_BASE 0x34
41 #define REG_RGMII_CNTRL 0x00
42 #define REG_RGMII_IB_STATUS 0x04
43 #define REG_RGMII_RX_CLOCK_DELAY_CNTRL 0x08
44 #define REG_RGMII_CNTRL_SIZE 0x0C
45 #define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_BASE + \
46 ((x) * REG_RGMII_CNTRL_SIZE))
47 /* Relative to REG_RGMII_CNTRL */
48 #define RGMII_MODE_EN (1 << 0)
49 #define ID_MODE_DIS (1 << 1)
50 #define PORT_MODE_SHIFT 2
51 #define INT_EPHY (0 << PORT_MODE_SHIFT)
52 #define INT_GPHY (1 << PORT_MODE_SHIFT)
53 #define EXT_EPHY (2 << PORT_MODE_SHIFT)
54 #define EXT_GPHY (3 << PORT_MODE_SHIFT)
55 #define EXT_REVMII (4 << PORT_MODE_SHIFT)
56 #define PORT_MODE_MASK 0x7
57 #define RVMII_REF_SEL (1 << 5)
58 #define RX_PAUSE_EN (1 << 6)
59 #define TX_PAUSE_EN (1 << 7)
60 #define TX_CLK_STOP_EN (1 << 8)
61 #define LPI_COUNT_SHIFT 9
62 #define LPI_COUNT_MASK 0x3F
64 #define REG_LED_CNTRL_BASE 0x90
65 #define REG_LED_CNTRL(x) (REG_LED_CNTRL_BASE + (x) * 4)
66 #define SPDLNK_SRC_SEL (1 << 24)
68 /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
69 #define INTRL2_CPU_STATUS 0x00
70 #define INTRL2_CPU_SET 0x04
71 #define INTRL2_CPU_CLEAR 0x08
72 #define INTRL2_CPU_MASK_STATUS 0x0c
73 #define INTRL2_CPU_MASK_SET 0x10
74 #define INTRL2_CPU_MASK_CLEAR 0x14
76 /* Shared INTRL2_0 and INTRL2_ interrupt sources macros */
77 #define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
78 #define P_LINK_DOWN_IRQ(x) (1 << (1 + (x)))
79 #define P_ENERGY_ON_IRQ(x) (1 << (2 + (x)))
80 #define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x)))
81 #define P_GPHY_IRQ(x) (1 << (4 + (x)))
82 #define P_NUM_IRQ 5
83 #define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \
84 P_LINK_DOWN_IRQ((x)) | \
85 P_ENERGY_ON_IRQ((x)) | \
86 P_ENERGY_OFF_IRQ((x)) | \
87 P_GPHY_IRQ((x)))
89 /* INTRL2_0 interrupt sources */
90 #define P0_IRQ_OFF 0
91 #define MEM_DOUBLE_IRQ (1 << 5)
92 #define EEE_LPI_IRQ (1 << 6)
93 #define P5_CPU_WAKE_IRQ (1 << 7)
94 #define P8_CPU_WAKE_IRQ (1 << 8)
95 #define P7_CPU_WAKE_IRQ (1 << 9)
96 #define IEEE1588_IRQ (1 << 10)
97 #define MDIO_ERR_IRQ (1 << 11)
98 #define MDIO_DONE_IRQ (1 << 12)
99 #define GISB_ERR_IRQ (1 << 13)
100 #define UBUS_ERR_IRQ (1 << 14)
101 #define FAILOVER_ON_IRQ (1 << 15)
102 #define FAILOVER_OFF_IRQ (1 << 16)
103 #define TCAM_SOFT_ERR_IRQ (1 << 17)
105 /* INTRL2_1 interrupt sources */
106 #define P7_IRQ_OFF 0
107 #define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ)
109 /* Register set relative to 'CORE' */
110 #define CORE_G_PCTL_PORT0 0x00000
111 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
112 #define CORE_IMP_CTL 0x00020
113 #define RX_DIS (1 << 0)
114 #define TX_DIS (1 << 1)
115 #define RX_BCST_EN (1 << 2)
116 #define RX_MCST_EN (1 << 3)
117 #define RX_UCST_EN (1 << 4)
119 #define CORE_SWMODE 0x0002c
120 #define SW_FWDG_MODE (1 << 0)
121 #define SW_FWDG_EN (1 << 1)
122 #define RTRY_LMT_DIS (1 << 2)
124 #define CORE_STS_OVERRIDE_IMP 0x00038
125 #define GMII_SPEED_UP_2G (1 << 6)
126 #define MII_SW_OR (1 << 7)
128 #define CORE_NEW_CTRL 0x00084
129 #define IP_MC (1 << 0)
130 #define OUTRANGEERR_DISCARD (1 << 1)
131 #define INRANGEERR_DISCARD (1 << 2)
132 #define CABLE_DIAG_LEN (1 << 3)
133 #define OVERRIDE_AUTO_PD_WAR (1 << 4)
134 #define EN_AUTO_PD_WAR (1 << 5)
135 #define UC_FWD_EN (1 << 6)
136 #define MC_FWD_EN (1 << 7)
138 #define CORE_SWITCH_CTRL 0x00088
139 #define MII_DUMB_FWDG_EN (1 << 6)
141 #define CORE_SFT_LRN_CTRL 0x000f8
142 #define SW_LEARN_CNTL(x) (1 << (x))
144 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
145 #define LINK_STS (1 << 0)
146 #define DUPLX_MODE (1 << 1)
147 #define SPEED_SHIFT 2
148 #define SPEED_MASK 0x3
149 #define RXFLOW_CNTL (1 << 4)
150 #define TXFLOW_CNTL (1 << 5)
151 #define SW_OVERRIDE (1 << 6)
153 #define CORE_WATCHDOG_CTRL 0x001e4
154 #define SOFTWARE_RESET (1 << 7)
155 #define EN_CHIP_RST (1 << 6)
156 #define EN_SW_RESET (1 << 4)
158 #define CORE_FAST_AGE_CTRL 0x00220
159 #define EN_FAST_AGE_STATIC (1 << 0)
160 #define EN_AGE_DYNAMIC (1 << 1)
161 #define EN_AGE_PORT (1 << 2)
162 #define EN_AGE_VLAN (1 << 3)
163 #define EN_AGE_SPT (1 << 4)
164 #define EN_AGE_MCAST (1 << 5)
165 #define FAST_AGE_STR_DONE (1 << 7)
167 #define CORE_FAST_AGE_PORT 0x00224
168 #define AGE_PORT_MASK 0xf
170 #define CORE_FAST_AGE_VID 0x00228
171 #define AGE_VID_MASK 0x3fff
173 #define CORE_LNKSTS 0x00400
174 #define LNK_STS_MASK 0x1ff
176 #define CORE_SPDSTS 0x00410
177 #define SPDSTS_10 0
178 #define SPDSTS_100 1
179 #define SPDSTS_1000 2
180 #define SPDSTS_SHIFT 2
181 #define SPDSTS_MASK 0x3
183 #define CORE_DUPSTS 0x00420
184 #define CORE_DUPSTS_MASK 0x1ff
186 #define CORE_PAUSESTS 0x00428
187 #define PAUSESTS_TX_PAUSE_SHIFT 9
189 #define CORE_GMNCFGCFG 0x0800
190 #define RST_MIB_CNT (1 << 0)
191 #define RXBPDU_EN (1 << 1)
193 #define CORE_IMP0_PRT_ID 0x0804
195 #define CORE_BRCM_HDR_CTRL 0x0080c
196 #define BRCM_HDR_EN_P8 (1 << 0)
197 #define BRCM_HDR_EN_P5 (1 << 1)
198 #define BRCM_HDR_EN_P7 (1 << 2)
200 #define CORE_RST_MIB_CNT_EN 0x0950
202 #define CORE_BRCM_HDR_RX_DIS 0x0980
203 #define CORE_BRCM_HDR_TX_DIS 0x0988
205 #define CORE_ARLA_VTBL_RWCTRL 0x1600
206 #define ARLA_VTBL_CMD_WRITE 0
207 #define ARLA_VTBL_CMD_READ 1
208 #define ARLA_VTBL_CMD_CLEAR 2
209 #define ARLA_VTBL_STDN (1 << 7)
211 #define CORE_ARLA_VTBL_ADDR 0x1604
212 #define VTBL_ADDR_INDEX_MASK 0xfff
214 #define CORE_ARLA_VTBL_ENTRY 0x160c
215 #define FWD_MAP_MASK 0x1ff
216 #define UNTAG_MAP_MASK 0x1ff
217 #define UNTAG_MAP_SHIFT 9
218 #define MSTP_INDEX_MASK 0x7
219 #define MSTP_INDEX_SHIFT 18
220 #define FWD_MODE (1 << 21)
222 #define CORE_MEM_PSM_VDD_CTRL 0x2380
223 #define P_TXQ_PSM_VDD_SHIFT 2
224 #define P_TXQ_PSM_VDD_MASK 0x3
225 #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
226 ((x) * P_TXQ_PSM_VDD_SHIFT))
228 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
229 #define PORT_VLAN_CTRL_MASK 0x1ff
231 #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
232 #define CFI_SHIFT 12
233 #define PRI_SHIFT 13
234 #define PRI_MASK 0x7
236 #define CORE_JOIN_ALL_VLAN_EN 0xd140
238 #define CORE_EEE_EN_CTRL 0x24800
239 #define CORE_EEE_LPI_INDICATE 0x24810