drivers/spi/spi-dw.c

   1 /*
   2  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/highmem.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/gpio.h>
  24
  25 #include "spi-dw.h"
  26
  27 #ifdef CONFIG_DEBUG_FS
  28 #include <linux/debugfs.h>
  29 #endif
  30
  31 /* Slave spi_dev related */
  32 struct chip_data {
  33         u8 cs;                  /* chip select pin */
  34         u8 tmode;               /* TR/TO/RO/EEPROM */
  35         u8 type;                /* SPI/SSP/MicroWire */
  36
  37         u8 poll_mode;           /* 1 means use poll mode */
  38
  39         u8 enable_dma;
  40         u16 clk_div;            /* baud rate divider */
  41         u32 speed_hz;           /* baud rate */
  42         void (*cs_control)(u32 command);
  43 };
  44
  45 #ifdef CONFIG_DEBUG_FS
  46 #define SPI_REGS_BUFSIZE        1024
  47 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
  48                 size_t count, loff_t *ppos)
  49 {
  50         struct dw_spi *dws = file->private_data;
  51         char *buf;
  52         u32 len = 0;
  53         ssize_t ret;
  54
  55         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  56         if (!buf)
  57                 return 0;
  58
  59         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  60                         "%s registers:\n", dev_name(&dws->master->dev));
  61         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  62                         "=================================\n");
  63         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  64                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  65         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  66                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  67         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  68                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  69         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  70                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  71         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  72                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  73         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  74                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  75         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  76                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  77         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  78                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
  79         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  80                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
  81         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  82                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
  83         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  84                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
  85         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  86                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
  87         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  88                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
  89         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  90                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
  91         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  92                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
  93         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  94                         "=================================\n");
  95
  96         ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  97         kfree(buf);
  98         return ret;
  99 }
 100
 101 static const struct file_operations dw_spi_regs_ops = {
 102         .owner          = THIS_MODULE,
 103         .open           = simple_open,
 104         .read           = dw_spi_show_regs,
 105         .llseek         = default_llseek,
 106 };
 107
 108 static int dw_spi_debugfs_init(struct dw_spi *dws)
 109 {
 110         dws->debugfs = debugfs_create_dir("dw_spi", NULL);
 111         if (!dws->debugfs)
 112                 return -ENOMEM;
 113
 114         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 115                 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
 116         return 0;
 117 }
 118
 119 static void dw_spi_debugfs_remove(struct dw_spi *dws)
 120 {
 121         debugfs_remove_recursive(dws->debugfs);
 122 }
 123
 124 #else
 125 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
 126 {
 127         return 0;
 128 }
 129
 130 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
 131 {
 132 }
 133 #endif /* CONFIG_DEBUG_FS */
 134
 135 static void dw_spi_set_cs(struct spi_device *spi, bool enable)
 136 {
 137         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 138         struct chip_data *chip = spi_get_ctldata(spi);
 139
 140         /* Chip select logic is inverted from spi_set_cs() */
 141         if (chip && chip->cs_control)
 142                 chip->cs_control(!enable);
 143
 144         if (!enable)
 145                 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
 146 }
 147
 148 /* Return the max entries we can fill into tx fifo */
 149 static inline u32 tx_max(struct dw_spi *dws)
 150 {
 151         u32 tx_left, tx_room, rxtx_gap;
 152
 153         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 154         tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
 155
 156         /*
 157          * Another concern is about the tx/rx mismatch, we
 158          * though to use (dws->fifo_len - rxflr - txflr) as
 159          * one maximum value for tx, but it doesn't cover the
 160          * data which is out of tx/rx fifo and inside the
 161          * shift registers. So a control from sw point of
 162          * view is taken.
 163          */
 164         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 165                         / dws->n_bytes;
 166
 167         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 168 }
 169
 170 /* Return the max entries we should read out of rx fifo */
 171 static inline u32 rx_max(struct dw_spi *dws)
 172 {
 173         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 174
 175         return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
 176 }
 177
 178 static void dw_writer(struct dw_spi *dws)
 179 {
 180         u32 max = tx_max(dws);
 181         u16 txw = 0;
 182
 183         while (max--) {
 184                 /* Set the tx word if the transfer's original "tx" is not null */
 185                 if (dws->tx_end - dws->len) {
 186                         if (dws->n_bytes == 1)
 187                                 txw = *(u8 *)(dws->tx);
 188                         else
 189                                 txw = *(u16 *)(dws->tx);
 190                 }
 191                 dw_write_io_reg(dws, DW_SPI_DR, txw);
 192                 dws->tx += dws->n_bytes;
 193         }
 194 }
 195
 196 static void dw_reader(struct dw_spi *dws)
 197 {
 198         u32 max = rx_max(dws);
 199         u16 rxw;
 200
 201         while (max--) {
 202                 rxw = dw_read_io_reg(dws, DW_SPI_DR);
 203                 /* Care rx only if the transfer's original "rx" is not null */
 204                 if (dws->rx_end - dws->len) {
 205                         if (dws->n_bytes == 1)
 206                                 *(u8 *)(dws->rx) = rxw;
 207                         else
 208                                 *(u16 *)(dws->rx) = rxw;
 209                 }
 210                 dws->rx += dws->n_bytes;
 211         }
 212 }
 213
 214 static void int_error_stop(struct dw_spi *dws, const char *msg)
 215 {
 216         spi_reset_chip(dws);
 217
 218         dev_err(&dws->master->dev, "%s\n", msg);
 219         dws->master->cur_msg->status = -EIO;
 220         spi_finalize_current_transfer(dws->master);
 221 }
 222
 223 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 224 {
 225         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 226
 227         /* Error handling */
 228         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 229                 dw_readl(dws, DW_SPI_ICR);
 230                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 231                 return IRQ_HANDLED;
 232         }
 233
 234         dw_reader(dws);
 235         if (dws->rx_end == dws->rx) {
 236                 spi_mask_intr(dws, SPI_INT_TXEI);
 237                 spi_finalize_current_transfer(dws->master);
 238                 return IRQ_HANDLED;
 239         }
 240         if (irq_status & SPI_INT_TXEI) {
 241                 spi_mask_intr(dws, SPI_INT_TXEI);
 242                 dw_writer(dws);
 243                 /* Enable TX irq always, it will be disabled when RX finished */
 244                 spi_umask_intr(dws, SPI_INT_TXEI);
 245         }
 246
 247         return IRQ_HANDLED;
 248 }
 249
 250 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 251 {
 252         struct spi_master *master = dev_id;
 253         struct dw_spi *dws = spi_master_get_devdata(master);
 254         u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
 255
 256         if (!irq_status)
 257                 return IRQ_NONE;
 258
 259         if (!master->cur_msg) {
 260                 spi_mask_intr(dws, SPI_INT_TXEI);
 261                 return IRQ_HANDLED;
 262         }
 263
 264         return dws->transfer_handler(dws);
 265 }
 266
 267 /* Must be called inside pump_transfers() */
 268 static int poll_transfer(struct dw_spi *dws)
 269 {
 270         do {
 271                 dw_writer(dws);
 272                 dw_reader(dws);
 273                 cpu_relax();
 274         } while (dws->rx_end > dws->rx);
 275
 276         return 0;
 277 }
 278
 279 static int dw_spi_transfer_one(struct spi_master *master,
 280                 struct spi_device *spi, struct spi_transfer *transfer)
 281 {
 282         struct dw_spi *dws = spi_master_get_devdata(master);
 283         struct chip_data *chip = spi_get_ctldata(spi);
 284         u8 imask = 0;
 285         u16 txlevel = 0;
 286         u32 cr0;
 287         int ret;
 288
 289         dws->dma_mapped = 0;
 290
 291         dws->tx = (void *)transfer->tx_buf;
 292         dws->tx_end = dws->tx + transfer->len;
 293         dws->rx = transfer->rx_buf;
 294         dws->rx_end = dws->rx + transfer->len;
 295         dws->len = transfer->len;
 296
 297         spi_enable_chip(dws, 0);
 298
 299         /* Handle per transfer options for bpw and speed */
 300         if (transfer->speed_hz != dws->current_freq) {
 301                 if (transfer->speed_hz != chip->speed_hz) {
 302                         /* clk_div doesn't support odd number */
 303                         chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
 304                         chip->speed_hz = transfer->speed_hz;
 305                 }
 306                 dws->current_freq = transfer->speed_hz;
 307                 spi_set_clk(dws, chip->clk_div);
 308         }
 309         if (transfer->bits_per_word == 8) {
 310                 dws->n_bytes = 1;
 311                 dws->dma_width = 1;
 312         } else if (transfer->bits_per_word == 16) {
 313                 dws->n_bytes = 2;
 314                 dws->dma_width = 2;
 315         } else {
 316                 return -EINVAL;
 317         }
 318         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 319         cr0 = (transfer->bits_per_word - 1)
 320                 | (chip->type << SPI_FRF_OFFSET)
 321                 | (spi->mode << SPI_MODE_OFFSET)
 322                 | (chip->tmode << SPI_TMOD_OFFSET);
 323
 324         /*
 325          * Adjust transfer mode if necessary. Requires platform dependent
 326          * chipselect mechanism.
 327          */
 328         if (chip->cs_control) {
 329                 if (dws->rx && dws->tx)
 330                         chip->tmode = SPI_TMOD_TR;
 331                 else if (dws->rx)
 332                         chip->tmode = SPI_TMOD_RO;
 333                 else
 334                         chip->tmode = SPI_TMOD_TO;
 335
 336                 cr0 &= ~SPI_TMOD_MASK;
 337                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 338         }
 339
 340         dw_writel(dws, DW_SPI_CTRL0, cr0);
 341
 342         /* Check if current transfer is a DMA transaction */
 343         if (master->can_dma && master->can_dma(master, spi, transfer))
 344                 dws->dma_mapped = master->cur_msg_mapped;
 345
 346         /* For poll mode just disable all interrupts */
 347         spi_mask_intr(dws, 0xff);
 348
 349         /*
 350          * Interrupt mode
 351          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 352          */
 353         if (dws->dma_mapped) {
 354                 ret = dws->dma_ops->dma_setup(dws, transfer);
 355                 if (ret < 0) {
 356                         spi_enable_chip(dws, 1);
 357                         return ret;
 358                 }
 359         } else if (!chip->poll_mode) {
 360                 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
 361                 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
 362
 363                 /* Set the interrupt mask */
 364                 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
 365                          SPI_INT_RXUI | SPI_INT_RXOI;
 366                 spi_umask_intr(dws, imask);
 367
 368                 dws->transfer_handler = interrupt_transfer;
 369         }
 370
 371         spi_enable_chip(dws, 1);
 372
 373         if (dws->dma_mapped) {
 374                 ret = dws->dma_ops->dma_transfer(dws, transfer);
 375                 if (ret < 0)
 376                         return ret;
 377         }
 378
 379         if (chip->poll_mode)
 380                 return poll_transfer(dws);
 381
 382         return 1;
 383 }
 384
 385 static void dw_spi_handle_err(struct spi_master *master,
 386                 struct spi_message *msg)
 387 {
 388         struct dw_spi *dws = spi_master_get_devdata(master);
 389
 390         if (dws->dma_mapped)
 391                 dws->dma_ops->dma_stop(dws);
 392
 393         spi_reset_chip(dws);
 394 }
 395
 396 /* This may be called twice for each spi dev */
 397 static int dw_spi_setup(struct spi_device *spi)
 398 {
 399         struct dw_spi_chip *chip_info = NULL;
 400         struct chip_data *chip;
 401         int ret;
 402
 403         /* Only alloc on first setup */
 404         chip = spi_get_ctldata(spi);
 405         if (!chip) {
 406                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 407                 if (!chip)
 408                         return -ENOMEM;
 409                 spi_set_ctldata(spi, chip);
 410         }
 411
 412         /*
 413          * Protocol drivers may change the chip settings, so...
 414          * if chip_info exists, use it
 415          */
 416         chip_info = spi->controller_data;
 417
 418         /* chip_info doesn't always exist */
 419         if (chip_info) {
 420                 if (chip_info->cs_control)
 421                         chip->cs_control = chip_info->cs_control;
 422
 423                 chip->poll_mode = chip_info->poll_mode;
 424                 chip->type = chip_info->type;
 425         }
 426
 427         chip->tmode = SPI_TMOD_TR;
 428
 429         if (gpio_is_valid(spi->cs_gpio)) {
 430                 ret = gpio_direction_output(spi->cs_gpio,
 431                                 !(spi->mode & SPI_CS_HIGH));
 432                 if (ret)
 433                         return ret;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static void dw_spi_cleanup(struct spi_device *spi)
 440 {
 441         struct chip_data *chip = spi_get_ctldata(spi);
 442
 443         kfree(chip);
 444         spi_set_ctldata(spi, NULL);
 445 }
 446
 447 /* Restart the controller, disable all interrupts, clean rx fifo */
 448 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
 449 {
 450         spi_reset_chip(dws);
 451
 452         /*
 453          * Try to detect the FIFO depth if not set by interface driver,
 454          * the depth could be from 2 to 256 from HW spec
 455          */
 456         if (!dws->fifo_len) {
 457                 u32 fifo;
 458
 459                 for (fifo = 1; fifo < 256; fifo++) {
 460                         dw_writel(dws, DW_SPI_TXFLTR, fifo);
 461                         if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
 462                                 break;
 463                 }
 464                 dw_writel(dws, DW_SPI_TXFLTR, 0);
 465
 466                 dws->fifo_len = (fifo == 1) ? 0 : fifo;
 467                 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
 468         }
 469 }
 470
 471 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 472 {
 473         struct spi_master *master;
 474         int ret;
 475
 476         BUG_ON(dws == NULL);
 477
 478         master = spi_alloc_master(dev, 0);
 479         if (!master)
 480                 return -ENOMEM;
 481
 482         dws->master = master;
 483         dws->type = SSI_MOTO_SPI;
 484         dws->dma_inited = 0;
 485         dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
 486         snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
 487
 488         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dws->name, master);
 489         if (ret < 0) {
 490                 dev_err(dev, "can not get IRQ\n");
 491                 goto err_free_master;
 492         }
 493
 494         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 495         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 496         master->bus_num = dws->bus_num;
 497         master->num_chipselect = dws->num_cs;
 498         master->setup = dw_spi_setup;
 499         master->cleanup = dw_spi_cleanup;
 500         master->set_cs = dw_spi_set_cs;
 501         master->transfer_one = dw_spi_transfer_one;
 502         master->handle_err = dw_spi_handle_err;
 503         master->max_speed_hz = dws->max_freq;
 504         master->dev.of_node = dev->of_node;
 505
 506         /* Basic HW init */
 507         spi_hw_init(dev, dws);
 508
 509         if (dws->dma_ops && dws->dma_ops->dma_init) {
 510                 ret = dws->dma_ops->dma_init(dws);
 511                 if (ret) {
 512                         dev_warn(dev, "DMA init failed\n");
 513                         dws->dma_inited = 0;
 514                 } else {
 515                         master->can_dma = dws->dma_ops->can_dma;
 516                 }
 517         }
 518
 519         spi_master_set_devdata(master, dws);
 520         ret = devm_spi_register_master(dev, master);
 521         if (ret) {
 522                 dev_err(&master->dev, "problem registering spi master\n");
 523                 goto err_dma_exit;
 524         }
 525
 526         dw_spi_debugfs_init(dws);
 527         return 0;
 528
 529 err_dma_exit:
 530         if (dws->dma_ops && dws->dma_ops->dma_exit)
 531                 dws->dma_ops->dma_exit(dws);
 532         spi_enable_chip(dws, 0);
 533         free_irq(dws->irq, master);
 534 err_free_master:
 535         spi_master_put(master);
 536         return ret;
 537 }
 538 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 539
 540 void dw_spi_remove_host(struct dw_spi *dws)
 541 {
 542         dw_spi_debugfs_remove(dws);
 543
 544         if (dws->dma_ops && dws->dma_ops->dma_exit)
 545                 dws->dma_ops->dma_exit(dws);
 546
 547         spi_shutdown_chip(dws);
 548
 549         free_irq(dws->irq, dws->master);
 550 }
 551 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 552
 553 int dw_spi_suspend_host(struct dw_spi *dws)
 554 {
 555         int ret;
 556
 557         ret = spi_master_suspend(dws->master);
 558         if (ret)
 559                 return ret;
 560
 561         spi_shutdown_chip(dws);
 562         return 0;
 563 }
 564 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 565
 566 int dw_spi_resume_host(struct dw_spi *dws)
 567 {
 568         int ret;
 569
 570         spi_hw_init(&dws->master->dev, dws);
 571         ret = spi_master_resume(dws->master);
 572         if (ret)
 573                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 574         return ret;
 575 }
 576 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 577
 578 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 579 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 580 MODULE_LICENSE("GPL v2");