arch/x86/kernel/cpu/mcheck/mce_amd.c

   1 /*
   2  *  (c) 2005, 2006 Advanced Micro Devices, Inc.
   3  *  Your use of this code is subject to the terms and conditions of the
   4  *  GNU general public license version 2. See "COPYING" or
   5  *  http://www.gnu.org/licenses/gpl.html
   6  *
   7  *  Written by Jacob Shin - AMD, Inc.
   8  *
   9  *  Support : jacob.shin@amd.com
  10  *
  11  *  April 2006
  12  *     - added support for AMD Family 0x10 processors
  13  *
  14  *  All MC4_MISCi registers are shared between multi-cores
  15  */
  16 #include <linux/interrupt.h>
  17 #include <linux/notifier.h>
  18 #include <linux/kobject.h>
  19 #include <linux/percpu.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/errno.h>
  22 #include <linux/sched.h>
  23 #include <linux/sysfs.h>
  24 #include <linux/slab.h>
  25 #include <linux/init.h>
  26 #include <linux/cpu.h>
  27 #include <linux/smp.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/idle.h>
  31 #include <asm/mce.h>
  32 #include <asm/msr.h>
  33
  34 #define PFX               "mce_threshold: "
  35 #define VERSION           "version 1.1.1"
  36 #define NR_BANKS          6
  37 #define NR_BLOCKS         9
  38 #define THRESHOLD_MAX     0xFFF
  39 #define INT_TYPE_APIC     0x00020000
  40 #define MASK_VALID_HI     0x80000000
  41 #define MASK_CNTP_HI      0x40000000
  42 #define MASK_LOCKED_HI    0x20000000
  43 #define MASK_LVTOFF_HI    0x00F00000
  44 #define MASK_COUNT_EN_HI  0x00080000
  45 #define MASK_INT_TYPE_HI  0x00060000
  46 #define MASK_OVERFLOW_HI  0x00010000
  47 #define MASK_ERR_COUNT_HI 0x00000FFF
  48 #define MASK_BLKPTR_LO    0xFF000000
  49 #define MCG_XBLK_ADDR     0xC0000400
  50
  51 struct threshold_block {
  52         unsigned int            block;
  53         unsigned int            bank;
  54         unsigned int            cpu;
  55         u32                     address;
  56         u16                     interrupt_enable;
  57         u16                     threshold_limit;
  58         struct kobject          kobj;
  59         struct list_head        miscj;
  60 };
  61
  62 /* defaults used early on boot */
  63 static struct threshold_block threshold_defaults = {
  64         .interrupt_enable       = 0,
  65         .threshold_limit        = THRESHOLD_MAX,
  66 };
  67
  68 struct threshold_bank {
  69         struct kobject          *kobj;
  70         struct threshold_block  *blocks;
  71         cpumask_var_t           cpus;
  72 };
  73 static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
  74
  75 #ifdef CONFIG_SMP
  76 static unsigned char shared_bank[NR_BANKS] = {
  77         0, 0, 0, 0, 1
  78 };
  79 #endif
  80
  81 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  82
  83 static void amd_threshold_interrupt(void);
  84
  85 /*
  86  * CPU Initialization
  87  */
  88
  89 struct thresh_restart {
  90         struct threshold_block  *b;
  91         int                     reset;
  92         u16                     old_limit;
  93 };
  94
  95 /* must be called with correct cpu affinity */
  96 /* Called via smp_call_function_single() */
  97 static void threshold_restart_bank(void *_tr)
  98 {
  99         struct thresh_restart *tr = _tr;
 100         u32 mci_misc_hi, mci_misc_lo;
 101
 102         rdmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
 103
 104         if (tr->b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
 105                 tr->reset = 1;  /* limit cannot be lower than err count */
 106
 107         if (tr->reset) {                /* reset err count and overflow bit */
 108                 mci_misc_hi =
 109                     (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
 110                     (THRESHOLD_MAX - tr->b->threshold_limit);
 111         } else if (tr->old_limit) {     /* change limit w/o reset */
 112                 int new_count = (mci_misc_hi & THRESHOLD_MAX) +
 113                     (tr->old_limit - tr->b->threshold_limit);
 114
 115                 mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
 116                     (new_count & THRESHOLD_MAX);
 117         }
 118
 119         tr->b->interrupt_enable ?
 120             (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
 121             (mci_misc_hi &= ~MASK_INT_TYPE_HI);
 122
 123         mci_misc_hi |= MASK_COUNT_EN_HI;
 124         wrmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
 125 }
 126
 127 /* cpu init entry point, called from mce.c with preempt off */
 128 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 129 {
 130         unsigned int cpu = smp_processor_id();
 131         u32 low = 0, high = 0, address = 0;
 132         unsigned int bank, block;
 133         struct thresh_restart tr;
 134         int lvt_off = -1;
 135         u8 offset;
 136
 137         for (bank = 0; bank < NR_BANKS; ++bank) {
 138                 for (block = 0; block < NR_BLOCKS; ++block) {
 139                         if (block == 0)
 140                                 address = MSR_IA32_MC0_MISC + bank * 4;
 141                         else if (block == 1) {
 142                                 address = (low & MASK_BLKPTR_LO) >> 21;
 143                                 if (!address)
 144                                         break;
 145
 146                                 address += MCG_XBLK_ADDR;
 147                         } else
 148                                 ++address;
 149
 150                         if (rdmsr_safe(address, &low, &high))
 151                                 break;
 152
 153                         if (!(high & MASK_VALID_HI))
 154                                 continue;
 155
 156                         if (!(high & MASK_CNTP_HI)  ||
 157                              (high & MASK_LOCKED_HI))
 158                                 continue;
 159
 160                         if (!block)
 161                                 per_cpu(bank_map, cpu) |= (1 << bank);
 162 #ifdef CONFIG_SMP
 163                         if (shared_bank[bank] && c->cpu_core_id)
 164                                 break;
 165 #endif
 166                         offset = (high & MASK_LVTOFF_HI) >> 20;
 167                         if (lvt_off < 0) {
 168                                 if (setup_APIC_eilvt(offset,
 169                                                      THRESHOLD_APIC_VECTOR,
 170                                                      APIC_EILVT_MSG_FIX, 0)) {
 171                                         pr_err(FW_BUG "cpu %d, failed to "
 172                                                "setup threshold interrupt "
 173                                                "for bank %d, block %d "
 174                                                "(MSR%08X=0x%x%08x)",
 175                                                smp_processor_id(), bank, block,
 176                                                address, high, low);
 177                                         continue;
 178                                 }
 179                                 lvt_off = offset;
 180                         } else if (lvt_off != offset) {
 181                                 pr_err(FW_BUG "cpu %d, invalid threshold "
 182                                        "interrupt offset %d for bank %d,"
 183                                        "block %d (MSR%08X=0x%x%08x)",
 184                                        smp_processor_id(), lvt_off, bank,
 185                                        block, address, high, low);
 186                                 continue;
 187                         }
 188
 189                         high &= ~MASK_LVTOFF_HI;
 190                         high |= lvt_off << 20;
 191                         wrmsr(address, low, high);
 192
 193                         threshold_defaults.address = address;
 194                         tr.b = &threshold_defaults;
 195                         tr.reset = 0;
 196                         tr.old_limit = 0;
 197                         threshold_restart_bank(&tr);
 198
 199                         mce_threshold_vector = amd_threshold_interrupt;
 200                 }
 201         }
 202 }
 203
 204 /*
 205  * APIC Interrupt Handler
 206  */
 207
 208 /*
 209  * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
 210  * the interrupt goes off when error_count reaches threshold_limit.
 211  * the handler will simply log mcelog w/ software defined bank number.
 212  */
 213 static void amd_threshold_interrupt(void)
 214 {
 215         u32 low = 0, high = 0, address = 0;
 216         unsigned int bank, block;
 217         struct mce m;
 218
 219         mce_setup(&m);
 220
 221         /* assume first bank caused it */
 222         for (bank = 0; bank < NR_BANKS; ++bank) {
 223                 if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
 224                         continue;
 225                 for (block = 0; block < NR_BLOCKS; ++block) {
 226                         if (block == 0) {
 227                                 address = MSR_IA32_MC0_MISC + bank * 4;
 228                         } else if (block == 1) {
 229                                 address = (low & MASK_BLKPTR_LO) >> 21;
 230                                 if (!address)
 231                                         break;
 232                                 address += MCG_XBLK_ADDR;
 233                         } else {
 234                                 ++address;
 235                         }
 236
 237                         if (rdmsr_safe(address, &low, &high))
 238                                 break;
 239
 240                         if (!(high & MASK_VALID_HI)) {
 241                                 if (block)
 242                                         continue;
 243                                 else
 244                                         break;
 245                         }
 246
 247                         if (!(high & MASK_CNTP_HI)  ||
 248                              (high & MASK_LOCKED_HI))
 249                                 continue;
 250
 251                         /*
 252                          * Log the machine check that caused the threshold
 253                          * event.
 254                          */
 255                         machine_check_poll(MCP_TIMESTAMP,
 256                                         &__get_cpu_var(mce_poll_banks));
 257
 258                         if (high & MASK_OVERFLOW_HI) {
 259                                 rdmsrl(address, m.misc);
 260                                 rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
 261                                        m.status);
 262                                 m.bank = K8_MCE_THRESHOLD_BASE
 263                                        + bank * NR_BLOCKS
 264                                        + block;
 265                                 mce_log(&m);
 266                                 return;
 267                         }
 268                 }
 269         }
 270 }
 271
 272 /*
 273  * Sysfs Interface
 274  */
 275
 276 struct threshold_attr {
 277         struct attribute attr;
 278         ssize_t (*show) (struct threshold_block *, char *);
 279         ssize_t (*store) (struct threshold_block *, const char *, size_t count);
 280 };
 281
 282 #define SHOW_FIELDS(name)                                               \
 283 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
 284 {                                                                       \
 285         return sprintf(buf, "%lx\n", (unsigned long) b->name);          \
 286 }
 287 SHOW_FIELDS(interrupt_enable)
 288 SHOW_FIELDS(threshold_limit)
 289
 290 static ssize_t
 291 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
 292 {
 293         struct thresh_restart tr;
 294         unsigned long new;
 295
 296         if (strict_strtoul(buf, 0, &new) < 0)
 297                 return -EINVAL;
 298
 299         b->interrupt_enable = !!new;
 300
 301         tr.b            = b;
 302         tr.reset        = 0;
 303         tr.old_limit    = 0;
 304
 305         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 306
 307         return size;
 308 }
 309
 310 static ssize_t
 311 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
 312 {
 313         struct thresh_restart tr;
 314         unsigned long new;
 315
 316         if (strict_strtoul(buf, 0, &new) < 0)
 317                 return -EINVAL;
 318
 319         if (new > THRESHOLD_MAX)
 320                 new = THRESHOLD_MAX;
 321         if (new < 1)
 322                 new = 1;
 323
 324         tr.old_limit = b->threshold_limit;
 325         b->threshold_limit = new;
 326         tr.b = b;
 327         tr.reset = 0;
 328
 329         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 330
 331         return size;
 332 }
 333
 334 struct threshold_block_cross_cpu {
 335         struct threshold_block  *tb;
 336         long                    retval;
 337 };
 338
 339 static void local_error_count_handler(void *_tbcc)
 340 {
 341         struct threshold_block_cross_cpu *tbcc = _tbcc;
 342         struct threshold_block *b = tbcc->tb;
 343         u32 low, high;
 344
 345         rdmsr(b->address, low, high);
 346         tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
 347 }
 348
 349 static ssize_t show_error_count(struct threshold_block *b, char *buf)
 350 {
 351         struct threshold_block_cross_cpu tbcc = { .tb = b, };
 352
 353         smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);
 354         return sprintf(buf, "%lx\n", tbcc.retval);
 355 }
 356
 357 static ssize_t store_error_count(struct threshold_block *b,
 358                                  const char *buf, size_t count)
 359 {
 360         struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
 361
 362         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 363         return 1;
 364 }
 365
 366 #define RW_ATTR(val)                                                    \
 367 static struct threshold_attr val = {                                    \
 368         .attr   = {.name = __stringify(val), .mode = 0644 },            \
 369         .show   = show_## val,                                          \
 370         .store  = store_## val,                                         \
 371 };
 372
 373 RW_ATTR(interrupt_enable);
 374 RW_ATTR(threshold_limit);
 375 RW_ATTR(error_count);
 376
 377 static struct attribute *default_attrs[] = {
 378         &interrupt_enable.attr,
 379         &threshold_limit.attr,
 380         &error_count.attr,
 381         NULL
 382 };
 383
 384 #define to_block(k)     container_of(k, struct threshold_block, kobj)
 385 #define to_attr(a)      container_of(a, struct threshold_attr, attr)
 386
 387 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
 388 {
 389         struct threshold_block *b = to_block(kobj);
 390         struct threshold_attr *a = to_attr(attr);
 391         ssize_t ret;
 392
 393         ret = a->show ? a->show(b, buf) : -EIO;
 394
 395         return ret;
 396 }
 397
 398 static ssize_t store(struct kobject *kobj, struct attribute *attr,
 399                      const char *buf, size_t count)
 400 {
 401         struct threshold_block *b = to_block(kobj);
 402         struct threshold_attr *a = to_attr(attr);
 403         ssize_t ret;
 404
 405         ret = a->store ? a->store(b, buf, count) : -EIO;
 406
 407         return ret;
 408 }
 409
 410 static const struct sysfs_ops threshold_ops = {
 411         .show                   = show,
 412         .store                  = store,
 413 };
 414
 415 static struct kobj_type threshold_ktype = {
 416         .sysfs_ops              = &threshold_ops,
 417         .default_attrs          = default_attrs,
 418 };
 419
 420 static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
 421                                                unsigned int bank,
 422                                                unsigned int block,
 423                                                u32 address)
 424 {
 425         struct threshold_block *b = NULL;
 426         u32 low, high;
 427         int err;
 428
 429         if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
 430                 return 0;
 431
 432         if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
 433                 return 0;
 434
 435         if (!(high & MASK_VALID_HI)) {
 436                 if (block)
 437                         goto recurse;
 438                 else
 439                         return 0;
 440         }
 441
 442         if (!(high & MASK_CNTP_HI)  ||
 443              (high & MASK_LOCKED_HI))
 444                 goto recurse;
 445
 446         b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
 447         if (!b)
 448                 return -ENOMEM;
 449
 450         b->block                = block;
 451         b->bank                 = bank;
 452         b->cpu                  = cpu;
 453         b->address              = address;
 454         b->interrupt_enable     = 0;
 455         b->threshold_limit      = THRESHOLD_MAX;
 456
 457         INIT_LIST_HEAD(&b->miscj);
 458
 459         if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
 460                 list_add(&b->miscj,
 461                          &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
 462         } else {
 463                 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
 464         }
 465
 466         err = kobject_init_and_add(&b->kobj, &threshold_ktype,
 467                                    per_cpu(threshold_banks, cpu)[bank]->kobj,
 468                                    "misc%i", block);
 469         if (err)
 470                 goto out_free;
 471 recurse:
 472         if (!block) {
 473                 address = (low & MASK_BLKPTR_LO) >> 21;
 474                 if (!address)
 475                         return 0;
 476                 address += MCG_XBLK_ADDR;
 477         } else {
 478                 ++address;
 479         }
 480
 481         err = allocate_threshold_blocks(cpu, bank, ++block, address);
 482         if (err)
 483                 goto out_free;
 484
 485         if (b)
 486                 kobject_uevent(&b->kobj, KOBJ_ADD);
 487
 488         return err;
 489
 490 out_free:
 491         if (b) {
 492                 kobject_put(&b->kobj);
 493                 kfree(b);
 494         }
 495         return err;
 496 }
 497
 498 static __cpuinit long
 499 local_allocate_threshold_blocks(int cpu, unsigned int bank)
 500 {
 501         return allocate_threshold_blocks(cpu, bank, 0,
 502                                          MSR_IA32_MC0_MISC + bank * 4);
 503 }
 504
 505 /* symlinks sibling shared banks to first core.  first core owns dir/files. */
 506 static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 507 {
 508         int i, err = 0;
 509         struct threshold_bank *b = NULL;
 510         char name[32];
 511 #ifdef CONFIG_SMP
 512         struct cpuinfo_x86 *c = &cpu_data(cpu);
 513 #endif
 514
 515         sprintf(name, "threshold_bank%i", bank);
 516
 517 #ifdef CONFIG_SMP
 518         if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) {   /* symlink */
 519                 i = cpumask_first(c->llc_shared_map);
 520
 521                 /* first core not up yet */
 522                 if (cpu_data(i).cpu_core_id)
 523                         goto out;
 524
 525                 /* already linked */
 526                 if (per_cpu(threshold_banks, cpu)[bank])
 527                         goto out;
 528
 529                 b = per_cpu(threshold_banks, i)[bank];
 530
 531                 if (!b)
 532                         goto out;
 533
 534                 err = sysfs_create_link(&per_cpu(mce_dev, cpu).kobj,
 535                                         b->kobj, name);
 536                 if (err)
 537                         goto out;
 538
 539                 cpumask_copy(b->cpus, c->llc_shared_map);
 540                 per_cpu(threshold_banks, cpu)[bank] = b;
 541
 542                 goto out;
 543         }
 544 #endif
 545
 546         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
 547         if (!b) {
 548                 err = -ENOMEM;
 549                 goto out;
 550         }
 551         if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
 552                 kfree(b);
 553                 err = -ENOMEM;
 554                 goto out;
 555         }
 556
 557         b->kobj = kobject_create_and_add(name, &per_cpu(mce_dev, cpu).kobj);
 558         if (!b->kobj)
 559                 goto out_free;
 560
 561 #ifndef CONFIG_SMP
 562         cpumask_setall(b->cpus);
 563 #else
 564         cpumask_set_cpu(cpu, b->cpus);
 565 #endif
 566
 567         per_cpu(threshold_banks, cpu)[bank] = b;
 568
 569         err = local_allocate_threshold_blocks(cpu, bank);
 570         if (err)
 571                 goto out_free;
 572
 573         for_each_cpu(i, b->cpus) {
 574                 if (i == cpu)
 575                         continue;
 576
 577                 err = sysfs_create_link(&per_cpu(mce_dev, i).kobj,
 578                                         b->kobj, name);
 579                 if (err)
 580                         goto out;
 581
 582                 per_cpu(threshold_banks, i)[bank] = b;
 583         }
 584
 585         goto out;
 586
 587 out_free:
 588         per_cpu(threshold_banks, cpu)[bank] = NULL;
 589         free_cpumask_var(b->cpus);
 590         kfree(b);
 591 out:
 592         return err;
 593 }
 594
 595 /* create dir/files for all valid threshold banks */
 596 static __cpuinit int threshold_create_device(unsigned int cpu)
 597 {
 598         unsigned int bank;
 599         int err = 0;
 600
 601         for (bank = 0; bank < NR_BANKS; ++bank) {
 602                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
 603                         continue;
 604                 err = threshold_create_bank(cpu, bank);
 605                 if (err)
 606                         goto out;
 607         }
 608 out:
 609         return err;
 610 }
 611
 612 /*
 613  * let's be hotplug friendly.
 614  * in case of multiple core processors, the first core always takes ownership
 615  *   of shared sysfs dir/files, and rest of the cores will be symlinked to it.
 616  */
 617
 618 static void deallocate_threshold_block(unsigned int cpu,
 619                                                  unsigned int bank)
 620 {
 621         struct threshold_block *pos = NULL;
 622         struct threshold_block *tmp = NULL;
 623         struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
 624
 625         if (!head)
 626                 return;
 627
 628         list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
 629                 kobject_put(&pos->kobj);
 630                 list_del(&pos->miscj);
 631                 kfree(pos);
 632         }
 633
 634         kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
 635         per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
 636 }
 637
 638 static void threshold_remove_bank(unsigned int cpu, int bank)
 639 {
 640         struct threshold_bank *b;
 641         char name[32];
 642         int i = 0;
 643
 644         b = per_cpu(threshold_banks, cpu)[bank];
 645         if (!b)
 646                 return;
 647         if (!b->blocks)
 648                 goto free_out;
 649
 650         sprintf(name, "threshold_bank%i", bank);
 651
 652 #ifdef CONFIG_SMP
 653         /* sibling symlink */
 654         if (shared_bank[bank] && b->blocks->cpu != cpu) {
 655                 sysfs_remove_link(&per_cpu(mce_dev, cpu).kobj, name);
 656                 per_cpu(threshold_banks, cpu)[bank] = NULL;
 657
 658                 return;
 659         }
 660 #endif
 661
 662         /* remove all sibling symlinks before unregistering */
 663         for_each_cpu(i, b->cpus) {
 664                 if (i == cpu)
 665                         continue;
 666
 667                 sysfs_remove_link(&per_cpu(mce_dev, i).kobj, name);
 668                 per_cpu(threshold_banks, i)[bank] = NULL;
 669         }
 670
 671         deallocate_threshold_block(cpu, bank);
 672
 673 free_out:
 674         kobject_del(b->kobj);
 675         kobject_put(b->kobj);
 676         free_cpumask_var(b->cpus);
 677         kfree(b);
 678         per_cpu(threshold_banks, cpu)[bank] = NULL;
 679 }
 680
 681 static void threshold_remove_device(unsigned int cpu)
 682 {
 683         unsigned int bank;
 684
 685         for (bank = 0; bank < NR_BANKS; ++bank) {
 686                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
 687                         continue;
 688                 threshold_remove_bank(cpu, bank);
 689         }
 690 }
 691
 692 /* get notified when a cpu comes on/off */
 693 static void __cpuinit
 694 amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
 695 {
 696         switch (action) {
 697         case CPU_ONLINE:
 698         case CPU_ONLINE_FROZEN:
 699                 threshold_create_device(cpu);
 700                 break;
 701         case CPU_DEAD:
 702         case CPU_DEAD_FROZEN:
 703                 threshold_remove_device(cpu);
 704                 break;
 705         default:
 706                 break;
 707         }
 708 }
 709
 710 static __init int threshold_init_device(void)
 711 {
 712         unsigned lcpu = 0;
 713
 714         /* to hit CPUs online before the notifier is up */
 715         for_each_online_cpu(lcpu) {
 716                 int err = threshold_create_device(lcpu);
 717
 718                 if (err)
 719                         return err;
 720         }
 721         threshold_cpu_callback = amd_64_threshold_cpu_callback;
 722
 723         return 0;
 724 }
 725 device_initcall(threshold_init_device);