arch/sh/kernel/cpu/sh4/setup-sh7750.c

   1 /*
   2  * SH7750/SH7751 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2006  Jamie Lenehan
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/io.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/serial_sci.h>
  17 #include <generated/machtypes.h>
  18
  19 static struct resource rtc_resources[] = {
  20         [0] = {
  21                 .start  = 0xffc80000,
  22                 .end    = 0xffc80000 + 0x58 - 1,
  23                 .flags  = IORESOURCE_IO,
  24         },
  25         [1] = {
  26                 /* Shared Period/Carry/Alarm IRQ */
  27                 .start  = 20,
  28                 .flags  = IORESOURCE_IRQ,
  29         },
  30 };
  31
  32 static struct platform_device rtc_device = {
  33         .name           = "sh-rtc",
  34         .id             = -1,
  35         .num_resources  = ARRAY_SIZE(rtc_resources),
  36         .resource       = rtc_resources,
  37 };
  38
  39 static struct plat_sci_port sci_platform_data = {
  40         .mapbase        = 0xffe00000,
  41         .flags          = UPF_BOOT_AUTOCONF,
  42         .scscr          = SCSCR_TE | SCSCR_RE,
  43         .scbrr_algo_id  = SCBRR_ALGO_2,
  44         .type           = PORT_SCI,
  45         .irqs           = { 23, 23, 23, 0 },
  46 };
  47
  48 static struct platform_device sci_device = {
  49         .name           = "sh-sci",
  50         .id             = 0,
  51         .dev            = {
  52                 .platform_data  = &sci_platform_data,
  53         },
  54 };
  55
  56 static struct plat_sci_port scif_platform_data = {
  57         .mapbase        = 0xffe80000,
  58         .flags          = UPF_BOOT_AUTOCONF,
  59         .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
  60         .scbrr_algo_id  = SCBRR_ALGO_2,
  61         .type           = PORT_SCIF,
  62         .irqs           = { 40, 40, 40, 40 },
  63 };
  64
  65 static struct platform_device scif_device = {
  66         .name           = "sh-sci",
  67         .id             = 1,
  68         .dev            = {
  69                 .platform_data  = &scif_platform_data,
  70         },
  71 };
  72
  73 static struct sh_timer_config tmu0_platform_data = {
  74         .channel_offset = 0x04,
  75         .timer_bit = 0,
  76         .clockevent_rating = 200,
  77 };
  78
  79 static struct resource tmu0_resources[] = {
  80         [0] = {
  81                 .start  = 0xffd80008,
  82                 .end    = 0xffd80013,
  83                 .flags  = IORESOURCE_MEM,
  84         },
  85         [1] = {
  86                 .start  = 16,
  87                 .flags  = IORESOURCE_IRQ,
  88         },
  89 };
  90
  91 static struct platform_device tmu0_device = {
  92         .name           = "sh_tmu",
  93         .id             = 0,
  94         .dev = {
  95                 .platform_data  = &tmu0_platform_data,
  96         },
  97         .resource       = tmu0_resources,
  98         .num_resources  = ARRAY_SIZE(tmu0_resources),
  99 };
 100
 101 static struct sh_timer_config tmu1_platform_data = {
 102         .channel_offset = 0x10,
 103         .timer_bit = 1,
 104         .clocksource_rating = 200,
 105 };
 106
 107 static struct resource tmu1_resources[] = {
 108         [0] = {
 109                 .start  = 0xffd80014,
 110                 .end    = 0xffd8001f,
 111                 .flags  = IORESOURCE_MEM,
 112         },
 113         [1] = {
 114                 .start  = 17,
 115                 .flags  = IORESOURCE_IRQ,
 116         },
 117 };
 118
 119 static struct platform_device tmu1_device = {
 120         .name           = "sh_tmu",
 121         .id             = 1,
 122         .dev = {
 123                 .platform_data  = &tmu1_platform_data,
 124         },
 125         .resource       = tmu1_resources,
 126         .num_resources  = ARRAY_SIZE(tmu1_resources),
 127 };
 128
 129 static struct sh_timer_config tmu2_platform_data = {
 130         .channel_offset = 0x1c,
 131         .timer_bit = 2,
 132 };
 133
 134 static struct resource tmu2_resources[] = {
 135         [0] = {
 136                 .start  = 0xffd80020,
 137                 .end    = 0xffd8002f,
 138                 .flags  = IORESOURCE_MEM,
 139         },
 140         [1] = {
 141                 .start  = 18,
 142                 .flags  = IORESOURCE_IRQ,
 143         },
 144 };
 145
 146 static struct platform_device tmu2_device = {
 147         .name           = "sh_tmu",
 148         .id             = 2,
 149         .dev = {
 150                 .platform_data  = &tmu2_platform_data,
 151         },
 152         .resource       = tmu2_resources,
 153         .num_resources  = ARRAY_SIZE(tmu2_resources),
 154 };
 155
 156 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 157 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 158         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 159         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 160
 161 static struct sh_timer_config tmu3_platform_data = {
 162         .channel_offset = 0x04,
 163         .timer_bit = 0,
 164 };
 165
 166 static struct resource tmu3_resources[] = {
 167         [0] = {
 168                 .start  = 0xfe100008,
 169                 .end    = 0xfe100013,
 170                 .flags  = IORESOURCE_MEM,
 171         },
 172         [1] = {
 173                 .start  = 72,
 174                 .flags  = IORESOURCE_IRQ,
 175         },
 176 };
 177
 178 static struct platform_device tmu3_device = {
 179         .name           = "sh_tmu",
 180         .id             = 3,
 181         .dev = {
 182                 .platform_data  = &tmu3_platform_data,
 183         },
 184         .resource       = tmu3_resources,
 185         .num_resources  = ARRAY_SIZE(tmu3_resources),
 186 };
 187
 188 static struct sh_timer_config tmu4_platform_data = {
 189         .channel_offset = 0x10,
 190         .timer_bit = 1,
 191 };
 192
 193 static struct resource tmu4_resources[] = {
 194         [0] = {
 195                 .start  = 0xfe100014,
 196                 .end    = 0xfe10001f,
 197                 .flags  = IORESOURCE_MEM,
 198         },
 199         [1] = {
 200                 .start  = 76,
 201                 .flags  = IORESOURCE_IRQ,
 202         },
 203 };
 204
 205 static struct platform_device tmu4_device = {
 206         .name           = "sh_tmu",
 207         .id             = 4,
 208         .dev = {
 209                 .platform_data  = &tmu4_platform_data,
 210         },
 211         .resource       = tmu4_resources,
 212         .num_resources  = ARRAY_SIZE(tmu4_resources),
 213 };
 214
 215 #endif
 216
 217 static struct platform_device *sh7750_devices[] __initdata = {
 218         &rtc_device,
 219         &tmu0_device,
 220         &tmu1_device,
 221         &tmu2_device,
 222 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 223         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 224         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 225         &tmu3_device,
 226         &tmu4_device,
 227 #endif
 228 };
 229
 230 static int __init sh7750_devices_setup(void)
 231 {
 232         if (mach_is_rts7751r2d()) {
 233                 platform_device_register(&scif_device);
 234         } else {
 235                 platform_device_register(&sci_device);
 236                 platform_device_register(&scif_device);
 237         }
 238
 239         return platform_add_devices(sh7750_devices,
 240                                     ARRAY_SIZE(sh7750_devices));
 241 }
 242 arch_initcall(sh7750_devices_setup);
 243
 244 static struct platform_device *sh7750_early_devices[] __initdata = {
 245         &tmu0_device,
 246         &tmu1_device,
 247         &tmu2_device,
 248 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 249         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 250         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 251         &tmu3_device,
 252         &tmu4_device,
 253 #endif
 254 };
 255
 256 void __init plat_early_device_setup(void)
 257 {
 258         struct platform_device *dev[1];
 259
 260         if (mach_is_rts7751r2d()) {
 261                 scif_platform_data.scscr |= SCSCR_CKE1;
 262                 dev[0] = &scif_device;
 263                 early_platform_add_devices(dev, 1);
 264         } else {
 265                 dev[0] = &sci_device;
 266                 early_platform_add_devices(dev, 1);
 267                 dev[0] = &scif_device;
 268                 early_platform_add_devices(dev, 1);
 269         }
 270
 271         early_platform_add_devices(sh7750_early_devices,
 272                                    ARRAY_SIZE(sh7750_early_devices));
 273 }
 274
 275 enum {
 276         UNUSED = 0,
 277
 278         /* interrupt sources */
 279         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
 280         HUDI, GPIOI, DMAC,
 281         PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 282         PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
 283         TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
 284
 285         /* interrupt groups */
 286         PCIC1,
 287 };
 288
 289 static struct intc_vect vectors[] __initdata = {
 290         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
 291         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 292         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
 293         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 294         INTC_VECT(RTC, 0x4c0),
 295         INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
 296         INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
 297         INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
 298         INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
 299         INTC_VECT(WDT, 0x560),
 300         INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
 301 };
 302
 303 static struct intc_prio_reg prio_registers[] __initdata = {
 304         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 305         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
 306         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
 307         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 308         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
 309                                                  TMU4, TMU3,
 310                                                  PCIC1, PCIC0_PCISERR } },
 311 };
 312
 313 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
 314                          NULL, prio_registers, NULL);
 315
 316 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
 317 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 318         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 319         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 320         defined(CONFIG_CPU_SUBTYPE_SH7091)
 321 static struct intc_vect vectors_dma4[] __initdata = {
 322         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 323         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 324         INTC_VECT(DMAC, 0x6c0),
 325 };
 326
 327 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
 328                          vectors_dma4, NULL,
 329                          NULL, prio_registers, NULL);
 330 #endif
 331
 332 /* SH7750R and SH7751R both have 8-channel DMA controllers */
 333 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 334 static struct intc_vect vectors_dma8[] __initdata = {
 335         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 336         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 337         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 338         INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
 339         INTC_VECT(DMAC, 0x6c0),
 340 };
 341
 342 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
 343                          vectors_dma8, NULL,
 344                          NULL, prio_registers, NULL);
 345 #endif
 346
 347 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 348 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 349         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 350         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 351 static struct intc_vect vectors_tmu34[] __initdata = {
 352         INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
 353 };
 354
 355 static struct intc_mask_reg mask_registers[] __initdata = {
 356         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
 357           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 358             0, 0, 0, 0, 0, 0, TMU4, TMU3,
 359             PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 360             PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
 361             PCIC1_PCIDMA3, PCIC0_PCISERR } },
 362 };
 363
 364 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
 365                          vectors_tmu34, NULL,
 366                          mask_registers, prio_registers, NULL);
 367 #endif
 368
 369 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
 370 static struct intc_vect vectors_irlm[] __initdata = {
 371         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 372         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 373 };
 374
 375 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
 376                          NULL, prio_registers, NULL);
 377
 378 /* SH7751 and SH7751R both have PCI */
 379 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 380 static struct intc_vect vectors_pci[] __initdata = {
 381         INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
 382         INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
 383         INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
 384         INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
 385 };
 386
 387 static struct intc_group groups_pci[] __initdata = {
 388         INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 389                    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 390 };
 391
 392 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
 393                          mask_registers, prio_registers, NULL);
 394 #endif
 395
 396 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 397         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 398         defined(CONFIG_CPU_SUBTYPE_SH7091)
 399 void __init plat_irq_setup(void)
 400 {
 401         /*
 402          * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
 403          * see below..
 404          */
 405         register_intc_controller(&intc_desc);
 406         register_intc_controller(&intc_desc_dma4);
 407 }
 408 #endif
 409
 410 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
 411 void __init plat_irq_setup(void)
 412 {
 413         register_intc_controller(&intc_desc);
 414         register_intc_controller(&intc_desc_dma8);
 415         register_intc_controller(&intc_desc_tmu34);
 416 }
 417 #endif
 418
 419 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
 420 void __init plat_irq_setup(void)
 421 {
 422         register_intc_controller(&intc_desc);
 423         register_intc_controller(&intc_desc_dma4);
 424         register_intc_controller(&intc_desc_tmu34);
 425         register_intc_controller(&intc_desc_pci);
 426 }
 427 #endif
 428
 429 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
 430 void __init plat_irq_setup(void)
 431 {
 432         register_intc_controller(&intc_desc);
 433         register_intc_controller(&intc_desc_dma8);
 434         register_intc_controller(&intc_desc_tmu34);
 435         register_intc_controller(&intc_desc_pci);
 436 }
 437 #endif
 438
 439 #define INTC_ICR        0xffd00000UL
 440 #define INTC_ICR_IRLM   (1<<7)
 441
 442 void __init plat_irq_setup_pins(int mode)
 443 {
 444 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
 445         BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
 446         return;
 447 #endif
 448
 449         switch (mode) {
 450         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
 451                 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 452                 register_intc_controller(&intc_desc_irlm);
 453                 break;
 454         default:
 455                 BUG();
 456         }
 457 }