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ARM: ep93xx: move timer to its own file
[linux/fpc-iii.git] / drivers / iommu / intel_irq_remapping.c
blobf15692a410c7e7064e844be2b7d83feee20ef5c5
1
2 #define pr_fmt(fmt) "DMAR-IR: " fmt
3
4 #include <linux/interrupt.h>
5 #include <linux/dmar.h>
6 #include <linux/spinlock.h>
7 #include <linux/slab.h>
8 #include <linux/jiffies.h>
9 #include <linux/hpet.h>
10 #include <linux/pci.h>
11 #include <linux/irq.h>
12 #include <linux/intel-iommu.h>
13 #include <linux/acpi.h>
14 #include <linux/irqdomain.h>
15 #include <linux/crash_dump.h>
16 #include <asm/io_apic.h>
17 #include <asm/smp.h>
18 #include <asm/cpu.h>
19 #include <asm/irq_remapping.h>
20 #include <asm/pci-direct.h>
21 #include <asm/msidef.h>
22
23 #include "irq_remapping.h"
24
25 enum irq_mode {
26 IRQ_REMAPPING,
27 IRQ_POSTING,
28 };
29
30 struct ioapic_scope {
31 struct intel_iommu *iommu;
32 unsigned int id;
33 unsigned int bus; /* PCI bus number */
34 unsigned int devfn; /* PCI devfn number */
35 };
36
37 struct hpet_scope {
38 struct intel_iommu *iommu;
39 u8 id;
40 unsigned int bus;
41 unsigned int devfn;
42 };
43
44 struct irq_2_iommu {
45 struct intel_iommu *iommu;
46 u16 irte_index;
47 u16 sub_handle;
48 u8 irte_mask;
49 enum irq_mode mode;
50 };
51
52 struct intel_ir_data {
53 struct irq_2_iommu irq_2_iommu;
54 struct irte irte_entry;
55 union {
56 struct msi_msg msi_entry;
57 };
58 };
59
60 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
61 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
62
63 static int __read_mostly eim_mode;
64 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
65 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
66
67 /*
68 * Lock ordering:
69 * ->dmar_global_lock
70 * ->irq_2_ir_lock
71 * ->qi->q_lock
72 * ->iommu->register_lock
73 * Note:
74 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
75 * in single-threaded environment with interrupt disabled, so no need to tabke
76 * the dmar_global_lock.
77 */
78 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
79 static struct irq_domain_ops intel_ir_domain_ops;
80
81 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
82 static int __init parse_ioapics_under_ir(void);
83
84 static bool ir_pre_enabled(struct intel_iommu *iommu)
85 {
86 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
87 }
88
89 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
90 {
91 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
92 }
93
94 static void init_ir_status(struct intel_iommu *iommu)
95 {
96 u32 gsts;
97
98 gsts = readl(iommu->reg + DMAR_GSTS_REG);
99 if (gsts & DMA_GSTS_IRES)
100 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
101 }
102
103 static int alloc_irte(struct intel_iommu *iommu, int irq,
104 struct irq_2_iommu *irq_iommu, u16 count)
105 {
106 struct ir_table *table = iommu->ir_table;
107 unsigned int mask = 0;
108 unsigned long flags;
109 int index;
110
111 if (!count || !irq_iommu)
112 return -1;
113
114 if (count > 1) {
115 count = __roundup_pow_of_two(count);
116 mask = ilog2(count);
117 }
118
119 if (mask > ecap_max_handle_mask(iommu->ecap)) {
120 pr_err("Requested mask %x exceeds the max invalidation handle"
121 " mask value %Lx\n", mask,
122 ecap_max_handle_mask(iommu->ecap));
123 return -1;
124 }
125
126 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
127 index = bitmap_find_free_region(table->bitmap,
128 INTR_REMAP_TABLE_ENTRIES, mask);
129 if (index < 0) {
130 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
131 } else {
132 irq_iommu->iommu = iommu;
133 irq_iommu->irte_index = index;
134 irq_iommu->sub_handle = 0;
135 irq_iommu->irte_mask = mask;
136 irq_iommu->mode = IRQ_REMAPPING;
137 }
138 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
139
140 return index;
141 }
142
143 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
144 {
145 struct qi_desc desc;
146
147 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
148 | QI_IEC_SELECTIVE;
149 desc.high = 0;
150
151 return qi_submit_sync(&desc, iommu);
152 }
153
154 static int modify_irte(struct irq_2_iommu *irq_iommu,
155 struct irte *irte_modified)
156 {
157 struct intel_iommu *iommu;
158 unsigned long flags;
159 struct irte *irte;
160 int rc, index;
161
162 if (!irq_iommu)
163 return -1;
164
165 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
166
167 iommu = irq_iommu->iommu;
168
169 index = irq_iommu->irte_index + irq_iommu->sub_handle;
170 irte = &iommu->ir_table->base[index];
171
172 set_64bit(&irte->low, irte_modified->low);
173 set_64bit(&irte->high, irte_modified->high);
174 __iommu_flush_cache(iommu, irte, sizeof(*irte));
175
176 rc = qi_flush_iec(iommu, index, 0);
177
178 /* Update iommu mode according to the IRTE mode */
179 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
180 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
181
182 return rc;
183 }
184
185 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
186 {
187 int i;
188
189 for (i = 0; i < MAX_HPET_TBS; i++)
190 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
191 return ir_hpet[i].iommu;
192 return NULL;
193 }
194
195 static struct intel_iommu *map_ioapic_to_ir(int apic)
196 {
197 int i;
198
199 for (i = 0; i < MAX_IO_APICS; i++)
200 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
201 return ir_ioapic[i].iommu;
202 return NULL;
203 }
204
205 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
206 {
207 struct dmar_drhd_unit *drhd;
208
209 drhd = dmar_find_matched_drhd_unit(dev);
210 if (!drhd)
211 return NULL;
212
213 return drhd->iommu;
214 }
215
216 static int clear_entries(struct irq_2_iommu *irq_iommu)
217 {
218 struct irte *start, *entry, *end;
219 struct intel_iommu *iommu;
220 int index;
221
222 if (irq_iommu->sub_handle)
223 return 0;
224
225 iommu = irq_iommu->iommu;
226 index = irq_iommu->irte_index;
227
228 start = iommu->ir_table->base + index;
229 end = start + (1 << irq_iommu->irte_mask);
230
231 for (entry = start; entry < end; entry++) {
232 set_64bit(&entry->low, 0);
233 set_64bit(&entry->high, 0);
234 }
235 bitmap_release_region(iommu->ir_table->bitmap, index,
236 irq_iommu->irte_mask);
237
238 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
239 }
240
241 /*
242 * source validation type
243 */
244 #define SVT_NO_VERIFY 0x0 /* no verification is required */
245 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
246 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
247
248 /*
249 * source-id qualifier
250 */
251 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
252 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
253 * the third least significant bit
254 */
255 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
256 * the second and third least significant bits
257 */
258 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
259 * the least three significant bits
260 */
261
262 /*
263 * set SVT, SQ and SID fields of irte to verify
264 * source ids of interrupt requests
265 */
266 static void set_irte_sid(struct irte *irte, unsigned int svt,
267 unsigned int sq, unsigned int sid)
268 {
269 if (disable_sourceid_checking)
270 svt = SVT_NO_VERIFY;
271 irte->svt = svt;
272 irte->sq = sq;
273 irte->sid = sid;
274 }
275
276 static int set_ioapic_sid(struct irte *irte, int apic)
277 {
278 int i;
279 u16 sid = 0;
280
281 if (!irte)
282 return -1;
283
284 down_read(&dmar_global_lock);
285 for (i = 0; i < MAX_IO_APICS; i++) {
286 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
287 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
288 break;
289 }
290 }
291 up_read(&dmar_global_lock);
292
293 if (sid == 0) {
294 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
295 return -1;
296 }
297
298 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
299
300 return 0;
301 }
302
303 static int set_hpet_sid(struct irte *irte, u8 id)
304 {
305 int i;
306 u16 sid = 0;
307
308 if (!irte)
309 return -1;
310
311 down_read(&dmar_global_lock);
312 for (i = 0; i < MAX_HPET_TBS; i++) {
313 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
314 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
315 break;
316 }
317 }
318 up_read(&dmar_global_lock);
319
320 if (sid == 0) {
321 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
322 return -1;
323 }
324
325 /*
326 * Should really use SQ_ALL_16. Some platforms are broken.
327 * While we figure out the right quirks for these broken platforms, use
328 * SQ_13_IGNORE_3 for now.
329 */
330 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
331
332 return 0;
333 }
334
335 struct set_msi_sid_data {
336 struct pci_dev *pdev;
337 u16 alias;
338 };
339
340 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
341 {
342 struct set_msi_sid_data *data = opaque;
343
344 data->pdev = pdev;
345 data->alias = alias;
346
347 return 0;
348 }
349
350 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
351 {
352 struct set_msi_sid_data data;
353
354 if (!irte || !dev)
355 return -1;
356
357 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
358
359 /*
360 * DMA alias provides us with a PCI device and alias. The only case
361 * where the it will return an alias on a different bus than the
362 * device is the case of a PCIe-to-PCI bridge, where the alias is for
363 * the subordinate bus. In this case we can only verify the bus.
364 *
365 * If the alias device is on a different bus than our source device
366 * then we have a topology based alias, use it.
367 *
368 * Otherwise, the alias is for a device DMA quirk and we cannot
369 * assume that MSI uses the same requester ID. Therefore use the
370 * original device.
371 */
372 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
373 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
374 PCI_DEVID(PCI_BUS_NUM(data.alias),
375 dev->bus->number));
376 else if (data.pdev->bus->number != dev->bus->number)
377 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
378 else
379 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
380 PCI_DEVID(dev->bus->number, dev->devfn));
381
382 return 0;
383 }
384
385 static int iommu_load_old_irte(struct intel_iommu *iommu)
386 {
387 struct irte *old_ir_table;
388 phys_addr_t irt_phys;
389 unsigned int i;
390 size_t size;
391 u64 irta;
392
393 if (!is_kdump_kernel()) {
394 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
395 iommu->name);
396 clear_ir_pre_enabled(iommu);
397 iommu_disable_irq_remapping(iommu);
398 return -EINVAL;
399 }
400
401 /* Check whether the old ir-table has the same size as ours */
402 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
403 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
404 != INTR_REMAP_TABLE_REG_SIZE)
405 return -EINVAL;
406
407 irt_phys = irta & VTD_PAGE_MASK;
408 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
409
410 /* Map the old IR table */
411 old_ir_table = ioremap_cache(irt_phys, size);
412 if (!old_ir_table)
413 return -ENOMEM;
414
415 /* Copy data over */
416 memcpy(iommu->ir_table->base, old_ir_table, size);
417
418 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
419
420 /*
421 * Now check the table for used entries and mark those as
422 * allocated in the bitmap
423 */
424 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
425 if (iommu->ir_table->base[i].present)
426 bitmap_set(iommu->ir_table->bitmap, i, 1);
427 }
428
429 return 0;
430 }
431
432
433 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
434 {
435 unsigned long flags;
436 u64 addr;
437 u32 sts;
438
439 addr = virt_to_phys((void *)iommu->ir_table->base);
440
441 raw_spin_lock_irqsave(&iommu->register_lock, flags);
442
443 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
444 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
445
446 /* Set interrupt-remapping table pointer */
447 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
448
449 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
450 readl, (sts & DMA_GSTS_IRTPS), sts);
451 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
452
453 /*
454 * Global invalidation of interrupt entry cache to make sure the
455 * hardware uses the new irq remapping table.
456 */
457 qi_global_iec(iommu);
458 }
459
460 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
461 {
462 unsigned long flags;
463 u32 sts;
464
465 raw_spin_lock_irqsave(&iommu->register_lock, flags);
466
467 /* Enable interrupt-remapping */
468 iommu->gcmd |= DMA_GCMD_IRE;
469 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
470 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
471
472 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
473 readl, (sts & DMA_GSTS_IRES), sts);
474
475 /*
476 * With CFI clear in the Global Command register, we should be
477 * protected from dangerous (i.e. compatibility) interrupts
478 * regardless of x2apic status. Check just to be sure.
479 */
480 if (sts & DMA_GSTS_CFIS)
481 WARN(1, KERN_WARNING
482 "Compatibility-format IRQs enabled despite intr remapping;\n"
483 "you are vulnerable to IRQ injection.\n");
484
485 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
486 }
487
488 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
489 {
490 struct ir_table *ir_table;
491 struct page *pages;
492 unsigned long *bitmap;
493
494 if (iommu->ir_table)
495 return 0;
496
497 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
498 if (!ir_table)
499 return -ENOMEM;
500
501 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
502 INTR_REMAP_PAGE_ORDER);
503 if (!pages) {
504 pr_err("IR%d: failed to allocate pages of order %d\n",
505 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
506 goto out_free_table;
507 }
508
509 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
510 sizeof(long), GFP_ATOMIC);
511 if (bitmap == NULL) {
512 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
513 goto out_free_pages;
514 }
515
516 iommu->ir_domain = irq_domain_add_hierarchy(arch_get_ir_parent_domain(),
517 0, INTR_REMAP_TABLE_ENTRIES,
518 NULL, &intel_ir_domain_ops,
519 iommu);
520 if (!iommu->ir_domain) {
521 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
522 goto out_free_bitmap;
523 }
524 iommu->ir_msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
525
526 ir_table->base = page_address(pages);
527 ir_table->bitmap = bitmap;
528 iommu->ir_table = ir_table;
529
530 /*
531 * If the queued invalidation is already initialized,
532 * shouldn't disable it.
533 */
534 if (!iommu->qi) {
535 /*
536 * Clear previous faults.
537 */
538 dmar_fault(-1, iommu);
539 dmar_disable_qi(iommu);
540
541 if (dmar_enable_qi(iommu)) {
542 pr_err("Failed to enable queued invalidation\n");
543 goto out_free_bitmap;
544 }
545 }
546
547 init_ir_status(iommu);
548
549 if (ir_pre_enabled(iommu)) {
550 if (iommu_load_old_irte(iommu))
551 pr_err("Failed to copy IR table for %s from previous kernel\n",
552 iommu->name);
553 else
554 pr_info("Copied IR table for %s from previous kernel\n",
555 iommu->name);
556 }
557
558 iommu_set_irq_remapping(iommu, eim_mode);
559
560 return 0;
561
562 out_free_bitmap:
563 kfree(bitmap);
564 out_free_pages:
565 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
566 out_free_table:
567 kfree(ir_table);
568
569 iommu->ir_table = NULL;
570
571 return -ENOMEM;
572 }
573
574 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
575 {
576 if (iommu && iommu->ir_table) {
577 if (iommu->ir_msi_domain) {
578 irq_domain_remove(iommu->ir_msi_domain);
579 iommu->ir_msi_domain = NULL;
580 }
581 if (iommu->ir_domain) {
582 irq_domain_remove(iommu->ir_domain);
583 iommu->ir_domain = NULL;
584 }
585 free_pages((unsigned long)iommu->ir_table->base,
586 INTR_REMAP_PAGE_ORDER);
587 kfree(iommu->ir_table->bitmap);
588 kfree(iommu->ir_table);
589 iommu->ir_table = NULL;
590 }
591 }
592
593 /*
594 * Disable Interrupt Remapping.
595 */
596 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
597 {
598 unsigned long flags;
599 u32 sts;
600
601 if (!ecap_ir_support(iommu->ecap))
602 return;
603
604 /*
605 * global invalidation of interrupt entry cache before disabling
606 * interrupt-remapping.
607 */
608 qi_global_iec(iommu);
609
610 raw_spin_lock_irqsave(&iommu->register_lock, flags);
611
612 sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
613 if (!(sts & DMA_GSTS_IRES))
614 goto end;
615
616 iommu->gcmd &= ~DMA_GCMD_IRE;
617 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
618
619 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
620 readl, !(sts & DMA_GSTS_IRES), sts);
621
622 end:
623 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
624 }
625
626 static int __init dmar_x2apic_optout(void)
627 {
628 struct acpi_table_dmar *dmar;
629 dmar = (struct acpi_table_dmar *)dmar_tbl;
630 if (!dmar || no_x2apic_optout)
631 return 0;
632 return dmar->flags & DMAR_X2APIC_OPT_OUT;
633 }
634
635 static void __init intel_cleanup_irq_remapping(void)
636 {
637 struct dmar_drhd_unit *drhd;
638 struct intel_iommu *iommu;
639
640 for_each_iommu(iommu, drhd) {
641 if (ecap_ir_support(iommu->ecap)) {
642 iommu_disable_irq_remapping(iommu);
643 intel_teardown_irq_remapping(iommu);
644 }
645 }
646
647 if (x2apic_supported())
648 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
649 }
650
651 static int __init intel_prepare_irq_remapping(void)
652 {
653 struct dmar_drhd_unit *drhd;
654 struct intel_iommu *iommu;
655 int eim = 0;
656
657 if (irq_remap_broken) {
658 pr_warn("This system BIOS has enabled interrupt remapping\n"
659 "on a chipset that contains an erratum making that\n"
660 "feature unstable. To maintain system stability\n"
661 "interrupt remapping is being disabled. Please\n"
662 "contact your BIOS vendor for an update\n");
663 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
664 return -ENODEV;
665 }
666
667 if (dmar_table_init() < 0)
668 return -ENODEV;
669
670 if (!dmar_ir_support())
671 return -ENODEV;
672
673 if (parse_ioapics_under_ir() != 1) {
674 pr_info("Not enabling interrupt remapping\n");
675 goto error;
676 }
677
678 /* First make sure all IOMMUs support IRQ remapping */
679 for_each_iommu(iommu, drhd)
680 if (!ecap_ir_support(iommu->ecap))
681 goto error;
682
683 /* Detect remapping mode: lapic or x2apic */
684 if (x2apic_supported()) {
685 eim = !dmar_x2apic_optout();
686 if (!eim) {
687 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
688 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
689 }
690 }
691
692 for_each_iommu(iommu, drhd) {
693 if (eim && !ecap_eim_support(iommu->ecap)) {
694 pr_info("%s does not support EIM\n", iommu->name);
695 eim = 0;
696 }
697 }
698
699 eim_mode = eim;
700 if (eim)
701 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
702
703 /* Do the initializations early */
704 for_each_iommu(iommu, drhd) {
705 if (intel_setup_irq_remapping(iommu)) {
706 pr_err("Failed to setup irq remapping for %s\n",
707 iommu->name);
708 goto error;
709 }
710 }
711
712 return 0;
713
714 error:
715 intel_cleanup_irq_remapping();
716 return -ENODEV;
717 }
718
719 /*
720 * Set Posted-Interrupts capability.
721 */
722 static inline void set_irq_posting_cap(void)
723 {
724 struct dmar_drhd_unit *drhd;
725 struct intel_iommu *iommu;
726
727 if (!disable_irq_post) {
728 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
729
730 for_each_iommu(iommu, drhd)
731 if (!cap_pi_support(iommu->cap)) {
732 intel_irq_remap_ops.capability &=
733 ~(1 << IRQ_POSTING_CAP);
734 break;
735 }
736 }
737 }
738
739 static int __init intel_enable_irq_remapping(void)
740 {
741 struct dmar_drhd_unit *drhd;
742 struct intel_iommu *iommu;
743 bool setup = false;
744
745 /*
746 * Setup Interrupt-remapping for all the DRHD's now.
747 */
748 for_each_iommu(iommu, drhd) {
749 if (!ir_pre_enabled(iommu))
750 iommu_enable_irq_remapping(iommu);
751 setup = true;
752 }
753
754 if (!setup)
755 goto error;
756
757 irq_remapping_enabled = 1;
758
759 set_irq_posting_cap();
760
761 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
762
763 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
764
765 error:
766 intel_cleanup_irq_remapping();
767 return -1;
768 }
769
770 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
771 struct intel_iommu *iommu,
772 struct acpi_dmar_hardware_unit *drhd)
773 {
774 struct acpi_dmar_pci_path *path;
775 u8 bus;
776 int count, free = -1;
777
778 bus = scope->bus;
779 path = (struct acpi_dmar_pci_path *)(scope + 1);
780 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
781 / sizeof(struct acpi_dmar_pci_path);
782
783 while (--count > 0) {
784 /*
785 * Access PCI directly due to the PCI
786 * subsystem isn't initialized yet.
787 */
788 bus = read_pci_config_byte(bus, path->device, path->function,
789 PCI_SECONDARY_BUS);
790 path++;
791 }
792
793 for (count = 0; count < MAX_HPET_TBS; count++) {
794 if (ir_hpet[count].iommu == iommu &&
795 ir_hpet[count].id == scope->enumeration_id)
796 return 0;
797 else if (ir_hpet[count].iommu == NULL && free == -1)
798 free = count;
799 }
800 if (free == -1) {
801 pr_warn("Exceeded Max HPET blocks\n");
802 return -ENOSPC;
803 }
804
805 ir_hpet[free].iommu = iommu;
806 ir_hpet[free].id = scope->enumeration_id;
807 ir_hpet[free].bus = bus;
808 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
809 pr_info("HPET id %d under DRHD base 0x%Lx\n",
810 scope->enumeration_id, drhd->address);
811
812 return 0;
813 }
814
815 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
816 struct intel_iommu *iommu,
817 struct acpi_dmar_hardware_unit *drhd)
818 {
819 struct acpi_dmar_pci_path *path;
820 u8 bus;
821 int count, free = -1;
822
823 bus = scope->bus;
824 path = (struct acpi_dmar_pci_path *)(scope + 1);
825 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
826 / sizeof(struct acpi_dmar_pci_path);
827
828 while (--count > 0) {
829 /*
830 * Access PCI directly due to the PCI
831 * subsystem isn't initialized yet.
832 */
833 bus = read_pci_config_byte(bus, path->device, path->function,
834 PCI_SECONDARY_BUS);
835 path++;
836 }
837
838 for (count = 0; count < MAX_IO_APICS; count++) {
839 if (ir_ioapic[count].iommu == iommu &&
840 ir_ioapic[count].id == scope->enumeration_id)
841 return 0;
842 else if (ir_ioapic[count].iommu == NULL && free == -1)
843 free = count;
844 }
845 if (free == -1) {
846 pr_warn("Exceeded Max IO APICS\n");
847 return -ENOSPC;
848 }
849
850 ir_ioapic[free].bus = bus;
851 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
852 ir_ioapic[free].iommu = iommu;
853 ir_ioapic[free].id = scope->enumeration_id;
854 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
855 scope->enumeration_id, drhd->address, iommu->seq_id);
856
857 return 0;
858 }
859
860 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
861 struct intel_iommu *iommu)
862 {
863 int ret = 0;
864 struct acpi_dmar_hardware_unit *drhd;
865 struct acpi_dmar_device_scope *scope;
866 void *start, *end;
867
868 drhd = (struct acpi_dmar_hardware_unit *)header;
869 start = (void *)(drhd + 1);
870 end = ((void *)drhd) + header->length;
871
872 while (start < end && ret == 0) {
873 scope = start;
874 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
875 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
876 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
877 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
878 start += scope->length;
879 }
880
881 return ret;
882 }
883
884 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
885 {
886 int i;
887
888 for (i = 0; i < MAX_HPET_TBS; i++)
889 if (ir_hpet[i].iommu == iommu)
890 ir_hpet[i].iommu = NULL;
891
892 for (i = 0; i < MAX_IO_APICS; i++)
893 if (ir_ioapic[i].iommu == iommu)
894 ir_ioapic[i].iommu = NULL;
895 }
896
897 /*
898 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
899 * hardware unit.
900 */
901 static int __init parse_ioapics_under_ir(void)
902 {
903 struct dmar_drhd_unit *drhd;
904 struct intel_iommu *iommu;
905 bool ir_supported = false;
906 int ioapic_idx;
907
908 for_each_iommu(iommu, drhd)
909 if (ecap_ir_support(iommu->ecap)) {
910 if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
911 return -1;
912
913 ir_supported = true;
914 }
915
916 if (!ir_supported)
917 return 0;
918
919 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
920 int ioapic_id = mpc_ioapic_id(ioapic_idx);
921 if (!map_ioapic_to_ir(ioapic_id)) {
922 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
923 "interrupt remapping will be disabled\n",
924 ioapic_id);
925 return -1;
926 }
927 }
928
929 return 1;
930 }
931
932 static int __init ir_dev_scope_init(void)
933 {
934 int ret;
935
936 if (!irq_remapping_enabled)
937 return 0;
938
939 down_write(&dmar_global_lock);
940 ret = dmar_dev_scope_init();
941 up_write(&dmar_global_lock);
942
943 return ret;
944 }
945 rootfs_initcall(ir_dev_scope_init);
946
947 static void disable_irq_remapping(void)
948 {
949 struct dmar_drhd_unit *drhd;
950 struct intel_iommu *iommu = NULL;
951
952 /*
953 * Disable Interrupt-remapping for all the DRHD's now.
954 */
955 for_each_iommu(iommu, drhd) {
956 if (!ecap_ir_support(iommu->ecap))
957 continue;
958
959 iommu_disable_irq_remapping(iommu);
960 }
961
962 /*
963 * Clear Posted-Interrupts capability.
964 */
965 if (!disable_irq_post)
966 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
967 }
968
969 static int reenable_irq_remapping(int eim)
970 {
971 struct dmar_drhd_unit *drhd;
972 bool setup = false;
973 struct intel_iommu *iommu = NULL;
974
975 for_each_iommu(iommu, drhd)
976 if (iommu->qi)
977 dmar_reenable_qi(iommu);
978
979 /*
980 * Setup Interrupt-remapping for all the DRHD's now.
981 */
982 for_each_iommu(iommu, drhd) {
983 if (!ecap_ir_support(iommu->ecap))
984 continue;
985
986 /* Set up interrupt remapping for iommu.*/
987 iommu_set_irq_remapping(iommu, eim);
988 iommu_enable_irq_remapping(iommu);
989 setup = true;
990 }
991
992 if (!setup)
993 goto error;
994
995 set_irq_posting_cap();
996
997 return 0;
998
999 error:
1000 /*
1001 * handle error condition gracefully here!
1002 */
1003 return -1;
1004 }
1005
1006 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1007 {
1008 memset(irte, 0, sizeof(*irte));
1009
1010 irte->present = 1;
1011 irte->dst_mode = apic->irq_dest_mode;
1012 /*
1013 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1014 * actual level or edge trigger will be setup in the IO-APIC
1015 * RTE. This will help simplify level triggered irq migration.
1016 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1017 * irq migration in the presence of interrupt-remapping.
1018 */
1019 irte->trigger_mode = 0;
1020 irte->dlvry_mode = apic->irq_delivery_mode;
1021 irte->vector = vector;
1022 irte->dest_id = IRTE_DEST(dest);
1023 irte->redir_hint = 1;
1024 }
1025
1026 static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
1027 {
1028 struct intel_iommu *iommu = NULL;
1029
1030 if (!info)
1031 return NULL;
1032
1033 switch (info->type) {
1034 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1035 iommu = map_ioapic_to_ir(info->ioapic_id);
1036 break;
1037 case X86_IRQ_ALLOC_TYPE_HPET:
1038 iommu = map_hpet_to_ir(info->hpet_id);
1039 break;
1040 case X86_IRQ_ALLOC_TYPE_MSI:
1041 case X86_IRQ_ALLOC_TYPE_MSIX:
1042 iommu = map_dev_to_ir(info->msi_dev);
1043 break;
1044 default:
1045 BUG_ON(1);
1046 break;
1047 }
1048
1049 return iommu ? iommu->ir_domain : NULL;
1050 }
1051
1052 static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
1053 {
1054 struct intel_iommu *iommu;
1055
1056 if (!info)
1057 return NULL;
1058
1059 switch (info->type) {
1060 case X86_IRQ_ALLOC_TYPE_MSI:
1061 case X86_IRQ_ALLOC_TYPE_MSIX:
1062 iommu = map_dev_to_ir(info->msi_dev);
1063 if (iommu)
1064 return iommu->ir_msi_domain;
1065 break;
1066 default:
1067 break;
1068 }
1069
1070 return NULL;
1071 }
1072
1073 struct irq_remap_ops intel_irq_remap_ops = {
1074 .prepare = intel_prepare_irq_remapping,
1075 .enable = intel_enable_irq_remapping,
1076 .disable = disable_irq_remapping,
1077 .reenable = reenable_irq_remapping,
1078 .enable_faulting = enable_drhd_fault_handling,
1079 .get_ir_irq_domain = intel_get_ir_irq_domain,
1080 .get_irq_domain = intel_get_irq_domain,
1081 };
1082
1083 /*
1084 * Migrate the IO-APIC irq in the presence of intr-remapping.
1085 *
1086 * For both level and edge triggered, irq migration is a simple atomic
1087 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1088 *
1089 * For level triggered, we eliminate the io-apic RTE modification (with the
1090 * updated vector information), by using a virtual vector (io-apic pin number).
1091 * Real vector that is used for interrupting cpu will be coming from
1092 * the interrupt-remapping table entry.
1093 *
1094 * As the migration is a simple atomic update of IRTE, the same mechanism
1095 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1096 */
1097 static int
1098 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1099 bool force)
1100 {
1101 struct intel_ir_data *ir_data = data->chip_data;
1102 struct irte *irte = &ir_data->irte_entry;
1103 struct irq_cfg *cfg = irqd_cfg(data);
1104 struct irq_data *parent = data->parent_data;
1105 int ret;
1106
1107 ret = parent->chip->irq_set_affinity(parent, mask, force);
1108 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1109 return ret;
1110
1111 /*
1112 * Atomically updates the IRTE with the new destination, vector
1113 * and flushes the interrupt entry cache.
1114 */
1115 irte->vector = cfg->vector;
1116 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1117
1118 /* Update the hardware only if the interrupt is in remapped mode. */
1119 if (ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1120 modify_irte(&ir_data->irq_2_iommu, irte);
1121
1122 /*
1123 * After this point, all the interrupts will start arriving
1124 * at the new destination. So, time to cleanup the previous
1125 * vector allocation.
1126 */
1127 send_cleanup_vector(cfg);
1128
1129 return IRQ_SET_MASK_OK_DONE;
1130 }
1131
1132 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1133 struct msi_msg *msg)
1134 {
1135 struct intel_ir_data *ir_data = irq_data->chip_data;
1136
1137 *msg = ir_data->msi_entry;
1138 }
1139
1140 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1141 {
1142 struct intel_ir_data *ir_data = data->chip_data;
1143 struct vcpu_data *vcpu_pi_info = info;
1144
1145 /* stop posting interrupts, back to remapping mode */
1146 if (!vcpu_pi_info) {
1147 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1148 } else {
1149 struct irte irte_pi;
1150
1151 /*
1152 * We are not caching the posted interrupt entry. We
1153 * copy the data from the remapped entry and modify
1154 * the fields which are relevant for posted mode. The
1155 * cached remapped entry is used for switching back to
1156 * remapped mode.
1157 */
1158 memset(&irte_pi, 0, sizeof(irte_pi));
1159 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1160
1161 /* Update the posted mode fields */
1162 irte_pi.p_pst = 1;
1163 irte_pi.p_urgent = 0;
1164 irte_pi.p_vector = vcpu_pi_info->vector;
1165 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1166 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1167 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1168 ~(-1UL << PDA_HIGH_BIT);
1169
1170 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1171 }
1172
1173 return 0;
1174 }
1175
1176 static struct irq_chip intel_ir_chip = {
1177 .irq_ack = ir_ack_apic_edge,
1178 .irq_set_affinity = intel_ir_set_affinity,
1179 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1180 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1181 };
1182
1183 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1184 struct irq_cfg *irq_cfg,
1185 struct irq_alloc_info *info,
1186 int index, int sub_handle)
1187 {
1188 struct IR_IO_APIC_route_entry *entry;
1189 struct irte *irte = &data->irte_entry;
1190 struct msi_msg *msg = &data->msi_entry;
1191
1192 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1193 switch (info->type) {
1194 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1195 /* Set source-id of interrupt request */
1196 set_ioapic_sid(irte, info->ioapic_id);
1197 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1198 info->ioapic_id, irte->present, irte->fpd,
1199 irte->dst_mode, irte->redir_hint,
1200 irte->trigger_mode, irte->dlvry_mode,
1201 irte->avail, irte->vector, irte->dest_id,
1202 irte->sid, irte->sq, irte->svt);
1203
1204 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1205 info->ioapic_entry = NULL;
1206 memset(entry, 0, sizeof(*entry));
1207 entry->index2 = (index >> 15) & 0x1;
1208 entry->zero = 0;
1209 entry->format = 1;
1210 entry->index = (index & 0x7fff);
1211 /*
1212 * IO-APIC RTE will be configured with virtual vector.
1213 * irq handler will do the explicit EOI to the io-apic.
1214 */
1215 entry->vector = info->ioapic_pin;
1216 entry->mask = 0; /* enable IRQ */
1217 entry->trigger = info->ioapic_trigger;
1218 entry->polarity = info->ioapic_polarity;
1219 if (info->ioapic_trigger)
1220 entry->mask = 1; /* Mask level triggered irqs. */
1221 break;
1222
1223 case X86_IRQ_ALLOC_TYPE_HPET:
1224 case X86_IRQ_ALLOC_TYPE_MSI:
1225 case X86_IRQ_ALLOC_TYPE_MSIX:
1226 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1227 set_hpet_sid(irte, info->hpet_id);
1228 else
1229 set_msi_sid(irte, info->msi_dev);
1230
1231 msg->address_hi = MSI_ADDR_BASE_HI;
1232 msg->data = sub_handle;
1233 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1234 MSI_ADDR_IR_SHV |
1235 MSI_ADDR_IR_INDEX1(index) |
1236 MSI_ADDR_IR_INDEX2(index);
1237 break;
1238
1239 default:
1240 BUG_ON(1);
1241 break;
1242 }
1243 }
1244
1245 static void intel_free_irq_resources(struct irq_domain *domain,
1246 unsigned int virq, unsigned int nr_irqs)
1247 {
1248 struct irq_data *irq_data;
1249 struct intel_ir_data *data;
1250 struct irq_2_iommu *irq_iommu;
1251 unsigned long flags;
1252 int i;
1253 for (i = 0; i < nr_irqs; i++) {
1254 irq_data = irq_domain_get_irq_data(domain, virq + i);
1255 if (irq_data && irq_data->chip_data) {
1256 data = irq_data->chip_data;
1257 irq_iommu = &data->irq_2_iommu;
1258 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1259 clear_entries(irq_iommu);
1260 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1261 irq_domain_reset_irq_data(irq_data);
1262 kfree(data);
1263 }
1264 }
1265 }
1266
1267 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1268 unsigned int virq, unsigned int nr_irqs,
1269 void *arg)
1270 {
1271 struct intel_iommu *iommu = domain->host_data;
1272 struct irq_alloc_info *info = arg;
1273 struct intel_ir_data *data, *ird;
1274 struct irq_data *irq_data;
1275 struct irq_cfg *irq_cfg;
1276 int i, ret, index;
1277
1278 if (!info || !iommu)
1279 return -EINVAL;
1280 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
1281 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
1282 return -EINVAL;
1283
1284 /*
1285 * With IRQ remapping enabled, don't need contiguous CPU vectors
1286 * to support multiple MSI interrupts.
1287 */
1288 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
1289 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1290
1291 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1292 if (ret < 0)
1293 return ret;
1294
1295 ret = -ENOMEM;
1296 data = kzalloc(sizeof(*data), GFP_KERNEL);
1297 if (!data)
1298 goto out_free_parent;
1299
1300 down_read(&dmar_global_lock);
1301 index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs);
1302 up_read(&dmar_global_lock);
1303 if (index < 0) {
1304 pr_warn("Failed to allocate IRTE\n");
1305 kfree(data);
1306 goto out_free_parent;
1307 }
1308
1309 for (i = 0; i < nr_irqs; i++) {
1310 irq_data = irq_domain_get_irq_data(domain, virq + i);
1311 irq_cfg = irqd_cfg(irq_data);
1312 if (!irq_data || !irq_cfg) {
1313 ret = -EINVAL;
1314 goto out_free_data;
1315 }
1316
1317 if (i > 0) {
1318 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1319 if (!ird)
1320 goto out_free_data;
1321 /* Initialize the common data */
1322 ird->irq_2_iommu = data->irq_2_iommu;
1323 ird->irq_2_iommu.sub_handle = i;
1324 } else {
1325 ird = data;
1326 }
1327
1328 irq_data->hwirq = (index << 16) + i;
1329 irq_data->chip_data = ird;
1330 irq_data->chip = &intel_ir_chip;
1331 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1332 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1333 }
1334 return 0;
1335
1336 out_free_data:
1337 intel_free_irq_resources(domain, virq, i);
1338 out_free_parent:
1339 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1340 return ret;
1341 }
1342
1343 static void intel_irq_remapping_free(struct irq_domain *domain,
1344 unsigned int virq, unsigned int nr_irqs)
1345 {
1346 intel_free_irq_resources(domain, virq, nr_irqs);
1347 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1348 }
1349
1350 static void intel_irq_remapping_activate(struct irq_domain *domain,
1351 struct irq_data *irq_data)
1352 {
1353 struct intel_ir_data *data = irq_data->chip_data;
1354
1355 modify_irte(&data->irq_2_iommu, &data->irte_entry);
1356 }
1357
1358 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1359 struct irq_data *irq_data)
1360 {
1361 struct intel_ir_data *data = irq_data->chip_data;
1362 struct irte entry;
1363
1364 memset(&entry, 0, sizeof(entry));
1365 modify_irte(&data->irq_2_iommu, &entry);
1366 }
1367
1368 static struct irq_domain_ops intel_ir_domain_ops = {
1369 .alloc = intel_irq_remapping_alloc,
1370 .free = intel_irq_remapping_free,
1371 .activate = intel_irq_remapping_activate,
1372 .deactivate = intel_irq_remapping_deactivate,
1373 };
1374
1375 /*
1376 * Support of Interrupt Remapping Unit Hotplug
1377 */
1378 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1379 {
1380 int ret;
1381 int eim = x2apic_enabled();
1382
1383 if (eim && !ecap_eim_support(iommu->ecap)) {
1384 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1385 iommu->reg_phys, iommu->ecap);
1386 return -ENODEV;
1387 }
1388
1389 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1390 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1391 iommu->reg_phys);
1392 return -ENODEV;
1393 }
1394
1395 /* TODO: check all IOAPICs are covered by IOMMU */
1396
1397 /* Setup Interrupt-remapping now. */
1398 ret = intel_setup_irq_remapping(iommu);
1399 if (ret) {
1400 pr_err("Failed to setup irq remapping for %s\n",
1401 iommu->name);
1402 intel_teardown_irq_remapping(iommu);
1403 ir_remove_ioapic_hpet_scope(iommu);
1404 } else {
1405 iommu_enable_irq_remapping(iommu);
1406 }
1407
1408 return ret;
1409 }
1410
1411 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1412 {
1413 int ret = 0;
1414 struct intel_iommu *iommu = dmaru->iommu;
1415
1416 if (!irq_remapping_enabled)
1417 return 0;
1418 if (iommu == NULL)
1419 return -EINVAL;
1420 if (!ecap_ir_support(iommu->ecap))
1421 return 0;
1422 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1423 !cap_pi_support(iommu->cap))
1424 return -EBUSY;
1425
1426 if (insert) {
1427 if (!iommu->ir_table)
1428 ret = dmar_ir_add(dmaru, iommu);
1429 } else {
1430 if (iommu->ir_table) {
1431 if (!bitmap_empty(iommu->ir_table->bitmap,
1432 INTR_REMAP_TABLE_ENTRIES)) {
1433 ret = -EBUSY;
1434 } else {
1435 iommu_disable_irq_remapping(iommu);
1436 intel_teardown_irq_remapping(iommu);
1437 ir_remove_ioapic_hpet_scope(iommu);
1438 }
1439 }
1440 }
1441
1442 return ret;
1443 }
Linux with added FPC-III support