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ARM: ep93xx: move timer to its own file
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_mr.c
blob6d190b4b82a072b2657e03ede8caa2d0a45e5d52
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include <linux/delay.h>
9 #include <linux/pci.h>
10 #include <linux/ratelimit.h>
11 #include <linux/vmalloc.h>
12 #include <scsi/scsi_tcq.h>
13 #include <linux/utsname.h>
14
15
16 /* QLAFX00 specific Mailbox implementation functions */
17
18 /*
19 * qlafx00_mailbox_command
20 * Issue mailbox command and waits for completion.
21 *
22 * Input:
23 * ha = adapter block pointer.
24 * mcp = driver internal mbx struct pointer.
25 *
26 * Output:
27 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
28 *
29 * Returns:
30 * 0 : QLA_SUCCESS = cmd performed success
31 * 1 : QLA_FUNCTION_FAILED (error encountered)
32 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
33 *
34 * Context:
35 * Kernel context.
36 */
37 static int
38 qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
39
40 {
41 int rval;
42 unsigned long flags = 0;
43 device_reg_t *reg;
44 uint8_t abort_active;
45 uint8_t io_lock_on;
46 uint16_t command = 0;
47 uint32_t *iptr;
48 uint32_t __iomem *optr;
49 uint32_t cnt;
50 uint32_t mboxes;
51 unsigned long wait_time;
52 struct qla_hw_data *ha = vha->hw;
53 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
54
55 if (ha->pdev->error_state > pci_channel_io_frozen) {
56 ql_log(ql_log_warn, vha, 0x115c,
57 "error_state is greater than pci_channel_io_frozen, "
58 "exiting.\n");
59 return QLA_FUNCTION_TIMEOUT;
60 }
61
62 if (vha->device_flags & DFLG_DEV_FAILED) {
63 ql_log(ql_log_warn, vha, 0x115f,
64 "Device in failed state, exiting.\n");
65 return QLA_FUNCTION_TIMEOUT;
66 }
67
68 reg = ha->iobase;
69 io_lock_on = base_vha->flags.init_done;
70
71 rval = QLA_SUCCESS;
72 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
73
74 if (ha->flags.pci_channel_io_perm_failure) {
75 ql_log(ql_log_warn, vha, 0x1175,
76 "Perm failure on EEH timeout MBX, exiting.\n");
77 return QLA_FUNCTION_TIMEOUT;
78 }
79
80 if (ha->flags.isp82xx_fw_hung) {
81 /* Setting Link-Down error */
82 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
83 ql_log(ql_log_warn, vha, 0x1176,
84 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
85 rval = QLA_FUNCTION_FAILED;
86 goto premature_exit;
87 }
88
89 /*
90 * Wait for active mailbox commands to finish by waiting at most tov
91 * seconds. This is to serialize actual issuing of mailbox cmds during
92 * non ISP abort time.
93 */
94 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
95 /* Timeout occurred. Return error. */
96 ql_log(ql_log_warn, vha, 0x1177,
97 "Cmd access timeout, cmd=0x%x, Exiting.\n",
98 mcp->mb[0]);
99 return QLA_FUNCTION_TIMEOUT;
100 }
101
102 ha->flags.mbox_busy = 1;
103 /* Save mailbox command for debug */
104 ha->mcp32 = mcp;
105
106 ql_dbg(ql_dbg_mbx, vha, 0x1178,
107 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
108
109 spin_lock_irqsave(&ha->hardware_lock, flags);
110
111 /* Load mailbox registers. */
112 optr = (uint32_t __iomem *)&reg->ispfx00.mailbox0;
113
114 iptr = mcp->mb;
115 command = mcp->mb[0];
116 mboxes = mcp->out_mb;
117
118 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
119 if (mboxes & BIT_0)
120 WRT_REG_DWORD(optr, *iptr);
121
122 mboxes >>= 1;
123 optr++;
124 iptr++;
125 }
126
127 /* Issue set host interrupt command to send cmd out. */
128 ha->flags.mbox_int = 0;
129 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
130
131 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
132 (uint8_t *)mcp->mb, 16);
133 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
134 ((uint8_t *)mcp->mb + 0x10), 16);
135 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
136 ((uint8_t *)mcp->mb + 0x20), 8);
137
138 /* Unlock mbx registers and wait for interrupt */
139 ql_dbg(ql_dbg_mbx, vha, 0x1179,
140 "Going to unlock irq & waiting for interrupts. "
141 "jiffies=%lx.\n", jiffies);
142
143 /* Wait for mbx cmd completion until timeout */
144 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
145 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
146
147 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
148 spin_unlock_irqrestore(&ha->hardware_lock, flags);
149
150 wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
151 } else {
152 ql_dbg(ql_dbg_mbx, vha, 0x112c,
153 "Cmd=%x Polling Mode.\n", command);
154
155 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
156 spin_unlock_irqrestore(&ha->hardware_lock, flags);
157
158 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
159 while (!ha->flags.mbox_int) {
160 if (time_after(jiffies, wait_time))
161 break;
162
163 /* Check for pending interrupts. */
164 qla2x00_poll(ha->rsp_q_map[0]);
165
166 if (!ha->flags.mbox_int &&
167 !(IS_QLA2200(ha) &&
168 command == MBC_LOAD_RISC_RAM_EXTENDED))
169 usleep_range(10000, 11000);
170 } /* while */
171 ql_dbg(ql_dbg_mbx, vha, 0x112d,
172 "Waited %d sec.\n",
173 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
174 }
175
176 /* Check whether we timed out */
177 if (ha->flags.mbox_int) {
178 uint32_t *iptr2;
179
180 ql_dbg(ql_dbg_mbx, vha, 0x112e,
181 "Cmd=%x completed.\n", command);
182
183 /* Got interrupt. Clear the flag. */
184 ha->flags.mbox_int = 0;
185 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
186
187 if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
188 rval = QLA_FUNCTION_FAILED;
189
190 /* Load return mailbox registers. */
191 iptr2 = mcp->mb;
192 iptr = (uint32_t *)&ha->mailbox_out32[0];
193 mboxes = mcp->in_mb;
194 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
195 if (mboxes & BIT_0)
196 *iptr2 = *iptr;
197
198 mboxes >>= 1;
199 iptr2++;
200 iptr++;
201 }
202 } else {
203
204 rval = QLA_FUNCTION_TIMEOUT;
205 }
206
207 ha->flags.mbox_busy = 0;
208
209 /* Clean up */
210 ha->mcp32 = NULL;
211
212 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
213 ql_dbg(ql_dbg_mbx, vha, 0x113a,
214 "checking for additional resp interrupt.\n");
215
216 /* polling mode for non isp_abort commands. */
217 qla2x00_poll(ha->rsp_q_map[0]);
218 }
219
220 if (rval == QLA_FUNCTION_TIMEOUT &&
221 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
222 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
223 ha->flags.eeh_busy) {
224 /* not in dpc. schedule it for dpc to take over. */
225 ql_dbg(ql_dbg_mbx, vha, 0x115d,
226 "Timeout, schedule isp_abort_needed.\n");
227
228 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
229 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
230 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
231
232 ql_log(ql_log_info, base_vha, 0x115e,
233 "Mailbox cmd timeout occurred, cmd=0x%x, "
234 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
235 "abort.\n", command, mcp->mb[0],
236 ha->flags.eeh_busy);
237 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
238 qla2xxx_wake_dpc(vha);
239 }
240 } else if (!abort_active) {
241 /* call abort directly since we are in the DPC thread */
242 ql_dbg(ql_dbg_mbx, vha, 0x1160,
243 "Timeout, calling abort_isp.\n");
244
245 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
246 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
247 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
248
249 ql_log(ql_log_info, base_vha, 0x1161,
250 "Mailbox cmd timeout occurred, cmd=0x%x, "
251 "mb[0]=0x%x. Scheduling ISP abort ",
252 command, mcp->mb[0]);
253
254 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
255 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
256 if (ha->isp_ops->abort_isp(vha)) {
257 /* Failed. retry later. */
258 set_bit(ISP_ABORT_NEEDED,
259 &vha->dpc_flags);
260 }
261 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
262 ql_dbg(ql_dbg_mbx, vha, 0x1162,
263 "Finished abort_isp.\n");
264 }
265 }
266 }
267
268 premature_exit:
269 /* Allow next mbx cmd to come in. */
270 complete(&ha->mbx_cmd_comp);
271
272 if (rval) {
273 ql_log(ql_log_warn, base_vha, 0x1163,
274 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, "
275 "mb[3]=%x, cmd=%x ****.\n",
276 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
277 } else {
278 ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
279 }
280
281 return rval;
282 }
283
284 /*
285 * qlafx00_driver_shutdown
286 * Indicate a driver shutdown to firmware.
287 *
288 * Input:
289 * ha = adapter block pointer.
290 *
291 * Returns:
292 * local function return status code.
293 *
294 * Context:
295 * Kernel context.
296 */
297 int
298 qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
299 {
300 int rval;
301 struct mbx_cmd_32 mc;
302 struct mbx_cmd_32 *mcp = &mc;
303
304 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
305 "Entered %s.\n", __func__);
306
307 mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
308 mcp->out_mb = MBX_0;
309 mcp->in_mb = MBX_0;
310 if (tmo)
311 mcp->tov = tmo;
312 else
313 mcp->tov = MBX_TOV_SECONDS;
314 mcp->flags = 0;
315 rval = qlafx00_mailbox_command(vha, mcp);
316
317 if (rval != QLA_SUCCESS) {
318 ql_dbg(ql_dbg_mbx, vha, 0x1167,
319 "Failed=%x.\n", rval);
320 } else {
321 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
322 "Done %s.\n", __func__);
323 }
324
325 return rval;
326 }
327
328 /*
329 * qlafx00_get_firmware_state
330 * Get adapter firmware state.
331 *
332 * Input:
333 * ha = adapter block pointer.
334 * TARGET_QUEUE_LOCK must be released.
335 * ADAPTER_STATE_LOCK must be released.
336 *
337 * Returns:
338 * qla7xxx local function return status code.
339 *
340 * Context:
341 * Kernel context.
342 */
343 static int
344 qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
345 {
346 int rval;
347 struct mbx_cmd_32 mc;
348 struct mbx_cmd_32 *mcp = &mc;
349
350 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
351 "Entered %s.\n", __func__);
352
353 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
354 mcp->out_mb = MBX_0;
355 mcp->in_mb = MBX_1|MBX_0;
356 mcp->tov = MBX_TOV_SECONDS;
357 mcp->flags = 0;
358 rval = qlafx00_mailbox_command(vha, mcp);
359
360 /* Return firmware states. */
361 states[0] = mcp->mb[1];
362
363 if (rval != QLA_SUCCESS) {
364 ql_dbg(ql_dbg_mbx, vha, 0x116a,
365 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
366 } else {
367 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
368 "Done %s.\n", __func__);
369 }
370 return rval;
371 }
372
373 /*
374 * qlafx00_init_firmware
375 * Initialize adapter firmware.
376 *
377 * Input:
378 * ha = adapter block pointer.
379 * dptr = Initialization control block pointer.
380 * size = size of initialization control block.
381 * TARGET_QUEUE_LOCK must be released.
382 * ADAPTER_STATE_LOCK must be released.
383 *
384 * Returns:
385 * qlafx00 local function return status code.
386 *
387 * Context:
388 * Kernel context.
389 */
390 int
391 qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
392 {
393 int rval;
394 struct mbx_cmd_32 mc;
395 struct mbx_cmd_32 *mcp = &mc;
396 struct qla_hw_data *ha = vha->hw;
397
398 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
399 "Entered %s.\n", __func__);
400
401 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
402
403 mcp->mb[1] = 0;
404 mcp->mb[2] = MSD(ha->init_cb_dma);
405 mcp->mb[3] = LSD(ha->init_cb_dma);
406
407 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
408 mcp->in_mb = MBX_0;
409 mcp->buf_size = size;
410 mcp->flags = MBX_DMA_OUT;
411 mcp->tov = MBX_TOV_SECONDS;
412 rval = qlafx00_mailbox_command(vha, mcp);
413
414 if (rval != QLA_SUCCESS) {
415 ql_dbg(ql_dbg_mbx, vha, 0x116d,
416 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
417 } else {
418 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
419 "Done %s.\n", __func__);
420 }
421 return rval;
422 }
423
424 /*
425 * qlafx00_mbx_reg_test
426 */
427 static int
428 qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
429 {
430 int rval;
431 struct mbx_cmd_32 mc;
432 struct mbx_cmd_32 *mcp = &mc;
433
434 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
435 "Entered %s.\n", __func__);
436
437
438 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
439 mcp->mb[1] = 0xAAAA;
440 mcp->mb[2] = 0x5555;
441 mcp->mb[3] = 0xAA55;
442 mcp->mb[4] = 0x55AA;
443 mcp->mb[5] = 0xA5A5;
444 mcp->mb[6] = 0x5A5A;
445 mcp->mb[7] = 0x2525;
446 mcp->mb[8] = 0xBBBB;
447 mcp->mb[9] = 0x6666;
448 mcp->mb[10] = 0xBB66;
449 mcp->mb[11] = 0x66BB;
450 mcp->mb[12] = 0xB6B6;
451 mcp->mb[13] = 0x6B6B;
452 mcp->mb[14] = 0x3636;
453 mcp->mb[15] = 0xCCCC;
454
455
456 mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
457 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
458 mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
459 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
460 mcp->buf_size = 0;
461 mcp->flags = MBX_DMA_OUT;
462 mcp->tov = MBX_TOV_SECONDS;
463 rval = qlafx00_mailbox_command(vha, mcp);
464 if (rval == QLA_SUCCESS) {
465 if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
466 mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
467 rval = QLA_FUNCTION_FAILED;
468 if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
469 mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
470 rval = QLA_FUNCTION_FAILED;
471 if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
472 mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
473 rval = QLA_FUNCTION_FAILED;
474 if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
475 mcp->mb[31] != 0xCCCC)
476 rval = QLA_FUNCTION_FAILED;
477 }
478
479 if (rval != QLA_SUCCESS) {
480 ql_dbg(ql_dbg_mbx, vha, 0x1170,
481 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
482 } else {
483 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
484 "Done %s.\n", __func__);
485 }
486 return rval;
487 }
488
489 /**
490 * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
491 * @ha: HA context
492 *
493 * Returns 0 on success.
494 */
495 int
496 qlafx00_pci_config(scsi_qla_host_t *vha)
497 {
498 uint16_t w;
499 struct qla_hw_data *ha = vha->hw;
500
501 pci_set_master(ha->pdev);
502 pci_try_set_mwi(ha->pdev);
503
504 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
505 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
506 w &= ~PCI_COMMAND_INTX_DISABLE;
507 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
508
509 /* PCIe -- adjust Maximum Read Request Size (2048). */
510 if (pci_is_pcie(ha->pdev))
511 pcie_set_readrq(ha->pdev, 2048);
512
513 ha->chip_revision = ha->pdev->revision;
514
515 return QLA_SUCCESS;
516 }
517
518 /**
519 * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
520 * @ha: HA context
521 *
522 */
523 static inline void
524 qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
525 {
526 unsigned long flags = 0;
527 struct qla_hw_data *ha = vha->hw;
528 int i, core;
529 uint32_t cnt;
530 uint32_t reg_val;
531
532 spin_lock_irqsave(&ha->hardware_lock, flags);
533
534 QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
535 QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
536
537 /* stop the XOR DMA engines */
538 QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
539 QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
540 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
541 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
542
543 /* stop the IDMA engines */
544 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
545 reg_val &= ~(1<<12);
546 QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
547
548 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
549 reg_val &= ~(1<<12);
550 QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
551
552 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
553 reg_val &= ~(1<<12);
554 QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
555
556 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
557 reg_val &= ~(1<<12);
558 QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
559
560 for (i = 0; i < 100000; i++) {
561 if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
562 (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
563 break;
564 udelay(100);
565 }
566
567 /* Set all 4 cores in reset */
568 for (i = 0; i < 4; i++) {
569 QLAFX00_SET_HBA_SOC_REG(ha,
570 (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
571 QLAFX00_SET_HBA_SOC_REG(ha,
572 (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
573 }
574
575 /* Reset all units in Fabric */
576 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
577
578 /* */
579 QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
580 QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
581
582 /* Set all 4 core Memory Power Down Registers */
583 for (i = 0; i < 5; i++) {
584 QLAFX00_SET_HBA_SOC_REG(ha,
585 (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
586 }
587
588 /* Reset all interrupt control registers */
589 for (i = 0; i < 115; i++) {
590 QLAFX00_SET_HBA_SOC_REG(ha,
591 (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
592 }
593
594 /* Reset Timers control registers. per core */
595 for (core = 0; core < 4; core++)
596 for (i = 0; i < 8; i++)
597 QLAFX00_SET_HBA_SOC_REG(ha,
598 (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
599
600 /* Reset per core IRQ ack register */
601 for (core = 0; core < 4; core++)
602 QLAFX00_SET_HBA_SOC_REG(ha,
603 (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
604
605 /* Set Fabric control and config to defaults */
606 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
607 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
608
609 /* Kick in Fabric units */
610 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
611
612 /* Kick in Core0 to start boot process */
613 QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
614
615 spin_unlock_irqrestore(&ha->hardware_lock, flags);
616
617 /* Wait 10secs for soft-reset to complete. */
618 for (cnt = 10; cnt; cnt--) {
619 msleep(1000);
620 barrier();
621 }
622 }
623
624 /**
625 * qlafx00_soft_reset() - Soft Reset ISPFx00.
626 * @ha: HA context
627 *
628 * Returns 0 on success.
629 */
630 void
631 qlafx00_soft_reset(scsi_qla_host_t *vha)
632 {
633 struct qla_hw_data *ha = vha->hw;
634
635 if (unlikely(pci_channel_offline(ha->pdev) &&
636 ha->flags.pci_channel_io_perm_failure))
637 return;
638
639 ha->isp_ops->disable_intrs(ha);
640 qlafx00_soc_cpu_reset(vha);
641 }
642
643 /**
644 * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
645 * @ha: HA context
646 *
647 * Returns 0 on success.
648 */
649 int
650 qlafx00_chip_diag(scsi_qla_host_t *vha)
651 {
652 int rval = 0;
653 struct qla_hw_data *ha = vha->hw;
654 struct req_que *req = ha->req_q_map[0];
655
656 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
657
658 rval = qlafx00_mbx_reg_test(vha);
659 if (rval) {
660 ql_log(ql_log_warn, vha, 0x1165,
661 "Failed mailbox send register test\n");
662 } else {
663 /* Flag a successful rval */
664 rval = QLA_SUCCESS;
665 }
666 return rval;
667 }
668
669 void
670 qlafx00_config_rings(struct scsi_qla_host *vha)
671 {
672 struct qla_hw_data *ha = vha->hw;
673 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
674
675 WRT_REG_DWORD(&reg->req_q_in, 0);
676 WRT_REG_DWORD(&reg->req_q_out, 0);
677
678 WRT_REG_DWORD(&reg->rsp_q_in, 0);
679 WRT_REG_DWORD(&reg->rsp_q_out, 0);
680
681 /* PCI posting */
682 RD_REG_DWORD(&reg->rsp_q_out);
683 }
684
685 char *
686 qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str)
687 {
688 struct qla_hw_data *ha = vha->hw;
689
690 if (pci_is_pcie(ha->pdev)) {
691 strcpy(str, "PCIe iSA");
692 return str;
693 }
694 return str;
695 }
696
697 char *
698 qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
699 {
700 struct qla_hw_data *ha = vha->hw;
701
702 snprintf(str, size, "%s", ha->mr.fw_version);
703 return str;
704 }
705
706 void
707 qlafx00_enable_intrs(struct qla_hw_data *ha)
708 {
709 unsigned long flags = 0;
710
711 spin_lock_irqsave(&ha->hardware_lock, flags);
712 ha->interrupts_on = 1;
713 QLAFX00_ENABLE_ICNTRL_REG(ha);
714 spin_unlock_irqrestore(&ha->hardware_lock, flags);
715 }
716
717 void
718 qlafx00_disable_intrs(struct qla_hw_data *ha)
719 {
720 unsigned long flags = 0;
721
722 spin_lock_irqsave(&ha->hardware_lock, flags);
723 ha->interrupts_on = 0;
724 QLAFX00_DISABLE_ICNTRL_REG(ha);
725 spin_unlock_irqrestore(&ha->hardware_lock, flags);
726 }
727
728 int
729 qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag)
730 {
731 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
732 }
733
734 int
735 qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag)
736 {
737 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
738 }
739
740 int
741 qlafx00_loop_reset(scsi_qla_host_t *vha)
742 {
743 int ret;
744 struct fc_port *fcport;
745 struct qla_hw_data *ha = vha->hw;
746
747 if (ql2xtargetreset) {
748 list_for_each_entry(fcport, &vha->vp_fcports, list) {
749 if (fcport->port_type != FCT_TARGET)
750 continue;
751
752 ret = ha->isp_ops->target_reset(fcport, 0, 0);
753 if (ret != QLA_SUCCESS) {
754 ql_dbg(ql_dbg_taskm, vha, 0x803d,
755 "Bus Reset failed: Reset=%d "
756 "d_id=%x.\n", ret, fcport->d_id.b24);
757 }
758 }
759 }
760 return QLA_SUCCESS;
761 }
762
763 int
764 qlafx00_iospace_config(struct qla_hw_data *ha)
765 {
766 if (pci_request_selected_regions(ha->pdev, ha->bars,
767 QLA2XXX_DRIVER_NAME)) {
768 ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
769 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
770 pci_name(ha->pdev));
771 goto iospace_error_exit;
772 }
773
774 /* Use MMIO operations for all accesses. */
775 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
776 ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
777 "Invalid pci I/O region size (%s).\n",
778 pci_name(ha->pdev));
779 goto iospace_error_exit;
780 }
781 if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
782 ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
783 "Invalid PCI mem BAR0 region size (%s), aborting\n",
784 pci_name(ha->pdev));
785 goto iospace_error_exit;
786 }
787
788 ha->cregbase =
789 ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
790 if (!ha->cregbase) {
791 ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
792 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
793 goto iospace_error_exit;
794 }
795
796 if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
797 ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
798 "region #2 not an MMIO resource (%s), aborting\n",
799 pci_name(ha->pdev));
800 goto iospace_error_exit;
801 }
802 if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
803 ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
804 "Invalid PCI mem BAR2 region size (%s), aborting\n",
805 pci_name(ha->pdev));
806 goto iospace_error_exit;
807 }
808
809 ha->iobase =
810 ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
811 if (!ha->iobase) {
812 ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
813 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
814 goto iospace_error_exit;
815 }
816
817 /* Determine queue resources */
818 ha->max_req_queues = ha->max_rsp_queues = 1;
819
820 ql_log_pci(ql_log_info, ha->pdev, 0x012c,
821 "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
822 ha->bars, ha->cregbase, ha->iobase);
823
824 return 0;
825
826 iospace_error_exit:
827 return -ENOMEM;
828 }
829
830 static void
831 qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
832 {
833 struct qla_hw_data *ha = vha->hw;
834 struct req_que *req = ha->req_q_map[0];
835 struct rsp_que *rsp = ha->rsp_q_map[0];
836
837 req->length_fx00 = req->length;
838 req->ring_fx00 = req->ring;
839 req->dma_fx00 = req->dma;
840
841 rsp->length_fx00 = rsp->length;
842 rsp->ring_fx00 = rsp->ring;
843 rsp->dma_fx00 = rsp->dma;
844
845 ql_dbg(ql_dbg_init, vha, 0x012d,
846 "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
847 "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
848 req->length_fx00, (u64)req->dma_fx00);
849
850 ql_dbg(ql_dbg_init, vha, 0x012e,
851 "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
852 "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
853 rsp->length_fx00, (u64)rsp->dma_fx00);
854 }
855
856 static int
857 qlafx00_config_queues(struct scsi_qla_host *vha)
858 {
859 struct qla_hw_data *ha = vha->hw;
860 struct req_que *req = ha->req_q_map[0];
861 struct rsp_que *rsp = ha->rsp_q_map[0];
862 dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
863
864 req->length = ha->req_que_len;
865 req->ring = (void *)ha->iobase + ha->req_que_off;
866 req->dma = bar2_hdl + ha->req_que_off;
867 if ((!req->ring) || (req->length == 0)) {
868 ql_log_pci(ql_log_info, ha->pdev, 0x012f,
869 "Unable to allocate memory for req_ring\n");
870 return QLA_FUNCTION_FAILED;
871 }
872
873 ql_dbg(ql_dbg_init, vha, 0x0130,
874 "req: %p req_ring pointer %p req len 0x%x "
875 "req off 0x%x\n, req->dma: 0x%llx",
876 req, req->ring, req->length,
877 ha->req_que_off, (u64)req->dma);
878
879 rsp->length = ha->rsp_que_len;
880 rsp->ring = (void *)ha->iobase + ha->rsp_que_off;
881 rsp->dma = bar2_hdl + ha->rsp_que_off;
882 if ((!rsp->ring) || (rsp->length == 0)) {
883 ql_log_pci(ql_log_info, ha->pdev, 0x0131,
884 "Unable to allocate memory for rsp_ring\n");
885 return QLA_FUNCTION_FAILED;
886 }
887
888 ql_dbg(ql_dbg_init, vha, 0x0132,
889 "rsp: %p rsp_ring pointer %p rsp len 0x%x "
890 "rsp off 0x%x, rsp->dma: 0x%llx\n",
891 rsp, rsp->ring, rsp->length,
892 ha->rsp_que_off, (u64)rsp->dma);
893
894 return QLA_SUCCESS;
895 }
896
897 static int
898 qlafx00_init_fw_ready(scsi_qla_host_t *vha)
899 {
900 int rval = 0;
901 unsigned long wtime;
902 uint16_t wait_time; /* Wait time */
903 struct qla_hw_data *ha = vha->hw;
904 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
905 uint32_t aenmbx, aenmbx7 = 0;
906 uint32_t pseudo_aen;
907 uint32_t state[5];
908 bool done = false;
909
910 /* 30 seconds wait - Adjust if required */
911 wait_time = 30;
912
913 pseudo_aen = RD_REG_DWORD(&reg->pseudoaen);
914 if (pseudo_aen == 1) {
915 aenmbx7 = RD_REG_DWORD(&reg->initval7);
916 ha->mbx_intr_code = MSW(aenmbx7);
917 ha->rqstq_intr_code = LSW(aenmbx7);
918 rval = qlafx00_driver_shutdown(vha, 10);
919 if (rval != QLA_SUCCESS)
920 qlafx00_soft_reset(vha);
921 }
922
923 /* wait time before firmware ready */
924 wtime = jiffies + (wait_time * HZ);
925 do {
926 aenmbx = RD_REG_DWORD(&reg->aenmailbox0);
927 barrier();
928 ql_dbg(ql_dbg_mbx, vha, 0x0133,
929 "aenmbx: 0x%x\n", aenmbx);
930
931 switch (aenmbx) {
932 case MBA_FW_NOT_STARTED:
933 case MBA_FW_STARTING:
934 break;
935
936 case MBA_SYSTEM_ERR:
937 case MBA_REQ_TRANSFER_ERR:
938 case MBA_RSP_TRANSFER_ERR:
939 case MBA_FW_INIT_FAILURE:
940 qlafx00_soft_reset(vha);
941 break;
942
943 case MBA_FW_RESTART_CMPLT:
944 /* Set the mbx and rqstq intr code */
945 aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
946 ha->mbx_intr_code = MSW(aenmbx7);
947 ha->rqstq_intr_code = LSW(aenmbx7);
948 ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
949 ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
950 ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
951 ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
952 WRT_REG_DWORD(&reg->aenmailbox0, 0);
953 RD_REG_DWORD_RELAXED(&reg->aenmailbox0);
954 ql_dbg(ql_dbg_init, vha, 0x0134,
955 "f/w returned mbx_intr_code: 0x%x, "
956 "rqstq_intr_code: 0x%x\n",
957 ha->mbx_intr_code, ha->rqstq_intr_code);
958 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
959 rval = QLA_SUCCESS;
960 done = true;
961 break;
962
963 default:
964 if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS)
965 break;
966
967 /* If fw is apparently not ready. In order to continue,
968 * we might need to issue Mbox cmd, but the problem is
969 * that the DoorBell vector values that come with the
970 * 8060 AEN are most likely gone by now (and thus no
971 * bell would be rung on the fw side when mbox cmd is
972 * issued). We have to therefore grab the 8060 AEN
973 * shadow regs (filled in by FW when the last 8060
974 * AEN was being posted).
975 * Do the following to determine what is needed in
976 * order to get the FW ready:
977 * 1. reload the 8060 AEN values from the shadow regs
978 * 2. clear int status to get rid of possible pending
979 * interrupts
980 * 3. issue Get FW State Mbox cmd to determine fw state
981 * Set the mbx and rqstq intr code from Shadow Regs
982 */
983 aenmbx7 = RD_REG_DWORD(&reg->initval7);
984 ha->mbx_intr_code = MSW(aenmbx7);
985 ha->rqstq_intr_code = LSW(aenmbx7);
986 ha->req_que_off = RD_REG_DWORD(&reg->initval1);
987 ha->rsp_que_off = RD_REG_DWORD(&reg->initval3);
988 ha->req_que_len = RD_REG_DWORD(&reg->initval5);
989 ha->rsp_que_len = RD_REG_DWORD(&reg->initval6);
990 ql_dbg(ql_dbg_init, vha, 0x0135,
991 "f/w returned mbx_intr_code: 0x%x, "
992 "rqstq_intr_code: 0x%x\n",
993 ha->mbx_intr_code, ha->rqstq_intr_code);
994 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
995
996 /* Get the FW state */
997 rval = qlafx00_get_firmware_state(vha, state);
998 if (rval != QLA_SUCCESS) {
999 /* Retry if timer has not expired */
1000 break;
1001 }
1002
1003 if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
1004 /* Firmware is waiting to be
1005 * initialized by driver
1006 */
1007 rval = QLA_SUCCESS;
1008 done = true;
1009 break;
1010 }
1011
1012 /* Issue driver shutdown and wait until f/w recovers.
1013 * Driver should continue to poll until 8060 AEN is
1014 * received indicating firmware recovery.
1015 */
1016 ql_dbg(ql_dbg_init, vha, 0x0136,
1017 "Sending Driver shutdown fw_state 0x%x\n",
1018 state[0]);
1019
1020 rval = qlafx00_driver_shutdown(vha, 10);
1021 if (rval != QLA_SUCCESS) {
1022 rval = QLA_FUNCTION_FAILED;
1023 break;
1024 }
1025 msleep(500);
1026
1027 wtime = jiffies + (wait_time * HZ);
1028 break;
1029 }
1030
1031 if (!done) {
1032 if (time_after_eq(jiffies, wtime)) {
1033 ql_dbg(ql_dbg_init, vha, 0x0137,
1034 "Init f/w failed: aen[7]: 0x%x\n",
1035 RD_REG_DWORD(&reg->aenmailbox7));
1036 rval = QLA_FUNCTION_FAILED;
1037 done = true;
1038 break;
1039 }
1040 /* Delay for a while */
1041 msleep(500);
1042 }
1043 } while (!done);
1044
1045 if (rval)
1046 ql_dbg(ql_dbg_init, vha, 0x0138,
1047 "%s **** FAILED ****.\n", __func__);
1048 else
1049 ql_dbg(ql_dbg_init, vha, 0x0139,
1050 "%s **** SUCCESS ****.\n", __func__);
1051
1052 return rval;
1053 }
1054
1055 /*
1056 * qlafx00_fw_ready() - Waits for firmware ready.
1057 * @ha: HA context
1058 *
1059 * Returns 0 on success.
1060 */
1061 int
1062 qlafx00_fw_ready(scsi_qla_host_t *vha)
1063 {
1064 int rval;
1065 unsigned long wtime;
1066 uint16_t wait_time; /* Wait time if loop is coming ready */
1067 uint32_t state[5];
1068
1069 rval = QLA_SUCCESS;
1070
1071 wait_time = 10;
1072
1073 /* wait time before firmware ready */
1074 wtime = jiffies + (wait_time * HZ);
1075
1076 /* Wait for ISP to finish init */
1077 if (!vha->flags.init_done)
1078 ql_dbg(ql_dbg_init, vha, 0x013a,
1079 "Waiting for init to complete...\n");
1080
1081 do {
1082 rval = qlafx00_get_firmware_state(vha, state);
1083
1084 if (rval == QLA_SUCCESS) {
1085 if (state[0] == FSTATE_FX00_INITIALIZED) {
1086 ql_dbg(ql_dbg_init, vha, 0x013b,
1087 "fw_state=%x\n", state[0]);
1088 rval = QLA_SUCCESS;
1089 break;
1090 }
1091 }
1092 rval = QLA_FUNCTION_FAILED;
1093
1094 if (time_after_eq(jiffies, wtime))
1095 break;
1096
1097 /* Delay for a while */
1098 msleep(500);
1099
1100 ql_dbg(ql_dbg_init, vha, 0x013c,
1101 "fw_state=%x curr time=%lx.\n", state[0], jiffies);
1102 } while (1);
1103
1104
1105 if (rval)
1106 ql_dbg(ql_dbg_init, vha, 0x013d,
1107 "Firmware ready **** FAILED ****.\n");
1108 else
1109 ql_dbg(ql_dbg_init, vha, 0x013e,
1110 "Firmware ready **** SUCCESS ****.\n");
1111
1112 return rval;
1113 }
1114
1115 static int
1116 qlafx00_find_all_targets(scsi_qla_host_t *vha,
1117 struct list_head *new_fcports)
1118 {
1119 int rval;
1120 uint16_t tgt_id;
1121 fc_port_t *fcport, *new_fcport;
1122 int found;
1123 struct qla_hw_data *ha = vha->hw;
1124
1125 rval = QLA_SUCCESS;
1126
1127 if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1128 return QLA_FUNCTION_FAILED;
1129
1130 if ((atomic_read(&vha->loop_down_timer) ||
1131 STATE_TRANSITION(vha))) {
1132 atomic_set(&vha->loop_down_timer, 0);
1133 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1134 return QLA_FUNCTION_FAILED;
1135 }
1136
1137 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
1138 "Listing Target bit map...\n");
1139 ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
1140 0x2089, (uint8_t *)ha->gid_list, 32);
1141
1142 /* Allocate temporary rmtport for any new rmtports discovered. */
1143 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1144 if (new_fcport == NULL)
1145 return QLA_MEMORY_ALLOC_FAILED;
1146
1147 for_each_set_bit(tgt_id, (void *)ha->gid_list,
1148 QLAFX00_TGT_NODE_LIST_SIZE) {
1149
1150 /* Send get target node info */
1151 new_fcport->tgt_id = tgt_id;
1152 rval = qlafx00_fx_disc(vha, new_fcport,
1153 FXDISC_GET_TGT_NODE_INFO);
1154 if (rval != QLA_SUCCESS) {
1155 ql_log(ql_log_warn, vha, 0x208a,
1156 "Target info scan failed -- assuming zero-entry "
1157 "result...\n");
1158 continue;
1159 }
1160
1161 /* Locate matching device in database. */
1162 found = 0;
1163 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1164 if (memcmp(new_fcport->port_name,
1165 fcport->port_name, WWN_SIZE))
1166 continue;
1167
1168 found++;
1169
1170 /*
1171 * If tgt_id is same and state FCS_ONLINE, nothing
1172 * changed.
1173 */
1174 if (fcport->tgt_id == new_fcport->tgt_id &&
1175 atomic_read(&fcport->state) == FCS_ONLINE)
1176 break;
1177
1178 /*
1179 * Tgt ID changed or device was marked to be updated.
1180 */
1181 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
1182 "TGT-ID Change(%s): Present tgt id: "
1183 "0x%x state: 0x%x "
1184 "wwnn = %llx wwpn = %llx.\n",
1185 __func__, fcport->tgt_id,
1186 atomic_read(&fcport->state),
1187 (unsigned long long)wwn_to_u64(fcport->node_name),
1188 (unsigned long long)wwn_to_u64(fcport->port_name));
1189
1190 ql_log(ql_log_info, vha, 0x208c,
1191 "TGT-ID Announce(%s): Discovered tgt "
1192 "id 0x%x wwnn = %llx "
1193 "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
1194 (unsigned long long)
1195 wwn_to_u64(new_fcport->node_name),
1196 (unsigned long long)
1197 wwn_to_u64(new_fcport->port_name));
1198
1199 if (atomic_read(&fcport->state) != FCS_ONLINE) {
1200 fcport->old_tgt_id = fcport->tgt_id;
1201 fcport->tgt_id = new_fcport->tgt_id;
1202 ql_log(ql_log_info, vha, 0x208d,
1203 "TGT-ID: New fcport Added: %p\n", fcport);
1204 qla2x00_update_fcport(vha, fcport);
1205 } else {
1206 ql_log(ql_log_info, vha, 0x208e,
1207 " Existing TGT-ID %x did not get "
1208 " offline event from firmware.\n",
1209 fcport->old_tgt_id);
1210 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1211 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1212 kfree(new_fcport);
1213 return rval;
1214 }
1215 break;
1216 }
1217
1218 if (found)
1219 continue;
1220
1221 /* If device was not in our fcports list, then add it. */
1222 list_add_tail(&new_fcport->list, new_fcports);
1223
1224 /* Allocate a new replacement fcport. */
1225 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1226 if (new_fcport == NULL)
1227 return QLA_MEMORY_ALLOC_FAILED;
1228 }
1229
1230 kfree(new_fcport);
1231 return rval;
1232 }
1233
1234 /*
1235 * qlafx00_configure_all_targets
1236 * Setup target devices with node ID's.
1237 *
1238 * Input:
1239 * ha = adapter block pointer.
1240 *
1241 * Returns:
1242 * 0 = success.
1243 * BIT_0 = error
1244 */
1245 static int
1246 qlafx00_configure_all_targets(scsi_qla_host_t *vha)
1247 {
1248 int rval;
1249 fc_port_t *fcport, *rmptemp;
1250 LIST_HEAD(new_fcports);
1251
1252 rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1253 FXDISC_GET_TGT_NODE_LIST);
1254 if (rval != QLA_SUCCESS) {
1255 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1256 return rval;
1257 }
1258
1259 rval = qlafx00_find_all_targets(vha, &new_fcports);
1260 if (rval != QLA_SUCCESS) {
1261 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1262 return rval;
1263 }
1264
1265 /*
1266 * Delete all previous devices marked lost.
1267 */
1268 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1269 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1270 break;
1271
1272 if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
1273 if (fcport->port_type != FCT_INITIATOR)
1274 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1275 }
1276 }
1277
1278 /*
1279 * Add the new devices to our devices list.
1280 */
1281 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1282 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1283 break;
1284
1285 qla2x00_update_fcport(vha, fcport);
1286 list_move_tail(&fcport->list, &vha->vp_fcports);
1287 ql_log(ql_log_info, vha, 0x208f,
1288 "Attach new target id 0x%x wwnn = %llx "
1289 "wwpn = %llx.\n",
1290 fcport->tgt_id,
1291 (unsigned long long)wwn_to_u64(fcport->node_name),
1292 (unsigned long long)wwn_to_u64(fcport->port_name));
1293 }
1294
1295 /* Free all new device structures not processed. */
1296 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1297 list_del(&fcport->list);
1298 kfree(fcport);
1299 }
1300
1301 return rval;
1302 }
1303
1304 /*
1305 * qlafx00_configure_devices
1306 * Updates Fibre Channel Device Database with what is actually on loop.
1307 *
1308 * Input:
1309 * ha = adapter block pointer.
1310 *
1311 * Returns:
1312 * 0 = success.
1313 * 1 = error.
1314 * 2 = database was full and device was not configured.
1315 */
1316 int
1317 qlafx00_configure_devices(scsi_qla_host_t *vha)
1318 {
1319 int rval;
1320 unsigned long flags, save_flags;
1321 rval = QLA_SUCCESS;
1322
1323 save_flags = flags = vha->dpc_flags;
1324
1325 ql_dbg(ql_dbg_disc, vha, 0x2090,
1326 "Configure devices -- dpc flags =0x%lx\n", flags);
1327
1328 rval = qlafx00_configure_all_targets(vha);
1329
1330 if (rval == QLA_SUCCESS) {
1331 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1332 rval = QLA_FUNCTION_FAILED;
1333 } else {
1334 atomic_set(&vha->loop_state, LOOP_READY);
1335 ql_log(ql_log_info, vha, 0x2091,
1336 "Device Ready\n");
1337 }
1338 }
1339
1340 if (rval) {
1341 ql_dbg(ql_dbg_disc, vha, 0x2092,
1342 "%s *** FAILED ***.\n", __func__);
1343 } else {
1344 ql_dbg(ql_dbg_disc, vha, 0x2093,
1345 "%s: exiting normally.\n", __func__);
1346 }
1347 return rval;
1348 }
1349
1350 static void
1351 qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
1352 {
1353 struct qla_hw_data *ha = vha->hw;
1354 fc_port_t *fcport;
1355
1356 vha->flags.online = 0;
1357 ha->mr.fw_hbt_en = 0;
1358
1359 if (!critemp) {
1360 ha->flags.chip_reset_done = 0;
1361 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1362 vha->qla_stats.total_isp_aborts++;
1363 ql_log(ql_log_info, vha, 0x013f,
1364 "Performing ISP error recovery - ha = %p.\n", ha);
1365 ha->isp_ops->reset_chip(vha);
1366 }
1367
1368 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
1369 atomic_set(&vha->loop_state, LOOP_DOWN);
1370 atomic_set(&vha->loop_down_timer,
1371 QLAFX00_LOOP_DOWN_TIME);
1372 } else {
1373 if (!atomic_read(&vha->loop_down_timer))
1374 atomic_set(&vha->loop_down_timer,
1375 QLAFX00_LOOP_DOWN_TIME);
1376 }
1377
1378 /* Clear all async request states across all VPs. */
1379 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1380 fcport->flags = 0;
1381 if (atomic_read(&fcport->state) == FCS_ONLINE)
1382 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1383 }
1384
1385 if (!ha->flags.eeh_busy) {
1386 if (critemp) {
1387 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
1388 } else {
1389 /* Requeue all commands in outstanding command list. */
1390 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
1391 }
1392 }
1393
1394 qla2x00_free_irqs(vha);
1395 if (critemp)
1396 set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
1397 else
1398 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1399
1400 /* Clear the Interrupts */
1401 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1402
1403 ql_log(ql_log_info, vha, 0x0140,
1404 "%s Done done - ha=%p.\n", __func__, ha);
1405 }
1406
1407 /**
1408 * qlafx00_init_response_q_entries() - Initializes response queue entries.
1409 * @ha: HA context
1410 *
1411 * Beginning of request ring has initialization control block already built
1412 * by nvram config routine.
1413 *
1414 * Returns 0 on success.
1415 */
1416 void
1417 qlafx00_init_response_q_entries(struct rsp_que *rsp)
1418 {
1419 uint16_t cnt;
1420 response_t *pkt;
1421
1422 rsp->ring_ptr = rsp->ring;
1423 rsp->ring_index = 0;
1424 rsp->status_srb = NULL;
1425 pkt = rsp->ring_ptr;
1426 for (cnt = 0; cnt < rsp->length; cnt++) {
1427 pkt->signature = RESPONSE_PROCESSED;
1428 WRT_REG_DWORD((void __iomem *)&pkt->signature,
1429 RESPONSE_PROCESSED);
1430 pkt++;
1431 }
1432 }
1433
1434 int
1435 qlafx00_rescan_isp(scsi_qla_host_t *vha)
1436 {
1437 uint32_t status = QLA_FUNCTION_FAILED;
1438 struct qla_hw_data *ha = vha->hw;
1439 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1440 uint32_t aenmbx7;
1441
1442 qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
1443
1444 aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
1445 ha->mbx_intr_code = MSW(aenmbx7);
1446 ha->rqstq_intr_code = LSW(aenmbx7);
1447 ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
1448 ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
1449 ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
1450 ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
1451
1452 ql_dbg(ql_dbg_disc, vha, 0x2094,
1453 "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
1454 " Req que offset 0x%x Rsp que offset 0x%x\n",
1455 ha->mbx_intr_code, ha->rqstq_intr_code,
1456 ha->req_que_off, ha->rsp_que_len);
1457
1458 /* Clear the Interrupts */
1459 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1460
1461 status = qla2x00_init_rings(vha);
1462 if (!status) {
1463 vha->flags.online = 1;
1464
1465 /* if no cable then assume it's good */
1466 if ((vha->device_flags & DFLG_NO_CABLE))
1467 status = 0;
1468 /* Register system information */
1469 if (qlafx00_fx_disc(vha,
1470 &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
1471 ql_dbg(ql_dbg_disc, vha, 0x2095,
1472 "failed to register host info\n");
1473 }
1474 scsi_unblock_requests(vha->host);
1475 return status;
1476 }
1477
1478 void
1479 qlafx00_timer_routine(scsi_qla_host_t *vha)
1480 {
1481 struct qla_hw_data *ha = vha->hw;
1482 uint32_t fw_heart_beat;
1483 uint32_t aenmbx0;
1484 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1485 uint32_t tempc;
1486
1487 /* Check firmware health */
1488 if (ha->mr.fw_hbt_cnt)
1489 ha->mr.fw_hbt_cnt--;
1490 else {
1491 if ((!ha->flags.mr_reset_hdlr_active) &&
1492 (!test_bit(UNLOADING, &vha->dpc_flags)) &&
1493 (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
1494 (ha->mr.fw_hbt_en)) {
1495 fw_heart_beat = RD_REG_DWORD(&reg->fwheartbeat);
1496 if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
1497 ha->mr.old_fw_hbt_cnt = fw_heart_beat;
1498 ha->mr.fw_hbt_miss_cnt = 0;
1499 } else {
1500 ha->mr.fw_hbt_miss_cnt++;
1501 if (ha->mr.fw_hbt_miss_cnt ==
1502 QLAFX00_HEARTBEAT_MISS_CNT) {
1503 set_bit(ISP_ABORT_NEEDED,
1504 &vha->dpc_flags);
1505 qla2xxx_wake_dpc(vha);
1506 ha->mr.fw_hbt_miss_cnt = 0;
1507 }
1508 }
1509 }
1510 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
1511 }
1512
1513 if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
1514 /* Reset recovery to be performed in timer routine */
1515 aenmbx0 = RD_REG_DWORD(&reg->aenmailbox0);
1516 if (ha->mr.fw_reset_timer_exp) {
1517 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1518 qla2xxx_wake_dpc(vha);
1519 ha->mr.fw_reset_timer_exp = 0;
1520 } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
1521 /* Wake up DPC to rescan the targets */
1522 set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
1523 clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1524 qla2xxx_wake_dpc(vha);
1525 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1526 } else if ((aenmbx0 == MBA_FW_STARTING) &&
1527 (!ha->mr.fw_hbt_en)) {
1528 ha->mr.fw_hbt_en = 1;
1529 } else if (!ha->mr.fw_reset_timer_tick) {
1530 if (aenmbx0 == ha->mr.old_aenmbx0_state)
1531 ha->mr.fw_reset_timer_exp = 1;
1532 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1533 } else if (aenmbx0 == 0xFFFFFFFF) {
1534 uint32_t data0, data1;
1535
1536 data0 = QLAFX00_RD_REG(ha,
1537 QLAFX00_BAR1_BASE_ADDR_REG);
1538 data1 = QLAFX00_RD_REG(ha,
1539 QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
1540
1541 data0 &= 0xffff0000;
1542 data1 &= 0x0000ffff;
1543
1544 QLAFX00_WR_REG(ha,
1545 QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
1546 (data0 | data1));
1547 } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
1548 ha->mr.fw_reset_timer_tick =
1549 QLAFX00_MAX_RESET_INTERVAL;
1550 } else if (aenmbx0 == MBA_FW_RESET_FCT) {
1551 ha->mr.fw_reset_timer_tick =
1552 QLAFX00_MAX_RESET_INTERVAL;
1553 }
1554 if (ha->mr.old_aenmbx0_state != aenmbx0) {
1555 ha->mr.old_aenmbx0_state = aenmbx0;
1556 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1557 }
1558 ha->mr.fw_reset_timer_tick--;
1559 }
1560 if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
1561 /*
1562 * Critical temperature recovery to be
1563 * performed in timer routine
1564 */
1565 if (ha->mr.fw_critemp_timer_tick == 0) {
1566 tempc = QLAFX00_GET_TEMPERATURE(ha);
1567 ql_dbg(ql_dbg_timer, vha, 0x6012,
1568 "ISPFx00(%s): Critical temp timer, "
1569 "current SOC temperature: %d\n",
1570 __func__, tempc);
1571 if (tempc < ha->mr.critical_temperature) {
1572 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1573 clear_bit(FX00_CRITEMP_RECOVERY,
1574 &vha->dpc_flags);
1575 qla2xxx_wake_dpc(vha);
1576 }
1577 ha->mr.fw_critemp_timer_tick =
1578 QLAFX00_CRITEMP_INTERVAL;
1579 } else {
1580 ha->mr.fw_critemp_timer_tick--;
1581 }
1582 }
1583 if (ha->mr.host_info_resend) {
1584 /*
1585 * Incomplete host info might be sent to firmware
1586 * durinng system boot - info should be resend
1587 */
1588 if (ha->mr.hinfo_resend_timer_tick == 0) {
1589 ha->mr.host_info_resend = false;
1590 set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags);
1591 ha->mr.hinfo_resend_timer_tick =
1592 QLAFX00_HINFO_RESEND_INTERVAL;
1593 qla2xxx_wake_dpc(vha);
1594 } else {
1595 ha->mr.hinfo_resend_timer_tick--;
1596 }
1597 }
1598
1599 }
1600
1601 /*
1602 * qlfx00a_reset_initialize
1603 * Re-initialize after a iSA device reset.
1604 *
1605 * Input:
1606 * ha = adapter block pointer.
1607 *
1608 * Returns:
1609 * 0 = success
1610 */
1611 int
1612 qlafx00_reset_initialize(scsi_qla_host_t *vha)
1613 {
1614 struct qla_hw_data *ha = vha->hw;
1615
1616 if (vha->device_flags & DFLG_DEV_FAILED) {
1617 ql_dbg(ql_dbg_init, vha, 0x0142,
1618 "Device in failed state\n");
1619 return QLA_SUCCESS;
1620 }
1621
1622 ha->flags.mr_reset_hdlr_active = 1;
1623
1624 if (vha->flags.online) {
1625 scsi_block_requests(vha->host);
1626 qlafx00_abort_isp_cleanup(vha, false);
1627 }
1628
1629 ql_log(ql_log_info, vha, 0x0143,
1630 "(%s): succeeded.\n", __func__);
1631 ha->flags.mr_reset_hdlr_active = 0;
1632 return QLA_SUCCESS;
1633 }
1634
1635 /*
1636 * qlafx00_abort_isp
1637 * Resets ISP and aborts all outstanding commands.
1638 *
1639 * Input:
1640 * ha = adapter block pointer.
1641 *
1642 * Returns:
1643 * 0 = success
1644 */
1645 int
1646 qlafx00_abort_isp(scsi_qla_host_t *vha)
1647 {
1648 struct qla_hw_data *ha = vha->hw;
1649
1650 if (vha->flags.online) {
1651 if (unlikely(pci_channel_offline(ha->pdev) &&
1652 ha->flags.pci_channel_io_perm_failure)) {
1653 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1654 return QLA_SUCCESS;
1655 }
1656
1657 scsi_block_requests(vha->host);
1658 qlafx00_abort_isp_cleanup(vha, false);
1659 } else {
1660 scsi_block_requests(vha->host);
1661 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1662 vha->qla_stats.total_isp_aborts++;
1663 ha->isp_ops->reset_chip(vha);
1664 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1665 /* Clear the Interrupts */
1666 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1667 }
1668
1669 ql_log(ql_log_info, vha, 0x0145,
1670 "(%s): succeeded.\n", __func__);
1671
1672 return QLA_SUCCESS;
1673 }
1674
1675 static inline fc_port_t*
1676 qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
1677 {
1678 fc_port_t *fcport;
1679
1680 /* Check for matching device in remote port list. */
1681 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1682 if (fcport->tgt_id == tgt_id) {
1683 ql_dbg(ql_dbg_async, vha, 0x5072,
1684 "Matching fcport(%p) found with TGT-ID: 0x%x "
1685 "and Remote TGT_ID: 0x%x\n",
1686 fcport, fcport->tgt_id, tgt_id);
1687 return fcport;
1688 }
1689 }
1690 return NULL;
1691 }
1692
1693 static void
1694 qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
1695 {
1696 fc_port_t *fcport;
1697
1698 ql_log(ql_log_info, vha, 0x5073,
1699 "Detach TGT-ID: 0x%x\n", tgt_id);
1700
1701 fcport = qlafx00_get_fcport(vha, tgt_id);
1702 if (!fcport)
1703 return;
1704
1705 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1706
1707 return;
1708 }
1709
1710 int
1711 qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
1712 {
1713 int rval = 0;
1714 uint32_t aen_code, aen_data;
1715
1716 aen_code = FCH_EVT_VENDOR_UNIQUE;
1717 aen_data = evt->u.aenfx.evtcode;
1718
1719 switch (evt->u.aenfx.evtcode) {
1720 case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
1721 if (evt->u.aenfx.mbx[1] == 0) {
1722 if (evt->u.aenfx.mbx[2] == 1) {
1723 if (!vha->flags.fw_tgt_reported)
1724 vha->flags.fw_tgt_reported = 1;
1725 atomic_set(&vha->loop_down_timer, 0);
1726 atomic_set(&vha->loop_state, LOOP_UP);
1727 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1728 qla2xxx_wake_dpc(vha);
1729 } else if (evt->u.aenfx.mbx[2] == 2) {
1730 qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
1731 }
1732 } else if (evt->u.aenfx.mbx[1] == 0xffff) {
1733 if (evt->u.aenfx.mbx[2] == 1) {
1734 if (!vha->flags.fw_tgt_reported)
1735 vha->flags.fw_tgt_reported = 1;
1736 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1737 } else if (evt->u.aenfx.mbx[2] == 2) {
1738 vha->device_flags |= DFLG_NO_CABLE;
1739 qla2x00_mark_all_devices_lost(vha, 1);
1740 }
1741 }
1742 break;
1743 case QLAFX00_MBA_LINK_UP:
1744 aen_code = FCH_EVT_LINKUP;
1745 aen_data = 0;
1746 break;
1747 case QLAFX00_MBA_LINK_DOWN:
1748 aen_code = FCH_EVT_LINKDOWN;
1749 aen_data = 0;
1750 break;
1751 case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
1752 ql_log(ql_log_info, vha, 0x5082,
1753 "Process critical temperature event "
1754 "aenmb[0]: %x\n",
1755 evt->u.aenfx.evtcode);
1756 scsi_block_requests(vha->host);
1757 qlafx00_abort_isp_cleanup(vha, true);
1758 scsi_unblock_requests(vha->host);
1759 break;
1760 }
1761
1762 fc_host_post_event(vha->host, fc_get_event_number(),
1763 aen_code, aen_data);
1764
1765 return rval;
1766 }
1767
1768 static void
1769 qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
1770 {
1771 u64 port_name = 0, node_name = 0;
1772
1773 port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
1774 node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
1775
1776 fc_host_node_name(vha->host) = node_name;
1777 fc_host_port_name(vha->host) = port_name;
1778 if (!pinfo->port_type)
1779 vha->hw->current_topology = ISP_CFG_F;
1780 if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
1781 atomic_set(&vha->loop_state, LOOP_READY);
1782 else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
1783 atomic_set(&vha->loop_state, LOOP_DOWN);
1784 vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
1785 }
1786
1787 static void
1788 qla2x00_fxdisc_iocb_timeout(void *data)
1789 {
1790 srb_t *sp = (srb_t *)data;
1791 struct srb_iocb *lio = &sp->u.iocb_cmd;
1792
1793 complete(&lio->u.fxiocb.fxiocb_comp);
1794 }
1795
1796 static void
1797 qla2x00_fxdisc_sp_done(void *data, void *ptr, int res)
1798 {
1799 srb_t *sp = (srb_t *)ptr;
1800 struct srb_iocb *lio = &sp->u.iocb_cmd;
1801
1802 complete(&lio->u.fxiocb.fxiocb_comp);
1803 }
1804
1805 int
1806 qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
1807 {
1808 srb_t *sp;
1809 struct srb_iocb *fdisc;
1810 int rval = QLA_FUNCTION_FAILED;
1811 struct qla_hw_data *ha = vha->hw;
1812 struct host_system_info *phost_info;
1813 struct register_host_info *preg_hsi;
1814 struct new_utsname *p_sysid = NULL;
1815 struct timeval tv;
1816
1817 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1818 if (!sp)
1819 goto done;
1820
1821 fdisc = &sp->u.iocb_cmd;
1822 switch (fx_type) {
1823 case FXDISC_GET_CONFIG_INFO:
1824 fdisc->u.fxiocb.flags =
1825 SRB_FXDISC_RESP_DMA_VALID;
1826 fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
1827 break;
1828 case FXDISC_GET_PORT_INFO:
1829 fdisc->u.fxiocb.flags =
1830 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1831 fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
1832 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
1833 break;
1834 case FXDISC_GET_TGT_NODE_INFO:
1835 fdisc->u.fxiocb.flags =
1836 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1837 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
1838 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
1839 break;
1840 case FXDISC_GET_TGT_NODE_LIST:
1841 fdisc->u.fxiocb.flags =
1842 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1843 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
1844 break;
1845 case FXDISC_REG_HOST_INFO:
1846 fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
1847 fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
1848 p_sysid = utsname();
1849 if (!p_sysid) {
1850 ql_log(ql_log_warn, vha, 0x303c,
1851 "Not able to get the system information\n");
1852 goto done_free_sp;
1853 }
1854 break;
1855 case FXDISC_ABORT_IOCTL:
1856 default:
1857 break;
1858 }
1859
1860 if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
1861 fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
1862 fdisc->u.fxiocb.req_len,
1863 &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
1864 if (!fdisc->u.fxiocb.req_addr)
1865 goto done_free_sp;
1866
1867 if (fx_type == FXDISC_REG_HOST_INFO) {
1868 preg_hsi = (struct register_host_info *)
1869 fdisc->u.fxiocb.req_addr;
1870 phost_info = &preg_hsi->hsi;
1871 memset(preg_hsi, 0, sizeof(struct register_host_info));
1872 phost_info->os_type = OS_TYPE_LINUX;
1873 strncpy(phost_info->sysname,
1874 p_sysid->sysname, SYSNAME_LENGTH);
1875 strncpy(phost_info->nodename,
1876 p_sysid->nodename, NODENAME_LENGTH);
1877 if (!strcmp(phost_info->nodename, "(none)"))
1878 ha->mr.host_info_resend = true;
1879 strncpy(phost_info->release,
1880 p_sysid->release, RELEASE_LENGTH);
1881 strncpy(phost_info->version,
1882 p_sysid->version, VERSION_LENGTH);
1883 strncpy(phost_info->machine,
1884 p_sysid->machine, MACHINE_LENGTH);
1885 strncpy(phost_info->domainname,
1886 p_sysid->domainname, DOMNAME_LENGTH);
1887 strncpy(phost_info->hostdriver,
1888 QLA2XXX_VERSION, VERSION_LENGTH);
1889 do_gettimeofday(&tv);
1890 preg_hsi->utc = (uint64_t)tv.tv_sec;
1891 ql_dbg(ql_dbg_init, vha, 0x0149,
1892 "ISP%04X: Host registration with firmware\n",
1893 ha->pdev->device);
1894 ql_dbg(ql_dbg_init, vha, 0x014a,
1895 "os_type = '%d', sysname = '%s', nodname = '%s'\n",
1896 phost_info->os_type,
1897 phost_info->sysname,
1898 phost_info->nodename);
1899 ql_dbg(ql_dbg_init, vha, 0x014b,
1900 "release = '%s', version = '%s'\n",
1901 phost_info->release,
1902 phost_info->version);
1903 ql_dbg(ql_dbg_init, vha, 0x014c,
1904 "machine = '%s' "
1905 "domainname = '%s', hostdriver = '%s'\n",
1906 phost_info->machine,
1907 phost_info->domainname,
1908 phost_info->hostdriver);
1909 ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
1910 (uint8_t *)phost_info,
1911 sizeof(struct host_system_info));
1912 }
1913 }
1914
1915 if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
1916 fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
1917 fdisc->u.fxiocb.rsp_len,
1918 &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
1919 if (!fdisc->u.fxiocb.rsp_addr)
1920 goto done_unmap_req;
1921 }
1922
1923 sp->type = SRB_FXIOCB_DCMD;
1924 sp->name = "fxdisc";
1925 qla2x00_init_timer(sp, FXDISC_TIMEOUT);
1926 fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
1927 fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
1928 sp->done = qla2x00_fxdisc_sp_done;
1929
1930 rval = qla2x00_start_sp(sp);
1931 if (rval != QLA_SUCCESS)
1932 goto done_unmap_dma;
1933
1934 wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
1935
1936 if (fx_type == FXDISC_GET_CONFIG_INFO) {
1937 struct config_info_data *pinfo =
1938 (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
1939 strcpy(vha->hw->model_number, pinfo->model_num);
1940 strcpy(vha->hw->model_desc, pinfo->model_description);
1941 memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
1942 sizeof(vha->hw->mr.symbolic_name));
1943 memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
1944 sizeof(vha->hw->mr.serial_num));
1945 memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
1946 sizeof(vha->hw->mr.hw_version));
1947 memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
1948 sizeof(vha->hw->mr.fw_version));
1949 strim(vha->hw->mr.fw_version);
1950 memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
1951 sizeof(vha->hw->mr.uboot_version));
1952 memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
1953 sizeof(vha->hw->mr.fru_serial_num));
1954 vha->hw->mr.critical_temperature =
1955 (pinfo->nominal_temp_value) ?
1956 pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD;
1957 ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
1958 QLAFX00_EXTENDED_IO_EN_MASK) != 0;
1959 } else if (fx_type == FXDISC_GET_PORT_INFO) {
1960 struct port_info_data *pinfo =
1961 (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
1962 memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
1963 memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
1964 vha->d_id.b.domain = pinfo->port_id[0];
1965 vha->d_id.b.area = pinfo->port_id[1];
1966 vha->d_id.b.al_pa = pinfo->port_id[2];
1967 qlafx00_update_host_attr(vha, pinfo);
1968 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
1969 (uint8_t *)pinfo, 16);
1970 } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
1971 struct qlafx00_tgt_node_info *pinfo =
1972 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1973 memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
1974 memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
1975 fcport->port_type = FCT_TARGET;
1976 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
1977 (uint8_t *)pinfo, 16);
1978 } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
1979 struct qlafx00_tgt_node_info *pinfo =
1980 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1981 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
1982 (uint8_t *)pinfo, 16);
1983 memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
1984 } else if (fx_type == FXDISC_ABORT_IOCTL)
1985 fdisc->u.fxiocb.result =
1986 (fdisc->u.fxiocb.result ==
1987 cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ?
1988 cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED);
1989
1990 rval = le32_to_cpu(fdisc->u.fxiocb.result);
1991
1992 done_unmap_dma:
1993 if (fdisc->u.fxiocb.rsp_addr)
1994 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
1995 fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
1996
1997 done_unmap_req:
1998 if (fdisc->u.fxiocb.req_addr)
1999 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
2000 fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
2001 done_free_sp:
2002 sp->free(vha, sp);
2003 done:
2004 return rval;
2005 }
2006
2007 /*
2008 * qlafx00_initialize_adapter
2009 * Initialize board.
2010 *
2011 * Input:
2012 * ha = adapter block pointer.
2013 *
2014 * Returns:
2015 * 0 = success
2016 */
2017 int
2018 qlafx00_initialize_adapter(scsi_qla_host_t *vha)
2019 {
2020 int rval;
2021 struct qla_hw_data *ha = vha->hw;
2022 uint32_t tempc;
2023
2024 /* Clear adapter flags. */
2025 vha->flags.online = 0;
2026 ha->flags.chip_reset_done = 0;
2027 vha->flags.reset_active = 0;
2028 ha->flags.pci_channel_io_perm_failure = 0;
2029 ha->flags.eeh_busy = 0;
2030 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2031 atomic_set(&vha->loop_state, LOOP_DOWN);
2032 vha->device_flags = DFLG_NO_CABLE;
2033 vha->dpc_flags = 0;
2034 vha->flags.management_server_logged_in = 0;
2035 ha->isp_abort_cnt = 0;
2036 ha->beacon_blink_led = 0;
2037
2038 set_bit(0, ha->req_qid_map);
2039 set_bit(0, ha->rsp_qid_map);
2040
2041 ql_dbg(ql_dbg_init, vha, 0x0147,
2042 "Configuring PCI space...\n");
2043
2044 rval = ha->isp_ops->pci_config(vha);
2045 if (rval) {
2046 ql_log(ql_log_warn, vha, 0x0148,
2047 "Unable to configure PCI space.\n");
2048 return rval;
2049 }
2050
2051 rval = qlafx00_init_fw_ready(vha);
2052 if (rval != QLA_SUCCESS)
2053 return rval;
2054
2055 qlafx00_save_queue_ptrs(vha);
2056
2057 rval = qlafx00_config_queues(vha);
2058 if (rval != QLA_SUCCESS)
2059 return rval;
2060
2061 /*
2062 * Allocate the array of outstanding commands
2063 * now that we know the firmware resources.
2064 */
2065 rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
2066 if (rval != QLA_SUCCESS)
2067 return rval;
2068
2069 rval = qla2x00_init_rings(vha);
2070 ha->flags.chip_reset_done = 1;
2071
2072 tempc = QLAFX00_GET_TEMPERATURE(ha);
2073 ql_dbg(ql_dbg_init, vha, 0x0152,
2074 "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
2075 __func__, tempc);
2076
2077 return rval;
2078 }
2079
2080 uint32_t
2081 qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
2082 char *buf)
2083 {
2084 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
2085 int rval = QLA_FUNCTION_FAILED;
2086 uint32_t state[1];
2087
2088 if (qla2x00_reset_active(vha))
2089 ql_log(ql_log_warn, vha, 0x70ce,
2090 "ISP reset active.\n");
2091 else if (!vha->hw->flags.eeh_busy) {
2092 rval = qlafx00_get_firmware_state(vha, state);
2093 }
2094 if (rval != QLA_SUCCESS)
2095 memset(state, -1, sizeof(state));
2096
2097 return state[0];
2098 }
2099
2100 void
2101 qlafx00_get_host_speed(struct Scsi_Host *shost)
2102 {
2103 struct qla_hw_data *ha = ((struct scsi_qla_host *)
2104 (shost_priv(shost)))->hw;
2105 u32 speed = FC_PORTSPEED_UNKNOWN;
2106
2107 switch (ha->link_data_rate) {
2108 case QLAFX00_PORT_SPEED_2G:
2109 speed = FC_PORTSPEED_2GBIT;
2110 break;
2111 case QLAFX00_PORT_SPEED_4G:
2112 speed = FC_PORTSPEED_4GBIT;
2113 break;
2114 case QLAFX00_PORT_SPEED_8G:
2115 speed = FC_PORTSPEED_8GBIT;
2116 break;
2117 case QLAFX00_PORT_SPEED_10G:
2118 speed = FC_PORTSPEED_10GBIT;
2119 break;
2120 }
2121 fc_host_speed(shost) = speed;
2122 }
2123
2124 /** QLAFX00 specific ISR implementation functions */
2125
2126 static inline void
2127 qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
2128 uint32_t sense_len, struct rsp_que *rsp, int res)
2129 {
2130 struct scsi_qla_host *vha = sp->fcport->vha;
2131 struct scsi_cmnd *cp = GET_CMD_SP(sp);
2132 uint32_t track_sense_len;
2133
2134 SET_FW_SENSE_LEN(sp, sense_len);
2135
2136 if (sense_len >= SCSI_SENSE_BUFFERSIZE)
2137 sense_len = SCSI_SENSE_BUFFERSIZE;
2138
2139 SET_CMD_SENSE_LEN(sp, sense_len);
2140 SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
2141 track_sense_len = sense_len;
2142
2143 if (sense_len > par_sense_len)
2144 sense_len = par_sense_len;
2145
2146 memcpy(cp->sense_buffer, sense_data, sense_len);
2147
2148 SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
2149
2150 SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
2151 track_sense_len -= sense_len;
2152 SET_CMD_SENSE_LEN(sp, track_sense_len);
2153
2154 ql_dbg(ql_dbg_io, vha, 0x304d,
2155 "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
2156 sense_len, par_sense_len, track_sense_len);
2157 if (GET_FW_SENSE_LEN(sp) > 0) {
2158 rsp->status_srb = sp;
2159 cp->result = res;
2160 }
2161
2162 if (sense_len) {
2163 ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
2164 "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
2165 sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
2166 cp);
2167 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
2168 cp->sense_buffer, sense_len);
2169 }
2170 }
2171
2172 static void
2173 qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2174 struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
2175 __le16 sstatus, __le16 cpstatus)
2176 {
2177 struct srb_iocb *tmf;
2178
2179 tmf = &sp->u.iocb_cmd;
2180 if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
2181 (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
2182 cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
2183 tmf->u.tmf.comp_status = cpstatus;
2184 sp->done(vha, sp, 0);
2185 }
2186
2187 static void
2188 qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2189 struct abort_iocb_entry_fx00 *pkt)
2190 {
2191 const char func[] = "ABT_IOCB";
2192 srb_t *sp;
2193 struct srb_iocb *abt;
2194
2195 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2196 if (!sp)
2197 return;
2198
2199 abt = &sp->u.iocb_cmd;
2200 abt->u.abt.comp_status = pkt->tgt_id_sts;
2201 sp->done(vha, sp, 0);
2202 }
2203
2204 static void
2205 qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
2206 struct ioctl_iocb_entry_fx00 *pkt)
2207 {
2208 const char func[] = "IOSB_IOCB";
2209 srb_t *sp;
2210 struct fc_bsg_job *bsg_job;
2211 struct srb_iocb *iocb_job;
2212 int res;
2213 struct qla_mt_iocb_rsp_fx00 fstatus;
2214 uint8_t *fw_sts_ptr;
2215
2216 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2217 if (!sp)
2218 return;
2219
2220 if (sp->type == SRB_FXIOCB_DCMD) {
2221 iocb_job = &sp->u.iocb_cmd;
2222 iocb_job->u.fxiocb.seq_number = pkt->seq_no;
2223 iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
2224 iocb_job->u.fxiocb.result = pkt->status;
2225 if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
2226 iocb_job->u.fxiocb.req_data =
2227 pkt->dataword_r;
2228 } else {
2229 bsg_job = sp->u.bsg_job;
2230
2231 memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
2232
2233 fstatus.reserved_1 = pkt->reserved_0;
2234 fstatus.func_type = pkt->comp_func_num;
2235 fstatus.ioctl_flags = pkt->fw_iotcl_flags;
2236 fstatus.ioctl_data = pkt->dataword_r;
2237 fstatus.adapid = pkt->adapid;
2238 fstatus.reserved_2 = pkt->dataword_r_extra;
2239 fstatus.res_count = pkt->residuallen;
2240 fstatus.status = pkt->status;
2241 fstatus.seq_number = pkt->seq_no;
2242 memcpy(fstatus.reserved_3,
2243 pkt->reserved_2, 20 * sizeof(uint8_t));
2244
2245 fw_sts_ptr = ((uint8_t *)bsg_job->req->sense) +
2246 sizeof(struct fc_bsg_reply);
2247
2248 memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
2249 sizeof(struct qla_mt_iocb_rsp_fx00));
2250 bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
2251 sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
2252
2253 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2254 sp->fcport->vha, 0x5080,
2255 (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
2256
2257 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2258 sp->fcport->vha, 0x5074,
2259 (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
2260
2261 res = bsg_job->reply->result = DID_OK << 16;
2262 bsg_job->reply->reply_payload_rcv_len =
2263 bsg_job->reply_payload.payload_len;
2264 }
2265 sp->done(vha, sp, res);
2266 }
2267
2268 /**
2269 * qlafx00_status_entry() - Process a Status IOCB entry.
2270 * @ha: SCSI driver HA context
2271 * @pkt: Entry pointer
2272 */
2273 static void
2274 qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
2275 {
2276 srb_t *sp;
2277 fc_port_t *fcport;
2278 struct scsi_cmnd *cp;
2279 struct sts_entry_fx00 *sts;
2280 __le16 comp_status;
2281 __le16 scsi_status;
2282 uint16_t ox_id;
2283 __le16 lscsi_status;
2284 int32_t resid;
2285 uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
2286 fw_resid_len;
2287 uint8_t *rsp_info = NULL, *sense_data = NULL;
2288 struct qla_hw_data *ha = vha->hw;
2289 uint32_t hindex, handle;
2290 uint16_t que;
2291 struct req_que *req;
2292 int logit = 1;
2293 int res = 0;
2294
2295 sts = (struct sts_entry_fx00 *) pkt;
2296
2297 comp_status = sts->comp_status;
2298 scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
2299 hindex = sts->handle;
2300 handle = LSW(hindex);
2301
2302 que = MSW(hindex);
2303 req = ha->req_q_map[que];
2304
2305 /* Validate handle. */
2306 if (handle < req->num_outstanding_cmds)
2307 sp = req->outstanding_cmds[handle];
2308 else
2309 sp = NULL;
2310
2311 if (sp == NULL) {
2312 ql_dbg(ql_dbg_io, vha, 0x3034,
2313 "Invalid status handle (0x%x).\n", handle);
2314
2315 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2316 qla2xxx_wake_dpc(vha);
2317 return;
2318 }
2319
2320 if (sp->type == SRB_TM_CMD) {
2321 req->outstanding_cmds[handle] = NULL;
2322 qlafx00_tm_iocb_entry(vha, req, pkt, sp,
2323 scsi_status, comp_status);
2324 return;
2325 }
2326
2327 /* Fast path completion. */
2328 if (comp_status == CS_COMPLETE && scsi_status == 0) {
2329 qla2x00_process_completed_request(vha, req, handle);
2330 return;
2331 }
2332
2333 req->outstanding_cmds[handle] = NULL;
2334 cp = GET_CMD_SP(sp);
2335 if (cp == NULL) {
2336 ql_dbg(ql_dbg_io, vha, 0x3048,
2337 "Command already returned (0x%x/%p).\n",
2338 handle, sp);
2339
2340 return;
2341 }
2342
2343 lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
2344
2345 fcport = sp->fcport;
2346
2347 ox_id = 0;
2348 sense_len = par_sense_len = rsp_info_len = resid_len =
2349 fw_resid_len = 0;
2350 if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
2351 sense_len = sts->sense_len;
2352 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2353 | (uint16_t)SS_RESIDUAL_OVER)))
2354 resid_len = le32_to_cpu(sts->residual_len);
2355 if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
2356 fw_resid_len = le32_to_cpu(sts->residual_len);
2357 rsp_info = sense_data = sts->data;
2358 par_sense_len = sizeof(sts->data);
2359
2360 /* Check for overrun. */
2361 if (comp_status == CS_COMPLETE &&
2362 scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
2363 comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
2364
2365 /*
2366 * Based on Host and scsi status generate status code for Linux
2367 */
2368 switch (le16_to_cpu(comp_status)) {
2369 case CS_COMPLETE:
2370 case CS_QUEUE_FULL:
2371 if (scsi_status == 0) {
2372 res = DID_OK << 16;
2373 break;
2374 }
2375 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2376 | (uint16_t)SS_RESIDUAL_OVER))) {
2377 resid = resid_len;
2378 scsi_set_resid(cp, resid);
2379
2380 if (!lscsi_status &&
2381 ((unsigned)(scsi_bufflen(cp) - resid) <
2382 cp->underflow)) {
2383 ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
2384 "Mid-layer underflow "
2385 "detected (0x%x of 0x%x bytes).\n",
2386 resid, scsi_bufflen(cp));
2387
2388 res = DID_ERROR << 16;
2389 break;
2390 }
2391 }
2392 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2393
2394 if (lscsi_status ==
2395 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2396 ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
2397 "QUEUE FULL detected.\n");
2398 break;
2399 }
2400 logit = 0;
2401 if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2402 break;
2403
2404 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2405 if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2406 break;
2407
2408 qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
2409 rsp, res);
2410 break;
2411
2412 case CS_DATA_UNDERRUN:
2413 /* Use F/W calculated residual length. */
2414 if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2415 resid = fw_resid_len;
2416 else
2417 resid = resid_len;
2418 scsi_set_resid(cp, resid);
2419 if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
2420 if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2421 && fw_resid_len != resid_len) {
2422 ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
2423 "Dropped frame(s) detected "
2424 "(0x%x of 0x%x bytes).\n",
2425 resid, scsi_bufflen(cp));
2426
2427 res = DID_ERROR << 16 |
2428 le16_to_cpu(lscsi_status);
2429 goto check_scsi_status;
2430 }
2431
2432 if (!lscsi_status &&
2433 ((unsigned)(scsi_bufflen(cp) - resid) <
2434 cp->underflow)) {
2435 ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
2436 "Mid-layer underflow "
2437 "detected (0x%x of 0x%x bytes, "
2438 "cp->underflow: 0x%x).\n",
2439 resid, scsi_bufflen(cp), cp->underflow);
2440
2441 res = DID_ERROR << 16;
2442 break;
2443 }
2444 } else if (lscsi_status !=
2445 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
2446 lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
2447 /*
2448 * scsi status of task set and busy are considered
2449 * to be task not completed.
2450 */
2451
2452 ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
2453 "Dropped frame(s) detected (0x%x "
2454 "of 0x%x bytes).\n", resid,
2455 scsi_bufflen(cp));
2456
2457 res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
2458 goto check_scsi_status;
2459 } else {
2460 ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
2461 "scsi_status: 0x%x, lscsi_status: 0x%x\n",
2462 scsi_status, lscsi_status);
2463 }
2464
2465 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2466 logit = 0;
2467
2468 check_scsi_status:
2469 /*
2470 * Check to see if SCSI Status is non zero. If so report SCSI
2471 * Status.
2472 */
2473 if (lscsi_status != 0) {
2474 if (lscsi_status ==
2475 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2476 ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
2477 "QUEUE FULL detected.\n");
2478 logit = 1;
2479 break;
2480 }
2481 if (lscsi_status !=
2482 cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2483 break;
2484
2485 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2486 if (!(scsi_status &
2487 cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2488 break;
2489
2490 qlafx00_handle_sense(sp, sense_data, par_sense_len,
2491 sense_len, rsp, res);
2492 }
2493 break;
2494
2495 case CS_PORT_LOGGED_OUT:
2496 case CS_PORT_CONFIG_CHG:
2497 case CS_PORT_BUSY:
2498 case CS_INCOMPLETE:
2499 case CS_PORT_UNAVAILABLE:
2500 case CS_TIMEOUT:
2501 case CS_RESET:
2502
2503 /*
2504 * We are going to have the fc class block the rport
2505 * while we try to recover so instruct the mid layer
2506 * to requeue until the class decides how to handle this.
2507 */
2508 res = DID_TRANSPORT_DISRUPTED << 16;
2509
2510 ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
2511 "Port down status: port-state=0x%x.\n",
2512 atomic_read(&fcport->state));
2513
2514 if (atomic_read(&fcport->state) == FCS_ONLINE)
2515 qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
2516 break;
2517
2518 case CS_ABORTED:
2519 res = DID_RESET << 16;
2520 break;
2521
2522 default:
2523 res = DID_ERROR << 16;
2524 break;
2525 }
2526
2527 if (logit)
2528 ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
2529 "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
2530 "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
2531 "rsp_info=0x%x resid=0x%x fw_resid=0x%x sense_len=0x%x, "
2532 "par_sense_len=0x%x, rsp_info_len=0x%x\n",
2533 comp_status, scsi_status, res, vha->host_no,
2534 cp->device->id, cp->device->lun, fcport->tgt_id,
2535 lscsi_status, cp->cmnd, scsi_bufflen(cp),
2536 rsp_info_len, resid_len, fw_resid_len, sense_len,
2537 par_sense_len, rsp_info_len);
2538
2539 if (rsp->status_srb == NULL)
2540 sp->done(ha, sp, res);
2541 }
2542
2543 /**
2544 * qlafx00_status_cont_entry() - Process a Status Continuations entry.
2545 * @ha: SCSI driver HA context
2546 * @pkt: Entry pointer
2547 *
2548 * Extended sense data.
2549 */
2550 static void
2551 qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
2552 {
2553 uint8_t sense_sz = 0;
2554 struct qla_hw_data *ha = rsp->hw;
2555 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
2556 srb_t *sp = rsp->status_srb;
2557 struct scsi_cmnd *cp;
2558 uint32_t sense_len;
2559 uint8_t *sense_ptr;
2560
2561 if (!sp) {
2562 ql_dbg(ql_dbg_io, vha, 0x3037,
2563 "no SP, sp = %p\n", sp);
2564 return;
2565 }
2566
2567 if (!GET_FW_SENSE_LEN(sp)) {
2568 ql_dbg(ql_dbg_io, vha, 0x304b,
2569 "no fw sense data, sp = %p\n", sp);
2570 return;
2571 }
2572 cp = GET_CMD_SP(sp);
2573 if (cp == NULL) {
2574 ql_log(ql_log_warn, vha, 0x303b,
2575 "cmd is NULL: already returned to OS (sp=%p).\n", sp);
2576
2577 rsp->status_srb = NULL;
2578 return;
2579 }
2580
2581 if (!GET_CMD_SENSE_LEN(sp)) {
2582 ql_dbg(ql_dbg_io, vha, 0x304c,
2583 "no sense data, sp = %p\n", sp);
2584 } else {
2585 sense_len = GET_CMD_SENSE_LEN(sp);
2586 sense_ptr = GET_CMD_SENSE_PTR(sp);
2587 ql_dbg(ql_dbg_io, vha, 0x304f,
2588 "sp=%p sense_len=0x%x sense_ptr=%p.\n",
2589 sp, sense_len, sense_ptr);
2590
2591 if (sense_len > sizeof(pkt->data))
2592 sense_sz = sizeof(pkt->data);
2593 else
2594 sense_sz = sense_len;
2595
2596 /* Move sense data. */
2597 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
2598 (uint8_t *)pkt, sizeof(sts_cont_entry_t));
2599 memcpy(sense_ptr, pkt->data, sense_sz);
2600 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
2601 sense_ptr, sense_sz);
2602
2603 sense_len -= sense_sz;
2604 sense_ptr += sense_sz;
2605
2606 SET_CMD_SENSE_PTR(sp, sense_ptr);
2607 SET_CMD_SENSE_LEN(sp, sense_len);
2608 }
2609 sense_len = GET_FW_SENSE_LEN(sp);
2610 sense_len = (sense_len > sizeof(pkt->data)) ?
2611 (sense_len - sizeof(pkt->data)) : 0;
2612 SET_FW_SENSE_LEN(sp, sense_len);
2613
2614 /* Place command on done queue. */
2615 if (sense_len == 0) {
2616 rsp->status_srb = NULL;
2617 sp->done(ha, sp, cp->result);
2618 }
2619 }
2620
2621 /**
2622 * qlafx00_multistatus_entry() - Process Multi response queue entries.
2623 * @ha: SCSI driver HA context
2624 */
2625 static void
2626 qlafx00_multistatus_entry(struct scsi_qla_host *vha,
2627 struct rsp_que *rsp, void *pkt)
2628 {
2629 srb_t *sp;
2630 struct multi_sts_entry_fx00 *stsmfx;
2631 struct qla_hw_data *ha = vha->hw;
2632 uint32_t handle, hindex, handle_count, i;
2633 uint16_t que;
2634 struct req_que *req;
2635 __le32 *handle_ptr;
2636
2637 stsmfx = (struct multi_sts_entry_fx00 *) pkt;
2638
2639 handle_count = stsmfx->handle_count;
2640
2641 if (handle_count > MAX_HANDLE_COUNT) {
2642 ql_dbg(ql_dbg_io, vha, 0x3035,
2643 "Invalid handle count (0x%x).\n", handle_count);
2644 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2645 qla2xxx_wake_dpc(vha);
2646 return;
2647 }
2648
2649 handle_ptr = &stsmfx->handles[0];
2650
2651 for (i = 0; i < handle_count; i++) {
2652 hindex = le32_to_cpu(*handle_ptr);
2653 handle = LSW(hindex);
2654 que = MSW(hindex);
2655 req = ha->req_q_map[que];
2656
2657 /* Validate handle. */
2658 if (handle < req->num_outstanding_cmds)
2659 sp = req->outstanding_cmds[handle];
2660 else
2661 sp = NULL;
2662
2663 if (sp == NULL) {
2664 ql_dbg(ql_dbg_io, vha, 0x3044,
2665 "Invalid status handle (0x%x).\n", handle);
2666 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2667 qla2xxx_wake_dpc(vha);
2668 return;
2669 }
2670 qla2x00_process_completed_request(vha, req, handle);
2671 handle_ptr++;
2672 }
2673 }
2674
2675 /**
2676 * qlafx00_error_entry() - Process an error entry.
2677 * @ha: SCSI driver HA context
2678 * @pkt: Entry pointer
2679 */
2680 static void
2681 qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
2682 struct sts_entry_fx00 *pkt, uint8_t estatus, uint8_t etype)
2683 {
2684 srb_t *sp;
2685 struct qla_hw_data *ha = vha->hw;
2686 const char func[] = "ERROR-IOCB";
2687 uint16_t que = 0;
2688 struct req_que *req = NULL;
2689 int res = DID_ERROR << 16;
2690
2691 ql_dbg(ql_dbg_async, vha, 0x507f,
2692 "type of error status in response: 0x%x\n", estatus);
2693
2694 req = ha->req_q_map[que];
2695
2696 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2697 if (sp) {
2698 sp->done(ha, sp, res);
2699 return;
2700 }
2701
2702 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2703 qla2xxx_wake_dpc(vha);
2704 }
2705
2706 /**
2707 * qlafx00_process_response_queue() - Process response queue entries.
2708 * @ha: SCSI driver HA context
2709 */
2710 static void
2711 qlafx00_process_response_queue(struct scsi_qla_host *vha,
2712 struct rsp_que *rsp)
2713 {
2714 struct sts_entry_fx00 *pkt;
2715 response_t *lptr;
2716 uint16_t lreq_q_in = 0;
2717 uint16_t lreq_q_out = 0;
2718
2719 lreq_q_in = RD_REG_DWORD(rsp->rsp_q_in);
2720 lreq_q_out = rsp->ring_index;
2721
2722 while (lreq_q_in != lreq_q_out) {
2723 lptr = rsp->ring_ptr;
2724 memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
2725 sizeof(rsp->rsp_pkt));
2726 pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
2727
2728 rsp->ring_index++;
2729 lreq_q_out++;
2730 if (rsp->ring_index == rsp->length) {
2731 lreq_q_out = 0;
2732 rsp->ring_index = 0;
2733 rsp->ring_ptr = rsp->ring;
2734 } else {
2735 rsp->ring_ptr++;
2736 }
2737
2738 if (pkt->entry_status != 0 &&
2739 pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
2740 qlafx00_error_entry(vha, rsp,
2741 (struct sts_entry_fx00 *)pkt, pkt->entry_status,
2742 pkt->entry_type);
2743 continue;
2744 }
2745
2746 switch (pkt->entry_type) {
2747 case STATUS_TYPE_FX00:
2748 qlafx00_status_entry(vha, rsp, pkt);
2749 break;
2750
2751 case STATUS_CONT_TYPE_FX00:
2752 qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
2753 break;
2754
2755 case MULTI_STATUS_TYPE_FX00:
2756 qlafx00_multistatus_entry(vha, rsp, pkt);
2757 break;
2758
2759 case ABORT_IOCB_TYPE_FX00:
2760 qlafx00_abort_iocb_entry(vha, rsp->req,
2761 (struct abort_iocb_entry_fx00 *)pkt);
2762 break;
2763
2764 case IOCTL_IOSB_TYPE_FX00:
2765 qlafx00_ioctl_iosb_entry(vha, rsp->req,
2766 (struct ioctl_iocb_entry_fx00 *)pkt);
2767 break;
2768 default:
2769 /* Type Not Supported. */
2770 ql_dbg(ql_dbg_async, vha, 0x5081,
2771 "Received unknown response pkt type %x "
2772 "entry status=%x.\n",
2773 pkt->entry_type, pkt->entry_status);
2774 break;
2775 }
2776 }
2777
2778 /* Adjust ring index */
2779 WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
2780 }
2781
2782 /**
2783 * qlafx00_async_event() - Process aynchronous events.
2784 * @ha: SCSI driver HA context
2785 */
2786 static void
2787 qlafx00_async_event(scsi_qla_host_t *vha)
2788 {
2789 struct qla_hw_data *ha = vha->hw;
2790 struct device_reg_fx00 __iomem *reg;
2791 int data_size = 1;
2792
2793 reg = &ha->iobase->ispfx00;
2794 /* Setup to process RIO completion. */
2795 switch (ha->aenmb[0]) {
2796 case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
2797 ql_log(ql_log_warn, vha, 0x5079,
2798 "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
2799 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2800 break;
2801
2802 case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
2803 ql_dbg(ql_dbg_async, vha, 0x5076,
2804 "Asynchronous FW shutdown requested.\n");
2805 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2806 qla2xxx_wake_dpc(vha);
2807 break;
2808
2809 case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
2810 ha->aenmb[1] = RD_REG_DWORD(&reg->aenmailbox1);
2811 ha->aenmb[2] = RD_REG_DWORD(&reg->aenmailbox2);
2812 ha->aenmb[3] = RD_REG_DWORD(&reg->aenmailbox3);
2813 ql_dbg(ql_dbg_async, vha, 0x5077,
2814 "Asynchronous port Update received "
2815 "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
2816 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
2817 data_size = 4;
2818 break;
2819
2820 case QLAFX00_MBA_TEMP_OVER: /* Over temperature event */
2821 ql_log(ql_log_info, vha, 0x5085,
2822 "Asynchronous over temperature event received "
2823 "aenmb[0]: %x\n",
2824 ha->aenmb[0]);
2825 break;
2826
2827 case QLAFX00_MBA_TEMP_NORM: /* Normal temperature event */
2828 ql_log(ql_log_info, vha, 0x5086,
2829 "Asynchronous normal temperature event received "
2830 "aenmb[0]: %x\n",
2831 ha->aenmb[0]);
2832 break;
2833
2834 case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
2835 ql_log(ql_log_info, vha, 0x5083,
2836 "Asynchronous critical temperature event received "
2837 "aenmb[0]: %x\n",
2838 ha->aenmb[0]);
2839 break;
2840
2841 default:
2842 ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
2843 ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
2844 ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
2845 ha->aenmb[4] = RD_REG_WORD(&reg->aenmailbox4);
2846 ha->aenmb[5] = RD_REG_WORD(&reg->aenmailbox5);
2847 ha->aenmb[6] = RD_REG_WORD(&reg->aenmailbox6);
2848 ha->aenmb[7] = RD_REG_WORD(&reg->aenmailbox7);
2849 ql_dbg(ql_dbg_async, vha, 0x5078,
2850 "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
2851 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
2852 ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
2853 break;
2854 }
2855 qlafx00_post_aenfx_work(vha, ha->aenmb[0],
2856 (uint32_t *)ha->aenmb, data_size);
2857 }
2858
2859 /**
2860 *
2861 * qlafx00x_mbx_completion() - Process mailbox command completions.
2862 * @ha: SCSI driver HA context
2863 * @mb16: Mailbox16 register
2864 */
2865 static void
2866 qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
2867 {
2868 uint16_t cnt;
2869 uint32_t __iomem *wptr;
2870 struct qla_hw_data *ha = vha->hw;
2871 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
2872
2873 if (!ha->mcp32)
2874 ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
2875
2876 /* Load return mailbox registers. */
2877 ha->flags.mbox_int = 1;
2878 ha->mailbox_out32[0] = mb0;
2879 wptr = (uint32_t __iomem *)&reg->mailbox17;
2880
2881 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2882 ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr);
2883 wptr++;
2884 }
2885 }
2886
2887 /**
2888 * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
2889 * @irq:
2890 * @dev_id: SCSI driver HA context
2891 *
2892 * Called by system whenever the host adapter generates an interrupt.
2893 *
2894 * Returns handled flag.
2895 */
2896 irqreturn_t
2897 qlafx00_intr_handler(int irq, void *dev_id)
2898 {
2899 scsi_qla_host_t *vha;
2900 struct qla_hw_data *ha;
2901 struct device_reg_fx00 __iomem *reg;
2902 int status;
2903 unsigned long iter;
2904 uint32_t stat;
2905 uint32_t mb[8];
2906 struct rsp_que *rsp;
2907 unsigned long flags;
2908 uint32_t clr_intr = 0;
2909 uint32_t intr_stat = 0;
2910
2911 rsp = (struct rsp_que *) dev_id;
2912 if (!rsp) {
2913 ql_log(ql_log_info, NULL, 0x507d,
2914 "%s: NULL response queue pointer.\n", __func__);
2915 return IRQ_NONE;
2916 }
2917
2918 ha = rsp->hw;
2919 reg = &ha->iobase->ispfx00;
2920 status = 0;
2921
2922 if (unlikely(pci_channel_offline(ha->pdev)))
2923 return IRQ_HANDLED;
2924
2925 spin_lock_irqsave(&ha->hardware_lock, flags);
2926 vha = pci_get_drvdata(ha->pdev);
2927 for (iter = 50; iter--; clr_intr = 0) {
2928 stat = QLAFX00_RD_INTR_REG(ha);
2929 if (qla2x00_check_reg32_for_disconnect(vha, stat))
2930 break;
2931 intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
2932 if (!intr_stat)
2933 break;
2934
2935 if (stat & QLAFX00_INTR_MB_CMPLT) {
2936 mb[0] = RD_REG_WORD(&reg->mailbox16);
2937 qlafx00_mbx_completion(vha, mb[0]);
2938 status |= MBX_INTERRUPT;
2939 clr_intr |= QLAFX00_INTR_MB_CMPLT;
2940 }
2941 if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
2942 ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0);
2943 qlafx00_async_event(vha);
2944 clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
2945 }
2946 if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
2947 qlafx00_process_response_queue(vha, rsp);
2948 clr_intr |= QLAFX00_INTR_RSP_CMPLT;
2949 }
2950
2951 QLAFX00_CLR_INTR_REG(ha, clr_intr);
2952 QLAFX00_RD_INTR_REG(ha);
2953 }
2954
2955 qla2x00_handle_mbx_completion(ha, status);
2956 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2957
2958 return IRQ_HANDLED;
2959 }
2960
2961 /** QLAFX00 specific IOCB implementation functions */
2962
2963 static inline cont_a64_entry_t *
2964 qlafx00_prep_cont_type1_iocb(struct req_que *req,
2965 cont_a64_entry_t *lcont_pkt)
2966 {
2967 cont_a64_entry_t *cont_pkt;
2968
2969 /* Adjust ring index. */
2970 req->ring_index++;
2971 if (req->ring_index == req->length) {
2972 req->ring_index = 0;
2973 req->ring_ptr = req->ring;
2974 } else {
2975 req->ring_ptr++;
2976 }
2977
2978 cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
2979
2980 /* Load packet defaults. */
2981 lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
2982
2983 return cont_pkt;
2984 }
2985
2986 static inline void
2987 qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
2988 uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
2989 {
2990 uint16_t avail_dsds;
2991 __le32 *cur_dsd;
2992 scsi_qla_host_t *vha;
2993 struct scsi_cmnd *cmd;
2994 struct scatterlist *sg;
2995 int i, cont;
2996 struct req_que *req;
2997 cont_a64_entry_t lcont_pkt;
2998 cont_a64_entry_t *cont_pkt;
2999
3000 vha = sp->fcport->vha;
3001 req = vha->req;
3002
3003 cmd = GET_CMD_SP(sp);
3004 cont = 0;
3005 cont_pkt = NULL;
3006
3007 /* Update entry type to indicate Command Type 3 IOCB */
3008 lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
3009
3010 /* No data transfer */
3011 if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
3012 lcmd_pkt->byte_count = __constant_cpu_to_le32(0);
3013 return;
3014 }
3015
3016 /* Set transfer direction */
3017 if (cmd->sc_data_direction == DMA_TO_DEVICE) {
3018 lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
3019 vha->qla_stats.output_bytes += scsi_bufflen(cmd);
3020 } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
3021 lcmd_pkt->cntrl_flags = TMF_READ_DATA;
3022 vha->qla_stats.input_bytes += scsi_bufflen(cmd);
3023 }
3024
3025 /* One DSD is available in the Command Type 3 IOCB */
3026 avail_dsds = 1;
3027 cur_dsd = (__le32 *)&lcmd_pkt->dseg_0_address;
3028
3029 /* Load data segments */
3030 scsi_for_each_sg(cmd, sg, tot_dsds, i) {
3031 dma_addr_t sle_dma;
3032
3033 /* Allocate additional continuation packets? */
3034 if (avail_dsds == 0) {
3035 /*
3036 * Five DSDs are available in the Continuation
3037 * Type 1 IOCB.
3038 */
3039 memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
3040 cont_pkt =
3041 qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
3042 cur_dsd = (__le32 *)lcont_pkt.dseg_0_address;
3043 avail_dsds = 5;
3044 cont = 1;
3045 }
3046
3047 sle_dma = sg_dma_address(sg);
3048 *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
3049 *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
3050 *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
3051 avail_dsds--;
3052 if (avail_dsds == 0 && cont == 1) {
3053 cont = 0;
3054 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3055 REQUEST_ENTRY_SIZE);
3056 }
3057
3058 }
3059 if (avail_dsds != 0 && cont == 1) {
3060 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3061 REQUEST_ENTRY_SIZE);
3062 }
3063 }
3064
3065 /**
3066 * qlafx00_start_scsi() - Send a SCSI command to the ISP
3067 * @sp: command to send to the ISP
3068 *
3069 * Returns non-zero if a failure occurred, else zero.
3070 */
3071 int
3072 qlafx00_start_scsi(srb_t *sp)
3073 {
3074 int ret, nseg;
3075 unsigned long flags;
3076 uint32_t index;
3077 uint32_t handle;
3078 uint16_t cnt;
3079 uint16_t req_cnt;
3080 uint16_t tot_dsds;
3081 struct req_que *req = NULL;
3082 struct rsp_que *rsp = NULL;
3083 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
3084 struct scsi_qla_host *vha = sp->fcport->vha;
3085 struct qla_hw_data *ha = vha->hw;
3086 struct cmd_type_7_fx00 *cmd_pkt;
3087 struct cmd_type_7_fx00 lcmd_pkt;
3088 struct scsi_lun llun;
3089
3090 /* Setup device pointers. */
3091 ret = 0;
3092
3093 rsp = ha->rsp_q_map[0];
3094 req = vha->req;
3095
3096 /* So we know we haven't pci_map'ed anything yet */
3097 tot_dsds = 0;
3098
3099 /* Acquire ring specific lock */
3100 spin_lock_irqsave(&ha->hardware_lock, flags);
3101
3102 /* Check for room in outstanding command list. */
3103 handle = req->current_outstanding_cmd;
3104 for (index = 1; index < req->num_outstanding_cmds; index++) {
3105 handle++;
3106 if (handle == req->num_outstanding_cmds)
3107 handle = 1;
3108 if (!req->outstanding_cmds[handle])
3109 break;
3110 }
3111 if (index == req->num_outstanding_cmds)
3112 goto queuing_error;
3113
3114 /* Map the sg table so we have an accurate count of sg entries needed */
3115 if (scsi_sg_count(cmd)) {
3116 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
3117 scsi_sg_count(cmd), cmd->sc_data_direction);
3118 if (unlikely(!nseg))
3119 goto queuing_error;
3120 } else
3121 nseg = 0;
3122
3123 tot_dsds = nseg;
3124 req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
3125 if (req->cnt < (req_cnt + 2)) {
3126 cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
3127
3128 if (req->ring_index < cnt)
3129 req->cnt = cnt - req->ring_index;
3130 else
3131 req->cnt = req->length -
3132 (req->ring_index - cnt);
3133 if (req->cnt < (req_cnt + 2))
3134 goto queuing_error;
3135 }
3136
3137 /* Build command packet. */
3138 req->current_outstanding_cmd = handle;
3139 req->outstanding_cmds[handle] = sp;
3140 sp->handle = handle;
3141 cmd->host_scribble = (unsigned char *)(unsigned long)handle;
3142 req->cnt -= req_cnt;
3143
3144 cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
3145
3146 memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
3147
3148 lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
3149 lcmd_pkt.reserved_0 = 0;
3150 lcmd_pkt.port_path_ctrl = 0;
3151 lcmd_pkt.reserved_1 = 0;
3152 lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
3153 lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
3154
3155 int_to_scsilun(cmd->device->lun, &llun);
3156 host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
3157 sizeof(lcmd_pkt.lun));
3158
3159 /* Load SCSI command packet. */
3160 host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
3161 lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
3162
3163 /* Build IOCB segments */
3164 qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
3165
3166 /* Set total data segment count. */
3167 lcmd_pkt.entry_count = (uint8_t)req_cnt;
3168
3169 /* Specify response queue number where completion should happen */
3170 lcmd_pkt.entry_status = (uint8_t) rsp->id;
3171
3172 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
3173 (uint8_t *)cmd->cmnd, cmd->cmd_len);
3174 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
3175 (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
3176
3177 memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
3178 wmb();
3179
3180 /* Adjust ring index. */
3181 req->ring_index++;
3182 if (req->ring_index == req->length) {
3183 req->ring_index = 0;
3184 req->ring_ptr = req->ring;
3185 } else
3186 req->ring_ptr++;
3187
3188 sp->flags |= SRB_DMA_VALID;
3189
3190 /* Set chip new ring index. */
3191 WRT_REG_DWORD(req->req_q_in, req->ring_index);
3192 QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
3193
3194 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3195 return QLA_SUCCESS;
3196
3197 queuing_error:
3198 if (tot_dsds)
3199 scsi_dma_unmap(cmd);
3200
3201 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3202
3203 return QLA_FUNCTION_FAILED;
3204 }
3205
3206 void
3207 qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
3208 {
3209 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3210 scsi_qla_host_t *vha = sp->fcport->vha;
3211 struct req_que *req = vha->req;
3212 struct tsk_mgmt_entry_fx00 tm_iocb;
3213 struct scsi_lun llun;
3214
3215 memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
3216 tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
3217 tm_iocb.entry_count = 1;
3218 tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
3219 tm_iocb.reserved_0 = 0;
3220 tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
3221 tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
3222 if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
3223 int_to_scsilun(fxio->u.tmf.lun, &llun);
3224 host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
3225 sizeof(struct scsi_lun));
3226 }
3227
3228 memcpy((void *)ptm_iocb, &tm_iocb,
3229 sizeof(struct tsk_mgmt_entry_fx00));
3230 wmb();
3231 }
3232
3233 void
3234 qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
3235 {
3236 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3237 scsi_qla_host_t *vha = sp->fcport->vha;
3238 struct req_que *req = vha->req;
3239 struct abort_iocb_entry_fx00 abt_iocb;
3240
3241 memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
3242 abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
3243 abt_iocb.entry_count = 1;
3244 abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
3245 abt_iocb.abort_handle =
3246 cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
3247 abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
3248 abt_iocb.req_que_no = cpu_to_le16(req->id);
3249
3250 memcpy((void *)pabt_iocb, &abt_iocb,
3251 sizeof(struct abort_iocb_entry_fx00));
3252 wmb();
3253 }
3254
3255 void
3256 qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
3257 {
3258 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3259 struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
3260 struct fc_bsg_job *bsg_job;
3261 struct fxdisc_entry_fx00 fx_iocb;
3262 uint8_t entry_cnt = 1;
3263
3264 memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
3265 fx_iocb.entry_type = FX00_IOCB_TYPE;
3266 fx_iocb.handle = cpu_to_le32(sp->handle);
3267 fx_iocb.entry_count = entry_cnt;
3268
3269 if (sp->type == SRB_FXIOCB_DCMD) {
3270 fx_iocb.func_num =
3271 sp->u.iocb_cmd.u.fxiocb.req_func_type;
3272 fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
3273 fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
3274 fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
3275 fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
3276 fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
3277
3278 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
3279 fx_iocb.req_dsdcnt = cpu_to_le16(1);
3280 fx_iocb.req_xfrcnt =
3281 cpu_to_le16(fxio->u.fxiocb.req_len);
3282 fx_iocb.dseg_rq_address[0] =
3283 cpu_to_le32(LSD(fxio->u.fxiocb.req_dma_handle));
3284 fx_iocb.dseg_rq_address[1] =
3285 cpu_to_le32(MSD(fxio->u.fxiocb.req_dma_handle));
3286 fx_iocb.dseg_rq_len =
3287 cpu_to_le32(fxio->u.fxiocb.req_len);
3288 }
3289
3290 if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
3291 fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
3292 fx_iocb.rsp_xfrcnt =
3293 cpu_to_le16(fxio->u.fxiocb.rsp_len);
3294 fx_iocb.dseg_rsp_address[0] =
3295 cpu_to_le32(LSD(fxio->u.fxiocb.rsp_dma_handle));
3296 fx_iocb.dseg_rsp_address[1] =
3297 cpu_to_le32(MSD(fxio->u.fxiocb.rsp_dma_handle));
3298 fx_iocb.dseg_rsp_len =
3299 cpu_to_le32(fxio->u.fxiocb.rsp_len);
3300 }
3301
3302 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
3303 fx_iocb.dataword = fxio->u.fxiocb.req_data;
3304 }
3305 fx_iocb.flags = fxio->u.fxiocb.flags;
3306 } else {
3307 struct scatterlist *sg;
3308 bsg_job = sp->u.bsg_job;
3309 piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
3310 &bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
3311
3312 fx_iocb.func_num = piocb_rqst->func_type;
3313 fx_iocb.adapid = piocb_rqst->adapid;
3314 fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
3315 fx_iocb.reserved_0 = piocb_rqst->reserved_0;
3316 fx_iocb.reserved_1 = piocb_rqst->reserved_1;
3317 fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
3318 fx_iocb.dataword = piocb_rqst->dataword;
3319 fx_iocb.req_xfrcnt = piocb_rqst->req_len;
3320 fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
3321
3322 if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
3323 int avail_dsds, tot_dsds;
3324 cont_a64_entry_t lcont_pkt;
3325 cont_a64_entry_t *cont_pkt = NULL;
3326 __le32 *cur_dsd;
3327 int index = 0, cont = 0;
3328
3329 fx_iocb.req_dsdcnt =
3330 cpu_to_le16(bsg_job->request_payload.sg_cnt);
3331 tot_dsds =
3332 bsg_job->request_payload.sg_cnt;
3333 cur_dsd = (__le32 *)&fx_iocb.dseg_rq_address[0];
3334 avail_dsds = 1;
3335 for_each_sg(bsg_job->request_payload.sg_list, sg,
3336 tot_dsds, index) {
3337 dma_addr_t sle_dma;
3338
3339 /* Allocate additional continuation packets? */
3340 if (avail_dsds == 0) {
3341 /*
3342 * Five DSDs are available in the Cont.
3343 * Type 1 IOCB.
3344 */
3345 memset(&lcont_pkt, 0,
3346 REQUEST_ENTRY_SIZE);
3347 cont_pkt =
3348 qlafx00_prep_cont_type1_iocb(
3349 sp->fcport->vha->req,
3350 &lcont_pkt);
3351 cur_dsd = (__le32 *)
3352 lcont_pkt.dseg_0_address;
3353 avail_dsds = 5;
3354 cont = 1;
3355 entry_cnt++;
3356 }
3357
3358 sle_dma = sg_dma_address(sg);
3359 *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
3360 *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
3361 *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
3362 avail_dsds--;
3363
3364 if (avail_dsds == 0 && cont == 1) {
3365 cont = 0;
3366 memcpy_toio(
3367 (void __iomem *)cont_pkt,
3368 &lcont_pkt, REQUEST_ENTRY_SIZE);
3369 ql_dump_buffer(
3370 ql_dbg_user + ql_dbg_verbose,
3371 sp->fcport->vha, 0x3042,
3372 (uint8_t *)&lcont_pkt,
3373 REQUEST_ENTRY_SIZE);
3374 }
3375 }
3376 if (avail_dsds != 0 && cont == 1) {
3377 memcpy_toio((void __iomem *)cont_pkt,
3378 &lcont_pkt, REQUEST_ENTRY_SIZE);
3379 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3380 sp->fcport->vha, 0x3043,
3381 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3382 }
3383 }
3384
3385 if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
3386 int avail_dsds, tot_dsds;
3387 cont_a64_entry_t lcont_pkt;
3388 cont_a64_entry_t *cont_pkt = NULL;
3389 __le32 *cur_dsd;
3390 int index = 0, cont = 0;
3391
3392 fx_iocb.rsp_dsdcnt =
3393 cpu_to_le16(bsg_job->reply_payload.sg_cnt);
3394 tot_dsds = bsg_job->reply_payload.sg_cnt;
3395 cur_dsd = (__le32 *)&fx_iocb.dseg_rsp_address[0];
3396 avail_dsds = 1;
3397
3398 for_each_sg(bsg_job->reply_payload.sg_list, sg,
3399 tot_dsds, index) {
3400 dma_addr_t sle_dma;
3401
3402 /* Allocate additional continuation packets? */
3403 if (avail_dsds == 0) {
3404 /*
3405 * Five DSDs are available in the Cont.
3406 * Type 1 IOCB.
3407 */
3408 memset(&lcont_pkt, 0,
3409 REQUEST_ENTRY_SIZE);
3410 cont_pkt =
3411 qlafx00_prep_cont_type1_iocb(
3412 sp->fcport->vha->req,
3413 &lcont_pkt);
3414 cur_dsd = (__le32 *)
3415 lcont_pkt.dseg_0_address;
3416 avail_dsds = 5;
3417 cont = 1;
3418 entry_cnt++;
3419 }
3420
3421 sle_dma = sg_dma_address(sg);
3422 *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
3423 *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
3424 *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
3425 avail_dsds--;
3426
3427 if (avail_dsds == 0 && cont == 1) {
3428 cont = 0;
3429 memcpy_toio((void __iomem *)cont_pkt,
3430 &lcont_pkt,
3431 REQUEST_ENTRY_SIZE);
3432 ql_dump_buffer(
3433 ql_dbg_user + ql_dbg_verbose,
3434 sp->fcport->vha, 0x3045,
3435 (uint8_t *)&lcont_pkt,
3436 REQUEST_ENTRY_SIZE);
3437 }
3438 }
3439 if (avail_dsds != 0 && cont == 1) {
3440 memcpy_toio((void __iomem *)cont_pkt,
3441 &lcont_pkt, REQUEST_ENTRY_SIZE);
3442 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3443 sp->fcport->vha, 0x3046,
3444 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3445 }
3446 }
3447
3448 if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
3449 fx_iocb.dataword = piocb_rqst->dataword;
3450 fx_iocb.flags = piocb_rqst->flags;
3451 fx_iocb.entry_count = entry_cnt;
3452 }
3453
3454 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3455 sp->fcport->vha, 0x3047,
3456 (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
3457
3458 memcpy_toio((void __iomem *)pfxiocb, &fx_iocb,
3459 sizeof(struct fxdisc_entry_fx00));
3460 wmb();
3461 }
Linux with added FPC-III support