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ARM: ep93xx: move timer to its own file
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250_core.c
blob37fff12dd4d06b9f561eeabfe2c22f1cb4aa88e4
1 /*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #define SUPPORT_SYSRQ
21 #endif
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/serial_8250.h>
36 #include <linux/nmi.h>
37 #include <linux/mutex.h>
38 #include <linux/slab.h>
39 #include <linux/uaccess.h>
40 #include <linux/pm_runtime.h>
41 #ifdef CONFIG_SPARC
42 #include <linux/sunserialcore.h>
43 #endif
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47
48 #include "8250.h"
49
50 /*
51 * Configuration:
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
59 static struct uart_driver serial8250_reg;
60
61 static int serial_index(struct uart_port *port)
62 {
63 return port->minor - 64;
64 }
65
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
68 /*
69 * Debugging.
70 */
71 #if 0
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
73 #else
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
75 #endif
76
77 #if 0
78 #define DEBUG_INTR(fmt...) printk(fmt)
79 #else
80 #define DEBUG_INTR(fmt...) do { } while (0)
81 #endif
82
83 #define PASS_LIMIT 512
84
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
88 #include <asm/serial.h>
89 /*
90 * SERIAL_PORT_DFNS tells us about built-in ports that have no
91 * standard enumeration mechanism. Platforms that can find all
92 * serial ports via mechanisms like ACPI or PCI need not supply it.
93 */
94 #ifndef SERIAL_PORT_DFNS
95 #define SERIAL_PORT_DFNS
96 #endif
97
98 static const struct old_serial_port old_serial_port[] = {
99 SERIAL_PORT_DFNS /* defined in asm/serial.h */
100 };
101
102 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
103
104 #ifdef CONFIG_SERIAL_8250_RSA
105
106 #define PORT_RSA_MAX 4
107 static unsigned long probe_rsa[PORT_RSA_MAX];
108 static unsigned int probe_rsa_count;
109 #endif /* CONFIG_SERIAL_8250_RSA */
110
111 struct irq_info {
112 struct hlist_node node;
113 int irq;
114 spinlock_t lock; /* Protects list not the hash */
115 struct list_head *head;
116 };
117
118 #define NR_IRQ_HASH 32 /* Can be adjusted later */
119 static struct hlist_head irq_lists[NR_IRQ_HASH];
120 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
121
122 /*
123 * Here we define the default xmit fifo size used for each type of UART.
124 */
125 static const struct serial8250_config uart_config[] = {
126 [PORT_UNKNOWN] = {
127 .name = "unknown",
128 .fifo_size = 1,
129 .tx_loadsz = 1,
130 },
131 [PORT_8250] = {
132 .name = "8250",
133 .fifo_size = 1,
134 .tx_loadsz = 1,
135 },
136 [PORT_16450] = {
137 .name = "16450",
138 .fifo_size = 1,
139 .tx_loadsz = 1,
140 },
141 [PORT_16550] = {
142 .name = "16550",
143 .fifo_size = 1,
144 .tx_loadsz = 1,
145 },
146 [PORT_16550A] = {
147 .name = "16550A",
148 .fifo_size = 16,
149 .tx_loadsz = 16,
150 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
151 .rxtrig_bytes = {1, 4, 8, 14},
152 .flags = UART_CAP_FIFO,
153 },
154 [PORT_CIRRUS] = {
155 .name = "Cirrus",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16650] = {
160 .name = "ST16650",
161 .fifo_size = 1,
162 .tx_loadsz = 1,
163 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
164 },
165 [PORT_16650V2] = {
166 .name = "ST16650V2",
167 .fifo_size = 32,
168 .tx_loadsz = 16,
169 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
170 UART_FCR_T_TRIG_00,
171 .rxtrig_bytes = {8, 16, 24, 28},
172 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
173 },
174 [PORT_16750] = {
175 .name = "TI16750",
176 .fifo_size = 64,
177 .tx_loadsz = 64,
178 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
179 UART_FCR7_64BYTE,
180 .rxtrig_bytes = {1, 16, 32, 56},
181 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
182 },
183 [PORT_STARTECH] = {
184 .name = "Startech",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16C950] = {
189 .name = "16C950/954",
190 .fifo_size = 128,
191 .tx_loadsz = 128,
192 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
193 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
194 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
195 },
196 [PORT_16654] = {
197 .name = "ST16654",
198 .fifo_size = 64,
199 .tx_loadsz = 32,
200 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
201 UART_FCR_T_TRIG_10,
202 .rxtrig_bytes = {8, 16, 56, 60},
203 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
204 },
205 [PORT_16850] = {
206 .name = "XR16850",
207 .fifo_size = 128,
208 .tx_loadsz = 128,
209 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
210 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
211 },
212 [PORT_RSA] = {
213 .name = "RSA",
214 .fifo_size = 2048,
215 .tx_loadsz = 2048,
216 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
217 .flags = UART_CAP_FIFO,
218 },
219 [PORT_NS16550A] = {
220 .name = "NS16550A",
221 .fifo_size = 16,
222 .tx_loadsz = 16,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
224 .flags = UART_CAP_FIFO | UART_NATSEMI,
225 },
226 [PORT_XSCALE] = {
227 .name = "XScale",
228 .fifo_size = 32,
229 .tx_loadsz = 32,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
231 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
232 },
233 [PORT_OCTEON] = {
234 .name = "OCTEON",
235 .fifo_size = 64,
236 .tx_loadsz = 64,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO,
239 },
240 [PORT_AR7] = {
241 .name = "AR7",
242 .fifo_size = 16,
243 .tx_loadsz = 16,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 },
247 [PORT_U6_16550A] = {
248 .name = "U6_16550A",
249 .fifo_size = 64,
250 .tx_loadsz = 64,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 },
254 [PORT_TEGRA] = {
255 .name = "Tegra",
256 .fifo_size = 32,
257 .tx_loadsz = 8,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
259 UART_FCR_T_TRIG_01,
260 .rxtrig_bytes = {1, 4, 8, 14},
261 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
262 },
263 [PORT_XR17D15X] = {
264 .name = "XR17D15X",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
269 UART_CAP_SLEEP,
270 },
271 [PORT_XR17V35X] = {
272 .name = "XR17V35X",
273 .fifo_size = 256,
274 .tx_loadsz = 256,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
276 UART_FCR_T_TRIG_11,
277 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
278 UART_CAP_SLEEP,
279 },
280 [PORT_LPC3220] = {
281 .name = "LPC3220",
282 .fifo_size = 64,
283 .tx_loadsz = 32,
284 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
285 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
286 .flags = UART_CAP_FIFO,
287 },
288 [PORT_BRCM_TRUMANAGE] = {
289 .name = "TruManage",
290 .fifo_size = 1,
291 .tx_loadsz = 1024,
292 .flags = UART_CAP_HFIFO,
293 },
294 [PORT_8250_CIR] = {
295 .name = "CIR port"
296 },
297 [PORT_ALTR_16550_F32] = {
298 .name = "Altera 16550 FIFO32",
299 .fifo_size = 32,
300 .tx_loadsz = 32,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 },
304 [PORT_ALTR_16550_F64] = {
305 .name = "Altera 16550 FIFO64",
306 .fifo_size = 64,
307 .tx_loadsz = 64,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
309 .flags = UART_CAP_FIFO | UART_CAP_AFE,
310 },
311 [PORT_ALTR_16550_F128] = {
312 .name = "Altera 16550 FIFO128",
313 .fifo_size = 128,
314 .tx_loadsz = 128,
315 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
316 .flags = UART_CAP_FIFO | UART_CAP_AFE,
317 },
318 /* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
319 workaround of errata A-008006 which states that tx_loadsz should be
320 configured less than Maximum supported fifo bytes */
321 [PORT_16550A_FSL64] = {
322 .name = "16550A_FSL64",
323 .fifo_size = 64,
324 .tx_loadsz = 63,
325 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
326 UART_FCR7_64BYTE,
327 .flags = UART_CAP_FIFO,
328 },
329 };
330
331 /* Uart divisor latch read */
332 static int default_serial_dl_read(struct uart_8250_port *up)
333 {
334 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
335 }
336
337 /* Uart divisor latch write */
338 static void default_serial_dl_write(struct uart_8250_port *up, int value)
339 {
340 serial_out(up, UART_DLL, value & 0xff);
341 serial_out(up, UART_DLM, value >> 8 & 0xff);
342 }
343
344 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
345
346 /* Au1x00/RT288x UART hardware has a weird register layout */
347 static const s8 au_io_in_map[8] = {
348 0, /* UART_RX */
349 2, /* UART_IER */
350 3, /* UART_IIR */
351 5, /* UART_LCR */
352 6, /* UART_MCR */
353 7, /* UART_LSR */
354 8, /* UART_MSR */
355 -1, /* UART_SCR (unmapped) */
356 };
357
358 static const s8 au_io_out_map[8] = {
359 1, /* UART_TX */
360 2, /* UART_IER */
361 4, /* UART_FCR */
362 5, /* UART_LCR */
363 6, /* UART_MCR */
364 -1, /* UART_LSR (unmapped) */
365 -1, /* UART_MSR (unmapped) */
366 -1, /* UART_SCR (unmapped) */
367 };
368
369 static unsigned int au_serial_in(struct uart_port *p, int offset)
370 {
371 if (offset >= ARRAY_SIZE(au_io_in_map))
372 return UINT_MAX;
373 offset = au_io_in_map[offset];
374 if (offset < 0)
375 return UINT_MAX;
376 return __raw_readl(p->membase + (offset << p->regshift));
377 }
378
379 static void au_serial_out(struct uart_port *p, int offset, int value)
380 {
381 if (offset >= ARRAY_SIZE(au_io_out_map))
382 return;
383 offset = au_io_out_map[offset];
384 if (offset < 0)
385 return;
386 __raw_writel(value, p->membase + (offset << p->regshift));
387 }
388
389 /* Au1x00 haven't got a standard divisor latch */
390 static int au_serial_dl_read(struct uart_8250_port *up)
391 {
392 return __raw_readl(up->port.membase + 0x28);
393 }
394
395 static void au_serial_dl_write(struct uart_8250_port *up, int value)
396 {
397 __raw_writel(value, up->port.membase + 0x28);
398 }
399
400 #endif
401
402 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
403 {
404 offset = offset << p->regshift;
405 outb(p->hub6 - 1 + offset, p->iobase);
406 return inb(p->iobase + 1);
407 }
408
409 static void hub6_serial_out(struct uart_port *p, int offset, int value)
410 {
411 offset = offset << p->regshift;
412 outb(p->hub6 - 1 + offset, p->iobase);
413 outb(value, p->iobase + 1);
414 }
415
416 static unsigned int mem_serial_in(struct uart_port *p, int offset)
417 {
418 offset = offset << p->regshift;
419 return readb(p->membase + offset);
420 }
421
422 static void mem_serial_out(struct uart_port *p, int offset, int value)
423 {
424 offset = offset << p->regshift;
425 writeb(value, p->membase + offset);
426 }
427
428 static void mem32_serial_out(struct uart_port *p, int offset, int value)
429 {
430 offset = offset << p->regshift;
431 writel(value, p->membase + offset);
432 }
433
434 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
435 {
436 offset = offset << p->regshift;
437 return readl(p->membase + offset);
438 }
439
440 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
441 {
442 offset = offset << p->regshift;
443 iowrite32be(value, p->membase + offset);
444 }
445
446 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
447 {
448 offset = offset << p->regshift;
449 return ioread32be(p->membase + offset);
450 }
451
452 static unsigned int io_serial_in(struct uart_port *p, int offset)
453 {
454 offset = offset << p->regshift;
455 return inb(p->iobase + offset);
456 }
457
458 static void io_serial_out(struct uart_port *p, int offset, int value)
459 {
460 offset = offset << p->regshift;
461 outb(value, p->iobase + offset);
462 }
463
464 static int serial8250_default_handle_irq(struct uart_port *port);
465 static int exar_handle_irq(struct uart_port *port);
466
467 static void set_io_from_upio(struct uart_port *p)
468 {
469 struct uart_8250_port *up = up_to_u8250p(p);
470
471 up->dl_read = default_serial_dl_read;
472 up->dl_write = default_serial_dl_write;
473
474 switch (p->iotype) {
475 case UPIO_HUB6:
476 p->serial_in = hub6_serial_in;
477 p->serial_out = hub6_serial_out;
478 break;
479
480 case UPIO_MEM:
481 p->serial_in = mem_serial_in;
482 p->serial_out = mem_serial_out;
483 break;
484
485 case UPIO_MEM32:
486 p->serial_in = mem32_serial_in;
487 p->serial_out = mem32_serial_out;
488 break;
489
490 case UPIO_MEM32BE:
491 p->serial_in = mem32be_serial_in;
492 p->serial_out = mem32be_serial_out;
493 break;
494
495 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
496 case UPIO_AU:
497 p->serial_in = au_serial_in;
498 p->serial_out = au_serial_out;
499 up->dl_read = au_serial_dl_read;
500 up->dl_write = au_serial_dl_write;
501 break;
502 #endif
503
504 default:
505 p->serial_in = io_serial_in;
506 p->serial_out = io_serial_out;
507 break;
508 }
509 /* Remember loaded iotype */
510 up->cur_iotype = p->iotype;
511 p->handle_irq = serial8250_default_handle_irq;
512 }
513
514 static void
515 serial_port_out_sync(struct uart_port *p, int offset, int value)
516 {
517 switch (p->iotype) {
518 case UPIO_MEM:
519 case UPIO_MEM32:
520 case UPIO_MEM32BE:
521 case UPIO_AU:
522 p->serial_out(p, offset, value);
523 p->serial_in(p, UART_LCR); /* safe, no side-effects */
524 break;
525 default:
526 p->serial_out(p, offset, value);
527 }
528 }
529
530 /*
531 * For the 16C950
532 */
533 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
534 {
535 serial_out(up, UART_SCR, offset);
536 serial_out(up, UART_ICR, value);
537 }
538
539 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
540 {
541 unsigned int value;
542
543 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
544 serial_out(up, UART_SCR, offset);
545 value = serial_in(up, UART_ICR);
546 serial_icr_write(up, UART_ACR, up->acr);
547
548 return value;
549 }
550
551 /*
552 * FIFO support.
553 */
554 static void serial8250_clear_fifos(struct uart_8250_port *p)
555 {
556 if (p->capabilities & UART_CAP_FIFO) {
557 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
558 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
559 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
560 serial_out(p, UART_FCR, 0);
561 }
562 }
563
564 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
565 {
566 serial8250_clear_fifos(p);
567 serial_out(p, UART_FCR, p->fcr);
568 }
569 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
570
571 void serial8250_rpm_get(struct uart_8250_port *p)
572 {
573 if (!(p->capabilities & UART_CAP_RPM))
574 return;
575 pm_runtime_get_sync(p->port.dev);
576 }
577 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
578
579 void serial8250_rpm_put(struct uart_8250_port *p)
580 {
581 if (!(p->capabilities & UART_CAP_RPM))
582 return;
583 pm_runtime_mark_last_busy(p->port.dev);
584 pm_runtime_put_autosuspend(p->port.dev);
585 }
586 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
587
588 /*
589 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
590 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
591 * empty and the HW can idle again.
592 */
593 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
594 {
595 unsigned char rpm_active;
596
597 if (!(p->capabilities & UART_CAP_RPM))
598 return;
599
600 rpm_active = xchg(&p->rpm_tx_active, 1);
601 if (rpm_active)
602 return;
603 pm_runtime_get_sync(p->port.dev);
604 }
605
606 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
607 {
608 unsigned char rpm_active;
609
610 if (!(p->capabilities & UART_CAP_RPM))
611 return;
612
613 rpm_active = xchg(&p->rpm_tx_active, 0);
614 if (!rpm_active)
615 return;
616 pm_runtime_mark_last_busy(p->port.dev);
617 pm_runtime_put_autosuspend(p->port.dev);
618 }
619
620 /*
621 * IER sleep support. UARTs which have EFRs need the "extended
622 * capability" bit enabled. Note that on XR16C850s, we need to
623 * reset LCR to write to IER.
624 */
625 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
626 {
627 unsigned char lcr = 0, efr = 0;
628 /*
629 * Exar UARTs have a SLEEP register that enables or disables
630 * each UART to enter sleep mode separately. On the XR17V35x the
631 * register is accessible to each UART at the UART_EXAR_SLEEP
632 * offset but the UART channel may only write to the corresponding
633 * bit.
634 */
635 serial8250_rpm_get(p);
636 if ((p->port.type == PORT_XR17V35X) ||
637 (p->port.type == PORT_XR17D15X)) {
638 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
639 goto out;
640 }
641
642 if (p->capabilities & UART_CAP_SLEEP) {
643 if (p->capabilities & UART_CAP_EFR) {
644 lcr = serial_in(p, UART_LCR);
645 efr = serial_in(p, UART_EFR);
646 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
647 serial_out(p, UART_EFR, UART_EFR_ECB);
648 serial_out(p, UART_LCR, 0);
649 }
650 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
651 if (p->capabilities & UART_CAP_EFR) {
652 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
653 serial_out(p, UART_EFR, efr);
654 serial_out(p, UART_LCR, lcr);
655 }
656 }
657 out:
658 serial8250_rpm_put(p);
659 }
660
661 #ifdef CONFIG_SERIAL_8250_RSA
662 /*
663 * Attempts to turn on the RSA FIFO. Returns zero on failure.
664 * We set the port uart clock rate if we succeed.
665 */
666 static int __enable_rsa(struct uart_8250_port *up)
667 {
668 unsigned char mode;
669 int result;
670
671 mode = serial_in(up, UART_RSA_MSR);
672 result = mode & UART_RSA_MSR_FIFO;
673
674 if (!result) {
675 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
676 mode = serial_in(up, UART_RSA_MSR);
677 result = mode & UART_RSA_MSR_FIFO;
678 }
679
680 if (result)
681 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
682
683 return result;
684 }
685
686 static void enable_rsa(struct uart_8250_port *up)
687 {
688 if (up->port.type == PORT_RSA) {
689 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
690 spin_lock_irq(&up->port.lock);
691 __enable_rsa(up);
692 spin_unlock_irq(&up->port.lock);
693 }
694 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
695 serial_out(up, UART_RSA_FRR, 0);
696 }
697 }
698
699 /*
700 * Attempts to turn off the RSA FIFO. Returns zero on failure.
701 * It is unknown why interrupts were disabled in here. However,
702 * the caller is expected to preserve this behaviour by grabbing
703 * the spinlock before calling this function.
704 */
705 static void disable_rsa(struct uart_8250_port *up)
706 {
707 unsigned char mode;
708 int result;
709
710 if (up->port.type == PORT_RSA &&
711 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
712 spin_lock_irq(&up->port.lock);
713
714 mode = serial_in(up, UART_RSA_MSR);
715 result = !(mode & UART_RSA_MSR_FIFO);
716
717 if (!result) {
718 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
719 mode = serial_in(up, UART_RSA_MSR);
720 result = !(mode & UART_RSA_MSR_FIFO);
721 }
722
723 if (result)
724 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
725 spin_unlock_irq(&up->port.lock);
726 }
727 }
728 #endif /* CONFIG_SERIAL_8250_RSA */
729
730 /*
731 * This is a quickie test to see how big the FIFO is.
732 * It doesn't work at all the time, more's the pity.
733 */
734 static int size_fifo(struct uart_8250_port *up)
735 {
736 unsigned char old_fcr, old_mcr, old_lcr;
737 unsigned short old_dl;
738 int count;
739
740 old_lcr = serial_in(up, UART_LCR);
741 serial_out(up, UART_LCR, 0);
742 old_fcr = serial_in(up, UART_FCR);
743 old_mcr = serial_in(up, UART_MCR);
744 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
745 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
746 serial_out(up, UART_MCR, UART_MCR_LOOP);
747 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
748 old_dl = serial_dl_read(up);
749 serial_dl_write(up, 0x0001);
750 serial_out(up, UART_LCR, 0x03);
751 for (count = 0; count < 256; count++)
752 serial_out(up, UART_TX, count);
753 mdelay(20);/* FIXME - schedule_timeout */
754 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
755 (count < 256); count++)
756 serial_in(up, UART_RX);
757 serial_out(up, UART_FCR, old_fcr);
758 serial_out(up, UART_MCR, old_mcr);
759 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
760 serial_dl_write(up, old_dl);
761 serial_out(up, UART_LCR, old_lcr);
762
763 return count;
764 }
765
766 /*
767 * Read UART ID using the divisor method - set DLL and DLM to zero
768 * and the revision will be in DLL and device type in DLM. We
769 * preserve the device state across this.
770 */
771 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
772 {
773 unsigned char old_dll, old_dlm, old_lcr;
774 unsigned int id;
775
776 old_lcr = serial_in(p, UART_LCR);
777 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
778
779 old_dll = serial_in(p, UART_DLL);
780 old_dlm = serial_in(p, UART_DLM);
781
782 serial_out(p, UART_DLL, 0);
783 serial_out(p, UART_DLM, 0);
784
785 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
786
787 serial_out(p, UART_DLL, old_dll);
788 serial_out(p, UART_DLM, old_dlm);
789 serial_out(p, UART_LCR, old_lcr);
790
791 return id;
792 }
793
794 /*
795 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
796 * When this function is called we know it is at least a StarTech
797 * 16650 V2, but it might be one of several StarTech UARTs, or one of
798 * its clones. (We treat the broken original StarTech 16650 V1 as a
799 * 16550, and why not? Startech doesn't seem to even acknowledge its
800 * existence.)
801 *
802 * What evil have men's minds wrought...
803 */
804 static void autoconfig_has_efr(struct uart_8250_port *up)
805 {
806 unsigned int id1, id2, id3, rev;
807
808 /*
809 * Everything with an EFR has SLEEP
810 */
811 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
812
813 /*
814 * First we check to see if it's an Oxford Semiconductor UART.
815 *
816 * If we have to do this here because some non-National
817 * Semiconductor clone chips lock up if you try writing to the
818 * LSR register (which serial_icr_read does)
819 */
820
821 /*
822 * Check for Oxford Semiconductor 16C950.
823 *
824 * EFR [4] must be set else this test fails.
825 *
826 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
827 * claims that it's needed for 952 dual UART's (which are not
828 * recommended for new designs).
829 */
830 up->acr = 0;
831 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
832 serial_out(up, UART_EFR, UART_EFR_ECB);
833 serial_out(up, UART_LCR, 0x00);
834 id1 = serial_icr_read(up, UART_ID1);
835 id2 = serial_icr_read(up, UART_ID2);
836 id3 = serial_icr_read(up, UART_ID3);
837 rev = serial_icr_read(up, UART_REV);
838
839 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
840
841 if (id1 == 0x16 && id2 == 0xC9 &&
842 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
843 up->port.type = PORT_16C950;
844
845 /*
846 * Enable work around for the Oxford Semiconductor 952 rev B
847 * chip which causes it to seriously miscalculate baud rates
848 * when DLL is 0.
849 */
850 if (id3 == 0x52 && rev == 0x01)
851 up->bugs |= UART_BUG_QUOT;
852 return;
853 }
854
855 /*
856 * We check for a XR16C850 by setting DLL and DLM to 0, and then
857 * reading back DLL and DLM. The chip type depends on the DLM
858 * value read back:
859 * 0x10 - XR16C850 and the DLL contains the chip revision.
860 * 0x12 - XR16C2850.
861 * 0x14 - XR16C854.
862 */
863 id1 = autoconfig_read_divisor_id(up);
864 DEBUG_AUTOCONF("850id=%04x ", id1);
865
866 id2 = id1 >> 8;
867 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
868 up->port.type = PORT_16850;
869 return;
870 }
871
872 /*
873 * It wasn't an XR16C850.
874 *
875 * We distinguish between the '654 and the '650 by counting
876 * how many bytes are in the FIFO. I'm using this for now,
877 * since that's the technique that was sent to me in the
878 * serial driver update, but I'm not convinced this works.
879 * I've had problems doing this in the past. -TYT
880 */
881 if (size_fifo(up) == 64)
882 up->port.type = PORT_16654;
883 else
884 up->port.type = PORT_16650V2;
885 }
886
887 /*
888 * We detected a chip without a FIFO. Only two fall into
889 * this category - the original 8250 and the 16450. The
890 * 16450 has a scratch register (accessible with LCR=0)
891 */
892 static void autoconfig_8250(struct uart_8250_port *up)
893 {
894 unsigned char scratch, status1, status2;
895
896 up->port.type = PORT_8250;
897
898 scratch = serial_in(up, UART_SCR);
899 serial_out(up, UART_SCR, 0xa5);
900 status1 = serial_in(up, UART_SCR);
901 serial_out(up, UART_SCR, 0x5a);
902 status2 = serial_in(up, UART_SCR);
903 serial_out(up, UART_SCR, scratch);
904
905 if (status1 == 0xa5 && status2 == 0x5a)
906 up->port.type = PORT_16450;
907 }
908
909 static int broken_efr(struct uart_8250_port *up)
910 {
911 /*
912 * Exar ST16C2550 "A2" devices incorrectly detect as
913 * having an EFR, and report an ID of 0x0201. See
914 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
915 */
916 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
917 return 1;
918
919 return 0;
920 }
921
922 /*
923 * We know that the chip has FIFOs. Does it have an EFR? The
924 * EFR is located in the same register position as the IIR and
925 * we know the top two bits of the IIR are currently set. The
926 * EFR should contain zero. Try to read the EFR.
927 */
928 static void autoconfig_16550a(struct uart_8250_port *up)
929 {
930 unsigned char status1, status2;
931 unsigned int iersave;
932
933 up->port.type = PORT_16550A;
934 up->capabilities |= UART_CAP_FIFO;
935
936 /*
937 * XR17V35x UARTs have an extra divisor register, DLD
938 * that gets enabled with when DLAB is set which will
939 * cause the device to incorrectly match and assign
940 * port type to PORT_16650. The EFR for this UART is
941 * found at offset 0x09. Instead check the Deice ID (DVID)
942 * register for a 2, 4 or 8 port UART.
943 */
944 if (up->port.flags & UPF_EXAR_EFR) {
945 status1 = serial_in(up, UART_EXAR_DVID);
946 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
947 DEBUG_AUTOCONF("Exar XR17V35x ");
948 up->port.type = PORT_XR17V35X;
949 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
950 UART_CAP_SLEEP;
951
952 return;
953 }
954
955 }
956
957 /*
958 * Check for presence of the EFR when DLAB is set.
959 * Only ST16C650V1 UARTs pass this test.
960 */
961 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
962 if (serial_in(up, UART_EFR) == 0) {
963 serial_out(up, UART_EFR, 0xA8);
964 if (serial_in(up, UART_EFR) != 0) {
965 DEBUG_AUTOCONF("EFRv1 ");
966 up->port.type = PORT_16650;
967 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
968 } else {
969 serial_out(up, UART_LCR, 0);
970 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
971 UART_FCR7_64BYTE);
972 status1 = serial_in(up, UART_IIR) >> 5;
973 serial_out(up, UART_FCR, 0);
974 serial_out(up, UART_LCR, 0);
975
976 if (status1 == 7)
977 up->port.type = PORT_16550A_FSL64;
978 else
979 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
980 }
981 serial_out(up, UART_EFR, 0);
982 return;
983 }
984
985 /*
986 * Maybe it requires 0xbf to be written to the LCR.
987 * (other ST16C650V2 UARTs, TI16C752A, etc)
988 */
989 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
990 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
991 DEBUG_AUTOCONF("EFRv2 ");
992 autoconfig_has_efr(up);
993 return;
994 }
995
996 /*
997 * Check for a National Semiconductor SuperIO chip.
998 * Attempt to switch to bank 2, read the value of the LOOP bit
999 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1000 * switch back to bank 2, read it from EXCR1 again and check
1001 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1002 */
1003 serial_out(up, UART_LCR, 0);
1004 status1 = serial_in(up, UART_MCR);
1005 serial_out(up, UART_LCR, 0xE0);
1006 status2 = serial_in(up, 0x02); /* EXCR1 */
1007
1008 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1009 serial_out(up, UART_LCR, 0);
1010 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1011 serial_out(up, UART_LCR, 0xE0);
1012 status2 = serial_in(up, 0x02); /* EXCR1 */
1013 serial_out(up, UART_LCR, 0);
1014 serial_out(up, UART_MCR, status1);
1015
1016 if ((status2 ^ status1) & UART_MCR_LOOP) {
1017 unsigned short quot;
1018
1019 serial_out(up, UART_LCR, 0xE0);
1020
1021 quot = serial_dl_read(up);
1022 quot <<= 3;
1023
1024 if (ns16550a_goto_highspeed(up))
1025 serial_dl_write(up, quot);
1026
1027 serial_out(up, UART_LCR, 0);
1028
1029 up->port.uartclk = 921600*16;
1030 up->port.type = PORT_NS16550A;
1031 up->capabilities |= UART_NATSEMI;
1032 return;
1033 }
1034 }
1035
1036 /*
1037 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1038 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1039 * Try setting it with and without DLAB set. Cheap clones
1040 * set bit 5 without DLAB set.
1041 */
1042 serial_out(up, UART_LCR, 0);
1043 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1044 status1 = serial_in(up, UART_IIR) >> 5;
1045 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1046 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1047 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1048 status2 = serial_in(up, UART_IIR) >> 5;
1049 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1050 serial_out(up, UART_LCR, 0);
1051
1052 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1053
1054 if (status1 == 6 && status2 == 7) {
1055 up->port.type = PORT_16750;
1056 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1057 return;
1058 }
1059
1060 /*
1061 * Try writing and reading the UART_IER_UUE bit (b6).
1062 * If it works, this is probably one of the Xscale platform's
1063 * internal UARTs.
1064 * We're going to explicitly set the UUE bit to 0 before
1065 * trying to write and read a 1 just to make sure it's not
1066 * already a 1 and maybe locked there before we even start start.
1067 */
1068 iersave = serial_in(up, UART_IER);
1069 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1070 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1071 /*
1072 * OK it's in a known zero state, try writing and reading
1073 * without disturbing the current state of the other bits.
1074 */
1075 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1076 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1077 /*
1078 * It's an Xscale.
1079 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1080 */
1081 DEBUG_AUTOCONF("Xscale ");
1082 up->port.type = PORT_XSCALE;
1083 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1084 return;
1085 }
1086 } else {
1087 /*
1088 * If we got here we couldn't force the IER_UUE bit to 0.
1089 * Log it and continue.
1090 */
1091 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1092 }
1093 serial_out(up, UART_IER, iersave);
1094
1095 /*
1096 * Exar uarts have EFR in a weird location
1097 */
1098 if (up->port.flags & UPF_EXAR_EFR) {
1099 DEBUG_AUTOCONF("Exar XR17D15x ");
1100 up->port.type = PORT_XR17D15X;
1101 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1102 UART_CAP_SLEEP;
1103
1104 return;
1105 }
1106
1107 /*
1108 * We distinguish between 16550A and U6 16550A by counting
1109 * how many bytes are in the FIFO.
1110 */
1111 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1112 up->port.type = PORT_U6_16550A;
1113 up->capabilities |= UART_CAP_AFE;
1114 }
1115 }
1116
1117 /*
1118 * This routine is called by rs_init() to initialize a specific serial
1119 * port. It determines what type of UART chip this serial port is
1120 * using: 8250, 16450, 16550, 16550A. The important question is
1121 * whether or not this UART is a 16550A or not, since this will
1122 * determine whether or not we can use its FIFO features or not.
1123 */
1124 static void autoconfig(struct uart_8250_port *up)
1125 {
1126 unsigned char status1, scratch, scratch2, scratch3;
1127 unsigned char save_lcr, save_mcr;
1128 struct uart_port *port = &up->port;
1129 unsigned long flags;
1130 unsigned int old_capabilities;
1131
1132 if (!port->iobase && !port->mapbase && !port->membase)
1133 return;
1134
1135 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1136 serial_index(port), port->iobase, port->membase);
1137
1138 /*
1139 * We really do need global IRQs disabled here - we're going to
1140 * be frobbing the chips IRQ enable register to see if it exists.
1141 */
1142 spin_lock_irqsave(&port->lock, flags);
1143
1144 up->capabilities = 0;
1145 up->bugs = 0;
1146
1147 if (!(port->flags & UPF_BUGGY_UART)) {
1148 /*
1149 * Do a simple existence test first; if we fail this,
1150 * there's no point trying anything else.
1151 *
1152 * 0x80 is used as a nonsense port to prevent against
1153 * false positives due to ISA bus float. The
1154 * assumption is that 0x80 is a non-existent port;
1155 * which should be safe since include/asm/io.h also
1156 * makes this assumption.
1157 *
1158 * Note: this is safe as long as MCR bit 4 is clear
1159 * and the device is in "PC" mode.
1160 */
1161 scratch = serial_in(up, UART_IER);
1162 serial_out(up, UART_IER, 0);
1163 #ifdef __i386__
1164 outb(0xff, 0x080);
1165 #endif
1166 /*
1167 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1168 * 16C754B) allow only to modify them if an EFR bit is set.
1169 */
1170 scratch2 = serial_in(up, UART_IER) & 0x0f;
1171 serial_out(up, UART_IER, 0x0F);
1172 #ifdef __i386__
1173 outb(0, 0x080);
1174 #endif
1175 scratch3 = serial_in(up, UART_IER) & 0x0f;
1176 serial_out(up, UART_IER, scratch);
1177 if (scratch2 != 0 || scratch3 != 0x0F) {
1178 /*
1179 * We failed; there's nothing here
1180 */
1181 spin_unlock_irqrestore(&port->lock, flags);
1182 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1183 scratch2, scratch3);
1184 goto out;
1185 }
1186 }
1187
1188 save_mcr = serial_in(up, UART_MCR);
1189 save_lcr = serial_in(up, UART_LCR);
1190
1191 /*
1192 * Check to see if a UART is really there. Certain broken
1193 * internal modems based on the Rockwell chipset fail this
1194 * test, because they apparently don't implement the loopback
1195 * test mode. So this test is skipped on the COM 1 through
1196 * COM 4 ports. This *should* be safe, since no board
1197 * manufacturer would be stupid enough to design a board
1198 * that conflicts with COM 1-4 --- we hope!
1199 */
1200 if (!(port->flags & UPF_SKIP_TEST)) {
1201 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1202 status1 = serial_in(up, UART_MSR) & 0xF0;
1203 serial_out(up, UART_MCR, save_mcr);
1204 if (status1 != 0x90) {
1205 spin_unlock_irqrestore(&port->lock, flags);
1206 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1207 status1);
1208 goto out;
1209 }
1210 }
1211
1212 /*
1213 * We're pretty sure there's a port here. Lets find out what
1214 * type of port it is. The IIR top two bits allows us to find
1215 * out if it's 8250 or 16450, 16550, 16550A or later. This
1216 * determines what we test for next.
1217 *
1218 * We also initialise the EFR (if any) to zero for later. The
1219 * EFR occupies the same register location as the FCR and IIR.
1220 */
1221 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1222 serial_out(up, UART_EFR, 0);
1223 serial_out(up, UART_LCR, 0);
1224
1225 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1226 scratch = serial_in(up, UART_IIR) >> 6;
1227
1228 switch (scratch) {
1229 case 0:
1230 autoconfig_8250(up);
1231 break;
1232 case 1:
1233 port->type = PORT_UNKNOWN;
1234 break;
1235 case 2:
1236 port->type = PORT_16550;
1237 break;
1238 case 3:
1239 autoconfig_16550a(up);
1240 break;
1241 }
1242
1243 #ifdef CONFIG_SERIAL_8250_RSA
1244 /*
1245 * Only probe for RSA ports if we got the region.
1246 */
1247 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1248 __enable_rsa(up))
1249 port->type = PORT_RSA;
1250 #endif
1251
1252 serial_out(up, UART_LCR, save_lcr);
1253
1254 port->fifosize = uart_config[up->port.type].fifo_size;
1255 old_capabilities = up->capabilities;
1256 up->capabilities = uart_config[port->type].flags;
1257 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1258
1259 if (port->type == PORT_UNKNOWN)
1260 goto out_lock;
1261
1262 /*
1263 * Reset the UART.
1264 */
1265 #ifdef CONFIG_SERIAL_8250_RSA
1266 if (port->type == PORT_RSA)
1267 serial_out(up, UART_RSA_FRR, 0);
1268 #endif
1269 serial_out(up, UART_MCR, save_mcr);
1270 serial8250_clear_fifos(up);
1271 serial_in(up, UART_RX);
1272 if (up->capabilities & UART_CAP_UUE)
1273 serial_out(up, UART_IER, UART_IER_UUE);
1274 else
1275 serial_out(up, UART_IER, 0);
1276
1277 out_lock:
1278 spin_unlock_irqrestore(&port->lock, flags);
1279 if (up->capabilities != old_capabilities) {
1280 printk(KERN_WARNING
1281 "ttyS%d: detected caps %08x should be %08x\n",
1282 serial_index(port), old_capabilities,
1283 up->capabilities);
1284 }
1285 out:
1286 DEBUG_AUTOCONF("iir=%d ", scratch);
1287 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1288 }
1289
1290 static void autoconfig_irq(struct uart_8250_port *up)
1291 {
1292 struct uart_port *port = &up->port;
1293 unsigned char save_mcr, save_ier;
1294 unsigned char save_ICP = 0;
1295 unsigned int ICP = 0;
1296 unsigned long irqs;
1297 int irq;
1298
1299 if (port->flags & UPF_FOURPORT) {
1300 ICP = (port->iobase & 0xfe0) | 0x1f;
1301 save_ICP = inb_p(ICP);
1302 outb_p(0x80, ICP);
1303 inb_p(ICP);
1304 }
1305
1306 /* forget possible initially masked and pending IRQ */
1307 probe_irq_off(probe_irq_on());
1308 save_mcr = serial_in(up, UART_MCR);
1309 save_ier = serial_in(up, UART_IER);
1310 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1311
1312 irqs = probe_irq_on();
1313 serial_out(up, UART_MCR, 0);
1314 udelay(10);
1315 if (port->flags & UPF_FOURPORT) {
1316 serial_out(up, UART_MCR,
1317 UART_MCR_DTR | UART_MCR_RTS);
1318 } else {
1319 serial_out(up, UART_MCR,
1320 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1321 }
1322 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1323 serial_in(up, UART_LSR);
1324 serial_in(up, UART_RX);
1325 serial_in(up, UART_IIR);
1326 serial_in(up, UART_MSR);
1327 serial_out(up, UART_TX, 0xFF);
1328 udelay(20);
1329 irq = probe_irq_off(irqs);
1330
1331 serial_out(up, UART_MCR, save_mcr);
1332 serial_out(up, UART_IER, save_ier);
1333
1334 if (port->flags & UPF_FOURPORT)
1335 outb_p(save_ICP, ICP);
1336
1337 port->irq = (irq > 0) ? irq : 0;
1338 }
1339
1340 static inline void __stop_tx(struct uart_8250_port *p)
1341 {
1342 if (p->ier & UART_IER_THRI) {
1343 p->ier &= ~UART_IER_THRI;
1344 serial_out(p, UART_IER, p->ier);
1345 serial8250_rpm_put_tx(p);
1346 }
1347 }
1348
1349 static void serial8250_stop_tx(struct uart_port *port)
1350 {
1351 struct uart_8250_port *up = up_to_u8250p(port);
1352
1353 serial8250_rpm_get(up);
1354 __stop_tx(up);
1355
1356 /*
1357 * We really want to stop the transmitter from sending.
1358 */
1359 if (port->type == PORT_16C950) {
1360 up->acr |= UART_ACR_TXDIS;
1361 serial_icr_write(up, UART_ACR, up->acr);
1362 }
1363 serial8250_rpm_put(up);
1364 }
1365
1366 static void serial8250_start_tx(struct uart_port *port)
1367 {
1368 struct uart_8250_port *up = up_to_u8250p(port);
1369
1370 serial8250_rpm_get_tx(up);
1371
1372 if (up->dma && !up->dma->tx_dma(up))
1373 return;
1374
1375 if (!(up->ier & UART_IER_THRI)) {
1376 up->ier |= UART_IER_THRI;
1377 serial_port_out(port, UART_IER, up->ier);
1378
1379 if (up->bugs & UART_BUG_TXEN) {
1380 unsigned char lsr;
1381 lsr = serial_in(up, UART_LSR);
1382 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1383 if (lsr & UART_LSR_THRE)
1384 serial8250_tx_chars(up);
1385 }
1386 }
1387
1388 /*
1389 * Re-enable the transmitter if we disabled it.
1390 */
1391 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1392 up->acr &= ~UART_ACR_TXDIS;
1393 serial_icr_write(up, UART_ACR, up->acr);
1394 }
1395 }
1396
1397 static void serial8250_throttle(struct uart_port *port)
1398 {
1399 port->throttle(port);
1400 }
1401
1402 static void serial8250_unthrottle(struct uart_port *port)
1403 {
1404 port->unthrottle(port);
1405 }
1406
1407 static void serial8250_stop_rx(struct uart_port *port)
1408 {
1409 struct uart_8250_port *up = up_to_u8250p(port);
1410
1411 serial8250_rpm_get(up);
1412
1413 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1414 up->port.read_status_mask &= ~UART_LSR_DR;
1415 serial_port_out(port, UART_IER, up->ier);
1416
1417 serial8250_rpm_put(up);
1418 }
1419
1420 static void serial8250_disable_ms(struct uart_port *port)
1421 {
1422 struct uart_8250_port *up =
1423 container_of(port, struct uart_8250_port, port);
1424
1425 /* no MSR capabilities */
1426 if (up->bugs & UART_BUG_NOMSR)
1427 return;
1428
1429 up->ier &= ~UART_IER_MSI;
1430 serial_port_out(port, UART_IER, up->ier);
1431 }
1432
1433 static void serial8250_enable_ms(struct uart_port *port)
1434 {
1435 struct uart_8250_port *up = up_to_u8250p(port);
1436
1437 /* no MSR capabilities */
1438 if (up->bugs & UART_BUG_NOMSR)
1439 return;
1440
1441 up->ier |= UART_IER_MSI;
1442
1443 serial8250_rpm_get(up);
1444 serial_port_out(port, UART_IER, up->ier);
1445 serial8250_rpm_put(up);
1446 }
1447
1448 /*
1449 * serial8250_rx_chars: processes according to the passed in LSR
1450 * value, and returns the remaining LSR bits not handled
1451 * by this Rx routine.
1452 */
1453 unsigned char
1454 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1455 {
1456 struct uart_port *port = &up->port;
1457 unsigned char ch;
1458 int max_count = 256;
1459 char flag;
1460
1461 do {
1462 if (likely(lsr & UART_LSR_DR))
1463 ch = serial_in(up, UART_RX);
1464 else
1465 /*
1466 * Intel 82571 has a Serial Over Lan device that will
1467 * set UART_LSR_BI without setting UART_LSR_DR when
1468 * it receives a break. To avoid reading from the
1469 * receive buffer without UART_LSR_DR bit set, we
1470 * just force the read character to be 0
1471 */
1472 ch = 0;
1473
1474 flag = TTY_NORMAL;
1475 port->icount.rx++;
1476
1477 lsr |= up->lsr_saved_flags;
1478 up->lsr_saved_flags = 0;
1479
1480 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1481 if (lsr & UART_LSR_BI) {
1482 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1483 port->icount.brk++;
1484 /*
1485 * We do the SysRQ and SAK checking
1486 * here because otherwise the break
1487 * may get masked by ignore_status_mask
1488 * or read_status_mask.
1489 */
1490 if (uart_handle_break(port))
1491 goto ignore_char;
1492 } else if (lsr & UART_LSR_PE)
1493 port->icount.parity++;
1494 else if (lsr & UART_LSR_FE)
1495 port->icount.frame++;
1496 if (lsr & UART_LSR_OE)
1497 port->icount.overrun++;
1498
1499 /*
1500 * Mask off conditions which should be ignored.
1501 */
1502 lsr &= port->read_status_mask;
1503
1504 if (lsr & UART_LSR_BI) {
1505 DEBUG_INTR("handling break....");
1506 flag = TTY_BREAK;
1507 } else if (lsr & UART_LSR_PE)
1508 flag = TTY_PARITY;
1509 else if (lsr & UART_LSR_FE)
1510 flag = TTY_FRAME;
1511 }
1512 if (uart_handle_sysrq_char(port, ch))
1513 goto ignore_char;
1514
1515 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1516
1517 ignore_char:
1518 lsr = serial_in(up, UART_LSR);
1519 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (--max_count > 0));
1520 spin_unlock(&port->lock);
1521 tty_flip_buffer_push(&port->state->port);
1522 spin_lock(&port->lock);
1523 return lsr;
1524 }
1525 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1526
1527 void serial8250_tx_chars(struct uart_8250_port *up)
1528 {
1529 struct uart_port *port = &up->port;
1530 struct circ_buf *xmit = &port->state->xmit;
1531 int count;
1532
1533 if (port->x_char) {
1534 serial_out(up, UART_TX, port->x_char);
1535 port->icount.tx++;
1536 port->x_char = 0;
1537 return;
1538 }
1539 if (uart_tx_stopped(port)) {
1540 serial8250_stop_tx(port);
1541 return;
1542 }
1543 if (uart_circ_empty(xmit)) {
1544 __stop_tx(up);
1545 return;
1546 }
1547
1548 count = up->tx_loadsz;
1549 do {
1550 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1551 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1552 port->icount.tx++;
1553 if (uart_circ_empty(xmit))
1554 break;
1555 if (up->capabilities & UART_CAP_HFIFO) {
1556 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1557 BOTH_EMPTY)
1558 break;
1559 }
1560 } while (--count > 0);
1561
1562 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1563 uart_write_wakeup(port);
1564
1565 DEBUG_INTR("THRE...");
1566
1567 /*
1568 * With RPM enabled, we have to wait until the FIFO is empty before the
1569 * HW can go idle. So we get here once again with empty FIFO and disable
1570 * the interrupt and RPM in __stop_tx()
1571 */
1572 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1573 __stop_tx(up);
1574 }
1575 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1576
1577 /* Caller holds uart port lock */
1578 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1579 {
1580 struct uart_port *port = &up->port;
1581 unsigned int status = serial_in(up, UART_MSR);
1582
1583 status |= up->msr_saved_flags;
1584 up->msr_saved_flags = 0;
1585 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1586 port->state != NULL) {
1587 if (status & UART_MSR_TERI)
1588 port->icount.rng++;
1589 if (status & UART_MSR_DDSR)
1590 port->icount.dsr++;
1591 if (status & UART_MSR_DDCD)
1592 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1593 if (status & UART_MSR_DCTS)
1594 uart_handle_cts_change(port, status & UART_MSR_CTS);
1595
1596 wake_up_interruptible(&port->state->port.delta_msr_wait);
1597 }
1598
1599 return status;
1600 }
1601 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1602
1603 /*
1604 * This handles the interrupt from one port.
1605 */
1606 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1607 {
1608 unsigned char status;
1609 unsigned long flags;
1610 struct uart_8250_port *up = up_to_u8250p(port);
1611 int dma_err = 0;
1612
1613 if (iir & UART_IIR_NO_INT)
1614 return 0;
1615
1616 spin_lock_irqsave(&port->lock, flags);
1617
1618 status = serial_port_in(port, UART_LSR);
1619
1620 DEBUG_INTR("status = %x...", status);
1621
1622 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1623 if (up->dma)
1624 dma_err = up->dma->rx_dma(up, iir);
1625
1626 if (!up->dma || dma_err)
1627 status = serial8250_rx_chars(up, status);
1628 }
1629 serial8250_modem_status(up);
1630 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1631 (status & UART_LSR_THRE))
1632 serial8250_tx_chars(up);
1633
1634 spin_unlock_irqrestore(&port->lock, flags);
1635 return 1;
1636 }
1637 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1638
1639 static int serial8250_default_handle_irq(struct uart_port *port)
1640 {
1641 struct uart_8250_port *up = up_to_u8250p(port);
1642 unsigned int iir;
1643 int ret;
1644
1645 serial8250_rpm_get(up);
1646
1647 iir = serial_port_in(port, UART_IIR);
1648 ret = serial8250_handle_irq(port, iir);
1649
1650 serial8250_rpm_put(up);
1651 return ret;
1652 }
1653
1654 /*
1655 * These Exar UARTs have an extra interrupt indicator that could
1656 * fire for a few unimplemented interrupts. One of which is a
1657 * wakeup event when coming out of sleep. Put this here just
1658 * to be on the safe side that these interrupts don't go unhandled.
1659 */
1660 static int exar_handle_irq(struct uart_port *port)
1661 {
1662 unsigned char int0, int1, int2, int3;
1663 unsigned int iir = serial_port_in(port, UART_IIR);
1664 int ret;
1665
1666 ret = serial8250_handle_irq(port, iir);
1667
1668 if ((port->type == PORT_XR17V35X) ||
1669 (port->type == PORT_XR17D15X)) {
1670 int0 = serial_port_in(port, 0x80);
1671 int1 = serial_port_in(port, 0x81);
1672 int2 = serial_port_in(port, 0x82);
1673 int3 = serial_port_in(port, 0x83);
1674 }
1675
1676 return ret;
1677 }
1678
1679 /*
1680 * This is the serial driver's interrupt routine.
1681 *
1682 * Arjan thinks the old way was overly complex, so it got simplified.
1683 * Alan disagrees, saying that need the complexity to handle the weird
1684 * nature of ISA shared interrupts. (This is a special exception.)
1685 *
1686 * In order to handle ISA shared interrupts properly, we need to check
1687 * that all ports have been serviced, and therefore the ISA interrupt
1688 * line has been de-asserted.
1689 *
1690 * This means we need to loop through all ports. checking that they
1691 * don't have an interrupt pending.
1692 */
1693 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1694 {
1695 struct irq_info *i = dev_id;
1696 struct list_head *l, *end = NULL;
1697 int pass_counter = 0, handled = 0;
1698
1699 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1700
1701 spin_lock(&i->lock);
1702
1703 l = i->head;
1704 do {
1705 struct uart_8250_port *up;
1706 struct uart_port *port;
1707
1708 up = list_entry(l, struct uart_8250_port, list);
1709 port = &up->port;
1710
1711 if (port->handle_irq(port)) {
1712 handled = 1;
1713 end = NULL;
1714 } else if (end == NULL)
1715 end = l;
1716
1717 l = l->next;
1718
1719 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1720 /* If we hit this, we're dead. */
1721 printk_ratelimited(KERN_ERR
1722 "serial8250: too much work for irq%d\n", irq);
1723 break;
1724 }
1725 } while (l != end);
1726
1727 spin_unlock(&i->lock);
1728
1729 DEBUG_INTR("end.\n");
1730
1731 return IRQ_RETVAL(handled);
1732 }
1733
1734 /*
1735 * To support ISA shared interrupts, we need to have one interrupt
1736 * handler that ensures that the IRQ line has been deasserted
1737 * before returning. Failing to do this will result in the IRQ
1738 * line being stuck active, and, since ISA irqs are edge triggered,
1739 * no more IRQs will be seen.
1740 */
1741 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1742 {
1743 spin_lock_irq(&i->lock);
1744
1745 if (!list_empty(i->head)) {
1746 if (i->head == &up->list)
1747 i->head = i->head->next;
1748 list_del(&up->list);
1749 } else {
1750 BUG_ON(i->head != &up->list);
1751 i->head = NULL;
1752 }
1753 spin_unlock_irq(&i->lock);
1754 /* List empty so throw away the hash node */
1755 if (i->head == NULL) {
1756 hlist_del(&i->node);
1757 kfree(i);
1758 }
1759 }
1760
1761 static int serial_link_irq_chain(struct uart_8250_port *up)
1762 {
1763 struct hlist_head *h;
1764 struct hlist_node *n;
1765 struct irq_info *i;
1766 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1767
1768 mutex_lock(&hash_mutex);
1769
1770 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1771
1772 hlist_for_each(n, h) {
1773 i = hlist_entry(n, struct irq_info, node);
1774 if (i->irq == up->port.irq)
1775 break;
1776 }
1777
1778 if (n == NULL) {
1779 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1780 if (i == NULL) {
1781 mutex_unlock(&hash_mutex);
1782 return -ENOMEM;
1783 }
1784 spin_lock_init(&i->lock);
1785 i->irq = up->port.irq;
1786 hlist_add_head(&i->node, h);
1787 }
1788 mutex_unlock(&hash_mutex);
1789
1790 spin_lock_irq(&i->lock);
1791
1792 if (i->head) {
1793 list_add(&up->list, i->head);
1794 spin_unlock_irq(&i->lock);
1795
1796 ret = 0;
1797 } else {
1798 INIT_LIST_HEAD(&up->list);
1799 i->head = &up->list;
1800 spin_unlock_irq(&i->lock);
1801 irq_flags |= up->port.irqflags;
1802 ret = request_irq(up->port.irq, serial8250_interrupt,
1803 irq_flags, "serial", i);
1804 if (ret < 0)
1805 serial_do_unlink(i, up);
1806 }
1807
1808 return ret;
1809 }
1810
1811 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1812 {
1813 /*
1814 * yes, some broken gcc emit "warning: 'i' may be used uninitialized"
1815 * but no, we are not going to take a patch that assigns NULL below.
1816 */
1817 struct irq_info *i;
1818 struct hlist_node *n;
1819 struct hlist_head *h;
1820
1821 mutex_lock(&hash_mutex);
1822
1823 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1824
1825 hlist_for_each(n, h) {
1826 i = hlist_entry(n, struct irq_info, node);
1827 if (i->irq == up->port.irq)
1828 break;
1829 }
1830
1831 BUG_ON(n == NULL);
1832 BUG_ON(i->head == NULL);
1833
1834 if (list_empty(i->head))
1835 free_irq(up->port.irq, i);
1836
1837 serial_do_unlink(i, up);
1838 mutex_unlock(&hash_mutex);
1839 }
1840
1841 /*
1842 * This function is used to handle ports that do not have an
1843 * interrupt. This doesn't work very well for 16450's, but gives
1844 * barely passable results for a 16550A. (Although at the expense
1845 * of much CPU overhead).
1846 */
1847 static void serial8250_timeout(unsigned long data)
1848 {
1849 struct uart_8250_port *up = (struct uart_8250_port *)data;
1850
1851 up->port.handle_irq(&up->port);
1852 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1853 }
1854
1855 static void serial8250_backup_timeout(unsigned long data)
1856 {
1857 struct uart_8250_port *up = (struct uart_8250_port *)data;
1858 unsigned int iir, ier = 0, lsr;
1859 unsigned long flags;
1860
1861 spin_lock_irqsave(&up->port.lock, flags);
1862
1863 /*
1864 * Must disable interrupts or else we risk racing with the interrupt
1865 * based handler.
1866 */
1867 if (up->port.irq) {
1868 ier = serial_in(up, UART_IER);
1869 serial_out(up, UART_IER, 0);
1870 }
1871
1872 iir = serial_in(up, UART_IIR);
1873
1874 /*
1875 * This should be a safe test for anyone who doesn't trust the
1876 * IIR bits on their UART, but it's specifically designed for
1877 * the "Diva" UART used on the management processor on many HP
1878 * ia64 and parisc boxes.
1879 */
1880 lsr = serial_in(up, UART_LSR);
1881 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1882 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1883 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1884 (lsr & UART_LSR_THRE)) {
1885 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1886 iir |= UART_IIR_THRI;
1887 }
1888
1889 if (!(iir & UART_IIR_NO_INT))
1890 serial8250_tx_chars(up);
1891
1892 if (up->port.irq)
1893 serial_out(up, UART_IER, ier);
1894
1895 spin_unlock_irqrestore(&up->port.lock, flags);
1896
1897 /* Standard timer interval plus 0.2s to keep the port running */
1898 mod_timer(&up->timer,
1899 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1900 }
1901
1902 static int univ8250_setup_irq(struct uart_8250_port *up)
1903 {
1904 struct uart_port *port = &up->port;
1905 int retval = 0;
1906
1907 /*
1908 * The above check will only give an accurate result the first time
1909 * the port is opened so this value needs to be preserved.
1910 */
1911 if (up->bugs & UART_BUG_THRE) {
1912 pr_debug("ttyS%d - using backup timer\n", serial_index(port));
1913
1914 up->timer.function = serial8250_backup_timeout;
1915 up->timer.data = (unsigned long)up;
1916 mod_timer(&up->timer, jiffies +
1917 uart_poll_timeout(port) + HZ / 5);
1918 }
1919
1920 /*
1921 * If the "interrupt" for this port doesn't correspond with any
1922 * hardware interrupt, we use a timer-based system. The original
1923 * driver used to do this with IRQ0.
1924 */
1925 if (!port->irq) {
1926 up->timer.data = (unsigned long)up;
1927 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1928 } else
1929 retval = serial_link_irq_chain(up);
1930
1931 return retval;
1932 }
1933
1934 static void univ8250_release_irq(struct uart_8250_port *up)
1935 {
1936 struct uart_port *port = &up->port;
1937
1938 del_timer_sync(&up->timer);
1939 up->timer.function = serial8250_timeout;
1940 if (port->irq)
1941 serial_unlink_irq_chain(up);
1942 }
1943
1944 static unsigned int serial8250_tx_empty(struct uart_port *port)
1945 {
1946 struct uart_8250_port *up = up_to_u8250p(port);
1947 unsigned long flags;
1948 unsigned int lsr;
1949
1950 serial8250_rpm_get(up);
1951
1952 spin_lock_irqsave(&port->lock, flags);
1953 lsr = serial_port_in(port, UART_LSR);
1954 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1955 spin_unlock_irqrestore(&port->lock, flags);
1956
1957 serial8250_rpm_put(up);
1958
1959 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1960 }
1961
1962 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1963 {
1964 struct uart_8250_port *up = up_to_u8250p(port);
1965 unsigned int status;
1966 unsigned int ret;
1967
1968 serial8250_rpm_get(up);
1969 status = serial8250_modem_status(up);
1970 serial8250_rpm_put(up);
1971
1972 ret = 0;
1973 if (status & UART_MSR_DCD)
1974 ret |= TIOCM_CAR;
1975 if (status & UART_MSR_RI)
1976 ret |= TIOCM_RNG;
1977 if (status & UART_MSR_DSR)
1978 ret |= TIOCM_DSR;
1979 if (status & UART_MSR_CTS)
1980 ret |= TIOCM_CTS;
1981 return ret;
1982 }
1983
1984 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1985 {
1986 struct uart_8250_port *up = up_to_u8250p(port);
1987 unsigned char mcr = 0;
1988
1989 if (mctrl & TIOCM_RTS)
1990 mcr |= UART_MCR_RTS;
1991 if (mctrl & TIOCM_DTR)
1992 mcr |= UART_MCR_DTR;
1993 if (mctrl & TIOCM_OUT1)
1994 mcr |= UART_MCR_OUT1;
1995 if (mctrl & TIOCM_OUT2)
1996 mcr |= UART_MCR_OUT2;
1997 if (mctrl & TIOCM_LOOP)
1998 mcr |= UART_MCR_LOOP;
1999
2000 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
2001
2002 serial_port_out(port, UART_MCR, mcr);
2003 }
2004 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2005
2006 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2007 {
2008 if (port->set_mctrl)
2009 port->set_mctrl(port, mctrl);
2010 else
2011 serial8250_do_set_mctrl(port, mctrl);
2012 }
2013
2014 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2015 {
2016 struct uart_8250_port *up = up_to_u8250p(port);
2017 unsigned long flags;
2018
2019 serial8250_rpm_get(up);
2020 spin_lock_irqsave(&port->lock, flags);
2021 if (break_state == -1)
2022 up->lcr |= UART_LCR_SBC;
2023 else
2024 up->lcr &= ~UART_LCR_SBC;
2025 serial_port_out(port, UART_LCR, up->lcr);
2026 spin_unlock_irqrestore(&port->lock, flags);
2027 serial8250_rpm_put(up);
2028 }
2029
2030 /*
2031 * Wait for transmitter & holding register to empty
2032 */
2033 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2034 {
2035 unsigned int status, tmout = 10000;
2036
2037 /* Wait up to 10ms for the character(s) to be sent. */
2038 for (;;) {
2039 status = serial_in(up, UART_LSR);
2040
2041 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2042
2043 if ((status & bits) == bits)
2044 break;
2045 if (--tmout == 0)
2046 break;
2047 udelay(1);
2048 }
2049
2050 /* Wait up to 1s for flow control if necessary */
2051 if (up->port.flags & UPF_CONS_FLOW) {
2052 unsigned int tmout;
2053 for (tmout = 1000000; tmout; tmout--) {
2054 unsigned int msr = serial_in(up, UART_MSR);
2055 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2056 if (msr & UART_MSR_CTS)
2057 break;
2058 udelay(1);
2059 touch_nmi_watchdog();
2060 }
2061 }
2062 }
2063
2064 #ifdef CONFIG_CONSOLE_POLL
2065 /*
2066 * Console polling routines for writing and reading from the uart while
2067 * in an interrupt or debug context.
2068 */
2069
2070 static int serial8250_get_poll_char(struct uart_port *port)
2071 {
2072 struct uart_8250_port *up = up_to_u8250p(port);
2073 unsigned char lsr;
2074 int status;
2075
2076 serial8250_rpm_get(up);
2077
2078 lsr = serial_port_in(port, UART_LSR);
2079
2080 if (!(lsr & UART_LSR_DR)) {
2081 status = NO_POLL_CHAR;
2082 goto out;
2083 }
2084
2085 status = serial_port_in(port, UART_RX);
2086 out:
2087 serial8250_rpm_put(up);
2088 return status;
2089 }
2090
2091
2092 static void serial8250_put_poll_char(struct uart_port *port,
2093 unsigned char c)
2094 {
2095 unsigned int ier;
2096 struct uart_8250_port *up = up_to_u8250p(port);
2097
2098 serial8250_rpm_get(up);
2099 /*
2100 * First save the IER then disable the interrupts
2101 */
2102 ier = serial_port_in(port, UART_IER);
2103 if (up->capabilities & UART_CAP_UUE)
2104 serial_port_out(port, UART_IER, UART_IER_UUE);
2105 else
2106 serial_port_out(port, UART_IER, 0);
2107
2108 wait_for_xmitr(up, BOTH_EMPTY);
2109 /*
2110 * Send the character out.
2111 */
2112 serial_port_out(port, UART_TX, c);
2113
2114 /*
2115 * Finally, wait for transmitter to become empty
2116 * and restore the IER
2117 */
2118 wait_for_xmitr(up, BOTH_EMPTY);
2119 serial_port_out(port, UART_IER, ier);
2120 serial8250_rpm_put(up);
2121 }
2122
2123 #endif /* CONFIG_CONSOLE_POLL */
2124
2125 int serial8250_do_startup(struct uart_port *port)
2126 {
2127 struct uart_8250_port *up = up_to_u8250p(port);
2128 unsigned long flags;
2129 unsigned char lsr, iir;
2130 int retval;
2131
2132 if (port->type == PORT_8250_CIR)
2133 return -ENODEV;
2134
2135 if (!port->fifosize)
2136 port->fifosize = uart_config[port->type].fifo_size;
2137 if (!up->tx_loadsz)
2138 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2139 if (!up->capabilities)
2140 up->capabilities = uart_config[port->type].flags;
2141 up->mcr = 0;
2142
2143 if (port->iotype != up->cur_iotype)
2144 set_io_from_upio(port);
2145
2146 serial8250_rpm_get(up);
2147 if (port->type == PORT_16C950) {
2148 /* Wake up and initialize UART */
2149 up->acr = 0;
2150 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2151 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2152 serial_port_out(port, UART_IER, 0);
2153 serial_port_out(port, UART_LCR, 0);
2154 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2155 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2156 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2157 serial_port_out(port, UART_LCR, 0);
2158 }
2159
2160 #ifdef CONFIG_SERIAL_8250_RSA
2161 /*
2162 * If this is an RSA port, see if we can kick it up to the
2163 * higher speed clock.
2164 */
2165 enable_rsa(up);
2166 #endif
2167 /*
2168 * Clear the FIFO buffers and disable them.
2169 * (they will be reenabled in set_termios())
2170 */
2171 serial8250_clear_fifos(up);
2172
2173 /*
2174 * Clear the interrupt registers.
2175 */
2176 serial_port_in(port, UART_LSR);
2177 serial_port_in(port, UART_RX);
2178 serial_port_in(port, UART_IIR);
2179 serial_port_in(port, UART_MSR);
2180
2181 /*
2182 * At this point, there's no way the LSR could still be 0xff;
2183 * if it is, then bail out, because there's likely no UART
2184 * here.
2185 */
2186 if (!(port->flags & UPF_BUGGY_UART) &&
2187 (serial_port_in(port, UART_LSR) == 0xff)) {
2188 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2189 serial_index(port));
2190 retval = -ENODEV;
2191 goto out;
2192 }
2193
2194 /*
2195 * For a XR16C850, we need to set the trigger levels
2196 */
2197 if (port->type == PORT_16850) {
2198 unsigned char fctr;
2199
2200 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2201
2202 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2203 serial_port_out(port, UART_FCTR,
2204 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2205 serial_port_out(port, UART_TRG, UART_TRG_96);
2206 serial_port_out(port, UART_FCTR,
2207 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2208 serial_port_out(port, UART_TRG, UART_TRG_96);
2209
2210 serial_port_out(port, UART_LCR, 0);
2211 }
2212
2213 if (port->irq) {
2214 unsigned char iir1;
2215 /*
2216 * Test for UARTs that do not reassert THRE when the
2217 * transmitter is idle and the interrupt has already
2218 * been cleared. Real 16550s should always reassert
2219 * this interrupt whenever the transmitter is idle and
2220 * the interrupt is enabled. Delays are necessary to
2221 * allow register changes to become visible.
2222 */
2223 spin_lock_irqsave(&port->lock, flags);
2224 if (up->port.irqflags & IRQF_SHARED)
2225 disable_irq_nosync(port->irq);
2226
2227 wait_for_xmitr(up, UART_LSR_THRE);
2228 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2229 udelay(1); /* allow THRE to set */
2230 iir1 = serial_port_in(port, UART_IIR);
2231 serial_port_out(port, UART_IER, 0);
2232 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2233 udelay(1); /* allow a working UART time to re-assert THRE */
2234 iir = serial_port_in(port, UART_IIR);
2235 serial_port_out(port, UART_IER, 0);
2236
2237 if (port->irqflags & IRQF_SHARED)
2238 enable_irq(port->irq);
2239 spin_unlock_irqrestore(&port->lock, flags);
2240
2241 /*
2242 * If the interrupt is not reasserted, or we otherwise
2243 * don't trust the iir, setup a timer to kick the UART
2244 * on a regular basis.
2245 */
2246 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2247 up->port.flags & UPF_BUG_THRE) {
2248 up->bugs |= UART_BUG_THRE;
2249 }
2250 }
2251
2252 retval = up->ops->setup_irq(up);
2253 if (retval)
2254 goto out;
2255
2256 /*
2257 * Now, initialize the UART
2258 */
2259 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2260
2261 spin_lock_irqsave(&port->lock, flags);
2262 if (up->port.flags & UPF_FOURPORT) {
2263 if (!up->port.irq)
2264 up->port.mctrl |= TIOCM_OUT1;
2265 } else
2266 /*
2267 * Most PC uarts need OUT2 raised to enable interrupts.
2268 */
2269 if (port->irq)
2270 up->port.mctrl |= TIOCM_OUT2;
2271
2272 serial8250_set_mctrl(port, port->mctrl);
2273
2274 /* Serial over Lan (SoL) hack:
2275 Intel 8257x Gigabit ethernet chips have a
2276 16550 emulation, to be used for Serial Over Lan.
2277 Those chips take a longer time than a normal
2278 serial device to signalize that a transmission
2279 data was queued. Due to that, the above test generally
2280 fails. One solution would be to delay the reading of
2281 iir. However, this is not reliable, since the timeout
2282 is variable. So, let's just don't test if we receive
2283 TX irq. This way, we'll never enable UART_BUG_TXEN.
2284 */
2285 if (up->port.flags & UPF_NO_TXEN_TEST)
2286 goto dont_test_tx_en;
2287
2288 /*
2289 * Do a quick test to see if we receive an
2290 * interrupt when we enable the TX irq.
2291 */
2292 serial_port_out(port, UART_IER, UART_IER_THRI);
2293 lsr = serial_port_in(port, UART_LSR);
2294 iir = serial_port_in(port, UART_IIR);
2295 serial_port_out(port, UART_IER, 0);
2296
2297 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2298 if (!(up->bugs & UART_BUG_TXEN)) {
2299 up->bugs |= UART_BUG_TXEN;
2300 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2301 serial_index(port));
2302 }
2303 } else {
2304 up->bugs &= ~UART_BUG_TXEN;
2305 }
2306
2307 dont_test_tx_en:
2308 spin_unlock_irqrestore(&port->lock, flags);
2309
2310 /*
2311 * Clear the interrupt registers again for luck, and clear the
2312 * saved flags to avoid getting false values from polling
2313 * routines or the previous session.
2314 */
2315 serial_port_in(port, UART_LSR);
2316 serial_port_in(port, UART_RX);
2317 serial_port_in(port, UART_IIR);
2318 serial_port_in(port, UART_MSR);
2319 up->lsr_saved_flags = 0;
2320 up->msr_saved_flags = 0;
2321
2322 /*
2323 * Request DMA channels for both RX and TX.
2324 */
2325 if (up->dma) {
2326 retval = serial8250_request_dma(up);
2327 if (retval) {
2328 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2329 serial_index(port));
2330 up->dma = NULL;
2331 }
2332 }
2333
2334 /*
2335 * Finally, enable interrupts. Note: Modem status interrupts
2336 * are set via set_termios(), which will be occurring imminently
2337 * anyway, so we don't enable them here.
2338 */
2339 up->ier = UART_IER_RLSI | UART_IER_RDI;
2340 serial_port_out(port, UART_IER, up->ier);
2341
2342 if (port->flags & UPF_FOURPORT) {
2343 unsigned int icp;
2344 /*
2345 * Enable interrupts on the AST Fourport board
2346 */
2347 icp = (port->iobase & 0xfe0) | 0x01f;
2348 outb_p(0x80, icp);
2349 inb_p(icp);
2350 }
2351 retval = 0;
2352 out:
2353 serial8250_rpm_put(up);
2354 return retval;
2355 }
2356 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2357
2358 static int serial8250_startup(struct uart_port *port)
2359 {
2360 if (port->startup)
2361 return port->startup(port);
2362 return serial8250_do_startup(port);
2363 }
2364
2365 void serial8250_do_shutdown(struct uart_port *port)
2366 {
2367 struct uart_8250_port *up = up_to_u8250p(port);
2368 unsigned long flags;
2369
2370 serial8250_rpm_get(up);
2371 /*
2372 * Disable interrupts from this port
2373 */
2374 up->ier = 0;
2375 serial_port_out(port, UART_IER, 0);
2376
2377 if (up->dma)
2378 serial8250_release_dma(up);
2379
2380 spin_lock_irqsave(&port->lock, flags);
2381 if (port->flags & UPF_FOURPORT) {
2382 /* reset interrupts on the AST Fourport board */
2383 inb((port->iobase & 0xfe0) | 0x1f);
2384 port->mctrl |= TIOCM_OUT1;
2385 } else
2386 port->mctrl &= ~TIOCM_OUT2;
2387
2388 serial8250_set_mctrl(port, port->mctrl);
2389 spin_unlock_irqrestore(&port->lock, flags);
2390
2391 /*
2392 * Disable break condition and FIFOs
2393 */
2394 serial_port_out(port, UART_LCR,
2395 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2396 serial8250_clear_fifos(up);
2397
2398 #ifdef CONFIG_SERIAL_8250_RSA
2399 /*
2400 * Reset the RSA board back to 115kbps compat mode.
2401 */
2402 disable_rsa(up);
2403 #endif
2404
2405 /*
2406 * Read data port to reset things, and then unlink from
2407 * the IRQ chain.
2408 */
2409 serial_port_in(port, UART_RX);
2410 serial8250_rpm_put(up);
2411
2412 up->ops->release_irq(up);
2413 }
2414 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2415
2416 static void serial8250_shutdown(struct uart_port *port)
2417 {
2418 if (port->shutdown)
2419 port->shutdown(port);
2420 else
2421 serial8250_do_shutdown(port);
2422 }
2423
2424 /*
2425 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2426 * Calculate divisor with extra 4-bit fractional portion
2427 */
2428 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2429 unsigned int baud,
2430 unsigned int *frac)
2431 {
2432 struct uart_port *port = &up->port;
2433 unsigned int quot_16;
2434
2435 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2436 *frac = quot_16 & 0x0f;
2437
2438 return quot_16 >> 4;
2439 }
2440
2441 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2442 unsigned int baud,
2443 unsigned int *frac)
2444 {
2445 struct uart_port *port = &up->port;
2446 unsigned int quot;
2447
2448 /*
2449 * Handle magic divisors for baud rates above baud_base on
2450 * SMSC SuperIO chips.
2451 *
2452 */
2453 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2454 baud == (port->uartclk/4))
2455 quot = 0x8001;
2456 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2457 baud == (port->uartclk/8))
2458 quot = 0x8002;
2459 else if (up->port.type == PORT_XR17V35X)
2460 quot = xr17v35x_get_divisor(up, baud, frac);
2461 else
2462 quot = uart_get_divisor(port, baud);
2463
2464 /*
2465 * Oxford Semi 952 rev B workaround
2466 */
2467 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2468 quot++;
2469
2470 return quot;
2471 }
2472
2473 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2474 tcflag_t c_cflag)
2475 {
2476 unsigned char cval;
2477
2478 switch (c_cflag & CSIZE) {
2479 case CS5:
2480 cval = UART_LCR_WLEN5;
2481 break;
2482 case CS6:
2483 cval = UART_LCR_WLEN6;
2484 break;
2485 case CS7:
2486 cval = UART_LCR_WLEN7;
2487 break;
2488 default:
2489 case CS8:
2490 cval = UART_LCR_WLEN8;
2491 break;
2492 }
2493
2494 if (c_cflag & CSTOPB)
2495 cval |= UART_LCR_STOP;
2496 if (c_cflag & PARENB) {
2497 cval |= UART_LCR_PARITY;
2498 if (up->bugs & UART_BUG_PARITY)
2499 up->fifo_bug = true;
2500 }
2501 if (!(c_cflag & PARODD))
2502 cval |= UART_LCR_EPAR;
2503 #ifdef CMSPAR
2504 if (c_cflag & CMSPAR)
2505 cval |= UART_LCR_SPAR;
2506 #endif
2507
2508 return cval;
2509 }
2510
2511 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2512 unsigned int quot, unsigned int quot_frac)
2513 {
2514 struct uart_8250_port *up = up_to_u8250p(port);
2515
2516 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2517 if (is_omap1510_8250(up)) {
2518 if (baud == 115200) {
2519 quot = 1;
2520 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2521 } else
2522 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2523 }
2524
2525 /*
2526 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2527 * otherwise just set DLAB
2528 */
2529 if (up->capabilities & UART_NATSEMI)
2530 serial_port_out(port, UART_LCR, 0xe0);
2531 else
2532 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2533
2534 serial_dl_write(up, quot);
2535
2536 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2537 if (up->port.type == PORT_XR17V35X)
2538 serial_port_out(port, 0x2, quot_frac);
2539 }
2540
2541 void
2542 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2543 struct ktermios *old)
2544 {
2545 struct uart_8250_port *up = up_to_u8250p(port);
2546 unsigned char cval;
2547 unsigned long flags;
2548 unsigned int baud, quot, frac = 0;
2549
2550 cval = serial8250_compute_lcr(up, termios->c_cflag);
2551
2552 /*
2553 * Ask the core to calculate the divisor for us.
2554 */
2555 baud = uart_get_baud_rate(port, termios, old,
2556 port->uartclk / 16 / 0xffff,
2557 port->uartclk / 16);
2558 quot = serial8250_get_divisor(up, baud, &frac);
2559
2560 /*
2561 * Ok, we're now changing the port state. Do it with
2562 * interrupts disabled.
2563 */
2564 serial8250_rpm_get(up);
2565 spin_lock_irqsave(&port->lock, flags);
2566
2567 up->lcr = cval; /* Save computed LCR */
2568
2569 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2570 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2571 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2572 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2573 up->fcr |= UART_FCR_TRIGGER_1;
2574 }
2575 }
2576
2577 /*
2578 * MCR-based auto flow control. When AFE is enabled, RTS will be
2579 * deasserted when the receive FIFO contains more characters than
2580 * the trigger, or the MCR RTS bit is cleared. In the case where
2581 * the remote UART is not using CTS auto flow control, we must
2582 * have sufficient FIFO entries for the latency of the remote
2583 * UART to respond. IOW, at least 32 bytes of FIFO.
2584 */
2585 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2586 up->mcr &= ~UART_MCR_AFE;
2587 if (termios->c_cflag & CRTSCTS)
2588 up->mcr |= UART_MCR_AFE;
2589 }
2590
2591 /*
2592 * Update the per-port timeout.
2593 */
2594 uart_update_timeout(port, termios->c_cflag, baud);
2595
2596 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2597 if (termios->c_iflag & INPCK)
2598 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2599 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2600 port->read_status_mask |= UART_LSR_BI;
2601
2602 /*
2603 * Characteres to ignore
2604 */
2605 port->ignore_status_mask = 0;
2606 if (termios->c_iflag & IGNPAR)
2607 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2608 if (termios->c_iflag & IGNBRK) {
2609 port->ignore_status_mask |= UART_LSR_BI;
2610 /*
2611 * If we're ignoring parity and break indicators,
2612 * ignore overruns too (for real raw support).
2613 */
2614 if (termios->c_iflag & IGNPAR)
2615 port->ignore_status_mask |= UART_LSR_OE;
2616 }
2617
2618 /*
2619 * ignore all characters if CREAD is not set
2620 */
2621 if ((termios->c_cflag & CREAD) == 0)
2622 port->ignore_status_mask |= UART_LSR_DR;
2623
2624 /*
2625 * CTS flow control flag and modem status interrupts
2626 */
2627 up->ier &= ~UART_IER_MSI;
2628 if (!(up->bugs & UART_BUG_NOMSR) &&
2629 UART_ENABLE_MS(&up->port, termios->c_cflag))
2630 up->ier |= UART_IER_MSI;
2631 if (up->capabilities & UART_CAP_UUE)
2632 up->ier |= UART_IER_UUE;
2633 if (up->capabilities & UART_CAP_RTOIE)
2634 up->ier |= UART_IER_RTOIE;
2635
2636 serial_port_out(port, UART_IER, up->ier);
2637
2638 if (up->capabilities & UART_CAP_EFR) {
2639 unsigned char efr = 0;
2640 /*
2641 * TI16C752/Startech hardware flow control. FIXME:
2642 * - TI16C752 requires control thresholds to be set.
2643 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2644 */
2645 if (termios->c_cflag & CRTSCTS)
2646 efr |= UART_EFR_CTS;
2647
2648 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2649 if (port->flags & UPF_EXAR_EFR)
2650 serial_port_out(port, UART_XR_EFR, efr);
2651 else
2652 serial_port_out(port, UART_EFR, efr);
2653 }
2654
2655 serial8250_set_divisor(port, baud, quot, frac);
2656
2657 /*
2658 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2659 * is written without DLAB set, this mode will be disabled.
2660 */
2661 if (port->type == PORT_16750)
2662 serial_port_out(port, UART_FCR, up->fcr);
2663
2664 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2665 if (port->type != PORT_16750) {
2666 /* emulated UARTs (Lucent Venus 167x) need two steps */
2667 if (up->fcr & UART_FCR_ENABLE_FIFO)
2668 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2669 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2670 }
2671 serial8250_set_mctrl(port, port->mctrl);
2672 spin_unlock_irqrestore(&port->lock, flags);
2673 serial8250_rpm_put(up);
2674
2675 /* Don't rewrite B0 */
2676 if (tty_termios_baud_rate(termios))
2677 tty_termios_encode_baud_rate(termios, baud, baud);
2678 }
2679 EXPORT_SYMBOL(serial8250_do_set_termios);
2680
2681 static void
2682 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2683 struct ktermios *old)
2684 {
2685 if (port->set_termios)
2686 port->set_termios(port, termios, old);
2687 else
2688 serial8250_do_set_termios(port, termios, old);
2689 }
2690
2691 static void
2692 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2693 {
2694 if (termios->c_line == N_PPS) {
2695 port->flags |= UPF_HARDPPS_CD;
2696 spin_lock_irq(&port->lock);
2697 serial8250_enable_ms(port);
2698 spin_unlock_irq(&port->lock);
2699 } else {
2700 port->flags &= ~UPF_HARDPPS_CD;
2701 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2702 spin_lock_irq(&port->lock);
2703 serial8250_disable_ms(port);
2704 spin_unlock_irq(&port->lock);
2705 }
2706 }
2707 }
2708
2709
2710 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2711 unsigned int oldstate)
2712 {
2713 struct uart_8250_port *p = up_to_u8250p(port);
2714
2715 serial8250_set_sleep(p, state != 0);
2716 }
2717 EXPORT_SYMBOL(serial8250_do_pm);
2718
2719 static void
2720 serial8250_pm(struct uart_port *port, unsigned int state,
2721 unsigned int oldstate)
2722 {
2723 if (port->pm)
2724 port->pm(port, state, oldstate);
2725 else
2726 serial8250_do_pm(port, state, oldstate);
2727 }
2728
2729 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2730 {
2731 if (pt->port.mapsize)
2732 return pt->port.mapsize;
2733 if (pt->port.iotype == UPIO_AU) {
2734 if (pt->port.type == PORT_RT2880)
2735 return 0x100;
2736 return 0x1000;
2737 }
2738 if (is_omap1_8250(pt))
2739 return 0x16 << pt->port.regshift;
2740
2741 return 8 << pt->port.regshift;
2742 }
2743
2744 /*
2745 * Resource handling.
2746 */
2747 static int serial8250_request_std_resource(struct uart_8250_port *up)
2748 {
2749 unsigned int size = serial8250_port_size(up);
2750 struct uart_port *port = &up->port;
2751 int ret = 0;
2752
2753 switch (port->iotype) {
2754 case UPIO_AU:
2755 case UPIO_TSI:
2756 case UPIO_MEM32:
2757 case UPIO_MEM32BE:
2758 case UPIO_MEM:
2759 if (!port->mapbase)
2760 break;
2761
2762 if (!request_mem_region(port->mapbase, size, "serial")) {
2763 ret = -EBUSY;
2764 break;
2765 }
2766
2767 if (port->flags & UPF_IOREMAP) {
2768 port->membase = ioremap_nocache(port->mapbase, size);
2769 if (!port->membase) {
2770 release_mem_region(port->mapbase, size);
2771 ret = -ENOMEM;
2772 }
2773 }
2774 break;
2775
2776 case UPIO_HUB6:
2777 case UPIO_PORT:
2778 if (!request_region(port->iobase, size, "serial"))
2779 ret = -EBUSY;
2780 break;
2781 }
2782 return ret;
2783 }
2784
2785 static void serial8250_release_std_resource(struct uart_8250_port *up)
2786 {
2787 unsigned int size = serial8250_port_size(up);
2788 struct uart_port *port = &up->port;
2789
2790 switch (port->iotype) {
2791 case UPIO_AU:
2792 case UPIO_TSI:
2793 case UPIO_MEM32:
2794 case UPIO_MEM32BE:
2795 case UPIO_MEM:
2796 if (!port->mapbase)
2797 break;
2798
2799 if (port->flags & UPF_IOREMAP) {
2800 iounmap(port->membase);
2801 port->membase = NULL;
2802 }
2803
2804 release_mem_region(port->mapbase, size);
2805 break;
2806
2807 case UPIO_HUB6:
2808 case UPIO_PORT:
2809 release_region(port->iobase, size);
2810 break;
2811 }
2812 }
2813
2814 #ifdef CONFIG_SERIAL_8250_RSA
2815 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2816 {
2817 unsigned long start = UART_RSA_BASE << up->port.regshift;
2818 unsigned int size = 8 << up->port.regshift;
2819 struct uart_port *port = &up->port;
2820 int ret = -EINVAL;
2821
2822 switch (port->iotype) {
2823 case UPIO_HUB6:
2824 case UPIO_PORT:
2825 start += port->iobase;
2826 if (request_region(start, size, "serial-rsa"))
2827 ret = 0;
2828 else
2829 ret = -EBUSY;
2830 break;
2831 }
2832
2833 return ret;
2834 }
2835
2836 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2837 {
2838 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2839 unsigned int size = 8 << up->port.regshift;
2840 struct uart_port *port = &up->port;
2841
2842 switch (port->iotype) {
2843 case UPIO_HUB6:
2844 case UPIO_PORT:
2845 release_region(port->iobase + offset, size);
2846 break;
2847 }
2848 }
2849 #endif
2850
2851 static void serial8250_release_port(struct uart_port *port)
2852 {
2853 struct uart_8250_port *up = up_to_u8250p(port);
2854
2855 serial8250_release_std_resource(up);
2856 }
2857
2858 static int serial8250_request_port(struct uart_port *port)
2859 {
2860 struct uart_8250_port *up = up_to_u8250p(port);
2861 int ret;
2862
2863 if (port->type == PORT_8250_CIR)
2864 return -ENODEV;
2865
2866 ret = serial8250_request_std_resource(up);
2867
2868 return ret;
2869 }
2870
2871 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2872 {
2873 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2874 unsigned char bytes;
2875
2876 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2877
2878 return bytes ? bytes : -EOPNOTSUPP;
2879 }
2880
2881 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2882 {
2883 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2884 int i;
2885
2886 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2887 return -EOPNOTSUPP;
2888
2889 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2890 if (bytes < conf_type->rxtrig_bytes[i])
2891 /* Use the nearest lower value */
2892 return (--i) << UART_FCR_R_TRIG_SHIFT;
2893 }
2894
2895 return UART_FCR_R_TRIG_11;
2896 }
2897
2898 static int do_get_rxtrig(struct tty_port *port)
2899 {
2900 struct uart_state *state = container_of(port, struct uart_state, port);
2901 struct uart_port *uport = state->uart_port;
2902 struct uart_8250_port *up =
2903 container_of(uport, struct uart_8250_port, port);
2904
2905 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2906 return -EINVAL;
2907
2908 return fcr_get_rxtrig_bytes(up);
2909 }
2910
2911 static int do_serial8250_get_rxtrig(struct tty_port *port)
2912 {
2913 int rxtrig_bytes;
2914
2915 mutex_lock(&port->mutex);
2916 rxtrig_bytes = do_get_rxtrig(port);
2917 mutex_unlock(&port->mutex);
2918
2919 return rxtrig_bytes;
2920 }
2921
2922 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2923 struct device_attribute *attr, char *buf)
2924 {
2925 struct tty_port *port = dev_get_drvdata(dev);
2926 int rxtrig_bytes;
2927
2928 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2929 if (rxtrig_bytes < 0)
2930 return rxtrig_bytes;
2931
2932 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2933 }
2934
2935 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2936 {
2937 struct uart_state *state = container_of(port, struct uart_state, port);
2938 struct uart_port *uport = state->uart_port;
2939 struct uart_8250_port *up =
2940 container_of(uport, struct uart_8250_port, port);
2941 int rxtrig;
2942
2943 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2944 up->fifo_bug)
2945 return -EINVAL;
2946
2947 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2948 if (rxtrig < 0)
2949 return rxtrig;
2950
2951 serial8250_clear_fifos(up);
2952 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2953 up->fcr |= (unsigned char)rxtrig;
2954 serial_out(up, UART_FCR, up->fcr);
2955 return 0;
2956 }
2957
2958 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2959 {
2960 int ret;
2961
2962 mutex_lock(&port->mutex);
2963 ret = do_set_rxtrig(port, bytes);
2964 mutex_unlock(&port->mutex);
2965
2966 return ret;
2967 }
2968
2969 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2970 struct device_attribute *attr, const char *buf, size_t count)
2971 {
2972 struct tty_port *port = dev_get_drvdata(dev);
2973 unsigned char bytes;
2974 int ret;
2975
2976 if (!count)
2977 return -EINVAL;
2978
2979 ret = kstrtou8(buf, 10, &bytes);
2980 if (ret < 0)
2981 return ret;
2982
2983 ret = do_serial8250_set_rxtrig(port, bytes);
2984 if (ret < 0)
2985 return ret;
2986
2987 return count;
2988 }
2989
2990 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2991 serial8250_get_attr_rx_trig_bytes,
2992 serial8250_set_attr_rx_trig_bytes);
2993
2994 static struct attribute *serial8250_dev_attrs[] = {
2995 &dev_attr_rx_trig_bytes.attr,
2996 NULL,
2997 };
2998
2999 static struct attribute_group serial8250_dev_attr_group = {
3000 .attrs = serial8250_dev_attrs,
3001 };
3002
3003 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3004 {
3005 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3006
3007 if (conf_type->rxtrig_bytes[0])
3008 up->port.attr_group = &serial8250_dev_attr_group;
3009 }
3010
3011 static void serial8250_config_port(struct uart_port *port, int flags)
3012 {
3013 struct uart_8250_port *up = up_to_u8250p(port);
3014 int ret;
3015
3016 if (port->type == PORT_8250_CIR)
3017 return;
3018
3019 /*
3020 * Find the region that we can probe for. This in turn
3021 * tells us whether we can probe for the type of port.
3022 */
3023 ret = serial8250_request_std_resource(up);
3024 if (ret < 0)
3025 return;
3026
3027 if (port->iotype != up->cur_iotype)
3028 set_io_from_upio(port);
3029
3030 if (flags & UART_CONFIG_TYPE)
3031 autoconfig(up);
3032
3033 /* if access method is AU, it is a 16550 with a quirk */
3034 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3035 up->bugs |= UART_BUG_NOMSR;
3036
3037 /* HW bugs may trigger IRQ while IIR == NO_INT */
3038 if (port->type == PORT_TEGRA)
3039 up->bugs |= UART_BUG_NOMSR;
3040
3041 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3042 autoconfig_irq(up);
3043
3044 if (port->type == PORT_UNKNOWN)
3045 serial8250_release_std_resource(up);
3046
3047 /* Fixme: probably not the best place for this */
3048 if ((port->type == PORT_XR17V35X) ||
3049 (port->type == PORT_XR17D15X))
3050 port->handle_irq = exar_handle_irq;
3051
3052 register_dev_spec_attr_grp(up);
3053 up->fcr = uart_config[up->port.type].fcr;
3054 }
3055
3056 static int
3057 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3058 {
3059 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3060 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3061 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3062 ser->type == PORT_STARTECH)
3063 return -EINVAL;
3064 return 0;
3065 }
3066
3067 static const char *
3068 serial8250_type(struct uart_port *port)
3069 {
3070 int type = port->type;
3071
3072 if (type >= ARRAY_SIZE(uart_config))
3073 type = 0;
3074 return uart_config[type].name;
3075 }
3076
3077 static const struct uart_ops serial8250_pops = {
3078 .tx_empty = serial8250_tx_empty,
3079 .set_mctrl = serial8250_set_mctrl,
3080 .get_mctrl = serial8250_get_mctrl,
3081 .stop_tx = serial8250_stop_tx,
3082 .start_tx = serial8250_start_tx,
3083 .throttle = serial8250_throttle,
3084 .unthrottle = serial8250_unthrottle,
3085 .stop_rx = serial8250_stop_rx,
3086 .enable_ms = serial8250_enable_ms,
3087 .break_ctl = serial8250_break_ctl,
3088 .startup = serial8250_startup,
3089 .shutdown = serial8250_shutdown,
3090 .set_termios = serial8250_set_termios,
3091 .set_ldisc = serial8250_set_ldisc,
3092 .pm = serial8250_pm,
3093 .type = serial8250_type,
3094 .release_port = serial8250_release_port,
3095 .request_port = serial8250_request_port,
3096 .config_port = serial8250_config_port,
3097 .verify_port = serial8250_verify_port,
3098 #ifdef CONFIG_CONSOLE_POLL
3099 .poll_get_char = serial8250_get_poll_char,
3100 .poll_put_char = serial8250_put_poll_char,
3101 #endif
3102 };
3103
3104 static const struct uart_ops *base_ops;
3105 static struct uart_ops univ8250_port_ops;
3106
3107 static const struct uart_8250_ops univ8250_driver_ops = {
3108 .setup_irq = univ8250_setup_irq,
3109 .release_irq = univ8250_release_irq,
3110 };
3111
3112 static struct uart_8250_port serial8250_ports[UART_NR];
3113
3114 /**
3115 * serial8250_get_port - retrieve struct uart_8250_port
3116 * @line: serial line number
3117 *
3118 * This function retrieves struct uart_8250_port for the specific line.
3119 * This struct *must* *not* be used to perform a 8250 or serial core operation
3120 * which is not accessible otherwise. Its only purpose is to make the struct
3121 * accessible to the runtime-pm callbacks for context suspend/restore.
3122 * The lock assumption made here is none because runtime-pm suspend/resume
3123 * callbacks should not be invoked if there is any operation performed on the
3124 * port.
3125 */
3126 struct uart_8250_port *serial8250_get_port(int line)
3127 {
3128 return &serial8250_ports[line];
3129 }
3130 EXPORT_SYMBOL_GPL(serial8250_get_port);
3131
3132 static void (*serial8250_isa_config)(int port, struct uart_port *up,
3133 unsigned short *capabilities);
3134
3135 void serial8250_set_isa_configurator(
3136 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
3137 {
3138 serial8250_isa_config = v;
3139 }
3140 EXPORT_SYMBOL(serial8250_set_isa_configurator);
3141
3142 static void serial8250_init_port(struct uart_8250_port *up)
3143 {
3144 struct uart_port *port = &up->port;
3145
3146 spin_lock_init(&port->lock);
3147 port->ops = &serial8250_pops;
3148
3149 up->cur_iotype = 0xFF;
3150 }
3151
3152 static void serial8250_set_defaults(struct uart_8250_port *up)
3153 {
3154 struct uart_port *port = &up->port;
3155
3156 if (up->port.flags & UPF_FIXED_TYPE) {
3157 unsigned int type = up->port.type;
3158
3159 if (!up->port.fifosize)
3160 up->port.fifosize = uart_config[type].fifo_size;
3161 if (!up->tx_loadsz)
3162 up->tx_loadsz = uart_config[type].tx_loadsz;
3163 if (!up->capabilities)
3164 up->capabilities = uart_config[type].flags;
3165 }
3166
3167 set_io_from_upio(port);
3168
3169 /* default dma handlers */
3170 if (up->dma) {
3171 if (!up->dma->tx_dma)
3172 up->dma->tx_dma = serial8250_tx_dma;
3173 if (!up->dma->rx_dma)
3174 up->dma->rx_dma = serial8250_rx_dma;
3175 }
3176 }
3177
3178 #ifdef CONFIG_SERIAL_8250_RSA
3179
3180 static void univ8250_config_port(struct uart_port *port, int flags)
3181 {
3182 struct uart_8250_port *up = up_to_u8250p(port);
3183
3184 up->probe &= ~UART_PROBE_RSA;
3185 if (port->type == PORT_RSA) {
3186 if (serial8250_request_rsa_resource(up) == 0)
3187 up->probe |= UART_PROBE_RSA;
3188 } else if (flags & UART_CONFIG_TYPE) {
3189 int i;
3190
3191 for (i = 0; i < probe_rsa_count; i++) {
3192 if (probe_rsa[i] == up->port.iobase) {
3193 if (serial8250_request_rsa_resource(up) == 0)
3194 up->probe |= UART_PROBE_RSA;
3195 break;
3196 }
3197 }
3198 }
3199
3200 base_ops->config_port(port, flags);
3201
3202 if (port->type != PORT_RSA && up->probe & UART_PROBE_RSA)
3203 serial8250_release_rsa_resource(up);
3204 }
3205
3206 static int univ8250_request_port(struct uart_port *port)
3207 {
3208 struct uart_8250_port *up = up_to_u8250p(port);
3209 int ret;
3210
3211 ret = base_ops->request_port(port);
3212 if (ret == 0 && port->type == PORT_RSA) {
3213 ret = serial8250_request_rsa_resource(up);
3214 if (ret < 0)
3215 base_ops->release_port(port);
3216 }
3217
3218 return ret;
3219 }
3220
3221 static void univ8250_release_port(struct uart_port *port)
3222 {
3223 struct uart_8250_port *up = up_to_u8250p(port);
3224
3225 if (port->type == PORT_RSA)
3226 serial8250_release_rsa_resource(up);
3227 base_ops->release_port(port);
3228 }
3229
3230 static void univ8250_rsa_support(struct uart_ops *ops)
3231 {
3232 ops->config_port = univ8250_config_port;
3233 ops->request_port = univ8250_request_port;
3234 ops->release_port = univ8250_release_port;
3235 }
3236
3237 #else
3238 #define univ8250_rsa_support(x) do { } while (0)
3239 #endif /* CONFIG_SERIAL_8250_RSA */
3240
3241 static void __init serial8250_isa_init_ports(void)
3242 {
3243 struct uart_8250_port *up;
3244 static int first = 1;
3245 int i, irqflag = 0;
3246
3247 if (!first)
3248 return;
3249 first = 0;
3250
3251 if (nr_uarts > UART_NR)
3252 nr_uarts = UART_NR;
3253
3254 for (i = 0; i < nr_uarts; i++) {
3255 struct uart_8250_port *up = &serial8250_ports[i];
3256 struct uart_port *port = &up->port;
3257
3258 port->line = i;
3259 serial8250_init_port(up);
3260 if (!base_ops)
3261 base_ops = port->ops;
3262 port->ops = &univ8250_port_ops;
3263
3264 init_timer(&up->timer);
3265 up->timer.function = serial8250_timeout;
3266
3267 up->ops = &univ8250_driver_ops;
3268
3269 /*
3270 * ALPHA_KLUDGE_MCR needs to be killed.
3271 */
3272 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
3273 up->mcr_force = ALPHA_KLUDGE_MCR;
3274 }
3275
3276 /* chain base port ops to support Remote Supervisor Adapter */
3277 univ8250_port_ops = *base_ops;
3278 univ8250_rsa_support(&univ8250_port_ops);
3279
3280 if (share_irqs)
3281 irqflag = IRQF_SHARED;
3282
3283 for (i = 0, up = serial8250_ports;
3284 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
3285 i++, up++) {
3286 struct uart_port *port = &up->port;
3287
3288 port->iobase = old_serial_port[i].port;
3289 port->irq = irq_canonicalize(old_serial_port[i].irq);
3290 port->irqflags = old_serial_port[i].irqflags;
3291 port->uartclk = old_serial_port[i].baud_base * 16;
3292 port->flags = old_serial_port[i].flags;
3293 port->hub6 = old_serial_port[i].hub6;
3294 port->membase = old_serial_port[i].iomem_base;
3295 port->iotype = old_serial_port[i].io_type;
3296 port->regshift = old_serial_port[i].iomem_reg_shift;
3297 serial8250_set_defaults(up);
3298
3299 port->irqflags |= irqflag;
3300 if (serial8250_isa_config != NULL)
3301 serial8250_isa_config(i, &up->port, &up->capabilities);
3302 }
3303 }
3304
3305 static void __init
3306 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
3307 {
3308 int i;
3309
3310 for (i = 0; i < nr_uarts; i++) {
3311 struct uart_8250_port *up = &serial8250_ports[i];
3312
3313 if (up->port.dev)
3314 continue;
3315
3316 up->port.dev = dev;
3317
3318 if (skip_txen_test)
3319 up->port.flags |= UPF_NO_TXEN_TEST;
3320
3321 uart_add_one_port(drv, &up->port);
3322 }
3323 }
3324
3325 #ifdef CONFIG_SERIAL_8250_CONSOLE
3326
3327 static void serial8250_console_putchar(struct uart_port *port, int ch)
3328 {
3329 struct uart_8250_port *up = up_to_u8250p(port);
3330
3331 wait_for_xmitr(up, UART_LSR_THRE);
3332 serial_port_out(port, UART_TX, ch);
3333 }
3334
3335 /*
3336 * Print a string to the serial port trying not to disturb
3337 * any possible real use of the port...
3338 *
3339 * The console_lock must be held when we get here.
3340 */
3341 static void serial8250_console_write(struct uart_8250_port *up, const char *s,
3342 unsigned int count)
3343 {
3344 struct uart_port *port = &up->port;
3345 unsigned long flags;
3346 unsigned int ier;
3347 int locked = 1;
3348
3349 touch_nmi_watchdog();
3350
3351 serial8250_rpm_get(up);
3352
3353 if (port->sysrq)
3354 locked = 0;
3355 else if (oops_in_progress)
3356 locked = spin_trylock_irqsave(&port->lock, flags);
3357 else
3358 spin_lock_irqsave(&port->lock, flags);
3359
3360 /*
3361 * First save the IER then disable the interrupts
3362 */
3363 ier = serial_port_in(port, UART_IER);
3364
3365 if (up->capabilities & UART_CAP_UUE)
3366 serial_port_out(port, UART_IER, UART_IER_UUE);
3367 else
3368 serial_port_out(port, UART_IER, 0);
3369
3370 /* check scratch reg to see if port powered off during system sleep */
3371 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3372 struct ktermios termios;
3373 unsigned int baud, quot, frac = 0;
3374
3375 termios.c_cflag = port->cons->cflag;
3376 if (port->state->port.tty && termios.c_cflag == 0)
3377 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3378
3379 baud = uart_get_baud_rate(port, &termios, NULL,
3380 port->uartclk / 16 / 0xffff,
3381 port->uartclk / 16);
3382 quot = serial8250_get_divisor(up, baud, &frac);
3383
3384 serial8250_set_divisor(port, baud, quot, frac);
3385 serial_port_out(port, UART_LCR, up->lcr);
3386 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
3387
3388 up->canary = 0;
3389 }
3390
3391 uart_console_write(port, s, count, serial8250_console_putchar);
3392
3393 /*
3394 * Finally, wait for transmitter to become empty
3395 * and restore the IER
3396 */
3397 wait_for_xmitr(up, BOTH_EMPTY);
3398 serial_port_out(port, UART_IER, ier);
3399
3400 /*
3401 * The receive handling will happen properly because the
3402 * receive ready bit will still be set; it is not cleared
3403 * on read. However, modem control will not, we must
3404 * call it if we have saved something in the saved flags
3405 * while processing with interrupts off.
3406 */
3407 if (up->msr_saved_flags)
3408 serial8250_modem_status(up);
3409
3410 if (locked)
3411 spin_unlock_irqrestore(&port->lock, flags);
3412 serial8250_rpm_put(up);
3413 }
3414
3415 static void univ8250_console_write(struct console *co, const char *s,
3416 unsigned int count)
3417 {
3418 struct uart_8250_port *up = &serial8250_ports[co->index];
3419
3420 serial8250_console_write(up, s, count);
3421 }
3422
3423 static unsigned int probe_baud(struct uart_port *port)
3424 {
3425 unsigned char lcr, dll, dlm;
3426 unsigned int quot;
3427
3428 lcr = serial_port_in(port, UART_LCR);
3429 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3430 dll = serial_port_in(port, UART_DLL);
3431 dlm = serial_port_in(port, UART_DLM);
3432 serial_port_out(port, UART_LCR, lcr);
3433
3434 quot = (dlm << 8) | dll;
3435 return (port->uartclk / 16) / quot;
3436 }
3437
3438 static int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3439 {
3440 int baud = 9600;
3441 int bits = 8;
3442 int parity = 'n';
3443 int flow = 'n';
3444
3445 if (!port->iobase && !port->membase)
3446 return -ENODEV;
3447
3448 if (options)
3449 uart_parse_options(options, &baud, &parity, &bits, &flow);
3450 else if (probe)
3451 baud = probe_baud(port);
3452
3453 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3454 }
3455
3456 static int univ8250_console_setup(struct console *co, char *options)
3457 {
3458 struct uart_port *port;
3459
3460 /*
3461 * Check whether an invalid uart number has been specified, and
3462 * if so, search for the first available port that does have
3463 * console support.
3464 */
3465 if (co->index >= nr_uarts)
3466 co->index = 0;
3467 port = &serial8250_ports[co->index].port;
3468 /* link port to console */
3469 port->cons = co;
3470
3471 return serial8250_console_setup(port, options, false);
3472 }
3473
3474 /**
3475 * univ8250_console_match - non-standard console matching
3476 * @co: registering console
3477 * @name: name from console command line
3478 * @idx: index from console command line
3479 * @options: ptr to option string from console command line
3480 *
3481 * Only attempts to match console command lines of the form:
3482 * console=uart[8250],io|mmio|mmio32,<addr>[,<options>]
3483 * console=uart[8250],0x<addr>[,<options>]
3484 * This form is used to register an initial earlycon boot console and
3485 * replace it with the serial8250_console at 8250 driver init.
3486 *
3487 * Performs console setup for a match (as required by interface)
3488 * If no <options> are specified, then assume the h/w is already setup.
3489 *
3490 * Returns 0 if console matches; otherwise non-zero to use default matching
3491 */
3492 static int univ8250_console_match(struct console *co, char *name, int idx,
3493 char *options)
3494 {
3495 char match[] = "uart"; /* 8250-specific earlycon name */
3496 unsigned char iotype;
3497 unsigned long addr;
3498 int i;
3499
3500 if (strncmp(name, match, 4) != 0)
3501 return -ENODEV;
3502
3503 if (uart_parse_earlycon(options, &iotype, &addr, &options))
3504 return -ENODEV;
3505
3506 /* try to match the port specified on the command line */
3507 for (i = 0; i < nr_uarts; i++) {
3508 struct uart_port *port = &serial8250_ports[i].port;
3509
3510 if (port->iotype != iotype)
3511 continue;
3512 if ((iotype == UPIO_MEM || iotype == UPIO_MEM32) &&
3513 (port->mapbase != addr))
3514 continue;
3515 if (iotype == UPIO_PORT && port->iobase != addr)
3516 continue;
3517
3518 co->index = i;
3519 port->cons = co;
3520 return serial8250_console_setup(port, options, true);
3521 }
3522
3523 return -ENODEV;
3524 }
3525
3526 static struct console univ8250_console = {
3527 .name = "ttyS",
3528 .write = univ8250_console_write,
3529 .device = uart_console_device,
3530 .setup = univ8250_console_setup,
3531 .match = univ8250_console_match,
3532 .flags = CON_PRINTBUFFER | CON_ANYTIME,
3533 .index = -1,
3534 .data = &serial8250_reg,
3535 };
3536
3537 static int __init univ8250_console_init(void)
3538 {
3539 if (nr_uarts == 0)
3540 return -ENODEV;
3541
3542 serial8250_isa_init_ports();
3543 register_console(&univ8250_console);
3544 return 0;
3545 }
3546 console_initcall(univ8250_console_init);
3547
3548 #define SERIAL8250_CONSOLE &univ8250_console
3549 #else
3550 #define SERIAL8250_CONSOLE NULL
3551 #endif
3552
3553 static struct uart_driver serial8250_reg = {
3554 .owner = THIS_MODULE,
3555 .driver_name = "serial",
3556 .dev_name = "ttyS",
3557 .major = TTY_MAJOR,
3558 .minor = 64,
3559 .cons = SERIAL8250_CONSOLE,
3560 };
3561
3562 /*
3563 * early_serial_setup - early registration for 8250 ports
3564 *
3565 * Setup an 8250 port structure prior to console initialisation. Use
3566 * after console initialisation will cause undefined behaviour.
3567 */
3568 int __init early_serial_setup(struct uart_port *port)
3569 {
3570 struct uart_port *p;
3571
3572 if (port->line >= ARRAY_SIZE(serial8250_ports) || nr_uarts == 0)
3573 return -ENODEV;
3574
3575 serial8250_isa_init_ports();
3576 p = &serial8250_ports[port->line].port;
3577 p->iobase = port->iobase;
3578 p->membase = port->membase;
3579 p->irq = port->irq;
3580 p->irqflags = port->irqflags;
3581 p->uartclk = port->uartclk;
3582 p->fifosize = port->fifosize;
3583 p->regshift = port->regshift;
3584 p->iotype = port->iotype;
3585 p->flags = port->flags;
3586 p->mapbase = port->mapbase;
3587 p->mapsize = port->mapsize;
3588 p->private_data = port->private_data;
3589 p->type = port->type;
3590 p->line = port->line;
3591
3592 serial8250_set_defaults(up_to_u8250p(p));
3593
3594 if (port->serial_in)
3595 p->serial_in = port->serial_in;
3596 if (port->serial_out)
3597 p->serial_out = port->serial_out;
3598 if (port->handle_irq)
3599 p->handle_irq = port->handle_irq;
3600
3601 return 0;
3602 }
3603
3604 /**
3605 * serial8250_suspend_port - suspend one serial port
3606 * @line: serial line number
3607 *
3608 * Suspend one serial port.
3609 */
3610 void serial8250_suspend_port(int line)
3611 {
3612 struct uart_8250_port *up = &serial8250_ports[line];
3613 struct uart_port *port = &up->port;
3614
3615 if (!console_suspend_enabled && uart_console(port) &&
3616 port->type != PORT_8250) {
3617 unsigned char canary = 0xa5;
3618 serial_out(up, UART_SCR, canary);
3619 if (serial_in(up, UART_SCR) == canary)
3620 up->canary = canary;
3621 }
3622
3623 uart_suspend_port(&serial8250_reg, port);
3624 }
3625
3626 /**
3627 * serial8250_resume_port - resume one serial port
3628 * @line: serial line number
3629 *
3630 * Resume one serial port.
3631 */
3632 void serial8250_resume_port(int line)
3633 {
3634 struct uart_8250_port *up = &serial8250_ports[line];
3635 struct uart_port *port = &up->port;
3636
3637 up->canary = 0;
3638
3639 if (up->capabilities & UART_NATSEMI) {
3640 /* Ensure it's still in high speed mode */
3641 serial_port_out(port, UART_LCR, 0xE0);
3642
3643 ns16550a_goto_highspeed(up);
3644
3645 serial_port_out(port, UART_LCR, 0);
3646 port->uartclk = 921600*16;
3647 }
3648 uart_resume_port(&serial8250_reg, port);
3649 }
3650
3651 /*
3652 * Register a set of serial devices attached to a platform device. The
3653 * list is terminated with a zero flags entry, which means we expect
3654 * all entries to have at least UPF_BOOT_AUTOCONF set.
3655 */
3656 static int serial8250_probe(struct platform_device *dev)
3657 {
3658 struct plat_serial8250_port *p = dev_get_platdata(&dev->dev);
3659 struct uart_8250_port uart;
3660 int ret, i, irqflag = 0;
3661
3662 memset(&uart, 0, sizeof(uart));
3663
3664 if (share_irqs)
3665 irqflag = IRQF_SHARED;
3666
3667 for (i = 0; p && p->flags != 0; p++, i++) {
3668 uart.port.iobase = p->iobase;
3669 uart.port.membase = p->membase;
3670 uart.port.irq = p->irq;
3671 uart.port.irqflags = p->irqflags;
3672 uart.port.uartclk = p->uartclk;
3673 uart.port.regshift = p->regshift;
3674 uart.port.iotype = p->iotype;
3675 uart.port.flags = p->flags;
3676 uart.port.mapbase = p->mapbase;
3677 uart.port.hub6 = p->hub6;
3678 uart.port.private_data = p->private_data;
3679 uart.port.type = p->type;
3680 uart.port.serial_in = p->serial_in;
3681 uart.port.serial_out = p->serial_out;
3682 uart.port.handle_irq = p->handle_irq;
3683 uart.port.handle_break = p->handle_break;
3684 uart.port.set_termios = p->set_termios;
3685 uart.port.pm = p->pm;
3686 uart.port.dev = &dev->dev;
3687 uart.port.irqflags |= irqflag;
3688 ret = serial8250_register_8250_port(&uart);
3689 if (ret < 0) {
3690 dev_err(&dev->dev, "unable to register port at index %d "
3691 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3692 p->iobase, (unsigned long long)p->mapbase,
3693 p->irq, ret);
3694 }
3695 }
3696 return 0;
3697 }
3698
3699 /*
3700 * Remove serial ports registered against a platform device.
3701 */
3702 static int serial8250_remove(struct platform_device *dev)
3703 {
3704 int i;
3705
3706 for (i = 0; i < nr_uarts; i++) {
3707 struct uart_8250_port *up = &serial8250_ports[i];
3708
3709 if (up->port.dev == &dev->dev)
3710 serial8250_unregister_port(i);
3711 }
3712 return 0;
3713 }
3714
3715 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3716 {
3717 int i;
3718
3719 for (i = 0; i < UART_NR; i++) {
3720 struct uart_8250_port *up = &serial8250_ports[i];
3721
3722 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3723 uart_suspend_port(&serial8250_reg, &up->port);
3724 }
3725
3726 return 0;
3727 }
3728
3729 static int serial8250_resume(struct platform_device *dev)
3730 {
3731 int i;
3732
3733 for (i = 0; i < UART_NR; i++) {
3734 struct uart_8250_port *up = &serial8250_ports[i];
3735
3736 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3737 serial8250_resume_port(i);
3738 }
3739
3740 return 0;
3741 }
3742
3743 static struct platform_driver serial8250_isa_driver = {
3744 .probe = serial8250_probe,
3745 .remove = serial8250_remove,
3746 .suspend = serial8250_suspend,
3747 .resume = serial8250_resume,
3748 .driver = {
3749 .name = "serial8250",
3750 },
3751 };
3752
3753 /*
3754 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3755 * in the table in include/asm/serial.h
3756 */
3757 static struct platform_device *serial8250_isa_devs;
3758
3759 /*
3760 * serial8250_register_8250_port and serial8250_unregister_port allows for
3761 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3762 * modems and PCI multiport cards.
3763 */
3764 static DEFINE_MUTEX(serial_mutex);
3765
3766 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3767 {
3768 int i;
3769
3770 /*
3771 * First, find a port entry which matches.
3772 */
3773 for (i = 0; i < nr_uarts; i++)
3774 if (uart_match_port(&serial8250_ports[i].port, port))
3775 return &serial8250_ports[i];
3776
3777 /* try line number first if still available */
3778 i = port->line;
3779 if (i < nr_uarts && serial8250_ports[i].port.type == PORT_UNKNOWN &&
3780 serial8250_ports[i].port.iobase == 0)
3781 return &serial8250_ports[i];
3782 /*
3783 * We didn't find a matching entry, so look for the first
3784 * free entry. We look for one which hasn't been previously
3785 * used (indicated by zero iobase).
3786 */
3787 for (i = 0; i < nr_uarts; i++)
3788 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3789 serial8250_ports[i].port.iobase == 0)
3790 return &serial8250_ports[i];
3791
3792 /*
3793 * That also failed. Last resort is to find any entry which
3794 * doesn't have a real port associated with it.
3795 */
3796 for (i = 0; i < nr_uarts; i++)
3797 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3798 return &serial8250_ports[i];
3799
3800 return NULL;
3801 }
3802
3803 /**
3804 * serial8250_register_8250_port - register a serial port
3805 * @up: serial port template
3806 *
3807 * Configure the serial port specified by the request. If the
3808 * port exists and is in use, it is hung up and unregistered
3809 * first.
3810 *
3811 * The port is then probed and if necessary the IRQ is autodetected
3812 * If this fails an error is returned.
3813 *
3814 * On success the port is ready to use and the line number is returned.
3815 */
3816 int serial8250_register_8250_port(struct uart_8250_port *up)
3817 {
3818 struct uart_8250_port *uart;
3819 int ret = -ENOSPC;
3820
3821 if (up->port.uartclk == 0)
3822 return -EINVAL;
3823
3824 mutex_lock(&serial_mutex);
3825
3826 uart = serial8250_find_match_or_unused(&up->port);
3827 if (uart && uart->port.type != PORT_8250_CIR) {
3828 if (uart->port.dev)
3829 uart_remove_one_port(&serial8250_reg, &uart->port);
3830
3831 uart->port.iobase = up->port.iobase;
3832 uart->port.membase = up->port.membase;
3833 uart->port.irq = up->port.irq;
3834 uart->port.irqflags = up->port.irqflags;
3835 uart->port.uartclk = up->port.uartclk;
3836 uart->port.fifosize = up->port.fifosize;
3837 uart->port.regshift = up->port.regshift;
3838 uart->port.iotype = up->port.iotype;
3839 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
3840 uart->bugs = up->bugs;
3841 uart->port.mapbase = up->port.mapbase;
3842 uart->port.mapsize = up->port.mapsize;
3843 uart->port.private_data = up->port.private_data;
3844 uart->tx_loadsz = up->tx_loadsz;
3845 uart->capabilities = up->capabilities;
3846 uart->port.throttle = up->port.throttle;
3847 uart->port.unthrottle = up->port.unthrottle;
3848 uart->port.rs485_config = up->port.rs485_config;
3849 uart->port.rs485 = up->port.rs485;
3850 uart->dma = up->dma;
3851
3852 /* Take tx_loadsz from fifosize if it wasn't set separately */
3853 if (uart->port.fifosize && !uart->tx_loadsz)
3854 uart->tx_loadsz = uart->port.fifosize;
3855
3856 if (up->port.dev)
3857 uart->port.dev = up->port.dev;
3858
3859 if (skip_txen_test)
3860 uart->port.flags |= UPF_NO_TXEN_TEST;
3861
3862 if (up->port.flags & UPF_FIXED_TYPE)
3863 uart->port.type = up->port.type;
3864
3865 serial8250_set_defaults(uart);
3866
3867 /* Possibly override default I/O functions. */
3868 if (up->port.serial_in)
3869 uart->port.serial_in = up->port.serial_in;
3870 if (up->port.serial_out)
3871 uart->port.serial_out = up->port.serial_out;
3872 if (up->port.handle_irq)
3873 uart->port.handle_irq = up->port.handle_irq;
3874 /* Possibly override set_termios call */
3875 if (up->port.set_termios)
3876 uart->port.set_termios = up->port.set_termios;
3877 if (up->port.set_mctrl)
3878 uart->port.set_mctrl = up->port.set_mctrl;
3879 if (up->port.startup)
3880 uart->port.startup = up->port.startup;
3881 if (up->port.shutdown)
3882 uart->port.shutdown = up->port.shutdown;
3883 if (up->port.pm)
3884 uart->port.pm = up->port.pm;
3885 if (up->port.handle_break)
3886 uart->port.handle_break = up->port.handle_break;
3887 if (up->dl_read)
3888 uart->dl_read = up->dl_read;
3889 if (up->dl_write)
3890 uart->dl_write = up->dl_write;
3891
3892 if (serial8250_isa_config != NULL)
3893 serial8250_isa_config(0, &uart->port,
3894 &uart->capabilities);
3895
3896 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3897 if (ret == 0)
3898 ret = uart->port.line;
3899 }
3900 mutex_unlock(&serial_mutex);
3901
3902 return ret;
3903 }
3904 EXPORT_SYMBOL(serial8250_register_8250_port);
3905
3906 /**
3907 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3908 * @line: serial line number
3909 *
3910 * Remove one serial port. This may not be called from interrupt
3911 * context. We hand the port back to the our control.
3912 */
3913 void serial8250_unregister_port(int line)
3914 {
3915 struct uart_8250_port *uart = &serial8250_ports[line];
3916
3917 mutex_lock(&serial_mutex);
3918 uart_remove_one_port(&serial8250_reg, &uart->port);
3919 if (serial8250_isa_devs) {
3920 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3921 if (skip_txen_test)
3922 uart->port.flags |= UPF_NO_TXEN_TEST;
3923 uart->port.type = PORT_UNKNOWN;
3924 uart->port.dev = &serial8250_isa_devs->dev;
3925 uart->capabilities = 0;
3926 uart_add_one_port(&serial8250_reg, &uart->port);
3927 } else {
3928 uart->port.dev = NULL;
3929 }
3930 mutex_unlock(&serial_mutex);
3931 }
3932 EXPORT_SYMBOL(serial8250_unregister_port);
3933
3934 static int __init serial8250_init(void)
3935 {
3936 int ret;
3937
3938 if (nr_uarts == 0)
3939 return -ENODEV;
3940
3941 serial8250_isa_init_ports();
3942
3943 printk(KERN_INFO "Serial: 8250/16550 driver, "
3944 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3945 share_irqs ? "en" : "dis");
3946
3947 #ifdef CONFIG_SPARC
3948 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3949 #else
3950 serial8250_reg.nr = UART_NR;
3951 ret = uart_register_driver(&serial8250_reg);
3952 #endif
3953 if (ret)
3954 goto out;
3955
3956 ret = serial8250_pnp_init();
3957 if (ret)
3958 goto unreg_uart_drv;
3959
3960 serial8250_isa_devs = platform_device_alloc("serial8250",
3961 PLAT8250_DEV_LEGACY);
3962 if (!serial8250_isa_devs) {
3963 ret = -ENOMEM;
3964 goto unreg_pnp;
3965 }
3966
3967 ret = platform_device_add(serial8250_isa_devs);
3968 if (ret)
3969 goto put_dev;
3970
3971 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3972
3973 ret = platform_driver_register(&serial8250_isa_driver);
3974 if (ret == 0)
3975 goto out;
3976
3977 platform_device_del(serial8250_isa_devs);
3978 put_dev:
3979 platform_device_put(serial8250_isa_devs);
3980 unreg_pnp:
3981 serial8250_pnp_exit();
3982 unreg_uart_drv:
3983 #ifdef CONFIG_SPARC
3984 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3985 #else
3986 uart_unregister_driver(&serial8250_reg);
3987 #endif
3988 out:
3989 return ret;
3990 }
3991
3992 static void __exit serial8250_exit(void)
3993 {
3994 struct platform_device *isa_dev = serial8250_isa_devs;
3995
3996 /*
3997 * This tells serial8250_unregister_port() not to re-register
3998 * the ports (thereby making serial8250_isa_driver permanently
3999 * in use.)
4000 */
4001 serial8250_isa_devs = NULL;
4002
4003 platform_driver_unregister(&serial8250_isa_driver);
4004 platform_device_unregister(isa_dev);
4005
4006 serial8250_pnp_exit();
4007
4008 #ifdef CONFIG_SPARC
4009 sunserial_unregister_minors(&serial8250_reg, UART_NR);
4010 #else
4011 uart_unregister_driver(&serial8250_reg);
4012 #endif
4013 }
4014
4015 module_init(serial8250_init);
4016 module_exit(serial8250_exit);
4017
4018 EXPORT_SYMBOL(serial8250_suspend_port);
4019 EXPORT_SYMBOL(serial8250_resume_port);
4020
4021 MODULE_LICENSE("GPL");
4022 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
4023
4024 module_param(share_irqs, uint, 0644);
4025 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
4026 " (unsafe)");
4027
4028 module_param(nr_uarts, uint, 0644);
4029 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
4030
4031 module_param(skip_txen_test, uint, 0644);
4032 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
4033
4034 #ifdef CONFIG_SERIAL_8250_RSA
4035 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
4036 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
4037 #endif
4038 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
4039
4040 #ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS
4041 #ifndef MODULE
4042 /* This module was renamed to 8250_core in 3.7. Keep the old "8250" name
4043 * working as well for the module options so we don't break people. We
4044 * need to keep the names identical and the convenient macros will happily
4045 * refuse to let us do that by failing the build with redefinition errors
4046 * of global variables. So we stick them inside a dummy function to avoid
4047 * those conflicts. The options still get parsed, and the redefined
4048 * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive.
4049 *
4050 * This is hacky. I'm sorry.
4051 */
4052 static void __used s8250_options(void)
4053 {
4054 #undef MODULE_PARAM_PREFIX
4055 #define MODULE_PARAM_PREFIX "8250_core."
4056
4057 module_param_cb(share_irqs, &param_ops_uint, &share_irqs, 0644);
4058 module_param_cb(nr_uarts, &param_ops_uint, &nr_uarts, 0644);
4059 module_param_cb(skip_txen_test, &param_ops_uint, &skip_txen_test, 0644);
4060 #ifdef CONFIG_SERIAL_8250_RSA
4061 __module_param_call(MODULE_PARAM_PREFIX, probe_rsa,
4062 &param_array_ops, .arr = &__param_arr_probe_rsa,
4063 0444, -1, 0);
4064 #endif
4065 }
4066 #else
4067 MODULE_ALIAS("8250_core");
4068 #endif
4069 #endif
Linux with added FPC-III support