?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: ep93xx: move timer to its own file
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250_pci.c
blobe55f18b93fe7e7334dce31ebab7e43aac1ad493e
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #undef DEBUG
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24 #include <linux/rational.h>
25
26 #include <asm/byteorder.h>
27 #include <asm/io.h>
28
29 #include <linux/dmaengine.h>
30 #include <linux/platform_data/dma-dw.h>
31 #include <linux/platform_data/dma-hsu.h>
32
33 #include "8250.h"
34
35 /*
36 * init function returns:
37 * > 0 - number of ports
38 * = 0 - use board->num_ports
39 * < 0 - error
40 */
41 struct pci_serial_quirk {
42 u32 vendor;
43 u32 device;
44 u32 subvendor;
45 u32 subdevice;
46 int (*probe)(struct pci_dev *dev);
47 int (*init)(struct pci_dev *dev);
48 int (*setup)(struct serial_private *,
49 const struct pciserial_board *,
50 struct uart_8250_port *, int);
51 void (*exit)(struct pci_dev *dev);
52 };
53
54 #define PCI_NUM_BAR_RESOURCES 6
55
56 struct serial_private {
57 struct pci_dev *dev;
58 unsigned int nr;
59 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
60 struct pci_serial_quirk *quirk;
61 int line[0];
62 };
63
64 static int pci_default_setup(struct serial_private*,
65 const struct pciserial_board*, struct uart_8250_port *, int);
66
67 static void moan_device(const char *str, struct pci_dev *dev)
68 {
69 dev_err(&dev->dev,
70 "%s: %s\n"
71 "Please send the output of lspci -vv, this\n"
72 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
73 "manufacturer and name of serial board or\n"
74 "modem board to <linux-serial@vger.kernel.org>.\n",
75 pci_name(dev), str, dev->vendor, dev->device,
76 dev->subsystem_vendor, dev->subsystem_device);
77 }
78
79 static int
80 setup_port(struct serial_private *priv, struct uart_8250_port *port,
81 int bar, int offset, int regshift)
82 {
83 struct pci_dev *dev = priv->dev;
84
85 if (bar >= PCI_NUM_BAR_RESOURCES)
86 return -EINVAL;
87
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
94 port->port.iotype = UPIO_MEM;
95 port->port.iobase = 0;
96 port->port.mapbase = pci_resource_start(dev, bar) + offset;
97 port->port.membase = priv->remapped_bar[bar] + offset;
98 port->port.regshift = regshift;
99 } else {
100 port->port.iotype = UPIO_PORT;
101 port->port.iobase = pci_resource_start(dev, bar) + offset;
102 port->port.mapbase = 0;
103 port->port.membase = NULL;
104 port->port.regshift = 0;
105 }
106 return 0;
107 }
108
109 /*
110 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 */
112 static int addidata_apci7800_setup(struct serial_private *priv,
113 const struct pciserial_board *board,
114 struct uart_8250_port *port, int idx)
115 {
116 unsigned int bar = 0, offset = board->first_offset;
117 bar = FL_GET_BASE(board->flags);
118
119 if (idx < 2) {
120 offset += idx * board->uart_offset;
121 } else if ((idx >= 2) && (idx < 4)) {
122 bar += 1;
123 offset += ((idx - 2) * board->uart_offset);
124 } else if ((idx >= 4) && (idx < 6)) {
125 bar += 2;
126 offset += ((idx - 4) * board->uart_offset);
127 } else if (idx >= 6) {
128 bar += 3;
129 offset += ((idx - 6) * board->uart_offset);
130 }
131
132 return setup_port(priv, port, bar, offset, board->reg_shift);
133 }
134
135 /*
136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
138 */
139 static int
140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
141 struct uart_8250_port *port, int idx)
142 {
143 unsigned int bar, offset = board->first_offset;
144
145 bar = FL_GET_BASE(board->flags);
146 if (idx < 4)
147 bar += idx;
148 else {
149 bar = 4;
150 offset += (idx - 4) * board->uart_offset;
151 }
152
153 return setup_port(priv, port, bar, offset, board->reg_shift);
154 }
155
156 /*
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
162 */
163 static int pci_hp_diva_init(struct pci_dev *dev)
164 {
165 int rc = 0;
166
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 rc = 3;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 rc = 2;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 rc = 4;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
182 rc = 1;
183 break;
184 }
185
186 return rc;
187 }
188
189 /*
190 * HP's Diva chip puts the 4th/5th serial port further out, and
191 * some serial ports are supposed to be hidden on certain models.
192 */
193 static int
194 pci_hp_diva_setup(struct serial_private *priv,
195 const struct pciserial_board *board,
196 struct uart_8250_port *port, int idx)
197 {
198 unsigned int offset = board->first_offset;
199 unsigned int bar = FL_GET_BASE(board->flags);
200
201 switch (priv->dev->subsystem_device) {
202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
203 if (idx == 3)
204 idx++;
205 break;
206 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
207 if (idx > 0)
208 idx++;
209 if (idx > 2)
210 idx++;
211 break;
212 }
213 if (idx > 2)
214 offset = 0x18;
215
216 offset += idx * board->uart_offset;
217
218 return setup_port(priv, port, bar, offset, board->reg_shift);
219 }
220
221 /*
222 * Added for EKF Intel i960 serial boards
223 */
224 static int pci_inteli960ni_init(struct pci_dev *dev)
225 {
226 u32 oldval;
227
228 if (!(dev->subsystem_device & 0x1000))
229 return -ENODEV;
230
231 /* is firmware started? */
232 pci_read_config_dword(dev, 0x44, &oldval);
233 if (oldval == 0x00001000L) { /* RESET value */
234 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
235 return -ENODEV;
236 }
237 return 0;
238 }
239
240 /*
241 * Some PCI serial cards using the PLX 9050 PCI interface chip require
242 * that the card interrupt be explicitly enabled or disabled. This
243 * seems to be mainly needed on card using the PLX which also use I/O
244 * mapped memory.
245 */
246 static int pci_plx9050_init(struct pci_dev *dev)
247 {
248 u8 irq_config;
249 void __iomem *p;
250
251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
252 moan_device("no memory in bar 0", dev);
253 return 0;
254 }
255
256 irq_config = 0x41;
257 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
259 irq_config = 0x43;
260
261 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
263 /*
264 * As the megawolf cards have the int pins active
265 * high, and have 2 UART chips, both ints must be
266 * enabled on the 9050. Also, the UARTS are set in
267 * 16450 mode by default, so we have to enable the
268 * 16C950 'enhanced' mode so that we can use the
269 * deep FIFOs
270 */
271 irq_config = 0x5b;
272 /*
273 * enable/disable interrupts
274 */
275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
276 if (p == NULL)
277 return -ENOMEM;
278 writel(irq_config, p + 0x4c);
279
280 /*
281 * Read the register back to ensure that it took effect.
282 */
283 readl(p + 0x4c);
284 iounmap(p);
285
286 return 0;
287 }
288
289 static void pci_plx9050_exit(struct pci_dev *dev)
290 {
291 u8 __iomem *p;
292
293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
294 return;
295
296 /*
297 * disable interrupts
298 */
299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
300 if (p != NULL) {
301 writel(0, p + 0x4c);
302
303 /*
304 * Read the register back to ensure that it took effect.
305 */
306 readl(p + 0x4c);
307 iounmap(p);
308 }
309 }
310
311 #define NI8420_INT_ENABLE_REG 0x38
312 #define NI8420_INT_ENABLE_BIT 0x2000
313
314 static void pci_ni8420_exit(struct pci_dev *dev)
315 {
316 void __iomem *p;
317 unsigned int bar = 0;
318
319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar", dev);
321 return;
322 }
323
324 p = pci_ioremap_bar(dev, bar);
325 if (p == NULL)
326 return;
327
328 /* Disable the CPU Interrupt */
329 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
330 p + NI8420_INT_ENABLE_REG);
331 iounmap(p);
332 }
333
334
335 /* MITE registers */
336 #define MITE_IOWBSR1 0xc4
337 #define MITE_IOWCR1 0xf4
338 #define MITE_LCIMR1 0x08
339 #define MITE_LCIMR2 0x10
340
341 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342
343 static void pci_ni8430_exit(struct pci_dev *dev)
344 {
345 void __iomem *p;
346 unsigned int bar = 0;
347
348 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
349 moan_device("no memory in bar", dev);
350 return;
351 }
352
353 p = pci_ioremap_bar(dev, bar);
354 if (p == NULL)
355 return;
356
357 /* Disable the CPU Interrupt */
358 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
359 iounmap(p);
360 }
361
362 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
363 static int
364 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
365 struct uart_8250_port *port, int idx)
366 {
367 unsigned int bar, offset = board->first_offset;
368
369 bar = 0;
370
371 if (idx < 4) {
372 /* first four channels map to 0, 0x100, 0x200, 0x300 */
373 offset += idx * board->uart_offset;
374 } else if (idx < 8) {
375 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
376 offset += idx * board->uart_offset + 0xC00;
377 } else /* we have only 8 ports on PMC-OCTALPRO */
378 return 1;
379
380 return setup_port(priv, port, bar, offset, board->reg_shift);
381 }
382
383 /*
384 * This does initialization for PMC OCTALPRO cards:
385 * maps the device memory, resets the UARTs (needed, bc
386 * if the module is removed and inserted again, the card
387 * is in the sleep mode) and enables global interrupt.
388 */
389
390 /* global control register offset for SBS PMC-OctalPro */
391 #define OCT_REG_CR_OFF 0x500
392
393 static int sbs_init(struct pci_dev *dev)
394 {
395 u8 __iomem *p;
396
397 p = pci_ioremap_bar(dev, 0);
398
399 if (p == NULL)
400 return -ENOMEM;
401 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
402 writeb(0x10, p + OCT_REG_CR_OFF);
403 udelay(50);
404 writeb(0x0, p + OCT_REG_CR_OFF);
405
406 /* Set bit-2 (INTENABLE) of Control Register */
407 writeb(0x4, p + OCT_REG_CR_OFF);
408 iounmap(p);
409
410 return 0;
411 }
412
413 /*
414 * Disables the global interrupt of PMC-OctalPro
415 */
416
417 static void sbs_exit(struct pci_dev *dev)
418 {
419 u8 __iomem *p;
420
421 p = pci_ioremap_bar(dev, 0);
422 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
423 if (p != NULL)
424 writeb(0, p + OCT_REG_CR_OFF);
425 iounmap(p);
426 }
427
428 /*
429 * SIIG serial cards have an PCI interface chip which also controls
430 * the UART clocking frequency. Each UART can be clocked independently
431 * (except cards equipped with 4 UARTs) and initial clocking settings
432 * are stored in the EEPROM chip. It can cause problems because this
433 * version of serial driver doesn't support differently clocked UART's
434 * on single PCI card. To prevent this, initialization functions set
435 * high frequency clocking for all UART's on given card. It is safe (I
436 * hope) because it doesn't touch EEPROM settings to prevent conflicts
437 * with other OSes (like M$ DOS).
438 *
439 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
440 *
441 * There is two family of SIIG serial cards with different PCI
442 * interface chip and different configuration methods:
443 * - 10x cards have control registers in IO and/or memory space;
444 * - 20x cards have control registers in standard PCI configuration space.
445 *
446 * Note: all 10x cards have PCI device ids 0x10..
447 * all 20x cards have PCI device ids 0x20..
448 *
449 * There are also Quartet Serial cards which use Oxford Semiconductor
450 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
451 *
452 * Note: some SIIG cards are probed by the parport_serial object.
453 */
454
455 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
456 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
457
458 static int pci_siig10x_init(struct pci_dev *dev)
459 {
460 u16 data;
461 void __iomem *p;
462
463 switch (dev->device & 0xfff8) {
464 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
465 data = 0xffdf;
466 break;
467 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
468 data = 0xf7ff;
469 break;
470 default: /* 1S1P, 4S */
471 data = 0xfffb;
472 break;
473 }
474
475 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
476 if (p == NULL)
477 return -ENOMEM;
478
479 writew(readw(p + 0x28) & data, p + 0x28);
480 readw(p + 0x28);
481 iounmap(p);
482 return 0;
483 }
484
485 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
486 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
487
488 static int pci_siig20x_init(struct pci_dev *dev)
489 {
490 u8 data;
491
492 /* Change clock frequency for the first UART. */
493 pci_read_config_byte(dev, 0x6f, &data);
494 pci_write_config_byte(dev, 0x6f, data & 0xef);
495
496 /* If this card has 2 UART, we have to do the same with second UART. */
497 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
498 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
499 pci_read_config_byte(dev, 0x73, &data);
500 pci_write_config_byte(dev, 0x73, data & 0xef);
501 }
502 return 0;
503 }
504
505 static int pci_siig_init(struct pci_dev *dev)
506 {
507 unsigned int type = dev->device & 0xff00;
508
509 if (type == 0x1000)
510 return pci_siig10x_init(dev);
511 else if (type == 0x2000)
512 return pci_siig20x_init(dev);
513
514 moan_device("Unknown SIIG card", dev);
515 return -ENODEV;
516 }
517
518 static int pci_siig_setup(struct serial_private *priv,
519 const struct pciserial_board *board,
520 struct uart_8250_port *port, int idx)
521 {
522 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
523
524 if (idx > 3) {
525 bar = 4;
526 offset = (idx - 4) * 8;
527 }
528
529 return setup_port(priv, port, bar, offset, 0);
530 }
531
532 /*
533 * Timedia has an explosion of boards, and to avoid the PCI table from
534 * growing *huge*, we use this function to collapse some 70 entries
535 * in the PCI table into one, for sanity's and compactness's sake.
536 */
537 static const unsigned short timedia_single_port[] = {
538 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
539 };
540
541 static const unsigned short timedia_dual_port[] = {
542 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
543 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
544 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
545 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
546 0xD079, 0
547 };
548
549 static const unsigned short timedia_quad_port[] = {
550 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
551 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
552 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
553 0xB157, 0
554 };
555
556 static const unsigned short timedia_eight_port[] = {
557 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
558 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
559 };
560
561 static const struct timedia_struct {
562 int num;
563 const unsigned short *ids;
564 } timedia_data[] = {
565 { 1, timedia_single_port },
566 { 2, timedia_dual_port },
567 { 4, timedia_quad_port },
568 { 8, timedia_eight_port }
569 };
570
571 /*
572 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
573 * listing them individually, this driver merely grabs them all with
574 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
575 * and should be left free to be claimed by parport_serial instead.
576 */
577 static int pci_timedia_probe(struct pci_dev *dev)
578 {
579 /*
580 * Check the third digit of the subdevice ID
581 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
582 */
583 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
584 dev_info(&dev->dev,
585 "ignoring Timedia subdevice %04x for parport_serial\n",
586 dev->subsystem_device);
587 return -ENODEV;
588 }
589
590 return 0;
591 }
592
593 static int pci_timedia_init(struct pci_dev *dev)
594 {
595 const unsigned short *ids;
596 int i, j;
597
598 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
599 ids = timedia_data[i].ids;
600 for (j = 0; ids[j]; j++)
601 if (dev->subsystem_device == ids[j])
602 return timedia_data[i].num;
603 }
604 return 0;
605 }
606
607 /*
608 * Timedia/SUNIX uses a mixture of BARs and offsets
609 * Ugh, this is ugly as all hell --- TYT
610 */
611 static int
612 pci_timedia_setup(struct serial_private *priv,
613 const struct pciserial_board *board,
614 struct uart_8250_port *port, int idx)
615 {
616 unsigned int bar = 0, offset = board->first_offset;
617
618 switch (idx) {
619 case 0:
620 bar = 0;
621 break;
622 case 1:
623 offset = board->uart_offset;
624 bar = 0;
625 break;
626 case 2:
627 bar = 1;
628 break;
629 case 3:
630 offset = board->uart_offset;
631 /* FALLTHROUGH */
632 case 4: /* BAR 2 */
633 case 5: /* BAR 3 */
634 case 6: /* BAR 4 */
635 case 7: /* BAR 5 */
636 bar = idx - 2;
637 }
638
639 return setup_port(priv, port, bar, offset, board->reg_shift);
640 }
641
642 /*
643 * Some Titan cards are also a little weird
644 */
645 static int
646 titan_400l_800l_setup(struct serial_private *priv,
647 const struct pciserial_board *board,
648 struct uart_8250_port *port, int idx)
649 {
650 unsigned int bar, offset = board->first_offset;
651
652 switch (idx) {
653 case 0:
654 bar = 1;
655 break;
656 case 1:
657 bar = 2;
658 break;
659 default:
660 bar = 4;
661 offset = (idx - 2) * board->uart_offset;
662 }
663
664 return setup_port(priv, port, bar, offset, board->reg_shift);
665 }
666
667 static int pci_xircom_init(struct pci_dev *dev)
668 {
669 msleep(100);
670 return 0;
671 }
672
673 static int pci_ni8420_init(struct pci_dev *dev)
674 {
675 void __iomem *p;
676 unsigned int bar = 0;
677
678 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
679 moan_device("no memory in bar", dev);
680 return 0;
681 }
682
683 p = pci_ioremap_bar(dev, bar);
684 if (p == NULL)
685 return -ENOMEM;
686
687 /* Enable CPU Interrupt */
688 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
689 p + NI8420_INT_ENABLE_REG);
690
691 iounmap(p);
692 return 0;
693 }
694
695 #define MITE_IOWBSR1_WSIZE 0xa
696 #define MITE_IOWBSR1_WIN_OFFSET 0x800
697 #define MITE_IOWBSR1_WENAB (1 << 7)
698 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
699 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
700 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
701
702 static int pci_ni8430_init(struct pci_dev *dev)
703 {
704 void __iomem *p;
705 struct pci_bus_region region;
706 u32 device_window;
707 unsigned int bar = 0;
708
709 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
710 moan_device("no memory in bar", dev);
711 return 0;
712 }
713
714 p = pci_ioremap_bar(dev, bar);
715 if (p == NULL)
716 return -ENOMEM;
717
718 /*
719 * Set device window address and size in BAR0, while acknowledging that
720 * the resource structure may contain a translated address that differs
721 * from the address the device responds to.
722 */
723 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
724 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
725 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
726 writel(device_window, p + MITE_IOWBSR1);
727
728 /* Set window access to go to RAMSEL IO address space */
729 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
730 p + MITE_IOWCR1);
731
732 /* Enable IO Bus Interrupt 0 */
733 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
734
735 /* Enable CPU Interrupt */
736 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
737
738 iounmap(p);
739 return 0;
740 }
741
742 /* UART Port Control Register */
743 #define NI8430_PORTCON 0x0f
744 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
745
746 static int
747 pci_ni8430_setup(struct serial_private *priv,
748 const struct pciserial_board *board,
749 struct uart_8250_port *port, int idx)
750 {
751 struct pci_dev *dev = priv->dev;
752 void __iomem *p;
753 unsigned int bar, offset = board->first_offset;
754
755 if (idx >= board->num_ports)
756 return 1;
757
758 bar = FL_GET_BASE(board->flags);
759 offset += idx * board->uart_offset;
760
761 p = pci_ioremap_bar(dev, bar);
762 if (!p)
763 return -ENOMEM;
764
765 /* enable the transceiver */
766 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
767 p + offset + NI8430_PORTCON);
768
769 iounmap(p);
770
771 return setup_port(priv, port, bar, offset, board->reg_shift);
772 }
773
774 static int pci_netmos_9900_setup(struct serial_private *priv,
775 const struct pciserial_board *board,
776 struct uart_8250_port *port, int idx)
777 {
778 unsigned int bar;
779
780 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
781 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
782 /* netmos apparently orders BARs by datasheet layout, so serial
783 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
784 */
785 bar = 3 * idx;
786
787 return setup_port(priv, port, bar, 0, board->reg_shift);
788 } else {
789 return pci_default_setup(priv, board, port, idx);
790 }
791 }
792
793 /* the 99xx series comes with a range of device IDs and a variety
794 * of capabilities:
795 *
796 * 9900 has varying capabilities and can cascade to sub-controllers
797 * (cascading should be purely internal)
798 * 9904 is hardwired with 4 serial ports
799 * 9912 and 9922 are hardwired with 2 serial ports
800 */
801 static int pci_netmos_9900_numports(struct pci_dev *dev)
802 {
803 unsigned int c = dev->class;
804 unsigned int pi;
805 unsigned short sub_serports;
806
807 pi = (c & 0xff);
808
809 if (pi == 2) {
810 return 1;
811 } else if ((pi == 0) &&
812 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
813 /* two possibilities: 0x30ps encodes number of parallel and
814 * serial ports, or 0x1000 indicates *something*. This is not
815 * immediately obvious, since the 2s1p+4s configuration seems
816 * to offer all functionality on functions 0..2, while still
817 * advertising the same function 3 as the 4s+2s1p config.
818 */
819 sub_serports = dev->subsystem_device & 0xf;
820 if (sub_serports > 0) {
821 return sub_serports;
822 } else {
823 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
824 return 0;
825 }
826 }
827
828 moan_device("unknown NetMos/Mostech program interface", dev);
829 return 0;
830 }
831
832 static int pci_netmos_init(struct pci_dev *dev)
833 {
834 /* subdevice 0x00PS means <P> parallel, <S> serial */
835 unsigned int num_serial = dev->subsystem_device & 0xf;
836
837 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
838 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
839 return 0;
840
841 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
842 dev->subsystem_device == 0x0299)
843 return 0;
844
845 switch (dev->device) { /* FALLTHROUGH on all */
846 case PCI_DEVICE_ID_NETMOS_9904:
847 case PCI_DEVICE_ID_NETMOS_9912:
848 case PCI_DEVICE_ID_NETMOS_9922:
849 case PCI_DEVICE_ID_NETMOS_9900:
850 num_serial = pci_netmos_9900_numports(dev);
851 break;
852
853 default:
854 if (num_serial == 0 ) {
855 moan_device("unknown NetMos/Mostech device", dev);
856 }
857 }
858
859 if (num_serial == 0)
860 return -ENODEV;
861
862 return num_serial;
863 }
864
865 /*
866 * These chips are available with optionally one parallel port and up to
867 * two serial ports. Unfortunately they all have the same product id.
868 *
869 * Basic configuration is done over a region of 32 I/O ports. The base
870 * ioport is called INTA or INTC, depending on docs/other drivers.
871 *
872 * The region of the 32 I/O ports is configured in POSIO0R...
873 */
874
875 /* registers */
876 #define ITE_887x_MISCR 0x9c
877 #define ITE_887x_INTCBAR 0x78
878 #define ITE_887x_UARTBAR 0x7c
879 #define ITE_887x_PS0BAR 0x10
880 #define ITE_887x_POSIO0 0x60
881
882 /* I/O space size */
883 #define ITE_887x_IOSIZE 32
884 /* I/O space size (bits 26-24; 8 bytes = 011b) */
885 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
886 /* I/O space size (bits 26-24; 32 bytes = 101b) */
887 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
888 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
889 #define ITE_887x_POSIO_SPEED (3 << 29)
890 /* enable IO_Space bit */
891 #define ITE_887x_POSIO_ENABLE (1 << 31)
892
893 static int pci_ite887x_init(struct pci_dev *dev)
894 {
895 /* inta_addr are the configuration addresses of the ITE */
896 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
897 0x200, 0x280, 0 };
898 int ret, i, type;
899 struct resource *iobase = NULL;
900 u32 miscr, uartbar, ioport;
901
902 /* search for the base-ioport */
903 i = 0;
904 while (inta_addr[i] && iobase == NULL) {
905 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
906 "ite887x");
907 if (iobase != NULL) {
908 /* write POSIO0R - speed | size | ioport */
909 pci_write_config_dword(dev, ITE_887x_POSIO0,
910 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
911 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
912 /* write INTCBAR - ioport */
913 pci_write_config_dword(dev, ITE_887x_INTCBAR,
914 inta_addr[i]);
915 ret = inb(inta_addr[i]);
916 if (ret != 0xff) {
917 /* ioport connected */
918 break;
919 }
920 release_region(iobase->start, ITE_887x_IOSIZE);
921 iobase = NULL;
922 }
923 i++;
924 }
925
926 if (!inta_addr[i]) {
927 dev_err(&dev->dev, "ite887x: could not find iobase\n");
928 return -ENODEV;
929 }
930
931 /* start of undocumented type checking (see parport_pc.c) */
932 type = inb(iobase->start + 0x18) & 0x0f;
933
934 switch (type) {
935 case 0x2: /* ITE8871 (1P) */
936 case 0xa: /* ITE8875 (1P) */
937 ret = 0;
938 break;
939 case 0xe: /* ITE8872 (2S1P) */
940 ret = 2;
941 break;
942 case 0x6: /* ITE8873 (1S) */
943 ret = 1;
944 break;
945 case 0x8: /* ITE8874 (2S) */
946 ret = 2;
947 break;
948 default:
949 moan_device("Unknown ITE887x", dev);
950 ret = -ENODEV;
951 }
952
953 /* configure all serial ports */
954 for (i = 0; i < ret; i++) {
955 /* read the I/O port from the device */
956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957 &ioport);
958 ioport &= 0x0000FF00; /* the actual base address */
959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
961 ITE_887x_POSIO_IOSIZE_8 | ioport);
962
963 /* write the ioport to the UARTBAR */
964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
966 uartbar |= (ioport << (16 * i)); /* set the ioport */
967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968
969 /* get current config */
970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
971 /* disable interrupts (UARTx_Routing[3:0]) */
972 miscr &= ~(0xf << (12 - 4 * i));
973 /* activate the UART (UARTx_En) */
974 miscr |= 1 << (23 - i);
975 /* write new config with activated UART */
976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
977 }
978
979 if (ret <= 0) {
980 /* the device has no UARTs if we get here */
981 release_region(iobase->start, ITE_887x_IOSIZE);
982 }
983
984 return ret;
985 }
986
987 static void pci_ite887x_exit(struct pci_dev *dev)
988 {
989 u32 ioport;
990 /* the ioport is bit 0-15 in POSIO0R */
991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992 ioport &= 0xffff;
993 release_region(ioport, ITE_887x_IOSIZE);
994 }
995
996 /*
997 * EndRun Technologies.
998 * Determine the number of ports available on the device.
999 */
1000 #define PCI_VENDOR_ID_ENDRUN 0x7401
1001 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1002
1003 static int pci_endrun_init(struct pci_dev *dev)
1004 {
1005 u8 __iomem *p;
1006 unsigned long deviceID;
1007 unsigned int number_uarts = 0;
1008
1009 /* EndRun device is all 0xexxx */
1010 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1011 (dev->device & 0xf000) != 0xe000)
1012 return 0;
1013
1014 p = pci_iomap(dev, 0, 5);
1015 if (p == NULL)
1016 return -ENOMEM;
1017
1018 deviceID = ioread32(p);
1019 /* EndRun device */
1020 if (deviceID == 0x07000200) {
1021 number_uarts = ioread8(p + 4);
1022 dev_dbg(&dev->dev,
1023 "%d ports detected on EndRun PCI Express device\n",
1024 number_uarts);
1025 }
1026 pci_iounmap(dev, p);
1027 return number_uarts;
1028 }
1029
1030 /*
1031 * Oxford Semiconductor Inc.
1032 * Check that device is part of the Tornado range of devices, then determine
1033 * the number of ports available on the device.
1034 */
1035 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036 {
1037 u8 __iomem *p;
1038 unsigned long deviceID;
1039 unsigned int number_uarts = 0;
1040
1041 /* OxSemi Tornado devices are all 0xCxxx */
1042 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1043 (dev->device & 0xF000) != 0xC000)
1044 return 0;
1045
1046 p = pci_iomap(dev, 0, 5);
1047 if (p == NULL)
1048 return -ENOMEM;
1049
1050 deviceID = ioread32(p);
1051 /* Tornado device */
1052 if (deviceID == 0x07000200) {
1053 number_uarts = ioread8(p + 4);
1054 dev_dbg(&dev->dev,
1055 "%d ports detected on Oxford PCI Express device\n",
1056 number_uarts);
1057 }
1058 pci_iounmap(dev, p);
1059 return number_uarts;
1060 }
1061
1062 static int pci_asix_setup(struct serial_private *priv,
1063 const struct pciserial_board *board,
1064 struct uart_8250_port *port, int idx)
1065 {
1066 port->bugs |= UART_BUG_PARITY;
1067 return pci_default_setup(priv, board, port, idx);
1068 }
1069
1070 /* Quatech devices have their own extra interface features */
1071
1072 struct quatech_feature {
1073 u16 devid;
1074 bool amcc;
1075 };
1076
1077 #define QPCR_TEST_FOR1 0x3F
1078 #define QPCR_TEST_GET1 0x00
1079 #define QPCR_TEST_FOR2 0x40
1080 #define QPCR_TEST_GET2 0x40
1081 #define QPCR_TEST_FOR3 0x80
1082 #define QPCR_TEST_GET3 0x40
1083 #define QPCR_TEST_FOR4 0xC0
1084 #define QPCR_TEST_GET4 0x80
1085
1086 #define QOPR_CLOCK_X1 0x0000
1087 #define QOPR_CLOCK_X2 0x0001
1088 #define QOPR_CLOCK_X4 0x0002
1089 #define QOPR_CLOCK_X8 0x0003
1090 #define QOPR_CLOCK_RATE_MASK 0x0003
1091
1092
1093 static struct quatech_feature quatech_cards[] = {
1094 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1096 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1097 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1098 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1099 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1100 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1101 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1102 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1103 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1104 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1105 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1108 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1109 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1111 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1112 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1113 { 0, }
1114 };
1115
1116 static int pci_quatech_amcc(u16 devid)
1117 {
1118 struct quatech_feature *qf = &quatech_cards[0];
1119 while (qf->devid) {
1120 if (qf->devid == devid)
1121 return qf->amcc;
1122 qf++;
1123 }
1124 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1125 return 0;
1126 };
1127
1128 static int pci_quatech_rqopr(struct uart_8250_port *port)
1129 {
1130 unsigned long base = port->port.iobase;
1131 u8 LCR, val;
1132
1133 LCR = inb(base + UART_LCR);
1134 outb(0xBF, base + UART_LCR);
1135 val = inb(base + UART_SCR);
1136 outb(LCR, base + UART_LCR);
1137 return val;
1138 }
1139
1140 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141 {
1142 unsigned long base = port->port.iobase;
1143 u8 LCR, val;
1144
1145 LCR = inb(base + UART_LCR);
1146 outb(0xBF, base + UART_LCR);
1147 val = inb(base + UART_SCR);
1148 outb(qopr, base + UART_SCR);
1149 outb(LCR, base + UART_LCR);
1150 }
1151
1152 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153 {
1154 unsigned long base = port->port.iobase;
1155 u8 LCR, val, qmcr;
1156
1157 LCR = inb(base + UART_LCR);
1158 outb(0xBF, base + UART_LCR);
1159 val = inb(base + UART_SCR);
1160 outb(val | 0x10, base + UART_SCR);
1161 qmcr = inb(base + UART_MCR);
1162 outb(val, base + UART_SCR);
1163 outb(LCR, base + UART_LCR);
1164
1165 return qmcr;
1166 }
1167
1168 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169 {
1170 unsigned long base = port->port.iobase;
1171 u8 LCR, val;
1172
1173 LCR = inb(base + UART_LCR);
1174 outb(0xBF, base + UART_LCR);
1175 val = inb(base + UART_SCR);
1176 outb(val | 0x10, base + UART_SCR);
1177 outb(qmcr, base + UART_MCR);
1178 outb(val, base + UART_SCR);
1179 outb(LCR, base + UART_LCR);
1180 }
1181
1182 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183 {
1184 unsigned long base = port->port.iobase;
1185 u8 LCR, val;
1186
1187 LCR = inb(base + UART_LCR);
1188 outb(0xBF, base + UART_LCR);
1189 val = inb(base + UART_SCR);
1190 if (val & 0x20) {
1191 outb(0x80, UART_LCR);
1192 if (!(inb(UART_SCR) & 0x20)) {
1193 outb(LCR, base + UART_LCR);
1194 return 1;
1195 }
1196 }
1197 return 0;
1198 }
1199
1200 static int pci_quatech_test(struct uart_8250_port *port)
1201 {
1202 u8 reg;
1203 u8 qopr = pci_quatech_rqopr(port);
1204 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205 reg = pci_quatech_rqopr(port) & 0xC0;
1206 if (reg != QPCR_TEST_GET1)
1207 return -EINVAL;
1208 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209 reg = pci_quatech_rqopr(port) & 0xC0;
1210 if (reg != QPCR_TEST_GET2)
1211 return -EINVAL;
1212 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213 reg = pci_quatech_rqopr(port) & 0xC0;
1214 if (reg != QPCR_TEST_GET3)
1215 return -EINVAL;
1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217 reg = pci_quatech_rqopr(port) & 0xC0;
1218 if (reg != QPCR_TEST_GET4)
1219 return -EINVAL;
1220
1221 pci_quatech_wqopr(port, qopr);
1222 return 0;
1223 }
1224
1225 static int pci_quatech_clock(struct uart_8250_port *port)
1226 {
1227 u8 qopr, reg, set;
1228 unsigned long clock;
1229
1230 if (pci_quatech_test(port) < 0)
1231 return 1843200;
1232
1233 qopr = pci_quatech_rqopr(port);
1234
1235 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236 reg = pci_quatech_rqopr(port);
1237 if (reg & QOPR_CLOCK_X8) {
1238 clock = 1843200;
1239 goto out;
1240 }
1241 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242 reg = pci_quatech_rqopr(port);
1243 if (!(reg & QOPR_CLOCK_X8)) {
1244 clock = 1843200;
1245 goto out;
1246 }
1247 reg &= QOPR_CLOCK_X8;
1248 if (reg == QOPR_CLOCK_X2) {
1249 clock = 3685400;
1250 set = QOPR_CLOCK_X2;
1251 } else if (reg == QOPR_CLOCK_X4) {
1252 clock = 7372800;
1253 set = QOPR_CLOCK_X4;
1254 } else if (reg == QOPR_CLOCK_X8) {
1255 clock = 14745600;
1256 set = QOPR_CLOCK_X8;
1257 } else {
1258 clock = 1843200;
1259 set = QOPR_CLOCK_X1;
1260 }
1261 qopr &= ~QOPR_CLOCK_RATE_MASK;
1262 qopr |= set;
1263
1264 out:
1265 pci_quatech_wqopr(port, qopr);
1266 return clock;
1267 }
1268
1269 static int pci_quatech_rs422(struct uart_8250_port *port)
1270 {
1271 u8 qmcr;
1272 int rs422 = 0;
1273
1274 if (!pci_quatech_has_qmcr(port))
1275 return 0;
1276 qmcr = pci_quatech_rqmcr(port);
1277 pci_quatech_wqmcr(port, 0xFF);
1278 if (pci_quatech_rqmcr(port))
1279 rs422 = 1;
1280 pci_quatech_wqmcr(port, qmcr);
1281 return rs422;
1282 }
1283
1284 static int pci_quatech_init(struct pci_dev *dev)
1285 {
1286 if (pci_quatech_amcc(dev->device)) {
1287 unsigned long base = pci_resource_start(dev, 0);
1288 if (base) {
1289 u32 tmp;
1290 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1291 tmp = inl(base + 0x3c);
1292 outl(tmp | 0x01000000, base + 0x3c);
1293 outl(tmp &= ~0x01000000, base + 0x3c);
1294 }
1295 }
1296 return 0;
1297 }
1298
1299 static int pci_quatech_setup(struct serial_private *priv,
1300 const struct pciserial_board *board,
1301 struct uart_8250_port *port, int idx)
1302 {
1303 /* Needed by pci_quatech calls below */
1304 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1305 /* Set up the clocking */
1306 port->port.uartclk = pci_quatech_clock(port);
1307 /* For now just warn about RS422 */
1308 if (pci_quatech_rs422(port))
1309 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1310 return pci_default_setup(priv, board, port, idx);
1311 }
1312
1313 static void pci_quatech_exit(struct pci_dev *dev)
1314 {
1315 }
1316
1317 static int pci_default_setup(struct serial_private *priv,
1318 const struct pciserial_board *board,
1319 struct uart_8250_port *port, int idx)
1320 {
1321 unsigned int bar, offset = board->first_offset, maxnr;
1322
1323 bar = FL_GET_BASE(board->flags);
1324 if (board->flags & FL_BASE_BARS)
1325 bar += idx;
1326 else
1327 offset += idx * board->uart_offset;
1328
1329 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1330 (board->reg_shift + 3);
1331
1332 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333 return 1;
1334
1335 return setup_port(priv, port, bar, offset, board->reg_shift);
1336 }
1337
1338 static int pci_pericom_setup(struct serial_private *priv,
1339 const struct pciserial_board *board,
1340 struct uart_8250_port *port, int idx)
1341 {
1342 unsigned int bar, offset = board->first_offset, maxnr;
1343
1344 bar = FL_GET_BASE(board->flags);
1345 if (board->flags & FL_BASE_BARS)
1346 bar += idx;
1347 else
1348 offset += idx * board->uart_offset;
1349
1350 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1351 (board->reg_shift + 3);
1352
1353 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354 return 1;
1355
1356 port->port.uartclk = 14745600;
1357
1358 return setup_port(priv, port, bar, offset, board->reg_shift);
1359 }
1360
1361 static int
1362 ce4100_serial_setup(struct serial_private *priv,
1363 const struct pciserial_board *board,
1364 struct uart_8250_port *port, int idx)
1365 {
1366 int ret;
1367
1368 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1369 port->port.iotype = UPIO_MEM32;
1370 port->port.type = PORT_XSCALE;
1371 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1372 port->port.regshift = 2;
1373
1374 return ret;
1375 }
1376
1377 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1378 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1379
1380 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1381 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1382
1383 #define BYT_PRV_CLK 0x800
1384 #define BYT_PRV_CLK_EN (1 << 0)
1385 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1386 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1387 #define BYT_PRV_CLK_UPDATE (1 << 31)
1388
1389 #define BYT_TX_OVF_INT 0x820
1390 #define BYT_TX_OVF_INT_MASK (1 << 1)
1391
1392 static void
1393 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1394 struct ktermios *old)
1395 {
1396 unsigned int baud = tty_termios_baud_rate(termios);
1397 unsigned long fref = 100000000, fuart = baud * 16;
1398 unsigned long w = BIT(15) - 1;
1399 unsigned long m, n;
1400 u32 reg;
1401
1402 /* Get Fuart closer to Fref */
1403 fuart *= rounddown_pow_of_two(fref / fuart);
1404
1405 /*
1406 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1407 * dividers must be adjusted.
1408 *
1409 * uartclk = (m / n) * 100 MHz, where m <= n
1410 */
1411 rational_best_approximation(fuart, fref, w, w, &m, &n);
1412 p->uartclk = fuart;
1413
1414 /* Reset the clock */
1415 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1416 writel(reg, p->membase + BYT_PRV_CLK);
1417 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1418 writel(reg, p->membase + BYT_PRV_CLK);
1419
1420 serial8250_do_set_termios(p, termios, old);
1421 }
1422
1423 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1424 {
1425 struct dw_dma_slave *dws = param;
1426
1427 if (dws->dma_dev != chan->device->dev)
1428 return false;
1429
1430 chan->private = dws;
1431 return true;
1432 }
1433
1434 static int
1435 byt_serial_setup(struct serial_private *priv,
1436 const struct pciserial_board *board,
1437 struct uart_8250_port *port, int idx)
1438 {
1439 struct pci_dev *pdev = priv->dev;
1440 struct device *dev = port->port.dev;
1441 struct uart_8250_dma *dma;
1442 struct dw_dma_slave *tx_param, *rx_param;
1443 struct pci_dev *dma_dev;
1444 int ret;
1445
1446 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1447 if (!dma)
1448 return -ENOMEM;
1449
1450 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1451 if (!tx_param)
1452 return -ENOMEM;
1453
1454 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1455 if (!rx_param)
1456 return -ENOMEM;
1457
1458 switch (pdev->device) {
1459 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1460 case PCI_DEVICE_ID_INTEL_BSW_UART1:
1461 rx_param->src_id = 3;
1462 tx_param->dst_id = 2;
1463 break;
1464 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1465 case PCI_DEVICE_ID_INTEL_BSW_UART2:
1466 rx_param->src_id = 5;
1467 tx_param->dst_id = 4;
1468 break;
1469 default:
1470 return -EINVAL;
1471 }
1472
1473 rx_param->src_master = 1;
1474 rx_param->dst_master = 0;
1475
1476 dma->rxconf.src_maxburst = 16;
1477
1478 tx_param->src_master = 1;
1479 tx_param->dst_master = 0;
1480
1481 dma->txconf.dst_maxburst = 16;
1482
1483 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1484 rx_param->dma_dev = &dma_dev->dev;
1485 tx_param->dma_dev = &dma_dev->dev;
1486
1487 dma->fn = byt_dma_filter;
1488 dma->rx_param = rx_param;
1489 dma->tx_param = tx_param;
1490
1491 ret = pci_default_setup(priv, board, port, idx);
1492 port->port.iotype = UPIO_MEM;
1493 port->port.type = PORT_16550A;
1494 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1495 port->port.set_termios = byt_set_termios;
1496 port->port.fifosize = 64;
1497 port->tx_loadsz = 64;
1498 port->dma = dma;
1499 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1500
1501 /* Disable Tx counter interrupts */
1502 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1503
1504 return ret;
1505 }
1506
1507 #define INTEL_MID_UART_PS 0x30
1508 #define INTEL_MID_UART_MUL 0x34
1509 #define INTEL_MID_UART_DIV 0x38
1510
1511 static void intel_mid_set_termios(struct uart_port *p,
1512 struct ktermios *termios,
1513 struct ktermios *old,
1514 unsigned long fref)
1515 {
1516 unsigned int baud = tty_termios_baud_rate(termios);
1517 unsigned short ps = 16;
1518 unsigned long fuart = baud * ps;
1519 unsigned long w = BIT(24) - 1;
1520 unsigned long mul, div;
1521
1522 if (fref < fuart) {
1523 /* Find prescaler value that satisfies Fuart < Fref */
1524 if (fref > baud)
1525 ps = fref / baud; /* baud rate too high */
1526 else
1527 ps = 1; /* PLL case */
1528 fuart = baud * ps;
1529 } else {
1530 /* Get Fuart closer to Fref */
1531 fuart *= rounddown_pow_of_two(fref / fuart);
1532 }
1533
1534 rational_best_approximation(fuart, fref, w, w, &mul, &div);
1535 p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */
1536
1537 writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
1538 writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
1539 writel(div, p->membase + INTEL_MID_UART_DIV);
1540
1541 serial8250_do_set_termios(p, termios, old);
1542 }
1543
1544 static void intel_mid_set_termios_38_4M(struct uart_port *p,
1545 struct ktermios *termios,
1546 struct ktermios *old)
1547 {
1548 intel_mid_set_termios(p, termios, old, 38400000);
1549 }
1550
1551 static void intel_mid_set_termios_50M(struct uart_port *p,
1552 struct ktermios *termios,
1553 struct ktermios *old)
1554 {
1555 /*
1556 * The uart clk is 50Mhz, and the baud rate come from:
1557 * baud = 50M * MUL / (DIV * PS * DLAB)
1558 */
1559 intel_mid_set_termios(p, termios, old, 50000000);
1560 }
1561
1562 static bool intel_mid_dma_filter(struct dma_chan *chan, void *param)
1563 {
1564 struct hsu_dma_slave *s = param;
1565
1566 if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
1567 return false;
1568
1569 chan->private = s;
1570 return true;
1571 }
1572
1573 static int intel_mid_serial_setup(struct serial_private *priv,
1574 const struct pciserial_board *board,
1575 struct uart_8250_port *port, int idx,
1576 int index, struct pci_dev *dma_dev)
1577 {
1578 struct device *dev = port->port.dev;
1579 struct uart_8250_dma *dma;
1580 struct hsu_dma_slave *tx_param, *rx_param;
1581
1582 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1583 if (!dma)
1584 return -ENOMEM;
1585
1586 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1587 if (!tx_param)
1588 return -ENOMEM;
1589
1590 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1591 if (!rx_param)
1592 return -ENOMEM;
1593
1594 rx_param->chan_id = index * 2 + 1;
1595 tx_param->chan_id = index * 2;
1596
1597 dma->rxconf.src_maxburst = 64;
1598 dma->txconf.dst_maxburst = 64;
1599
1600 rx_param->dma_dev = &dma_dev->dev;
1601 tx_param->dma_dev = &dma_dev->dev;
1602
1603 dma->fn = intel_mid_dma_filter;
1604 dma->rx_param = rx_param;
1605 dma->tx_param = tx_param;
1606
1607 port->port.type = PORT_16750;
1608 port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE;
1609 port->dma = dma;
1610
1611 return pci_default_setup(priv, board, port, idx);
1612 }
1613
1614 #define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b
1615 #define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c
1616 #define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d
1617
1618 static int pnw_serial_setup(struct serial_private *priv,
1619 const struct pciserial_board *board,
1620 struct uart_8250_port *port, int idx)
1621 {
1622 struct pci_dev *pdev = priv->dev;
1623 struct pci_dev *dma_dev;
1624 int index;
1625
1626 switch (pdev->device) {
1627 case PCI_DEVICE_ID_INTEL_PNW_UART1:
1628 index = 0;
1629 break;
1630 case PCI_DEVICE_ID_INTEL_PNW_UART2:
1631 index = 1;
1632 break;
1633 case PCI_DEVICE_ID_INTEL_PNW_UART3:
1634 index = 2;
1635 break;
1636 default:
1637 return -EINVAL;
1638 }
1639
1640 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
1641
1642 port->port.set_termios = intel_mid_set_termios_50M;
1643
1644 return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1645 }
1646
1647 #define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191
1648
1649 static int tng_serial_setup(struct serial_private *priv,
1650 const struct pciserial_board *board,
1651 struct uart_8250_port *port, int idx)
1652 {
1653 struct pci_dev *pdev = priv->dev;
1654 struct pci_dev *dma_dev;
1655 int index = PCI_FUNC(pdev->devfn);
1656
1657 /* Currently no support for HSU port0 */
1658 if (index-- == 0)
1659 return -ENODEV;
1660
1661 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
1662
1663 port->port.set_termios = intel_mid_set_termios_38_4M;
1664
1665 return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1666 }
1667
1668 static int
1669 pci_omegapci_setup(struct serial_private *priv,
1670 const struct pciserial_board *board,
1671 struct uart_8250_port *port, int idx)
1672 {
1673 return setup_port(priv, port, 2, idx * 8, 0);
1674 }
1675
1676 static int
1677 pci_brcm_trumanage_setup(struct serial_private *priv,
1678 const struct pciserial_board *board,
1679 struct uart_8250_port *port, int idx)
1680 {
1681 int ret = pci_default_setup(priv, board, port, idx);
1682
1683 port->port.type = PORT_BRCM_TRUMANAGE;
1684 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1685 return ret;
1686 }
1687
1688 static int pci_fintek_setup(struct serial_private *priv,
1689 const struct pciserial_board *board,
1690 struct uart_8250_port *port, int idx)
1691 {
1692 struct pci_dev *pdev = priv->dev;
1693 u8 config_base;
1694 u16 iobase;
1695
1696 config_base = 0x40 + 0x08 * idx;
1697
1698 /* Get the io address from configuration space */
1699 pci_read_config_word(pdev, config_base + 4, &iobase);
1700
1701 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1702
1703 port->port.iotype = UPIO_PORT;
1704 port->port.iobase = iobase;
1705
1706 return 0;
1707 }
1708
1709 static int pci_fintek_init(struct pci_dev *dev)
1710 {
1711 unsigned long iobase;
1712 u32 max_port, i;
1713 u32 bar_data[3];
1714 u8 config_base;
1715
1716 switch (dev->device) {
1717 case 0x1104: /* 4 ports */
1718 case 0x1108: /* 8 ports */
1719 max_port = dev->device & 0xff;
1720 break;
1721 case 0x1112: /* 12 ports */
1722 max_port = 12;
1723 break;
1724 default:
1725 return -EINVAL;
1726 }
1727
1728 /* Get the io address dispatch from the BIOS */
1729 pci_read_config_dword(dev, 0x24, &bar_data[0]);
1730 pci_read_config_dword(dev, 0x20, &bar_data[1]);
1731 pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1732
1733 for (i = 0; i < max_port; ++i) {
1734 /* UART0 configuration offset start from 0x40 */
1735 config_base = 0x40 + 0x08 * i;
1736
1737 /* Calculate Real IO Port */
1738 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1739
1740 /* Enable UART I/O port */
1741 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1742
1743 /* Select 128-byte FIFO and 8x FIFO threshold */
1744 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1745
1746 /* LSB UART */
1747 pci_write_config_byte(dev, config_base + 0x04,
1748 (u8)(iobase & 0xff));
1749
1750 /* MSB UART */
1751 pci_write_config_byte(dev, config_base + 0x05,
1752 (u8)((iobase & 0xff00) >> 8));
1753
1754 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1755 }
1756
1757 return max_port;
1758 }
1759
1760 static int skip_tx_en_setup(struct serial_private *priv,
1761 const struct pciserial_board *board,
1762 struct uart_8250_port *port, int idx)
1763 {
1764 port->port.flags |= UPF_NO_TXEN_TEST;
1765 dev_dbg(&priv->dev->dev,
1766 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1767 priv->dev->vendor, priv->dev->device,
1768 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1769
1770 return pci_default_setup(priv, board, port, idx);
1771 }
1772
1773 static void kt_handle_break(struct uart_port *p)
1774 {
1775 struct uart_8250_port *up = up_to_u8250p(p);
1776 /*
1777 * On receipt of a BI, serial device in Intel ME (Intel
1778 * management engine) needs to have its fifos cleared for sane
1779 * SOL (Serial Over Lan) output.
1780 */
1781 serial8250_clear_and_reinit_fifos(up);
1782 }
1783
1784 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1785 {
1786 struct uart_8250_port *up = up_to_u8250p(p);
1787 unsigned int val;
1788
1789 /*
1790 * When the Intel ME (management engine) gets reset its serial
1791 * port registers could return 0 momentarily. Functions like
1792 * serial8250_console_write, read and save the IER, perform
1793 * some operation and then restore it. In order to avoid
1794 * setting IER register inadvertently to 0, if the value read
1795 * is 0, double check with ier value in uart_8250_port and use
1796 * that instead. up->ier should be the same value as what is
1797 * currently configured.
1798 */
1799 val = inb(p->iobase + offset);
1800 if (offset == UART_IER) {
1801 if (val == 0)
1802 val = up->ier;
1803 }
1804 return val;
1805 }
1806
1807 static int kt_serial_setup(struct serial_private *priv,
1808 const struct pciserial_board *board,
1809 struct uart_8250_port *port, int idx)
1810 {
1811 port->port.flags |= UPF_BUG_THRE;
1812 port->port.serial_in = kt_serial_in;
1813 port->port.handle_break = kt_handle_break;
1814 return skip_tx_en_setup(priv, board, port, idx);
1815 }
1816
1817 static int pci_eg20t_init(struct pci_dev *dev)
1818 {
1819 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1820 return -ENODEV;
1821 #else
1822 return 0;
1823 #endif
1824 }
1825
1826 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1827 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1828
1829 static int
1830 pci_xr17c154_setup(struct serial_private *priv,
1831 const struct pciserial_board *board,
1832 struct uart_8250_port *port, int idx)
1833 {
1834 port->port.flags |= UPF_EXAR_EFR;
1835 return pci_default_setup(priv, board, port, idx);
1836 }
1837
1838 static inline int
1839 xr17v35x_has_slave(struct serial_private *priv)
1840 {
1841 const int dev_id = priv->dev->device;
1842
1843 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1844 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1845 }
1846
1847 static int
1848 pci_xr17v35x_setup(struct serial_private *priv,
1849 const struct pciserial_board *board,
1850 struct uart_8250_port *port, int idx)
1851 {
1852 u8 __iomem *p;
1853
1854 p = pci_ioremap_bar(priv->dev, 0);
1855 if (p == NULL)
1856 return -ENOMEM;
1857
1858 port->port.flags |= UPF_EXAR_EFR;
1859
1860 /*
1861 * Setup the uart clock for the devices on expansion slot to
1862 * half the clock speed of the main chip (which is 125MHz)
1863 */
1864 if (xr17v35x_has_slave(priv) && idx >= 8)
1865 port->port.uartclk = (7812500 * 16 / 2);
1866
1867 /*
1868 * Setup Multipurpose Input/Output pins.
1869 */
1870 if (idx == 0) {
1871 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1872 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1873 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1874 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1875 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1876 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1877 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1878 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1879 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1880 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1881 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1882 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1883 }
1884 writeb(0x00, p + UART_EXAR_8XMODE);
1885 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1886 writeb(128, p + UART_EXAR_TXTRG);
1887 writeb(128, p + UART_EXAR_RXTRG);
1888 iounmap(p);
1889
1890 return pci_default_setup(priv, board, port, idx);
1891 }
1892
1893 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1894 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1895 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1896 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1897
1898 static int
1899 pci_fastcom335_setup(struct serial_private *priv,
1900 const struct pciserial_board *board,
1901 struct uart_8250_port *port, int idx)
1902 {
1903 u8 __iomem *p;
1904
1905 p = pci_ioremap_bar(priv->dev, 0);
1906 if (p == NULL)
1907 return -ENOMEM;
1908
1909 port->port.flags |= UPF_EXAR_EFR;
1910
1911 /*
1912 * Setup Multipurpose Input/Output pins.
1913 */
1914 if (idx == 0) {
1915 switch (priv->dev->device) {
1916 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1917 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1918 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1919 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1920 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1921 break;
1922 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1923 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1924 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1925 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1926 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1927 break;
1928 }
1929 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1930 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1931 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1932 }
1933 writeb(0x00, p + UART_EXAR_8XMODE);
1934 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1935 writeb(32, p + UART_EXAR_TXTRG);
1936 writeb(32, p + UART_EXAR_RXTRG);
1937 iounmap(p);
1938
1939 return pci_default_setup(priv, board, port, idx);
1940 }
1941
1942 static int
1943 pci_wch_ch353_setup(struct serial_private *priv,
1944 const struct pciserial_board *board,
1945 struct uart_8250_port *port, int idx)
1946 {
1947 port->port.flags |= UPF_FIXED_TYPE;
1948 port->port.type = PORT_16550A;
1949 return pci_default_setup(priv, board, port, idx);
1950 }
1951
1952 static int
1953 pci_wch_ch38x_setup(struct serial_private *priv,
1954 const struct pciserial_board *board,
1955 struct uart_8250_port *port, int idx)
1956 {
1957 port->port.flags |= UPF_FIXED_TYPE;
1958 port->port.type = PORT_16850;
1959 return pci_default_setup(priv, board, port, idx);
1960 }
1961
1962 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1963 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1964 #define PCI_DEVICE_ID_OCTPRO 0x0001
1965 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1966 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1967 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1968 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1969 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1970 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1971 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1972 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1973 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1974 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1975 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1976 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1977 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1978 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1979 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1980 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1981 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1982 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1983 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1984 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1985 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1986 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1987 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1988 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1989 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1990 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1991 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1992 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1993 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1994 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1995 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1996 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1997 #define PCI_VENDOR_ID_WCH 0x4348
1998 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1999 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
2000 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
2001 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
2002 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
2003 #define PCI_VENDOR_ID_AGESTAR 0x5372
2004 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
2005 #define PCI_VENDOR_ID_ASIX 0x9710
2006 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
2007 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
2008 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
2009 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
2010 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
2011 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
2012
2013 #define PCI_VENDOR_ID_SUNIX 0x1fd4
2014 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
2015
2016 #define PCIE_VENDOR_ID_WCH 0x1c00
2017 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
2018 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
2019
2020 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
2021 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
2022 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
2023
2024 /*
2025 * Master list of serial port init/setup/exit quirks.
2026 * This does not describe the general nature of the port.
2027 * (ie, baud base, number and location of ports, etc)
2028 *
2029 * This list is ordered alphabetically by vendor then device.
2030 * Specific entries must come before more generic entries.
2031 */
2032 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
2033 /*
2034 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2035 */
2036 {
2037 .vendor = PCI_VENDOR_ID_AMCC,
2038 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2039 .subvendor = PCI_ANY_ID,
2040 .subdevice = PCI_ANY_ID,
2041 .setup = addidata_apci7800_setup,
2042 },
2043 /*
2044 * AFAVLAB cards - these may be called via parport_serial
2045 * It is not clear whether this applies to all products.
2046 */
2047 {
2048 .vendor = PCI_VENDOR_ID_AFAVLAB,
2049 .device = PCI_ANY_ID,
2050 .subvendor = PCI_ANY_ID,
2051 .subdevice = PCI_ANY_ID,
2052 .setup = afavlab_setup,
2053 },
2054 /*
2055 * HP Diva
2056 */
2057 {
2058 .vendor = PCI_VENDOR_ID_HP,
2059 .device = PCI_DEVICE_ID_HP_DIVA,
2060 .subvendor = PCI_ANY_ID,
2061 .subdevice = PCI_ANY_ID,
2062 .init = pci_hp_diva_init,
2063 .setup = pci_hp_diva_setup,
2064 },
2065 /*
2066 * Intel
2067 */
2068 {
2069 .vendor = PCI_VENDOR_ID_INTEL,
2070 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2071 .subvendor = 0xe4bf,
2072 .subdevice = PCI_ANY_ID,
2073 .init = pci_inteli960ni_init,
2074 .setup = pci_default_setup,
2075 },
2076 {
2077 .vendor = PCI_VENDOR_ID_INTEL,
2078 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2079 .subvendor = PCI_ANY_ID,
2080 .subdevice = PCI_ANY_ID,
2081 .setup = skip_tx_en_setup,
2082 },
2083 {
2084 .vendor = PCI_VENDOR_ID_INTEL,
2085 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2086 .subvendor = PCI_ANY_ID,
2087 .subdevice = PCI_ANY_ID,
2088 .setup = skip_tx_en_setup,
2089 },
2090 {
2091 .vendor = PCI_VENDOR_ID_INTEL,
2092 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2093 .subvendor = PCI_ANY_ID,
2094 .subdevice = PCI_ANY_ID,
2095 .setup = skip_tx_en_setup,
2096 },
2097 {
2098 .vendor = PCI_VENDOR_ID_INTEL,
2099 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2100 .subvendor = PCI_ANY_ID,
2101 .subdevice = PCI_ANY_ID,
2102 .setup = ce4100_serial_setup,
2103 },
2104 {
2105 .vendor = PCI_VENDOR_ID_INTEL,
2106 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2107 .subvendor = PCI_ANY_ID,
2108 .subdevice = PCI_ANY_ID,
2109 .setup = kt_serial_setup,
2110 },
2111 {
2112 .vendor = PCI_VENDOR_ID_INTEL,
2113 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
2114 .subvendor = PCI_ANY_ID,
2115 .subdevice = PCI_ANY_ID,
2116 .setup = byt_serial_setup,
2117 },
2118 {
2119 .vendor = PCI_VENDOR_ID_INTEL,
2120 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
2121 .subvendor = PCI_ANY_ID,
2122 .subdevice = PCI_ANY_ID,
2123 .setup = byt_serial_setup,
2124 },
2125 {
2126 .vendor = PCI_VENDOR_ID_INTEL,
2127 .device = PCI_DEVICE_ID_INTEL_PNW_UART1,
2128 .subvendor = PCI_ANY_ID,
2129 .subdevice = PCI_ANY_ID,
2130 .setup = pnw_serial_setup,
2131 },
2132 {
2133 .vendor = PCI_VENDOR_ID_INTEL,
2134 .device = PCI_DEVICE_ID_INTEL_PNW_UART2,
2135 .subvendor = PCI_ANY_ID,
2136 .subdevice = PCI_ANY_ID,
2137 .setup = pnw_serial_setup,
2138 },
2139 {
2140 .vendor = PCI_VENDOR_ID_INTEL,
2141 .device = PCI_DEVICE_ID_INTEL_PNW_UART3,
2142 .subvendor = PCI_ANY_ID,
2143 .subdevice = PCI_ANY_ID,
2144 .setup = pnw_serial_setup,
2145 },
2146 {
2147 .vendor = PCI_VENDOR_ID_INTEL,
2148 .device = PCI_DEVICE_ID_INTEL_TNG_UART,
2149 .subvendor = PCI_ANY_ID,
2150 .subdevice = PCI_ANY_ID,
2151 .setup = tng_serial_setup,
2152 },
2153 {
2154 .vendor = PCI_VENDOR_ID_INTEL,
2155 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
2156 .subvendor = PCI_ANY_ID,
2157 .subdevice = PCI_ANY_ID,
2158 .setup = byt_serial_setup,
2159 },
2160 {
2161 .vendor = PCI_VENDOR_ID_INTEL,
2162 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2163 .subvendor = PCI_ANY_ID,
2164 .subdevice = PCI_ANY_ID,
2165 .setup = byt_serial_setup,
2166 },
2167 /*
2168 * ITE
2169 */
2170 {
2171 .vendor = PCI_VENDOR_ID_ITE,
2172 .device = PCI_DEVICE_ID_ITE_8872,
2173 .subvendor = PCI_ANY_ID,
2174 .subdevice = PCI_ANY_ID,
2175 .init = pci_ite887x_init,
2176 .setup = pci_default_setup,
2177 .exit = pci_ite887x_exit,
2178 },
2179 /*
2180 * National Instruments
2181 */
2182 {
2183 .vendor = PCI_VENDOR_ID_NI,
2184 .device = PCI_DEVICE_ID_NI_PCI23216,
2185 .subvendor = PCI_ANY_ID,
2186 .subdevice = PCI_ANY_ID,
2187 .init = pci_ni8420_init,
2188 .setup = pci_default_setup,
2189 .exit = pci_ni8420_exit,
2190 },
2191 {
2192 .vendor = PCI_VENDOR_ID_NI,
2193 .device = PCI_DEVICE_ID_NI_PCI2328,
2194 .subvendor = PCI_ANY_ID,
2195 .subdevice = PCI_ANY_ID,
2196 .init = pci_ni8420_init,
2197 .setup = pci_default_setup,
2198 .exit = pci_ni8420_exit,
2199 },
2200 {
2201 .vendor = PCI_VENDOR_ID_NI,
2202 .device = PCI_DEVICE_ID_NI_PCI2324,
2203 .subvendor = PCI_ANY_ID,
2204 .subdevice = PCI_ANY_ID,
2205 .init = pci_ni8420_init,
2206 .setup = pci_default_setup,
2207 .exit = pci_ni8420_exit,
2208 },
2209 {
2210 .vendor = PCI_VENDOR_ID_NI,
2211 .device = PCI_DEVICE_ID_NI_PCI2322,
2212 .subvendor = PCI_ANY_ID,
2213 .subdevice = PCI_ANY_ID,
2214 .init = pci_ni8420_init,
2215 .setup = pci_default_setup,
2216 .exit = pci_ni8420_exit,
2217 },
2218 {
2219 .vendor = PCI_VENDOR_ID_NI,
2220 .device = PCI_DEVICE_ID_NI_PCI2324I,
2221 .subvendor = PCI_ANY_ID,
2222 .subdevice = PCI_ANY_ID,
2223 .init = pci_ni8420_init,
2224 .setup = pci_default_setup,
2225 .exit = pci_ni8420_exit,
2226 },
2227 {
2228 .vendor = PCI_VENDOR_ID_NI,
2229 .device = PCI_DEVICE_ID_NI_PCI2322I,
2230 .subvendor = PCI_ANY_ID,
2231 .subdevice = PCI_ANY_ID,
2232 .init = pci_ni8420_init,
2233 .setup = pci_default_setup,
2234 .exit = pci_ni8420_exit,
2235 },
2236 {
2237 .vendor = PCI_VENDOR_ID_NI,
2238 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2239 .subvendor = PCI_ANY_ID,
2240 .subdevice = PCI_ANY_ID,
2241 .init = pci_ni8420_init,
2242 .setup = pci_default_setup,
2243 .exit = pci_ni8420_exit,
2244 },
2245 {
2246 .vendor = PCI_VENDOR_ID_NI,
2247 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2248 .subvendor = PCI_ANY_ID,
2249 .subdevice = PCI_ANY_ID,
2250 .init = pci_ni8420_init,
2251 .setup = pci_default_setup,
2252 .exit = pci_ni8420_exit,
2253 },
2254 {
2255 .vendor = PCI_VENDOR_ID_NI,
2256 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2257 .subvendor = PCI_ANY_ID,
2258 .subdevice = PCI_ANY_ID,
2259 .init = pci_ni8420_init,
2260 .setup = pci_default_setup,
2261 .exit = pci_ni8420_exit,
2262 },
2263 {
2264 .vendor = PCI_VENDOR_ID_NI,
2265 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2266 .subvendor = PCI_ANY_ID,
2267 .subdevice = PCI_ANY_ID,
2268 .init = pci_ni8420_init,
2269 .setup = pci_default_setup,
2270 .exit = pci_ni8420_exit,
2271 },
2272 {
2273 .vendor = PCI_VENDOR_ID_NI,
2274 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2275 .subvendor = PCI_ANY_ID,
2276 .subdevice = PCI_ANY_ID,
2277 .init = pci_ni8420_init,
2278 .setup = pci_default_setup,
2279 .exit = pci_ni8420_exit,
2280 },
2281 {
2282 .vendor = PCI_VENDOR_ID_NI,
2283 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2284 .subvendor = PCI_ANY_ID,
2285 .subdevice = PCI_ANY_ID,
2286 .init = pci_ni8420_init,
2287 .setup = pci_default_setup,
2288 .exit = pci_ni8420_exit,
2289 },
2290 {
2291 .vendor = PCI_VENDOR_ID_NI,
2292 .device = PCI_ANY_ID,
2293 .subvendor = PCI_ANY_ID,
2294 .subdevice = PCI_ANY_ID,
2295 .init = pci_ni8430_init,
2296 .setup = pci_ni8430_setup,
2297 .exit = pci_ni8430_exit,
2298 },
2299 /* Quatech */
2300 {
2301 .vendor = PCI_VENDOR_ID_QUATECH,
2302 .device = PCI_ANY_ID,
2303 .subvendor = PCI_ANY_ID,
2304 .subdevice = PCI_ANY_ID,
2305 .init = pci_quatech_init,
2306 .setup = pci_quatech_setup,
2307 .exit = pci_quatech_exit,
2308 },
2309 /*
2310 * Panacom
2311 */
2312 {
2313 .vendor = PCI_VENDOR_ID_PANACOM,
2314 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2315 .subvendor = PCI_ANY_ID,
2316 .subdevice = PCI_ANY_ID,
2317 .init = pci_plx9050_init,
2318 .setup = pci_default_setup,
2319 .exit = pci_plx9050_exit,
2320 },
2321 {
2322 .vendor = PCI_VENDOR_ID_PANACOM,
2323 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2324 .subvendor = PCI_ANY_ID,
2325 .subdevice = PCI_ANY_ID,
2326 .init = pci_plx9050_init,
2327 .setup = pci_default_setup,
2328 .exit = pci_plx9050_exit,
2329 },
2330 /*
2331 * Pericom
2332 */
2333 {
2334 .vendor = 0x12d8,
2335 .device = 0x7952,
2336 .subvendor = PCI_ANY_ID,
2337 .subdevice = PCI_ANY_ID,
2338 .setup = pci_pericom_setup,
2339 },
2340 {
2341 .vendor = 0x12d8,
2342 .device = 0x7954,
2343 .subvendor = PCI_ANY_ID,
2344 .subdevice = PCI_ANY_ID,
2345 .setup = pci_pericom_setup,
2346 },
2347 {
2348 .vendor = 0x12d8,
2349 .device = 0x7958,
2350 .subvendor = PCI_ANY_ID,
2351 .subdevice = PCI_ANY_ID,
2352 .setup = pci_pericom_setup,
2353 },
2354
2355 /*
2356 * PLX
2357 */
2358 {
2359 .vendor = PCI_VENDOR_ID_PLX,
2360 .device = PCI_DEVICE_ID_PLX_9050,
2361 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2362 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2363 .init = pci_plx9050_init,
2364 .setup = pci_default_setup,
2365 .exit = pci_plx9050_exit,
2366 },
2367 {
2368 .vendor = PCI_VENDOR_ID_PLX,
2369 .device = PCI_DEVICE_ID_PLX_9050,
2370 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2371 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2372 .init = pci_plx9050_init,
2373 .setup = pci_default_setup,
2374 .exit = pci_plx9050_exit,
2375 },
2376 {
2377 .vendor = PCI_VENDOR_ID_PLX,
2378 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2379 .subvendor = PCI_VENDOR_ID_PLX,
2380 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2381 .init = pci_plx9050_init,
2382 .setup = pci_default_setup,
2383 .exit = pci_plx9050_exit,
2384 },
2385 /*
2386 * SBS Technologies, Inc., PMC-OCTALPRO 232
2387 */
2388 {
2389 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2390 .device = PCI_DEVICE_ID_OCTPRO,
2391 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2392 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2393 .init = sbs_init,
2394 .setup = sbs_setup,
2395 .exit = sbs_exit,
2396 },
2397 /*
2398 * SBS Technologies, Inc., PMC-OCTALPRO 422
2399 */
2400 {
2401 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2402 .device = PCI_DEVICE_ID_OCTPRO,
2403 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2404 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2405 .init = sbs_init,
2406 .setup = sbs_setup,
2407 .exit = sbs_exit,
2408 },
2409 /*
2410 * SBS Technologies, Inc., P-Octal 232
2411 */
2412 {
2413 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2414 .device = PCI_DEVICE_ID_OCTPRO,
2415 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2416 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2417 .init = sbs_init,
2418 .setup = sbs_setup,
2419 .exit = sbs_exit,
2420 },
2421 /*
2422 * SBS Technologies, Inc., P-Octal 422
2423 */
2424 {
2425 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2426 .device = PCI_DEVICE_ID_OCTPRO,
2427 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2428 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2429 .init = sbs_init,
2430 .setup = sbs_setup,
2431 .exit = sbs_exit,
2432 },
2433 /*
2434 * SIIG cards - these may be called via parport_serial
2435 */
2436 {
2437 .vendor = PCI_VENDOR_ID_SIIG,
2438 .device = PCI_ANY_ID,
2439 .subvendor = PCI_ANY_ID,
2440 .subdevice = PCI_ANY_ID,
2441 .init = pci_siig_init,
2442 .setup = pci_siig_setup,
2443 },
2444 /*
2445 * Titan cards
2446 */
2447 {
2448 .vendor = PCI_VENDOR_ID_TITAN,
2449 .device = PCI_DEVICE_ID_TITAN_400L,
2450 .subvendor = PCI_ANY_ID,
2451 .subdevice = PCI_ANY_ID,
2452 .setup = titan_400l_800l_setup,
2453 },
2454 {
2455 .vendor = PCI_VENDOR_ID_TITAN,
2456 .device = PCI_DEVICE_ID_TITAN_800L,
2457 .subvendor = PCI_ANY_ID,
2458 .subdevice = PCI_ANY_ID,
2459 .setup = titan_400l_800l_setup,
2460 },
2461 /*
2462 * Timedia cards
2463 */
2464 {
2465 .vendor = PCI_VENDOR_ID_TIMEDIA,
2466 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2467 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2468 .subdevice = PCI_ANY_ID,
2469 .probe = pci_timedia_probe,
2470 .init = pci_timedia_init,
2471 .setup = pci_timedia_setup,
2472 },
2473 {
2474 .vendor = PCI_VENDOR_ID_TIMEDIA,
2475 .device = PCI_ANY_ID,
2476 .subvendor = PCI_ANY_ID,
2477 .subdevice = PCI_ANY_ID,
2478 .setup = pci_timedia_setup,
2479 },
2480 /*
2481 * SUNIX (Timedia) cards
2482 * Do not "probe" for these cards as there is at least one combination
2483 * card that should be handled by parport_pc that doesn't match the
2484 * rule in pci_timedia_probe.
2485 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2486 * There are some boards with part number SER5037AL that report
2487 * subdevice ID 0x0002.
2488 */
2489 {
2490 .vendor = PCI_VENDOR_ID_SUNIX,
2491 .device = PCI_DEVICE_ID_SUNIX_1999,
2492 .subvendor = PCI_VENDOR_ID_SUNIX,
2493 .subdevice = PCI_ANY_ID,
2494 .init = pci_timedia_init,
2495 .setup = pci_timedia_setup,
2496 },
2497 /*
2498 * Exar cards
2499 */
2500 {
2501 .vendor = PCI_VENDOR_ID_EXAR,
2502 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2503 .subvendor = PCI_ANY_ID,
2504 .subdevice = PCI_ANY_ID,
2505 .setup = pci_xr17c154_setup,
2506 },
2507 {
2508 .vendor = PCI_VENDOR_ID_EXAR,
2509 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2510 .subvendor = PCI_ANY_ID,
2511 .subdevice = PCI_ANY_ID,
2512 .setup = pci_xr17c154_setup,
2513 },
2514 {
2515 .vendor = PCI_VENDOR_ID_EXAR,
2516 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2517 .subvendor = PCI_ANY_ID,
2518 .subdevice = PCI_ANY_ID,
2519 .setup = pci_xr17c154_setup,
2520 },
2521 {
2522 .vendor = PCI_VENDOR_ID_EXAR,
2523 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2524 .subvendor = PCI_ANY_ID,
2525 .subdevice = PCI_ANY_ID,
2526 .setup = pci_xr17v35x_setup,
2527 },
2528 {
2529 .vendor = PCI_VENDOR_ID_EXAR,
2530 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2531 .subvendor = PCI_ANY_ID,
2532 .subdevice = PCI_ANY_ID,
2533 .setup = pci_xr17v35x_setup,
2534 },
2535 {
2536 .vendor = PCI_VENDOR_ID_EXAR,
2537 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2538 .subvendor = PCI_ANY_ID,
2539 .subdevice = PCI_ANY_ID,
2540 .setup = pci_xr17v35x_setup,
2541 },
2542 {
2543 .vendor = PCI_VENDOR_ID_EXAR,
2544 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2545 .subvendor = PCI_ANY_ID,
2546 .subdevice = PCI_ANY_ID,
2547 .setup = pci_xr17v35x_setup,
2548 },
2549 {
2550 .vendor = PCI_VENDOR_ID_EXAR,
2551 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2552 .subvendor = PCI_ANY_ID,
2553 .subdevice = PCI_ANY_ID,
2554 .setup = pci_xr17v35x_setup,
2555 },
2556 /*
2557 * Xircom cards
2558 */
2559 {
2560 .vendor = PCI_VENDOR_ID_XIRCOM,
2561 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2562 .subvendor = PCI_ANY_ID,
2563 .subdevice = PCI_ANY_ID,
2564 .init = pci_xircom_init,
2565 .setup = pci_default_setup,
2566 },
2567 /*
2568 * Netmos cards - these may be called via parport_serial
2569 */
2570 {
2571 .vendor = PCI_VENDOR_ID_NETMOS,
2572 .device = PCI_ANY_ID,
2573 .subvendor = PCI_ANY_ID,
2574 .subdevice = PCI_ANY_ID,
2575 .init = pci_netmos_init,
2576 .setup = pci_netmos_9900_setup,
2577 },
2578 /*
2579 * EndRun Technologies
2580 */
2581 {
2582 .vendor = PCI_VENDOR_ID_ENDRUN,
2583 .device = PCI_ANY_ID,
2584 .subvendor = PCI_ANY_ID,
2585 .subdevice = PCI_ANY_ID,
2586 .init = pci_endrun_init,
2587 .setup = pci_default_setup,
2588 },
2589 /*
2590 * For Oxford Semiconductor Tornado based devices
2591 */
2592 {
2593 .vendor = PCI_VENDOR_ID_OXSEMI,
2594 .device = PCI_ANY_ID,
2595 .subvendor = PCI_ANY_ID,
2596 .subdevice = PCI_ANY_ID,
2597 .init = pci_oxsemi_tornado_init,
2598 .setup = pci_default_setup,
2599 },
2600 {
2601 .vendor = PCI_VENDOR_ID_MAINPINE,
2602 .device = PCI_ANY_ID,
2603 .subvendor = PCI_ANY_ID,
2604 .subdevice = PCI_ANY_ID,
2605 .init = pci_oxsemi_tornado_init,
2606 .setup = pci_default_setup,
2607 },
2608 {
2609 .vendor = PCI_VENDOR_ID_DIGI,
2610 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2611 .subvendor = PCI_SUBVENDOR_ID_IBM,
2612 .subdevice = PCI_ANY_ID,
2613 .init = pci_oxsemi_tornado_init,
2614 .setup = pci_default_setup,
2615 },
2616 {
2617 .vendor = PCI_VENDOR_ID_INTEL,
2618 .device = 0x8811,
2619 .subvendor = PCI_ANY_ID,
2620 .subdevice = PCI_ANY_ID,
2621 .init = pci_eg20t_init,
2622 .setup = pci_default_setup,
2623 },
2624 {
2625 .vendor = PCI_VENDOR_ID_INTEL,
2626 .device = 0x8812,
2627 .subvendor = PCI_ANY_ID,
2628 .subdevice = PCI_ANY_ID,
2629 .init = pci_eg20t_init,
2630 .setup = pci_default_setup,
2631 },
2632 {
2633 .vendor = PCI_VENDOR_ID_INTEL,
2634 .device = 0x8813,
2635 .subvendor = PCI_ANY_ID,
2636 .subdevice = PCI_ANY_ID,
2637 .init = pci_eg20t_init,
2638 .setup = pci_default_setup,
2639 },
2640 {
2641 .vendor = PCI_VENDOR_ID_INTEL,
2642 .device = 0x8814,
2643 .subvendor = PCI_ANY_ID,
2644 .subdevice = PCI_ANY_ID,
2645 .init = pci_eg20t_init,
2646 .setup = pci_default_setup,
2647 },
2648 {
2649 .vendor = 0x10DB,
2650 .device = 0x8027,
2651 .subvendor = PCI_ANY_ID,
2652 .subdevice = PCI_ANY_ID,
2653 .init = pci_eg20t_init,
2654 .setup = pci_default_setup,
2655 },
2656 {
2657 .vendor = 0x10DB,
2658 .device = 0x8028,
2659 .subvendor = PCI_ANY_ID,
2660 .subdevice = PCI_ANY_ID,
2661 .init = pci_eg20t_init,
2662 .setup = pci_default_setup,
2663 },
2664 {
2665 .vendor = 0x10DB,
2666 .device = 0x8029,
2667 .subvendor = PCI_ANY_ID,
2668 .subdevice = PCI_ANY_ID,
2669 .init = pci_eg20t_init,
2670 .setup = pci_default_setup,
2671 },
2672 {
2673 .vendor = 0x10DB,
2674 .device = 0x800C,
2675 .subvendor = PCI_ANY_ID,
2676 .subdevice = PCI_ANY_ID,
2677 .init = pci_eg20t_init,
2678 .setup = pci_default_setup,
2679 },
2680 {
2681 .vendor = 0x10DB,
2682 .device = 0x800D,
2683 .subvendor = PCI_ANY_ID,
2684 .subdevice = PCI_ANY_ID,
2685 .init = pci_eg20t_init,
2686 .setup = pci_default_setup,
2687 },
2688 /*
2689 * Cronyx Omega PCI (PLX-chip based)
2690 */
2691 {
2692 .vendor = PCI_VENDOR_ID_PLX,
2693 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2694 .subvendor = PCI_ANY_ID,
2695 .subdevice = PCI_ANY_ID,
2696 .setup = pci_omegapci_setup,
2697 },
2698 /* WCH CH353 1S1P card (16550 clone) */
2699 {
2700 .vendor = PCI_VENDOR_ID_WCH,
2701 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2702 .subvendor = PCI_ANY_ID,
2703 .subdevice = PCI_ANY_ID,
2704 .setup = pci_wch_ch353_setup,
2705 },
2706 /* WCH CH353 2S1P card (16550 clone) */
2707 {
2708 .vendor = PCI_VENDOR_ID_WCH,
2709 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2710 .subvendor = PCI_ANY_ID,
2711 .subdevice = PCI_ANY_ID,
2712 .setup = pci_wch_ch353_setup,
2713 },
2714 /* WCH CH353 4S card (16550 clone) */
2715 {
2716 .vendor = PCI_VENDOR_ID_WCH,
2717 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2718 .subvendor = PCI_ANY_ID,
2719 .subdevice = PCI_ANY_ID,
2720 .setup = pci_wch_ch353_setup,
2721 },
2722 /* WCH CH353 2S1PF card (16550 clone) */
2723 {
2724 .vendor = PCI_VENDOR_ID_WCH,
2725 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2726 .subvendor = PCI_ANY_ID,
2727 .subdevice = PCI_ANY_ID,
2728 .setup = pci_wch_ch353_setup,
2729 },
2730 /* WCH CH352 2S card (16550 clone) */
2731 {
2732 .vendor = PCI_VENDOR_ID_WCH,
2733 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2734 .subvendor = PCI_ANY_ID,
2735 .subdevice = PCI_ANY_ID,
2736 .setup = pci_wch_ch353_setup,
2737 },
2738 /* WCH CH382 2S1P card (16850 clone) */
2739 {
2740 .vendor = PCIE_VENDOR_ID_WCH,
2741 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2742 .subvendor = PCI_ANY_ID,
2743 .subdevice = PCI_ANY_ID,
2744 .setup = pci_wch_ch38x_setup,
2745 },
2746 /* WCH CH384 4S card (16850 clone) */
2747 {
2748 .vendor = PCIE_VENDOR_ID_WCH,
2749 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2750 .subvendor = PCI_ANY_ID,
2751 .subdevice = PCI_ANY_ID,
2752 .setup = pci_wch_ch38x_setup,
2753 },
2754 /*
2755 * ASIX devices with FIFO bug
2756 */
2757 {
2758 .vendor = PCI_VENDOR_ID_ASIX,
2759 .device = PCI_ANY_ID,
2760 .subvendor = PCI_ANY_ID,
2761 .subdevice = PCI_ANY_ID,
2762 .setup = pci_asix_setup,
2763 },
2764 /*
2765 * Commtech, Inc. Fastcom adapters
2766 *
2767 */
2768 {
2769 .vendor = PCI_VENDOR_ID_COMMTECH,
2770 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2771 .subvendor = PCI_ANY_ID,
2772 .subdevice = PCI_ANY_ID,
2773 .setup = pci_fastcom335_setup,
2774 },
2775 {
2776 .vendor = PCI_VENDOR_ID_COMMTECH,
2777 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2778 .subvendor = PCI_ANY_ID,
2779 .subdevice = PCI_ANY_ID,
2780 .setup = pci_fastcom335_setup,
2781 },
2782 {
2783 .vendor = PCI_VENDOR_ID_COMMTECH,
2784 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2785 .subvendor = PCI_ANY_ID,
2786 .subdevice = PCI_ANY_ID,
2787 .setup = pci_fastcom335_setup,
2788 },
2789 {
2790 .vendor = PCI_VENDOR_ID_COMMTECH,
2791 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2792 .subvendor = PCI_ANY_ID,
2793 .subdevice = PCI_ANY_ID,
2794 .setup = pci_fastcom335_setup,
2795 },
2796 {
2797 .vendor = PCI_VENDOR_ID_COMMTECH,
2798 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2799 .subvendor = PCI_ANY_ID,
2800 .subdevice = PCI_ANY_ID,
2801 .setup = pci_xr17v35x_setup,
2802 },
2803 {
2804 .vendor = PCI_VENDOR_ID_COMMTECH,
2805 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2806 .subvendor = PCI_ANY_ID,
2807 .subdevice = PCI_ANY_ID,
2808 .setup = pci_xr17v35x_setup,
2809 },
2810 {
2811 .vendor = PCI_VENDOR_ID_COMMTECH,
2812 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2813 .subvendor = PCI_ANY_ID,
2814 .subdevice = PCI_ANY_ID,
2815 .setup = pci_xr17v35x_setup,
2816 },
2817 /*
2818 * Broadcom TruManage (NetXtreme)
2819 */
2820 {
2821 .vendor = PCI_VENDOR_ID_BROADCOM,
2822 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2823 .subvendor = PCI_ANY_ID,
2824 .subdevice = PCI_ANY_ID,
2825 .setup = pci_brcm_trumanage_setup,
2826 },
2827 {
2828 .vendor = 0x1c29,
2829 .device = 0x1104,
2830 .subvendor = PCI_ANY_ID,
2831 .subdevice = PCI_ANY_ID,
2832 .setup = pci_fintek_setup,
2833 .init = pci_fintek_init,
2834 },
2835 {
2836 .vendor = 0x1c29,
2837 .device = 0x1108,
2838 .subvendor = PCI_ANY_ID,
2839 .subdevice = PCI_ANY_ID,
2840 .setup = pci_fintek_setup,
2841 .init = pci_fintek_init,
2842 },
2843 {
2844 .vendor = 0x1c29,
2845 .device = 0x1112,
2846 .subvendor = PCI_ANY_ID,
2847 .subdevice = PCI_ANY_ID,
2848 .setup = pci_fintek_setup,
2849 .init = pci_fintek_init,
2850 },
2851
2852 /*
2853 * Default "match everything" terminator entry
2854 */
2855 {
2856 .vendor = PCI_ANY_ID,
2857 .device = PCI_ANY_ID,
2858 .subvendor = PCI_ANY_ID,
2859 .subdevice = PCI_ANY_ID,
2860 .setup = pci_default_setup,
2861 }
2862 };
2863
2864 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2865 {
2866 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2867 }
2868
2869 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2870 {
2871 struct pci_serial_quirk *quirk;
2872
2873 for (quirk = pci_serial_quirks; ; quirk++)
2874 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2875 quirk_id_matches(quirk->device, dev->device) &&
2876 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2877 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2878 break;
2879 return quirk;
2880 }
2881
2882 static inline int get_pci_irq(struct pci_dev *dev,
2883 const struct pciserial_board *board)
2884 {
2885 if (board->flags & FL_NOIRQ)
2886 return 0;
2887 else
2888 return dev->irq;
2889 }
2890
2891 /*
2892 * This is the configuration table for all of the PCI serial boards
2893 * which we support. It is directly indexed by the pci_board_num_t enum
2894 * value, which is encoded in the pci_device_id PCI probe table's
2895 * driver_data member.
2896 *
2897 * The makeup of these names are:
2898 * pbn_bn{_bt}_n_baud{_offsetinhex}
2899 *
2900 * bn = PCI BAR number
2901 * bt = Index using PCI BARs
2902 * n = number of serial ports
2903 * baud = baud rate
2904 * offsetinhex = offset for each sequential port (in hex)
2905 *
2906 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2907 *
2908 * Please note: in theory if n = 1, _bt infix should make no difference.
2909 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2910 */
2911 enum pci_board_num_t {
2912 pbn_default = 0,
2913
2914 pbn_b0_1_115200,
2915 pbn_b0_2_115200,
2916 pbn_b0_4_115200,
2917 pbn_b0_5_115200,
2918 pbn_b0_8_115200,
2919
2920 pbn_b0_1_921600,
2921 pbn_b0_2_921600,
2922 pbn_b0_4_921600,
2923
2924 pbn_b0_2_1130000,
2925
2926 pbn_b0_4_1152000,
2927
2928 pbn_b0_2_1152000_200,
2929 pbn_b0_4_1152000_200,
2930 pbn_b0_8_1152000_200,
2931
2932 pbn_b0_2_1843200,
2933 pbn_b0_4_1843200,
2934
2935 pbn_b0_2_1843200_200,
2936 pbn_b0_4_1843200_200,
2937 pbn_b0_8_1843200_200,
2938
2939 pbn_b0_1_4000000,
2940
2941 pbn_b0_bt_1_115200,
2942 pbn_b0_bt_2_115200,
2943 pbn_b0_bt_4_115200,
2944 pbn_b0_bt_8_115200,
2945
2946 pbn_b0_bt_1_460800,
2947 pbn_b0_bt_2_460800,
2948 pbn_b0_bt_4_460800,
2949
2950 pbn_b0_bt_1_921600,
2951 pbn_b0_bt_2_921600,
2952 pbn_b0_bt_4_921600,
2953 pbn_b0_bt_8_921600,
2954
2955 pbn_b1_1_115200,
2956 pbn_b1_2_115200,
2957 pbn_b1_4_115200,
2958 pbn_b1_8_115200,
2959 pbn_b1_16_115200,
2960
2961 pbn_b1_1_921600,
2962 pbn_b1_2_921600,
2963 pbn_b1_4_921600,
2964 pbn_b1_8_921600,
2965
2966 pbn_b1_2_1250000,
2967
2968 pbn_b1_bt_1_115200,
2969 pbn_b1_bt_2_115200,
2970 pbn_b1_bt_4_115200,
2971
2972 pbn_b1_bt_2_921600,
2973
2974 pbn_b1_1_1382400,
2975 pbn_b1_2_1382400,
2976 pbn_b1_4_1382400,
2977 pbn_b1_8_1382400,
2978
2979 pbn_b2_1_115200,
2980 pbn_b2_2_115200,
2981 pbn_b2_4_115200,
2982 pbn_b2_8_115200,
2983
2984 pbn_b2_1_460800,
2985 pbn_b2_4_460800,
2986 pbn_b2_8_460800,
2987 pbn_b2_16_460800,
2988
2989 pbn_b2_1_921600,
2990 pbn_b2_4_921600,
2991 pbn_b2_8_921600,
2992
2993 pbn_b2_8_1152000,
2994
2995 pbn_b2_bt_1_115200,
2996 pbn_b2_bt_2_115200,
2997 pbn_b2_bt_4_115200,
2998
2999 pbn_b2_bt_2_921600,
3000 pbn_b2_bt_4_921600,
3001
3002 pbn_b3_2_115200,
3003 pbn_b3_4_115200,
3004 pbn_b3_8_115200,
3005
3006 pbn_b4_bt_2_921600,
3007 pbn_b4_bt_4_921600,
3008 pbn_b4_bt_8_921600,
3009
3010 /*
3011 * Board-specific versions.
3012 */
3013 pbn_panacom,
3014 pbn_panacom2,
3015 pbn_panacom4,
3016 pbn_plx_romulus,
3017 pbn_endrun_2_4000000,
3018 pbn_oxsemi,
3019 pbn_oxsemi_1_4000000,
3020 pbn_oxsemi_2_4000000,
3021 pbn_oxsemi_4_4000000,
3022 pbn_oxsemi_8_4000000,
3023 pbn_intel_i960,
3024 pbn_sgi_ioc3,
3025 pbn_computone_4,
3026 pbn_computone_6,
3027 pbn_computone_8,
3028 pbn_sbsxrsio,
3029 pbn_exar_XR17C152,
3030 pbn_exar_XR17C154,
3031 pbn_exar_XR17C158,
3032 pbn_exar_XR17V352,
3033 pbn_exar_XR17V354,
3034 pbn_exar_XR17V358,
3035 pbn_exar_XR17V4358,
3036 pbn_exar_XR17V8358,
3037 pbn_exar_ibm_saturn,
3038 pbn_pasemi_1682M,
3039 pbn_ni8430_2,
3040 pbn_ni8430_4,
3041 pbn_ni8430_8,
3042 pbn_ni8430_16,
3043 pbn_ADDIDATA_PCIe_1_3906250,
3044 pbn_ADDIDATA_PCIe_2_3906250,
3045 pbn_ADDIDATA_PCIe_4_3906250,
3046 pbn_ADDIDATA_PCIe_8_3906250,
3047 pbn_ce4100_1_115200,
3048 pbn_byt,
3049 pbn_pnw,
3050 pbn_tng,
3051 pbn_qrk,
3052 pbn_omegapci,
3053 pbn_NETMOS9900_2s_115200,
3054 pbn_brcm_trumanage,
3055 pbn_fintek_4,
3056 pbn_fintek_8,
3057 pbn_fintek_12,
3058 pbn_wch384_4,
3059 };
3060
3061 /*
3062 * uart_offset - the space between channels
3063 * reg_shift - describes how the UART registers are mapped
3064 * to PCI memory by the card.
3065 * For example IER register on SBS, Inc. PMC-OctPro is located at
3066 * offset 0x10 from the UART base, while UART_IER is defined as 1
3067 * in include/linux/serial_reg.h,
3068 * see first lines of serial_in() and serial_out() in 8250.c
3069 */
3070
3071 static struct pciserial_board pci_boards[] = {
3072 [pbn_default] = {
3073 .flags = FL_BASE0,
3074 .num_ports = 1,
3075 .base_baud = 115200,
3076 .uart_offset = 8,
3077 },
3078 [pbn_b0_1_115200] = {
3079 .flags = FL_BASE0,
3080 .num_ports = 1,
3081 .base_baud = 115200,
3082 .uart_offset = 8,
3083 },
3084 [pbn_b0_2_115200] = {
3085 .flags = FL_BASE0,
3086 .num_ports = 2,
3087 .base_baud = 115200,
3088 .uart_offset = 8,
3089 },
3090 [pbn_b0_4_115200] = {
3091 .flags = FL_BASE0,
3092 .num_ports = 4,
3093 .base_baud = 115200,
3094 .uart_offset = 8,
3095 },
3096 [pbn_b0_5_115200] = {
3097 .flags = FL_BASE0,
3098 .num_ports = 5,
3099 .base_baud = 115200,
3100 .uart_offset = 8,
3101 },
3102 [pbn_b0_8_115200] = {
3103 .flags = FL_BASE0,
3104 .num_ports = 8,
3105 .base_baud = 115200,
3106 .uart_offset = 8,
3107 },
3108 [pbn_b0_1_921600] = {
3109 .flags = FL_BASE0,
3110 .num_ports = 1,
3111 .base_baud = 921600,
3112 .uart_offset = 8,
3113 },
3114 [pbn_b0_2_921600] = {
3115 .flags = FL_BASE0,
3116 .num_ports = 2,
3117 .base_baud = 921600,
3118 .uart_offset = 8,
3119 },
3120 [pbn_b0_4_921600] = {
3121 .flags = FL_BASE0,
3122 .num_ports = 4,
3123 .base_baud = 921600,
3124 .uart_offset = 8,
3125 },
3126
3127 [pbn_b0_2_1130000] = {
3128 .flags = FL_BASE0,
3129 .num_ports = 2,
3130 .base_baud = 1130000,
3131 .uart_offset = 8,
3132 },
3133
3134 [pbn_b0_4_1152000] = {
3135 .flags = FL_BASE0,
3136 .num_ports = 4,
3137 .base_baud = 1152000,
3138 .uart_offset = 8,
3139 },
3140
3141 [pbn_b0_2_1152000_200] = {
3142 .flags = FL_BASE0,
3143 .num_ports = 2,
3144 .base_baud = 1152000,
3145 .uart_offset = 0x200,
3146 },
3147
3148 [pbn_b0_4_1152000_200] = {
3149 .flags = FL_BASE0,
3150 .num_ports = 4,
3151 .base_baud = 1152000,
3152 .uart_offset = 0x200,
3153 },
3154
3155 [pbn_b0_8_1152000_200] = {
3156 .flags = FL_BASE0,
3157 .num_ports = 8,
3158 .base_baud = 1152000,
3159 .uart_offset = 0x200,
3160 },
3161
3162 [pbn_b0_2_1843200] = {
3163 .flags = FL_BASE0,
3164 .num_ports = 2,
3165 .base_baud = 1843200,
3166 .uart_offset = 8,
3167 },
3168 [pbn_b0_4_1843200] = {
3169 .flags = FL_BASE0,
3170 .num_ports = 4,
3171 .base_baud = 1843200,
3172 .uart_offset = 8,
3173 },
3174
3175 [pbn_b0_2_1843200_200] = {
3176 .flags = FL_BASE0,
3177 .num_ports = 2,
3178 .base_baud = 1843200,
3179 .uart_offset = 0x200,
3180 },
3181 [pbn_b0_4_1843200_200] = {
3182 .flags = FL_BASE0,
3183 .num_ports = 4,
3184 .base_baud = 1843200,
3185 .uart_offset = 0x200,
3186 },
3187 [pbn_b0_8_1843200_200] = {
3188 .flags = FL_BASE0,
3189 .num_ports = 8,
3190 .base_baud = 1843200,
3191 .uart_offset = 0x200,
3192 },
3193 [pbn_b0_1_4000000] = {
3194 .flags = FL_BASE0,
3195 .num_ports = 1,
3196 .base_baud = 4000000,
3197 .uart_offset = 8,
3198 },
3199
3200 [pbn_b0_bt_1_115200] = {
3201 .flags = FL_BASE0|FL_BASE_BARS,
3202 .num_ports = 1,
3203 .base_baud = 115200,
3204 .uart_offset = 8,
3205 },
3206 [pbn_b0_bt_2_115200] = {
3207 .flags = FL_BASE0|FL_BASE_BARS,
3208 .num_ports = 2,
3209 .base_baud = 115200,
3210 .uart_offset = 8,
3211 },
3212 [pbn_b0_bt_4_115200] = {
3213 .flags = FL_BASE0|FL_BASE_BARS,
3214 .num_ports = 4,
3215 .base_baud = 115200,
3216 .uart_offset = 8,
3217 },
3218 [pbn_b0_bt_8_115200] = {
3219 .flags = FL_BASE0|FL_BASE_BARS,
3220 .num_ports = 8,
3221 .base_baud = 115200,
3222 .uart_offset = 8,
3223 },
3224
3225 [pbn_b0_bt_1_460800] = {
3226 .flags = FL_BASE0|FL_BASE_BARS,
3227 .num_ports = 1,
3228 .base_baud = 460800,
3229 .uart_offset = 8,
3230 },
3231 [pbn_b0_bt_2_460800] = {
3232 .flags = FL_BASE0|FL_BASE_BARS,
3233 .num_ports = 2,
3234 .base_baud = 460800,
3235 .uart_offset = 8,
3236 },
3237 [pbn_b0_bt_4_460800] = {
3238 .flags = FL_BASE0|FL_BASE_BARS,
3239 .num_ports = 4,
3240 .base_baud = 460800,
3241 .uart_offset = 8,
3242 },
3243
3244 [pbn_b0_bt_1_921600] = {
3245 .flags = FL_BASE0|FL_BASE_BARS,
3246 .num_ports = 1,
3247 .base_baud = 921600,
3248 .uart_offset = 8,
3249 },
3250 [pbn_b0_bt_2_921600] = {
3251 .flags = FL_BASE0|FL_BASE_BARS,
3252 .num_ports = 2,
3253 .base_baud = 921600,
3254 .uart_offset = 8,
3255 },
3256 [pbn_b0_bt_4_921600] = {
3257 .flags = FL_BASE0|FL_BASE_BARS,
3258 .num_ports = 4,
3259 .base_baud = 921600,
3260 .uart_offset = 8,
3261 },
3262 [pbn_b0_bt_8_921600] = {
3263 .flags = FL_BASE0|FL_BASE_BARS,
3264 .num_ports = 8,
3265 .base_baud = 921600,
3266 .uart_offset = 8,
3267 },
3268
3269 [pbn_b1_1_115200] = {
3270 .flags = FL_BASE1,
3271 .num_ports = 1,
3272 .base_baud = 115200,
3273 .uart_offset = 8,
3274 },
3275 [pbn_b1_2_115200] = {
3276 .flags = FL_BASE1,
3277 .num_ports = 2,
3278 .base_baud = 115200,
3279 .uart_offset = 8,
3280 },
3281 [pbn_b1_4_115200] = {
3282 .flags = FL_BASE1,
3283 .num_ports = 4,
3284 .base_baud = 115200,
3285 .uart_offset = 8,
3286 },
3287 [pbn_b1_8_115200] = {
3288 .flags = FL_BASE1,
3289 .num_ports = 8,
3290 .base_baud = 115200,
3291 .uart_offset = 8,
3292 },
3293 [pbn_b1_16_115200] = {
3294 .flags = FL_BASE1,
3295 .num_ports = 16,
3296 .base_baud = 115200,
3297 .uart_offset = 8,
3298 },
3299
3300 [pbn_b1_1_921600] = {
3301 .flags = FL_BASE1,
3302 .num_ports = 1,
3303 .base_baud = 921600,
3304 .uart_offset = 8,
3305 },
3306 [pbn_b1_2_921600] = {
3307 .flags = FL_BASE1,
3308 .num_ports = 2,
3309 .base_baud = 921600,
3310 .uart_offset = 8,
3311 },
3312 [pbn_b1_4_921600] = {
3313 .flags = FL_BASE1,
3314 .num_ports = 4,
3315 .base_baud = 921600,
3316 .uart_offset = 8,
3317 },
3318 [pbn_b1_8_921600] = {
3319 .flags = FL_BASE1,
3320 .num_ports = 8,
3321 .base_baud = 921600,
3322 .uart_offset = 8,
3323 },
3324 [pbn_b1_2_1250000] = {
3325 .flags = FL_BASE1,
3326 .num_ports = 2,
3327 .base_baud = 1250000,
3328 .uart_offset = 8,
3329 },
3330
3331 [pbn_b1_bt_1_115200] = {
3332 .flags = FL_BASE1|FL_BASE_BARS,
3333 .num_ports = 1,
3334 .base_baud = 115200,
3335 .uart_offset = 8,
3336 },
3337 [pbn_b1_bt_2_115200] = {
3338 .flags = FL_BASE1|FL_BASE_BARS,
3339 .num_ports = 2,
3340 .base_baud = 115200,
3341 .uart_offset = 8,
3342 },
3343 [pbn_b1_bt_4_115200] = {
3344 .flags = FL_BASE1|FL_BASE_BARS,
3345 .num_ports = 4,
3346 .base_baud = 115200,
3347 .uart_offset = 8,
3348 },
3349
3350 [pbn_b1_bt_2_921600] = {
3351 .flags = FL_BASE1|FL_BASE_BARS,
3352 .num_ports = 2,
3353 .base_baud = 921600,
3354 .uart_offset = 8,
3355 },
3356
3357 [pbn_b1_1_1382400] = {
3358 .flags = FL_BASE1,
3359 .num_ports = 1,
3360 .base_baud = 1382400,
3361 .uart_offset = 8,
3362 },
3363 [pbn_b1_2_1382400] = {
3364 .flags = FL_BASE1,
3365 .num_ports = 2,
3366 .base_baud = 1382400,
3367 .uart_offset = 8,
3368 },
3369 [pbn_b1_4_1382400] = {
3370 .flags = FL_BASE1,
3371 .num_ports = 4,
3372 .base_baud = 1382400,
3373 .uart_offset = 8,
3374 },
3375 [pbn_b1_8_1382400] = {
3376 .flags = FL_BASE1,
3377 .num_ports = 8,
3378 .base_baud = 1382400,
3379 .uart_offset = 8,
3380 },
3381
3382 [pbn_b2_1_115200] = {
3383 .flags = FL_BASE2,
3384 .num_ports = 1,
3385 .base_baud = 115200,
3386 .uart_offset = 8,
3387 },
3388 [pbn_b2_2_115200] = {
3389 .flags = FL_BASE2,
3390 .num_ports = 2,
3391 .base_baud = 115200,
3392 .uart_offset = 8,
3393 },
3394 [pbn_b2_4_115200] = {
3395 .flags = FL_BASE2,
3396 .num_ports = 4,
3397 .base_baud = 115200,
3398 .uart_offset = 8,
3399 },
3400 [pbn_b2_8_115200] = {
3401 .flags = FL_BASE2,
3402 .num_ports = 8,
3403 .base_baud = 115200,
3404 .uart_offset = 8,
3405 },
3406
3407 [pbn_b2_1_460800] = {
3408 .flags = FL_BASE2,
3409 .num_ports = 1,
3410 .base_baud = 460800,
3411 .uart_offset = 8,
3412 },
3413 [pbn_b2_4_460800] = {
3414 .flags = FL_BASE2,
3415 .num_ports = 4,
3416 .base_baud = 460800,
3417 .uart_offset = 8,
3418 },
3419 [pbn_b2_8_460800] = {
3420 .flags = FL_BASE2,
3421 .num_ports = 8,
3422 .base_baud = 460800,
3423 .uart_offset = 8,
3424 },
3425 [pbn_b2_16_460800] = {
3426 .flags = FL_BASE2,
3427 .num_ports = 16,
3428 .base_baud = 460800,
3429 .uart_offset = 8,
3430 },
3431
3432 [pbn_b2_1_921600] = {
3433 .flags = FL_BASE2,
3434 .num_ports = 1,
3435 .base_baud = 921600,
3436 .uart_offset = 8,
3437 },
3438 [pbn_b2_4_921600] = {
3439 .flags = FL_BASE2,
3440 .num_ports = 4,
3441 .base_baud = 921600,
3442 .uart_offset = 8,
3443 },
3444 [pbn_b2_8_921600] = {
3445 .flags = FL_BASE2,
3446 .num_ports = 8,
3447 .base_baud = 921600,
3448 .uart_offset = 8,
3449 },
3450
3451 [pbn_b2_8_1152000] = {
3452 .flags = FL_BASE2,
3453 .num_ports = 8,
3454 .base_baud = 1152000,
3455 .uart_offset = 8,
3456 },
3457
3458 [pbn_b2_bt_1_115200] = {
3459 .flags = FL_BASE2|FL_BASE_BARS,
3460 .num_ports = 1,
3461 .base_baud = 115200,
3462 .uart_offset = 8,
3463 },
3464 [pbn_b2_bt_2_115200] = {
3465 .flags = FL_BASE2|FL_BASE_BARS,
3466 .num_ports = 2,
3467 .base_baud = 115200,
3468 .uart_offset = 8,
3469 },
3470 [pbn_b2_bt_4_115200] = {
3471 .flags = FL_BASE2|FL_BASE_BARS,
3472 .num_ports = 4,
3473 .base_baud = 115200,
3474 .uart_offset = 8,
3475 },
3476
3477 [pbn_b2_bt_2_921600] = {
3478 .flags = FL_BASE2|FL_BASE_BARS,
3479 .num_ports = 2,
3480 .base_baud = 921600,
3481 .uart_offset = 8,
3482 },
3483 [pbn_b2_bt_4_921600] = {
3484 .flags = FL_BASE2|FL_BASE_BARS,
3485 .num_ports = 4,
3486 .base_baud = 921600,
3487 .uart_offset = 8,
3488 },
3489
3490 [pbn_b3_2_115200] = {
3491 .flags = FL_BASE3,
3492 .num_ports = 2,
3493 .base_baud = 115200,
3494 .uart_offset = 8,
3495 },
3496 [pbn_b3_4_115200] = {
3497 .flags = FL_BASE3,
3498 .num_ports = 4,
3499 .base_baud = 115200,
3500 .uart_offset = 8,
3501 },
3502 [pbn_b3_8_115200] = {
3503 .flags = FL_BASE3,
3504 .num_ports = 8,
3505 .base_baud = 115200,
3506 .uart_offset = 8,
3507 },
3508
3509 [pbn_b4_bt_2_921600] = {
3510 .flags = FL_BASE4,
3511 .num_ports = 2,
3512 .base_baud = 921600,
3513 .uart_offset = 8,
3514 },
3515 [pbn_b4_bt_4_921600] = {
3516 .flags = FL_BASE4,
3517 .num_ports = 4,
3518 .base_baud = 921600,
3519 .uart_offset = 8,
3520 },
3521 [pbn_b4_bt_8_921600] = {
3522 .flags = FL_BASE4,
3523 .num_ports = 8,
3524 .base_baud = 921600,
3525 .uart_offset = 8,
3526 },
3527
3528 /*
3529 * Entries following this are board-specific.
3530 */
3531
3532 /*
3533 * Panacom - IOMEM
3534 */
3535 [pbn_panacom] = {
3536 .flags = FL_BASE2,
3537 .num_ports = 2,
3538 .base_baud = 921600,
3539 .uart_offset = 0x400,
3540 .reg_shift = 7,
3541 },
3542 [pbn_panacom2] = {
3543 .flags = FL_BASE2|FL_BASE_BARS,
3544 .num_ports = 2,
3545 .base_baud = 921600,
3546 .uart_offset = 0x400,
3547 .reg_shift = 7,
3548 },
3549 [pbn_panacom4] = {
3550 .flags = FL_BASE2|FL_BASE_BARS,
3551 .num_ports = 4,
3552 .base_baud = 921600,
3553 .uart_offset = 0x400,
3554 .reg_shift = 7,
3555 },
3556
3557 /* I think this entry is broken - the first_offset looks wrong --rmk */
3558 [pbn_plx_romulus] = {
3559 .flags = FL_BASE2,
3560 .num_ports = 4,
3561 .base_baud = 921600,
3562 .uart_offset = 8 << 2,
3563 .reg_shift = 2,
3564 .first_offset = 0x03,
3565 },
3566
3567 /*
3568 * EndRun Technologies
3569 * Uses the size of PCI Base region 0 to
3570 * signal now many ports are available
3571 * 2 port 952 Uart support
3572 */
3573 [pbn_endrun_2_4000000] = {
3574 .flags = FL_BASE0,
3575 .num_ports = 2,
3576 .base_baud = 4000000,
3577 .uart_offset = 0x200,
3578 .first_offset = 0x1000,
3579 },
3580
3581 /*
3582 * This board uses the size of PCI Base region 0 to
3583 * signal now many ports are available
3584 */
3585 [pbn_oxsemi] = {
3586 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3587 .num_ports = 32,
3588 .base_baud = 115200,
3589 .uart_offset = 8,
3590 },
3591 [pbn_oxsemi_1_4000000] = {
3592 .flags = FL_BASE0,
3593 .num_ports = 1,
3594 .base_baud = 4000000,
3595 .uart_offset = 0x200,
3596 .first_offset = 0x1000,
3597 },
3598 [pbn_oxsemi_2_4000000] = {
3599 .flags = FL_BASE0,
3600 .num_ports = 2,
3601 .base_baud = 4000000,
3602 .uart_offset = 0x200,
3603 .first_offset = 0x1000,
3604 },
3605 [pbn_oxsemi_4_4000000] = {
3606 .flags = FL_BASE0,
3607 .num_ports = 4,
3608 .base_baud = 4000000,
3609 .uart_offset = 0x200,
3610 .first_offset = 0x1000,
3611 },
3612 [pbn_oxsemi_8_4000000] = {
3613 .flags = FL_BASE0,
3614 .num_ports = 8,
3615 .base_baud = 4000000,
3616 .uart_offset = 0x200,
3617 .first_offset = 0x1000,
3618 },
3619
3620
3621 /*
3622 * EKF addition for i960 Boards form EKF with serial port.
3623 * Max 256 ports.
3624 */
3625 [pbn_intel_i960] = {
3626 .flags = FL_BASE0,
3627 .num_ports = 32,
3628 .base_baud = 921600,
3629 .uart_offset = 8 << 2,
3630 .reg_shift = 2,
3631 .first_offset = 0x10000,
3632 },
3633 [pbn_sgi_ioc3] = {
3634 .flags = FL_BASE0|FL_NOIRQ,
3635 .num_ports = 1,
3636 .base_baud = 458333,
3637 .uart_offset = 8,
3638 .reg_shift = 0,
3639 .first_offset = 0x20178,
3640 },
3641
3642 /*
3643 * Computone - uses IOMEM.
3644 */
3645 [pbn_computone_4] = {
3646 .flags = FL_BASE0,
3647 .num_ports = 4,
3648 .base_baud = 921600,
3649 .uart_offset = 0x40,
3650 .reg_shift = 2,
3651 .first_offset = 0x200,
3652 },
3653 [pbn_computone_6] = {
3654 .flags = FL_BASE0,
3655 .num_ports = 6,
3656 .base_baud = 921600,
3657 .uart_offset = 0x40,
3658 .reg_shift = 2,
3659 .first_offset = 0x200,
3660 },
3661 [pbn_computone_8] = {
3662 .flags = FL_BASE0,
3663 .num_ports = 8,
3664 .base_baud = 921600,
3665 .uart_offset = 0x40,
3666 .reg_shift = 2,
3667 .first_offset = 0x200,
3668 },
3669 [pbn_sbsxrsio] = {
3670 .flags = FL_BASE0,
3671 .num_ports = 8,
3672 .base_baud = 460800,
3673 .uart_offset = 256,
3674 .reg_shift = 4,
3675 },
3676 /*
3677 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3678 * Only basic 16550A support.
3679 * XR17C15[24] are not tested, but they should work.
3680 */
3681 [pbn_exar_XR17C152] = {
3682 .flags = FL_BASE0,
3683 .num_ports = 2,
3684 .base_baud = 921600,
3685 .uart_offset = 0x200,
3686 },
3687 [pbn_exar_XR17C154] = {
3688 .flags = FL_BASE0,
3689 .num_ports = 4,
3690 .base_baud = 921600,
3691 .uart_offset = 0x200,
3692 },
3693 [pbn_exar_XR17C158] = {
3694 .flags = FL_BASE0,
3695 .num_ports = 8,
3696 .base_baud = 921600,
3697 .uart_offset = 0x200,
3698 },
3699 [pbn_exar_XR17V352] = {
3700 .flags = FL_BASE0,
3701 .num_ports = 2,
3702 .base_baud = 7812500,
3703 .uart_offset = 0x400,
3704 .reg_shift = 0,
3705 .first_offset = 0,
3706 },
3707 [pbn_exar_XR17V354] = {
3708 .flags = FL_BASE0,
3709 .num_ports = 4,
3710 .base_baud = 7812500,
3711 .uart_offset = 0x400,
3712 .reg_shift = 0,
3713 .first_offset = 0,
3714 },
3715 [pbn_exar_XR17V358] = {
3716 .flags = FL_BASE0,
3717 .num_ports = 8,
3718 .base_baud = 7812500,
3719 .uart_offset = 0x400,
3720 .reg_shift = 0,
3721 .first_offset = 0,
3722 },
3723 [pbn_exar_XR17V4358] = {
3724 .flags = FL_BASE0,
3725 .num_ports = 12,
3726 .base_baud = 7812500,
3727 .uart_offset = 0x400,
3728 .reg_shift = 0,
3729 .first_offset = 0,
3730 },
3731 [pbn_exar_XR17V8358] = {
3732 .flags = FL_BASE0,
3733 .num_ports = 16,
3734 .base_baud = 7812500,
3735 .uart_offset = 0x400,
3736 .reg_shift = 0,
3737 .first_offset = 0,
3738 },
3739 [pbn_exar_ibm_saturn] = {
3740 .flags = FL_BASE0,
3741 .num_ports = 1,
3742 .base_baud = 921600,
3743 .uart_offset = 0x200,
3744 },
3745
3746 /*
3747 * PA Semi PWRficient PA6T-1682M on-chip UART
3748 */
3749 [pbn_pasemi_1682M] = {
3750 .flags = FL_BASE0,
3751 .num_ports = 1,
3752 .base_baud = 8333333,
3753 },
3754 /*
3755 * National Instruments 843x
3756 */
3757 [pbn_ni8430_16] = {
3758 .flags = FL_BASE0,
3759 .num_ports = 16,
3760 .base_baud = 3686400,
3761 .uart_offset = 0x10,
3762 .first_offset = 0x800,
3763 },
3764 [pbn_ni8430_8] = {
3765 .flags = FL_BASE0,
3766 .num_ports = 8,
3767 .base_baud = 3686400,
3768 .uart_offset = 0x10,
3769 .first_offset = 0x800,
3770 },
3771 [pbn_ni8430_4] = {
3772 .flags = FL_BASE0,
3773 .num_ports = 4,
3774 .base_baud = 3686400,
3775 .uart_offset = 0x10,
3776 .first_offset = 0x800,
3777 },
3778 [pbn_ni8430_2] = {
3779 .flags = FL_BASE0,
3780 .num_ports = 2,
3781 .base_baud = 3686400,
3782 .uart_offset = 0x10,
3783 .first_offset = 0x800,
3784 },
3785 /*
3786 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3787 */
3788 [pbn_ADDIDATA_PCIe_1_3906250] = {
3789 .flags = FL_BASE0,
3790 .num_ports = 1,
3791 .base_baud = 3906250,
3792 .uart_offset = 0x200,
3793 .first_offset = 0x1000,
3794 },
3795 [pbn_ADDIDATA_PCIe_2_3906250] = {
3796 .flags = FL_BASE0,
3797 .num_ports = 2,
3798 .base_baud = 3906250,
3799 .uart_offset = 0x200,
3800 .first_offset = 0x1000,
3801 },
3802 [pbn_ADDIDATA_PCIe_4_3906250] = {
3803 .flags = FL_BASE0,
3804 .num_ports = 4,
3805 .base_baud = 3906250,
3806 .uart_offset = 0x200,
3807 .first_offset = 0x1000,
3808 },
3809 [pbn_ADDIDATA_PCIe_8_3906250] = {
3810 .flags = FL_BASE0,
3811 .num_ports = 8,
3812 .base_baud = 3906250,
3813 .uart_offset = 0x200,
3814 .first_offset = 0x1000,
3815 },
3816 [pbn_ce4100_1_115200] = {
3817 .flags = FL_BASE_BARS,
3818 .num_ports = 2,
3819 .base_baud = 921600,
3820 .reg_shift = 2,
3821 },
3822 /*
3823 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3824 * but is overridden by byt_set_termios.
3825 */
3826 [pbn_byt] = {
3827 .flags = FL_BASE0,
3828 .num_ports = 1,
3829 .base_baud = 2764800,
3830 .uart_offset = 0x80,
3831 .reg_shift = 2,
3832 },
3833 [pbn_pnw] = {
3834 .flags = FL_BASE0,
3835 .num_ports = 1,
3836 .base_baud = 115200,
3837 },
3838 [pbn_tng] = {
3839 .flags = FL_BASE0,
3840 .num_ports = 1,
3841 .base_baud = 1843200,
3842 },
3843 [pbn_qrk] = {
3844 .flags = FL_BASE0,
3845 .num_ports = 1,
3846 .base_baud = 2764800,
3847 .reg_shift = 2,
3848 },
3849 [pbn_omegapci] = {
3850 .flags = FL_BASE0,
3851 .num_ports = 8,
3852 .base_baud = 115200,
3853 .uart_offset = 0x200,
3854 },
3855 [pbn_NETMOS9900_2s_115200] = {
3856 .flags = FL_BASE0,
3857 .num_ports = 2,
3858 .base_baud = 115200,
3859 },
3860 [pbn_brcm_trumanage] = {
3861 .flags = FL_BASE0,
3862 .num_ports = 1,
3863 .reg_shift = 2,
3864 .base_baud = 115200,
3865 },
3866 [pbn_fintek_4] = {
3867 .num_ports = 4,
3868 .uart_offset = 8,
3869 .base_baud = 115200,
3870 .first_offset = 0x40,
3871 },
3872 [pbn_fintek_8] = {
3873 .num_ports = 8,
3874 .uart_offset = 8,
3875 .base_baud = 115200,
3876 .first_offset = 0x40,
3877 },
3878 [pbn_fintek_12] = {
3879 .num_ports = 12,
3880 .uart_offset = 8,
3881 .base_baud = 115200,
3882 .first_offset = 0x40,
3883 },
3884
3885 [pbn_wch384_4] = {
3886 .flags = FL_BASE0,
3887 .num_ports = 4,
3888 .base_baud = 115200,
3889 .uart_offset = 8,
3890 .first_offset = 0xC0,
3891 },
3892 };
3893
3894 static const struct pci_device_id blacklist[] = {
3895 /* softmodems */
3896 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3897 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3898 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3899
3900 /* multi-io cards handled by parport_serial */
3901 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3902 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3903 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3904 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3905 };
3906
3907 /*
3908 * Given a complete unknown PCI device, try to use some heuristics to
3909 * guess what the configuration might be, based on the pitiful PCI
3910 * serial specs. Returns 0 on success, 1 on failure.
3911 */
3912 static int
3913 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3914 {
3915 const struct pci_device_id *bldev;
3916 int num_iomem, num_port, first_port = -1, i;
3917
3918 /*
3919 * If it is not a communications device or the programming
3920 * interface is greater than 6, give up.
3921 *
3922 * (Should we try to make guesses for multiport serial devices
3923 * later?)
3924 */
3925 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3926 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3927 (dev->class & 0xff) > 6)
3928 return -ENODEV;
3929
3930 /*
3931 * Do not access blacklisted devices that are known not to
3932 * feature serial ports or are handled by other modules.
3933 */
3934 for (bldev = blacklist;
3935 bldev < blacklist + ARRAY_SIZE(blacklist);
3936 bldev++) {
3937 if (dev->vendor == bldev->vendor &&
3938 dev->device == bldev->device)
3939 return -ENODEV;
3940 }
3941
3942 num_iomem = num_port = 0;
3943 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3944 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3945 num_port++;
3946 if (first_port == -1)
3947 first_port = i;
3948 }
3949 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3950 num_iomem++;
3951 }
3952
3953 /*
3954 * If there is 1 or 0 iomem regions, and exactly one port,
3955 * use it. We guess the number of ports based on the IO
3956 * region size.
3957 */
3958 if (num_iomem <= 1 && num_port == 1) {
3959 board->flags = first_port;
3960 board->num_ports = pci_resource_len(dev, first_port) / 8;
3961 return 0;
3962 }
3963
3964 /*
3965 * Now guess if we've got a board which indexes by BARs.
3966 * Each IO BAR should be 8 bytes, and they should follow
3967 * consecutively.
3968 */
3969 first_port = -1;
3970 num_port = 0;
3971 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3972 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3973 pci_resource_len(dev, i) == 8 &&
3974 (first_port == -1 || (first_port + num_port) == i)) {
3975 num_port++;
3976 if (first_port == -1)
3977 first_port = i;
3978 }
3979 }
3980
3981 if (num_port > 1) {
3982 board->flags = first_port | FL_BASE_BARS;
3983 board->num_ports = num_port;
3984 return 0;
3985 }
3986
3987 return -ENODEV;
3988 }
3989
3990 static inline int
3991 serial_pci_matches(const struct pciserial_board *board,
3992 const struct pciserial_board *guessed)
3993 {
3994 return
3995 board->num_ports == guessed->num_ports &&
3996 board->base_baud == guessed->base_baud &&
3997 board->uart_offset == guessed->uart_offset &&
3998 board->reg_shift == guessed->reg_shift &&
3999 board->first_offset == guessed->first_offset;
4000 }
4001
4002 struct serial_private *
4003 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4004 {
4005 struct uart_8250_port uart;
4006 struct serial_private *priv;
4007 struct pci_serial_quirk *quirk;
4008 int rc, nr_ports, i;
4009
4010 nr_ports = board->num_ports;
4011
4012 /*
4013 * Find an init and setup quirks.
4014 */
4015 quirk = find_quirk(dev);
4016
4017 /*
4018 * Run the new-style initialization function.
4019 * The initialization function returns:
4020 * <0 - error
4021 * 0 - use board->num_ports
4022 * >0 - number of ports
4023 */
4024 if (quirk->init) {
4025 rc = quirk->init(dev);
4026 if (rc < 0) {
4027 priv = ERR_PTR(rc);
4028 goto err_out;
4029 }
4030 if (rc)
4031 nr_ports = rc;
4032 }
4033
4034 priv = kzalloc(sizeof(struct serial_private) +
4035 sizeof(unsigned int) * nr_ports,
4036 GFP_KERNEL);
4037 if (!priv) {
4038 priv = ERR_PTR(-ENOMEM);
4039 goto err_deinit;
4040 }
4041
4042 priv->dev = dev;
4043 priv->quirk = quirk;
4044
4045 memset(&uart, 0, sizeof(uart));
4046 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4047 uart.port.uartclk = board->base_baud * 16;
4048 uart.port.irq = get_pci_irq(dev, board);
4049 uart.port.dev = &dev->dev;
4050
4051 for (i = 0; i < nr_ports; i++) {
4052 if (quirk->setup(priv, board, &uart, i))
4053 break;
4054
4055 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4056 uart.port.iobase, uart.port.irq, uart.port.iotype);
4057
4058 priv->line[i] = serial8250_register_8250_port(&uart);
4059 if (priv->line[i] < 0) {
4060 dev_err(&dev->dev,
4061 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4062 uart.port.iobase, uart.port.irq,
4063 uart.port.iotype, priv->line[i]);
4064 break;
4065 }
4066 }
4067 priv->nr = i;
4068 return priv;
4069
4070 err_deinit:
4071 if (quirk->exit)
4072 quirk->exit(dev);
4073 err_out:
4074 return priv;
4075 }
4076 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4077
4078 void pciserial_remove_ports(struct serial_private *priv)
4079 {
4080 struct pci_serial_quirk *quirk;
4081 int i;
4082
4083 for (i = 0; i < priv->nr; i++)
4084 serial8250_unregister_port(priv->line[i]);
4085
4086 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4087 if (priv->remapped_bar[i])
4088 iounmap(priv->remapped_bar[i]);
4089 priv->remapped_bar[i] = NULL;
4090 }
4091
4092 /*
4093 * Find the exit quirks.
4094 */
4095 quirk = find_quirk(priv->dev);
4096 if (quirk->exit)
4097 quirk->exit(priv->dev);
4098
4099 kfree(priv);
4100 }
4101 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4102
4103 void pciserial_suspend_ports(struct serial_private *priv)
4104 {
4105 int i;
4106
4107 for (i = 0; i < priv->nr; i++)
4108 if (priv->line[i] >= 0)
4109 serial8250_suspend_port(priv->line[i]);
4110
4111 /*
4112 * Ensure that every init quirk is properly torn down
4113 */
4114 if (priv->quirk->exit)
4115 priv->quirk->exit(priv->dev);
4116 }
4117 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4118
4119 void pciserial_resume_ports(struct serial_private *priv)
4120 {
4121 int i;
4122
4123 /*
4124 * Ensure that the board is correctly configured.
4125 */
4126 if (priv->quirk->init)
4127 priv->quirk->init(priv->dev);
4128
4129 for (i = 0; i < priv->nr; i++)
4130 if (priv->line[i] >= 0)
4131 serial8250_resume_port(priv->line[i]);
4132 }
4133 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4134
4135 /*
4136 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4137 * to the arrangement of serial ports on a PCI card.
4138 */
4139 static int
4140 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4141 {
4142 struct pci_serial_quirk *quirk;
4143 struct serial_private *priv;
4144 const struct pciserial_board *board;
4145 struct pciserial_board tmp;
4146 int rc;
4147
4148 quirk = find_quirk(dev);
4149 if (quirk->probe) {
4150 rc = quirk->probe(dev);
4151 if (rc)
4152 return rc;
4153 }
4154
4155 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4156 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4157 ent->driver_data);
4158 return -EINVAL;
4159 }
4160
4161 board = &pci_boards[ent->driver_data];
4162
4163 rc = pci_enable_device(dev);
4164 pci_save_state(dev);
4165 if (rc)
4166 return rc;
4167
4168 if (ent->driver_data == pbn_default) {
4169 /*
4170 * Use a copy of the pci_board entry for this;
4171 * avoid changing entries in the table.
4172 */
4173 memcpy(&tmp, board, sizeof(struct pciserial_board));
4174 board = &tmp;
4175
4176 /*
4177 * We matched one of our class entries. Try to
4178 * determine the parameters of this board.
4179 */
4180 rc = serial_pci_guess_board(dev, &tmp);
4181 if (rc)
4182 goto disable;
4183 } else {
4184 /*
4185 * We matched an explicit entry. If we are able to
4186 * detect this boards settings with our heuristic,
4187 * then we no longer need this entry.
4188 */
4189 memcpy(&tmp, &pci_boards[pbn_default],
4190 sizeof(struct pciserial_board));
4191 rc = serial_pci_guess_board(dev, &tmp);
4192 if (rc == 0 && serial_pci_matches(board, &tmp))
4193 moan_device("Redundant entry in serial pci_table.",
4194 dev);
4195 }
4196
4197 priv = pciserial_init_ports(dev, board);
4198 if (!IS_ERR(priv)) {
4199 pci_set_drvdata(dev, priv);
4200 return 0;
4201 }
4202
4203 rc = PTR_ERR(priv);
4204
4205 disable:
4206 pci_disable_device(dev);
4207 return rc;
4208 }
4209
4210 static void pciserial_remove_one(struct pci_dev *dev)
4211 {
4212 struct serial_private *priv = pci_get_drvdata(dev);
4213
4214 pciserial_remove_ports(priv);
4215
4216 pci_disable_device(dev);
4217 }
4218
4219 #ifdef CONFIG_PM_SLEEP
4220 static int pciserial_suspend_one(struct device *dev)
4221 {
4222 struct pci_dev *pdev = to_pci_dev(dev);
4223 struct serial_private *priv = pci_get_drvdata(pdev);
4224
4225 if (priv)
4226 pciserial_suspend_ports(priv);
4227
4228 return 0;
4229 }
4230
4231 static int pciserial_resume_one(struct device *dev)
4232 {
4233 struct pci_dev *pdev = to_pci_dev(dev);
4234 struct serial_private *priv = pci_get_drvdata(pdev);
4235 int err;
4236
4237 if (priv) {
4238 /*
4239 * The device may have been disabled. Re-enable it.
4240 */
4241 err = pci_enable_device(pdev);
4242 /* FIXME: We cannot simply error out here */
4243 if (err)
4244 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4245 pciserial_resume_ports(priv);
4246 }
4247 return 0;
4248 }
4249 #endif
4250
4251 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4252 pciserial_resume_one);
4253
4254 static struct pci_device_id serial_pci_tbl[] = {
4255 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4256 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4257 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4258 pbn_b2_8_921600 },
4259 /* Advantech also use 0x3618 and 0xf618 */
4260 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4261 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4262 pbn_b0_4_921600 },
4263 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4264 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4265 pbn_b0_4_921600 },
4266 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4267 PCI_SUBVENDOR_ID_CONNECT_TECH,
4268 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4269 pbn_b1_8_1382400 },
4270 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4271 PCI_SUBVENDOR_ID_CONNECT_TECH,
4272 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4273 pbn_b1_4_1382400 },
4274 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4275 PCI_SUBVENDOR_ID_CONNECT_TECH,
4276 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4277 pbn_b1_2_1382400 },
4278 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4279 PCI_SUBVENDOR_ID_CONNECT_TECH,
4280 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4281 pbn_b1_8_1382400 },
4282 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4283 PCI_SUBVENDOR_ID_CONNECT_TECH,
4284 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4285 pbn_b1_4_1382400 },
4286 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4287 PCI_SUBVENDOR_ID_CONNECT_TECH,
4288 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4289 pbn_b1_2_1382400 },
4290 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4291 PCI_SUBVENDOR_ID_CONNECT_TECH,
4292 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4293 pbn_b1_8_921600 },
4294 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4295 PCI_SUBVENDOR_ID_CONNECT_TECH,
4296 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4297 pbn_b1_8_921600 },
4298 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4299 PCI_SUBVENDOR_ID_CONNECT_TECH,
4300 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4301 pbn_b1_4_921600 },
4302 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4303 PCI_SUBVENDOR_ID_CONNECT_TECH,
4304 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4305 pbn_b1_4_921600 },
4306 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4307 PCI_SUBVENDOR_ID_CONNECT_TECH,
4308 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4309 pbn_b1_2_921600 },
4310 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4311 PCI_SUBVENDOR_ID_CONNECT_TECH,
4312 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4313 pbn_b1_8_921600 },
4314 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4315 PCI_SUBVENDOR_ID_CONNECT_TECH,
4316 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4317 pbn_b1_8_921600 },
4318 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4319 PCI_SUBVENDOR_ID_CONNECT_TECH,
4320 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4321 pbn_b1_4_921600 },
4322 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4323 PCI_SUBVENDOR_ID_CONNECT_TECH,
4324 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4325 pbn_b1_2_1250000 },
4326 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4327 PCI_SUBVENDOR_ID_CONNECT_TECH,
4328 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4329 pbn_b0_2_1843200 },
4330 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4331 PCI_SUBVENDOR_ID_CONNECT_TECH,
4332 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4333 pbn_b0_4_1843200 },
4334 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4335 PCI_VENDOR_ID_AFAVLAB,
4336 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4337 pbn_b0_4_1152000 },
4338 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4339 PCI_SUBVENDOR_ID_CONNECT_TECH,
4340 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4341 pbn_b0_2_1843200_200 },
4342 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4343 PCI_SUBVENDOR_ID_CONNECT_TECH,
4344 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4345 pbn_b0_4_1843200_200 },
4346 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4347 PCI_SUBVENDOR_ID_CONNECT_TECH,
4348 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4349 pbn_b0_8_1843200_200 },
4350 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4351 PCI_SUBVENDOR_ID_CONNECT_TECH,
4352 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4353 pbn_b0_2_1843200_200 },
4354 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4355 PCI_SUBVENDOR_ID_CONNECT_TECH,
4356 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4357 pbn_b0_4_1843200_200 },
4358 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4359 PCI_SUBVENDOR_ID_CONNECT_TECH,
4360 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4361 pbn_b0_8_1843200_200 },
4362 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4363 PCI_SUBVENDOR_ID_CONNECT_TECH,
4364 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4365 pbn_b0_2_1843200_200 },
4366 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4367 PCI_SUBVENDOR_ID_CONNECT_TECH,
4368 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4369 pbn_b0_4_1843200_200 },
4370 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4371 PCI_SUBVENDOR_ID_CONNECT_TECH,
4372 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4373 pbn_b0_8_1843200_200 },
4374 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4375 PCI_SUBVENDOR_ID_CONNECT_TECH,
4376 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4377 pbn_b0_2_1843200_200 },
4378 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4379 PCI_SUBVENDOR_ID_CONNECT_TECH,
4380 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4381 pbn_b0_4_1843200_200 },
4382 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4383 PCI_SUBVENDOR_ID_CONNECT_TECH,
4384 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4385 pbn_b0_8_1843200_200 },
4386 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4387 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4388 0, 0, pbn_exar_ibm_saturn },
4389
4390 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4392 pbn_b2_bt_1_115200 },
4393 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4395 pbn_b2_bt_2_115200 },
4396 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4398 pbn_b2_bt_4_115200 },
4399 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4401 pbn_b2_bt_2_115200 },
4402 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4404 pbn_b2_bt_4_115200 },
4405 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4407 pbn_b2_8_115200 },
4408 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 pbn_b2_8_460800 },
4411 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 pbn_b2_8_115200 },
4414
4415 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4417 pbn_b2_bt_2_115200 },
4418 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4420 pbn_b2_bt_2_921600 },
4421 /*
4422 * VScom SPCOM800, from sl@s.pl
4423 */
4424 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426 pbn_b2_8_921600 },
4427 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429 pbn_b2_4_921600 },
4430 /* Unknown card - subdevice 0x1584 */
4431 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4432 PCI_VENDOR_ID_PLX,
4433 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4434 pbn_b2_4_115200 },
4435 /* Unknown card - subdevice 0x1588 */
4436 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4437 PCI_VENDOR_ID_PLX,
4438 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4439 pbn_b2_8_115200 },
4440 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4441 PCI_SUBVENDOR_ID_KEYSPAN,
4442 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4443 pbn_panacom },
4444 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446 pbn_panacom4 },
4447 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449 pbn_panacom2 },
4450 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4451 PCI_VENDOR_ID_ESDGMBH,
4452 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4453 pbn_b2_4_115200 },
4454 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4455 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4456 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4457 pbn_b2_4_460800 },
4458 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4459 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4460 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4461 pbn_b2_8_460800 },
4462 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4463 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4464 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4465 pbn_b2_16_460800 },
4466 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4467 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4468 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4469 pbn_b2_16_460800 },
4470 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4471 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4472 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4473 pbn_b2_4_460800 },
4474 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4475 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4476 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4477 pbn_b2_8_460800 },
4478 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4479 PCI_SUBVENDOR_ID_EXSYS,
4480 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4481 pbn_b2_4_115200 },
4482 /*
4483 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4484 * (Exoray@isys.ca)
4485 */
4486 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4487 0x10b5, 0x106a, 0, 0,
4488 pbn_plx_romulus },
4489 /*
4490 * EndRun Technologies. PCI express device range.
4491 * EndRun PTP/1588 has 2 Native UARTs.
4492 */
4493 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495 pbn_endrun_2_4000000 },
4496 /*
4497 * Quatech cards. These actually have configurable clocks but for
4498 * now we just use the default.
4499 *
4500 * 100 series are RS232, 200 series RS422,
4501 */
4502 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 pbn_b1_4_115200 },
4505 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 pbn_b1_2_115200 },
4508 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_b2_2_115200 },
4511 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 pbn_b1_2_115200 },
4514 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 pbn_b2_2_115200 },
4517 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519 pbn_b1_4_115200 },
4520 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522 pbn_b1_8_115200 },
4523 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 pbn_b1_8_115200 },
4526 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528 pbn_b1_4_115200 },
4529 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531 pbn_b1_2_115200 },
4532 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534 pbn_b1_4_115200 },
4535 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537 pbn_b1_2_115200 },
4538 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4539 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4540 pbn_b2_4_115200 },
4541 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4543 pbn_b2_2_115200 },
4544 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4546 pbn_b2_1_115200 },
4547 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549 pbn_b2_4_115200 },
4550 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552 pbn_b2_2_115200 },
4553 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4554 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4555 pbn_b2_1_115200 },
4556 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4557 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4558 pbn_b0_8_115200 },
4559
4560 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4561 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4562 0, 0,
4563 pbn_b0_4_921600 },
4564 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4565 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4566 0, 0,
4567 pbn_b0_4_1152000 },
4568 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570 pbn_b0_bt_2_921600 },
4571
4572 /*
4573 * The below card is a little controversial since it is the
4574 * subject of a PCI vendor/device ID clash. (See
4575 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4576 * For now just used the hex ID 0x950a.
4577 */
4578 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4579 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4580 0, 0, pbn_b0_2_115200 },
4581 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4582 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4583 0, 0, pbn_b0_2_115200 },
4584 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_b0_2_1130000 },
4587 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4588 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4589 pbn_b0_1_921600 },
4590 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_b0_4_115200 },
4593 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_b0_bt_2_921600 },
4596 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4597 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4598 pbn_b2_8_1152000 },
4599
4600 /*
4601 * Oxford Semiconductor Inc. Tornado PCI express device range.
4602 */
4603 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b0_1_4000000 },
4606 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_b0_1_4000000 },
4609 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_oxsemi_1_4000000 },
4612 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_oxsemi_1_4000000 },
4615 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_b0_1_4000000 },
4618 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_b0_1_4000000 },
4621 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_oxsemi_1_4000000 },
4624 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_oxsemi_1_4000000 },
4627 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_b0_1_4000000 },
4630 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_b0_1_4000000 },
4633 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_b0_1_4000000 },
4636 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_b0_1_4000000 },
4639 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_oxsemi_2_4000000 },
4642 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_oxsemi_2_4000000 },
4645 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_oxsemi_4_4000000 },
4648 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_oxsemi_4_4000000 },
4651 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_oxsemi_8_4000000 },
4654 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_oxsemi_8_4000000 },
4657 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659 pbn_oxsemi_1_4000000 },
4660 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_oxsemi_1_4000000 },
4663 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 pbn_oxsemi_1_4000000 },
4666 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4668 pbn_oxsemi_1_4000000 },
4669 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4671 pbn_oxsemi_1_4000000 },
4672 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 pbn_oxsemi_1_4000000 },
4675 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677 pbn_oxsemi_1_4000000 },
4678 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680 pbn_oxsemi_1_4000000 },
4681 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683 pbn_oxsemi_1_4000000 },
4684 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686 pbn_oxsemi_1_4000000 },
4687 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689 pbn_oxsemi_1_4000000 },
4690 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692 pbn_oxsemi_1_4000000 },
4693 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 pbn_oxsemi_1_4000000 },
4696 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698 pbn_oxsemi_1_4000000 },
4699 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 pbn_oxsemi_1_4000000 },
4702 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 pbn_oxsemi_1_4000000 },
4705 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_oxsemi_1_4000000 },
4708 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_oxsemi_1_4000000 },
4711 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 pbn_oxsemi_1_4000000 },
4714 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_oxsemi_1_4000000 },
4717 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_oxsemi_1_4000000 },
4720 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_oxsemi_1_4000000 },
4723 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 pbn_oxsemi_1_4000000 },
4726 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_oxsemi_1_4000000 },
4729 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_oxsemi_1_4000000 },
4732 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_oxsemi_1_4000000 },
4735 /*
4736 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4737 */
4738 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4739 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4740 pbn_oxsemi_1_4000000 },
4741 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4742 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4743 pbn_oxsemi_2_4000000 },
4744 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4745 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4746 pbn_oxsemi_4_4000000 },
4747 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4748 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4749 pbn_oxsemi_8_4000000 },
4750
4751 /*
4752 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4753 */
4754 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4755 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4756 pbn_oxsemi_2_4000000 },
4757
4758 /*
4759 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4760 * from skokodyn@yahoo.com
4761 */
4762 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4763 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4764 pbn_sbsxrsio },
4765 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4766 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4767 pbn_sbsxrsio },
4768 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4769 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4770 pbn_sbsxrsio },
4771 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4772 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4773 pbn_sbsxrsio },
4774
4775 /*
4776 * Digitan DS560-558, from jimd@esoft.com
4777 */
4778 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 pbn_b1_1_115200 },
4781
4782 /*
4783 * Titan Electronic cards
4784 * The 400L and 800L have a custom setup quirk.
4785 */
4786 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788 pbn_b0_1_921600 },
4789 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791 pbn_b0_2_921600 },
4792 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794 pbn_b0_4_921600 },
4795 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4797 pbn_b0_4_921600 },
4798 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800 pbn_b1_1_921600 },
4801 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4803 pbn_b1_bt_2_921600 },
4804 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806 pbn_b0_bt_4_921600 },
4807 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4809 pbn_b0_bt_8_921600 },
4810 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4812 pbn_b4_bt_2_921600 },
4813 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4815 pbn_b4_bt_4_921600 },
4816 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4818 pbn_b4_bt_8_921600 },
4819 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4821 pbn_b0_4_921600 },
4822 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4824 pbn_b0_4_921600 },
4825 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4827 pbn_b0_4_921600 },
4828 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4830 pbn_oxsemi_1_4000000 },
4831 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4833 pbn_oxsemi_2_4000000 },
4834 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4836 pbn_oxsemi_4_4000000 },
4837 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4839 pbn_oxsemi_8_4000000 },
4840 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4842 pbn_oxsemi_2_4000000 },
4843 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4845 pbn_oxsemi_2_4000000 },
4846 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4848 pbn_b0_bt_2_921600 },
4849 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4851 pbn_b0_4_921600 },
4852 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4854 pbn_b0_4_921600 },
4855 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4857 pbn_b0_4_921600 },
4858 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4860 pbn_b0_4_921600 },
4861
4862 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4864 pbn_b2_1_460800 },
4865 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4867 pbn_b2_1_460800 },
4868 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4870 pbn_b2_1_460800 },
4871 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4872 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4873 pbn_b2_bt_2_921600 },
4874 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4876 pbn_b2_bt_2_921600 },
4877 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879 pbn_b2_bt_2_921600 },
4880 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 pbn_b2_bt_4_921600 },
4883 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 pbn_b2_bt_4_921600 },
4886 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888 pbn_b2_bt_4_921600 },
4889 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 pbn_b0_1_921600 },
4892 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 pbn_b0_1_921600 },
4895 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897 pbn_b0_1_921600 },
4898 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900 pbn_b0_bt_2_921600 },
4901 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903 pbn_b0_bt_2_921600 },
4904 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906 pbn_b0_bt_2_921600 },
4907 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909 pbn_b0_bt_4_921600 },
4910 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912 pbn_b0_bt_4_921600 },
4913 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915 pbn_b0_bt_4_921600 },
4916 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918 pbn_b0_bt_8_921600 },
4919 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921 pbn_b0_bt_8_921600 },
4922 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4924 pbn_b0_bt_8_921600 },
4925
4926 /*
4927 * Computone devices submitted by Doug McNash dmcnash@computone.com
4928 */
4929 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4930 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4931 0, 0, pbn_computone_4 },
4932 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4933 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4934 0, 0, pbn_computone_8 },
4935 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4936 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4937 0, 0, pbn_computone_6 },
4938
4939 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941 pbn_oxsemi },
4942 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4943 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4944 pbn_b0_bt_1_921600 },
4945
4946 /*
4947 * SUNIX (TIMEDIA)
4948 */
4949 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4950 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4951 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4952 pbn_b0_bt_1_921600 },
4953
4954 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4955 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4956 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4957 pbn_b0_bt_1_921600 },
4958
4959 /*
4960 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4961 */
4962 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4964 pbn_b0_bt_8_115200 },
4965 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4967 pbn_b0_bt_8_115200 },
4968
4969 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971 pbn_b0_bt_2_115200 },
4972 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4974 pbn_b0_bt_2_115200 },
4975 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977 pbn_b0_bt_2_115200 },
4978 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4980 pbn_b0_bt_2_115200 },
4981 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4983 pbn_b0_bt_2_115200 },
4984 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986 pbn_b0_bt_4_460800 },
4987 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989 pbn_b0_bt_4_460800 },
4990 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992 pbn_b0_bt_2_460800 },
4993 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4995 pbn_b0_bt_2_460800 },
4996 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998 pbn_b0_bt_2_460800 },
4999 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001 pbn_b0_bt_1_115200 },
5002 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004 pbn_b0_bt_1_460800 },
5005
5006 /*
5007 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5008 * Cards are identified by their subsystem vendor IDs, which
5009 * (in hex) match the model number.
5010 *
5011 * Note that JC140x are RS422/485 cards which require ox950
5012 * ACR = 0x10, and as such are not currently fully supported.
5013 */
5014 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5015 0x1204, 0x0004, 0, 0,
5016 pbn_b0_4_921600 },
5017 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5018 0x1208, 0x0004, 0, 0,
5019 pbn_b0_4_921600 },
5020 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5021 0x1402, 0x0002, 0, 0,
5022 pbn_b0_2_921600 }, */
5023 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5024 0x1404, 0x0004, 0, 0,
5025 pbn_b0_4_921600 }, */
5026 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5027 0x1208, 0x0004, 0, 0,
5028 pbn_b0_4_921600 },
5029
5030 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5031 0x1204, 0x0004, 0, 0,
5032 pbn_b0_4_921600 },
5033 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5034 0x1208, 0x0004, 0, 0,
5035 pbn_b0_4_921600 },
5036 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5037 0x1208, 0x0004, 0, 0,
5038 pbn_b0_4_921600 },
5039 /*
5040 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5041 */
5042 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044 pbn_b1_1_1382400 },
5045
5046 /*
5047 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5048 */
5049 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5051 pbn_b1_1_1382400 },
5052
5053 /*
5054 * RAStel 2 port modem, gerg@moreton.com.au
5055 */
5056 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5058 pbn_b2_bt_2_115200 },
5059
5060 /*
5061 * EKF addition for i960 Boards form EKF with serial port
5062 */
5063 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5064 0xE4BF, PCI_ANY_ID, 0, 0,
5065 pbn_intel_i960 },
5066
5067 /*
5068 * Xircom Cardbus/Ethernet combos
5069 */
5070 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5072 pbn_b0_1_115200 },
5073 /*
5074 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5075 */
5076 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5078 pbn_b0_1_115200 },
5079
5080 /*
5081 * Untested PCI modems, sent in from various folks...
5082 */
5083
5084 /*
5085 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5086 */
5087 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5088 0x1048, 0x1500, 0, 0,
5089 pbn_b1_1_115200 },
5090
5091 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5092 0xFF00, 0, 0, 0,
5093 pbn_sgi_ioc3 },
5094
5095 /*
5096 * HP Diva card
5097 */
5098 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5099 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5100 pbn_b1_1_115200 },
5101 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5103 pbn_b0_5_115200 },
5104 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5106 pbn_b2_1_115200 },
5107
5108 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5110 pbn_b3_2_115200 },
5111 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5113 pbn_b3_4_115200 },
5114 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5116 pbn_b3_8_115200 },
5117
5118 /*
5119 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5120 */
5121 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5122 PCI_ANY_ID, PCI_ANY_ID,
5123 0,
5124 0, pbn_exar_XR17C152 },
5125 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5126 PCI_ANY_ID, PCI_ANY_ID,
5127 0,
5128 0, pbn_exar_XR17C154 },
5129 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5130 PCI_ANY_ID, PCI_ANY_ID,
5131 0,
5132 0, pbn_exar_XR17C158 },
5133 /*
5134 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5135 */
5136 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5137 PCI_ANY_ID, PCI_ANY_ID,
5138 0,
5139 0, pbn_exar_XR17V352 },
5140 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5141 PCI_ANY_ID, PCI_ANY_ID,
5142 0,
5143 0, pbn_exar_XR17V354 },
5144 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5145 PCI_ANY_ID, PCI_ANY_ID,
5146 0,
5147 0, pbn_exar_XR17V358 },
5148 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5149 PCI_ANY_ID, PCI_ANY_ID,
5150 0,
5151 0, pbn_exar_XR17V4358 },
5152 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5153 PCI_ANY_ID, PCI_ANY_ID,
5154 0,
5155 0, pbn_exar_XR17V8358 },
5156 /*
5157 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5158 */
5159 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5161 pbn_b0_1_115200 },
5162 /*
5163 * ITE
5164 */
5165 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5166 PCI_ANY_ID, PCI_ANY_ID,
5167 0, 0,
5168 pbn_b1_bt_1_115200 },
5169
5170 /*
5171 * IntaShield IS-200
5172 */
5173 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5175 pbn_b2_2_115200 },
5176 /*
5177 * IntaShield IS-400
5178 */
5179 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5181 pbn_b2_4_115200 },
5182 /*
5183 * Perle PCI-RAS cards
5184 */
5185 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5186 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5187 0, 0, pbn_b2_4_921600 },
5188 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5189 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5190 0, 0, pbn_b2_8_921600 },
5191
5192 /*
5193 * Mainpine series cards: Fairly standard layout but fools
5194 * parts of the autodetect in some cases and uses otherwise
5195 * unmatched communications subclasses in the PCI Express case
5196 */
5197
5198 { /* RockForceDUO */
5199 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5200 PCI_VENDOR_ID_MAINPINE, 0x0200,
5201 0, 0, pbn_b0_2_115200 },
5202 { /* RockForceQUATRO */
5203 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5204 PCI_VENDOR_ID_MAINPINE, 0x0300,
5205 0, 0, pbn_b0_4_115200 },
5206 { /* RockForceDUO+ */
5207 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5208 PCI_VENDOR_ID_MAINPINE, 0x0400,
5209 0, 0, pbn_b0_2_115200 },
5210 { /* RockForceQUATRO+ */
5211 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5212 PCI_VENDOR_ID_MAINPINE, 0x0500,
5213 0, 0, pbn_b0_4_115200 },
5214 { /* RockForce+ */
5215 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5216 PCI_VENDOR_ID_MAINPINE, 0x0600,
5217 0, 0, pbn_b0_2_115200 },
5218 { /* RockForce+ */
5219 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5220 PCI_VENDOR_ID_MAINPINE, 0x0700,
5221 0, 0, pbn_b0_4_115200 },
5222 { /* RockForceOCTO+ */
5223 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5224 PCI_VENDOR_ID_MAINPINE, 0x0800,
5225 0, 0, pbn_b0_8_115200 },
5226 { /* RockForceDUO+ */
5227 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5228 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5229 0, 0, pbn_b0_2_115200 },
5230 { /* RockForceQUARTRO+ */
5231 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5232 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5233 0, 0, pbn_b0_4_115200 },
5234 { /* RockForceOCTO+ */
5235 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5236 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5237 0, 0, pbn_b0_8_115200 },
5238 { /* RockForceD1 */
5239 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5240 PCI_VENDOR_ID_MAINPINE, 0x2000,
5241 0, 0, pbn_b0_1_115200 },
5242 { /* RockForceF1 */
5243 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5244 PCI_VENDOR_ID_MAINPINE, 0x2100,
5245 0, 0, pbn_b0_1_115200 },
5246 { /* RockForceD2 */
5247 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5248 PCI_VENDOR_ID_MAINPINE, 0x2200,
5249 0, 0, pbn_b0_2_115200 },
5250 { /* RockForceF2 */
5251 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5252 PCI_VENDOR_ID_MAINPINE, 0x2300,
5253 0, 0, pbn_b0_2_115200 },
5254 { /* RockForceD4 */
5255 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5256 PCI_VENDOR_ID_MAINPINE, 0x2400,
5257 0, 0, pbn_b0_4_115200 },
5258 { /* RockForceF4 */
5259 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5260 PCI_VENDOR_ID_MAINPINE, 0x2500,
5261 0, 0, pbn_b0_4_115200 },
5262 { /* RockForceD8 */
5263 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5264 PCI_VENDOR_ID_MAINPINE, 0x2600,
5265 0, 0, pbn_b0_8_115200 },
5266 { /* RockForceF8 */
5267 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5268 PCI_VENDOR_ID_MAINPINE, 0x2700,
5269 0, 0, pbn_b0_8_115200 },
5270 { /* IQ Express D1 */
5271 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5272 PCI_VENDOR_ID_MAINPINE, 0x3000,
5273 0, 0, pbn_b0_1_115200 },
5274 { /* IQ Express F1 */
5275 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5276 PCI_VENDOR_ID_MAINPINE, 0x3100,
5277 0, 0, pbn_b0_1_115200 },
5278 { /* IQ Express D2 */
5279 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5280 PCI_VENDOR_ID_MAINPINE, 0x3200,
5281 0, 0, pbn_b0_2_115200 },
5282 { /* IQ Express F2 */
5283 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5284 PCI_VENDOR_ID_MAINPINE, 0x3300,
5285 0, 0, pbn_b0_2_115200 },
5286 { /* IQ Express D4 */
5287 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5288 PCI_VENDOR_ID_MAINPINE, 0x3400,
5289 0, 0, pbn_b0_4_115200 },
5290 { /* IQ Express F4 */
5291 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5292 PCI_VENDOR_ID_MAINPINE, 0x3500,
5293 0, 0, pbn_b0_4_115200 },
5294 { /* IQ Express D8 */
5295 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5296 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5297 0, 0, pbn_b0_8_115200 },
5298 { /* IQ Express F8 */
5299 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5300 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5301 0, 0, pbn_b0_8_115200 },
5302
5303
5304 /*
5305 * PA Semi PA6T-1682M on-chip UART
5306 */
5307 { PCI_VENDOR_ID_PASEMI, 0xa004,
5308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5309 pbn_pasemi_1682M },
5310
5311 /*
5312 * National Instruments
5313 */
5314 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5316 pbn_b1_16_115200 },
5317 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5319 pbn_b1_8_115200 },
5320 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5322 pbn_b1_bt_4_115200 },
5323 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5325 pbn_b1_bt_2_115200 },
5326 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5328 pbn_b1_bt_4_115200 },
5329 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5331 pbn_b1_bt_2_115200 },
5332 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5334 pbn_b1_16_115200 },
5335 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5337 pbn_b1_8_115200 },
5338 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5340 pbn_b1_bt_4_115200 },
5341 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5343 pbn_b1_bt_2_115200 },
5344 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5346 pbn_b1_bt_4_115200 },
5347 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5349 pbn_b1_bt_2_115200 },
5350 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5351 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5352 pbn_ni8430_2 },
5353 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5355 pbn_ni8430_2 },
5356 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5358 pbn_ni8430_4 },
5359 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5361 pbn_ni8430_4 },
5362 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5364 pbn_ni8430_8 },
5365 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5367 pbn_ni8430_8 },
5368 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5370 pbn_ni8430_16 },
5371 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5373 pbn_ni8430_16 },
5374 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5376 pbn_ni8430_2 },
5377 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5378 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5379 pbn_ni8430_2 },
5380 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5381 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5382 pbn_ni8430_4 },
5383 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5384 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5385 pbn_ni8430_4 },
5386
5387 /*
5388 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5389 */
5390 { PCI_VENDOR_ID_ADDIDATA,
5391 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5392 PCI_ANY_ID,
5393 PCI_ANY_ID,
5394 0,
5395 0,
5396 pbn_b0_4_115200 },
5397
5398 { PCI_VENDOR_ID_ADDIDATA,
5399 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5400 PCI_ANY_ID,
5401 PCI_ANY_ID,
5402 0,
5403 0,
5404 pbn_b0_2_115200 },
5405
5406 { PCI_VENDOR_ID_ADDIDATA,
5407 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5408 PCI_ANY_ID,
5409 PCI_ANY_ID,
5410 0,
5411 0,
5412 pbn_b0_1_115200 },
5413
5414 { PCI_VENDOR_ID_AMCC,
5415 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5416 PCI_ANY_ID,
5417 PCI_ANY_ID,
5418 0,
5419 0,
5420 pbn_b1_8_115200 },
5421
5422 { PCI_VENDOR_ID_ADDIDATA,
5423 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5424 PCI_ANY_ID,
5425 PCI_ANY_ID,
5426 0,
5427 0,
5428 pbn_b0_4_115200 },
5429
5430 { PCI_VENDOR_ID_ADDIDATA,
5431 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5432 PCI_ANY_ID,
5433 PCI_ANY_ID,
5434 0,
5435 0,
5436 pbn_b0_2_115200 },
5437
5438 { PCI_VENDOR_ID_ADDIDATA,
5439 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5440 PCI_ANY_ID,
5441 PCI_ANY_ID,
5442 0,
5443 0,
5444 pbn_b0_1_115200 },
5445
5446 { PCI_VENDOR_ID_ADDIDATA,
5447 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5448 PCI_ANY_ID,
5449 PCI_ANY_ID,
5450 0,
5451 0,
5452 pbn_b0_4_115200 },
5453
5454 { PCI_VENDOR_ID_ADDIDATA,
5455 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5456 PCI_ANY_ID,
5457 PCI_ANY_ID,
5458 0,
5459 0,
5460 pbn_b0_2_115200 },
5461
5462 { PCI_VENDOR_ID_ADDIDATA,
5463 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5464 PCI_ANY_ID,
5465 PCI_ANY_ID,
5466 0,
5467 0,
5468 pbn_b0_1_115200 },
5469
5470 { PCI_VENDOR_ID_ADDIDATA,
5471 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5472 PCI_ANY_ID,
5473 PCI_ANY_ID,
5474 0,
5475 0,
5476 pbn_b0_8_115200 },
5477
5478 { PCI_VENDOR_ID_ADDIDATA,
5479 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5480 PCI_ANY_ID,
5481 PCI_ANY_ID,
5482 0,
5483 0,
5484 pbn_ADDIDATA_PCIe_4_3906250 },
5485
5486 { PCI_VENDOR_ID_ADDIDATA,
5487 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5488 PCI_ANY_ID,
5489 PCI_ANY_ID,
5490 0,
5491 0,
5492 pbn_ADDIDATA_PCIe_2_3906250 },
5493
5494 { PCI_VENDOR_ID_ADDIDATA,
5495 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5496 PCI_ANY_ID,
5497 PCI_ANY_ID,
5498 0,
5499 0,
5500 pbn_ADDIDATA_PCIe_1_3906250 },
5501
5502 { PCI_VENDOR_ID_ADDIDATA,
5503 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5504 PCI_ANY_ID,
5505 PCI_ANY_ID,
5506 0,
5507 0,
5508 pbn_ADDIDATA_PCIe_8_3906250 },
5509
5510 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5511 PCI_VENDOR_ID_IBM, 0x0299,
5512 0, 0, pbn_b0_bt_2_115200 },
5513
5514 /*
5515 * other NetMos 9835 devices are most likely handled by the
5516 * parport_serial driver, check drivers/parport/parport_serial.c
5517 * before adding them here.
5518 */
5519
5520 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5521 0xA000, 0x1000,
5522 0, 0, pbn_b0_1_115200 },
5523
5524 /* the 9901 is a rebranded 9912 */
5525 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5526 0xA000, 0x1000,
5527 0, 0, pbn_b0_1_115200 },
5528
5529 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5530 0xA000, 0x1000,
5531 0, 0, pbn_b0_1_115200 },
5532
5533 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5534 0xA000, 0x1000,
5535 0, 0, pbn_b0_1_115200 },
5536
5537 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5538 0xA000, 0x1000,
5539 0, 0, pbn_b0_1_115200 },
5540
5541 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5542 0xA000, 0x3002,
5543 0, 0, pbn_NETMOS9900_2s_115200 },
5544
5545 /*
5546 * Best Connectivity and Rosewill PCI Multi I/O cards
5547 */
5548
5549 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5550 0xA000, 0x1000,
5551 0, 0, pbn_b0_1_115200 },
5552
5553 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5554 0xA000, 0x3002,
5555 0, 0, pbn_b0_bt_2_115200 },
5556
5557 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5558 0xA000, 0x3004,
5559 0, 0, pbn_b0_bt_4_115200 },
5560 /* Intel CE4100 */
5561 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5563 pbn_ce4100_1_115200 },
5564 /* Intel BayTrail */
5565 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5566 PCI_ANY_ID, PCI_ANY_ID,
5567 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5568 pbn_byt },
5569 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5570 PCI_ANY_ID, PCI_ANY_ID,
5571 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5572 pbn_byt },
5573 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5574 PCI_ANY_ID, PCI_ANY_ID,
5575 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5576 pbn_byt },
5577 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5578 PCI_ANY_ID, PCI_ANY_ID,
5579 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5580 pbn_byt },
5581
5582 /*
5583 * Intel Penwell
5584 */
5585 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1,
5586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5587 pbn_pnw},
5588 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2,
5589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5590 pbn_pnw},
5591 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3,
5592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5593 pbn_pnw},
5594
5595 /*
5596 * Intel Tangier
5597 */
5598 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TNG_UART,
5599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5600 pbn_tng},
5601
5602 /*
5603 * Intel Quark x1000
5604 */
5605 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5607 pbn_qrk },
5608 /*
5609 * Cronyx Omega PCI
5610 */
5611 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5613 pbn_omegapci },
5614
5615 /*
5616 * Broadcom TruManage
5617 */
5618 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5620 pbn_brcm_trumanage },
5621
5622 /*
5623 * AgeStar as-prs2-009
5624 */
5625 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5626 PCI_ANY_ID, PCI_ANY_ID,
5627 0, 0, pbn_b0_bt_2_115200 },
5628
5629 /*
5630 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5631 * so not listed here.
5632 */
5633 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5634 PCI_ANY_ID, PCI_ANY_ID,
5635 0, 0, pbn_b0_bt_4_115200 },
5636
5637 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5638 PCI_ANY_ID, PCI_ANY_ID,
5639 0, 0, pbn_b0_bt_2_115200 },
5640
5641 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5642 PCI_ANY_ID, PCI_ANY_ID,
5643 0, 0, pbn_wch384_4 },
5644
5645 /*
5646 * Commtech, Inc. Fastcom adapters
5647 */
5648 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5649 PCI_ANY_ID, PCI_ANY_ID,
5650 0,
5651 0, pbn_b0_2_1152000_200 },
5652 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5653 PCI_ANY_ID, PCI_ANY_ID,
5654 0,
5655 0, pbn_b0_4_1152000_200 },
5656 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5657 PCI_ANY_ID, PCI_ANY_ID,
5658 0,
5659 0, pbn_b0_4_1152000_200 },
5660 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5661 PCI_ANY_ID, PCI_ANY_ID,
5662 0,
5663 0, pbn_b0_8_1152000_200 },
5664 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5665 PCI_ANY_ID, PCI_ANY_ID,
5666 0,
5667 0, pbn_exar_XR17V352 },
5668 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5669 PCI_ANY_ID, PCI_ANY_ID,
5670 0,
5671 0, pbn_exar_XR17V354 },
5672 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5673 PCI_ANY_ID, PCI_ANY_ID,
5674 0,
5675 0, pbn_exar_XR17V358 },
5676
5677 /* Fintek PCI serial cards */
5678 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5679 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5680 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5681
5682 /*
5683 * These entries match devices with class COMMUNICATION_SERIAL,
5684 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5685 */
5686 { PCI_ANY_ID, PCI_ANY_ID,
5687 PCI_ANY_ID, PCI_ANY_ID,
5688 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5689 0xffff00, pbn_default },
5690 { PCI_ANY_ID, PCI_ANY_ID,
5691 PCI_ANY_ID, PCI_ANY_ID,
5692 PCI_CLASS_COMMUNICATION_MODEM << 8,
5693 0xffff00, pbn_default },
5694 { PCI_ANY_ID, PCI_ANY_ID,
5695 PCI_ANY_ID, PCI_ANY_ID,
5696 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5697 0xffff00, pbn_default },
5698 { 0, }
5699 };
5700
5701 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5702 pci_channel_state_t state)
5703 {
5704 struct serial_private *priv = pci_get_drvdata(dev);
5705
5706 if (state == pci_channel_io_perm_failure)
5707 return PCI_ERS_RESULT_DISCONNECT;
5708
5709 if (priv)
5710 pciserial_suspend_ports(priv);
5711
5712 pci_disable_device(dev);
5713
5714 return PCI_ERS_RESULT_NEED_RESET;
5715 }
5716
5717 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5718 {
5719 int rc;
5720
5721 rc = pci_enable_device(dev);
5722
5723 if (rc)
5724 return PCI_ERS_RESULT_DISCONNECT;
5725
5726 pci_restore_state(dev);
5727 pci_save_state(dev);
5728
5729 return PCI_ERS_RESULT_RECOVERED;
5730 }
5731
5732 static void serial8250_io_resume(struct pci_dev *dev)
5733 {
5734 struct serial_private *priv = pci_get_drvdata(dev);
5735
5736 if (priv)
5737 pciserial_resume_ports(priv);
5738 }
5739
5740 static const struct pci_error_handlers serial8250_err_handler = {
5741 .error_detected = serial8250_io_error_detected,
5742 .slot_reset = serial8250_io_slot_reset,
5743 .resume = serial8250_io_resume,
5744 };
5745
5746 static struct pci_driver serial_pci_driver = {
5747 .name = "serial",
5748 .probe = pciserial_init_one,
5749 .remove = pciserial_remove_one,
5750 .driver = {
5751 .pm = &pciserial_pm_ops,
5752 },
5753 .id_table = serial_pci_tbl,
5754 .err_handler = &serial8250_err_handler,
5755 };
5756
5757 module_pci_driver(serial_pci_driver);
5758
5759 MODULE_LICENSE("GPL");
5760 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5761 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux with added FPC-III support