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ARM: ep93xx: move timer to its own file
[linux/fpc-iii.git] / drivers / tty / serial / imx.c
blob2c90dc31bfaabc0242e168dd688faadadd9f164a
1 /*
2 * Driver for Motorola/Freescale IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/rational.h>
37 #include <linux/slab.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/io.h>
41 #include <linux/dma-mapping.h>
42
43 #include <asm/irq.h>
44 #include <linux/platform_data/serial-imx.h>
45 #include <linux/platform_data/dma-imx.h>
46
47 /* Register definitions */
48 #define URXD0 0x0 /* Receiver Register */
49 #define URTX0 0x40 /* Transmitter Register */
50 #define UCR1 0x80 /* Control Register 1 */
51 #define UCR2 0x84 /* Control Register 2 */
52 #define UCR3 0x88 /* Control Register 3 */
53 #define UCR4 0x8c /* Control Register 4 */
54 #define UFCR 0x90 /* FIFO Control Register */
55 #define USR1 0x94 /* Status Register 1 */
56 #define USR2 0x98 /* Status Register 2 */
57 #define UESC 0x9c /* Escape Character Register */
58 #define UTIM 0xa0 /* Escape Timer Register */
59 #define UBIR 0xa4 /* BRM Incremental Register */
60 #define UBMR 0xa8 /* BRM Modulator Register */
61 #define UBRC 0xac /* Baud Rate Count Register */
62 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
63 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
64 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
65
66 /* UART Control Register Bit Fields.*/
67 #define URXD_DUMMY_READ (1<<16)
68 #define URXD_CHARRDY (1<<15)
69 #define URXD_ERR (1<<14)
70 #define URXD_OVRRUN (1<<13)
71 #define URXD_FRMERR (1<<12)
72 #define URXD_BRK (1<<11)
73 #define URXD_PRERR (1<<10)
74 #define URXD_RX_DATA (0xFF<<0)
75 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
76 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
77 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
78 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
79 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
80 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
81 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
82 #define UCR1_IREN (1<<7) /* Infrared interface enable */
83 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
84 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
85 #define UCR1_SNDBRK (1<<4) /* Send break */
86 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
87 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
88 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
89 #define UCR1_DOZE (1<<1) /* Doze */
90 #define UCR1_UARTEN (1<<0) /* UART enabled */
91 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
92 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
93 #define UCR2_CTSC (1<<13) /* CTS pin control */
94 #define UCR2_CTS (1<<12) /* Clear to send */
95 #define UCR2_ESCEN (1<<11) /* Escape enable */
96 #define UCR2_PREN (1<<8) /* Parity enable */
97 #define UCR2_PROE (1<<7) /* Parity odd/even */
98 #define UCR2_STPB (1<<6) /* Stop */
99 #define UCR2_WS (1<<5) /* Word size */
100 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
101 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
102 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
103 #define UCR2_RXEN (1<<1) /* Receiver enabled */
104 #define UCR2_SRST (1<<0) /* SW reset */
105 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
106 #define UCR3_PARERREN (1<<12) /* Parity enable */
107 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
108 #define UCR3_DSR (1<<10) /* Data set ready */
109 #define UCR3_DCD (1<<9) /* Data carrier detect */
110 #define UCR3_RI (1<<8) /* Ring indicator */
111 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
112 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
113 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
114 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
115 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
116 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
117 #define UCR3_BPEN (1<<0) /* Preset registers enable */
118 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
119 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
120 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
121 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
122 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
123 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
124 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
125 #define UCR4_IRSC (1<<5) /* IR special case */
126 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
127 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
128 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
129 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
130 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
131 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
132 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
133 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
134 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136 #define USR1_RTSS (1<<14) /* RTS pin status */
137 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138 #define USR1_RTSD (1<<12) /* RTS delta */
139 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149 #define USR2_IDLE (1<<12) /* Idle condition */
150 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151 #define USR2_WAKE (1<<7) /* Wake */
152 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153 #define USR2_TXDC (1<<3) /* Transmitter complete */
154 #define USR2_BRCD (1<<2) /* Break condition */
155 #define USR2_ORE (1<<1) /* Overrun error */
156 #define USR2_RDR (1<<0) /* Recv data ready */
157 #define UTS_FRCPERR (1<<13) /* Force parity error */
158 #define UTS_LOOP (1<<12) /* Loop tx and rx */
159 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161 #define UTS_TXFULL (1<<4) /* TxFIFO full */
162 #define UTS_RXFULL (1<<3) /* RxFIFO full */
163 #define UTS_SOFTRST (1<<0) /* Software reset */
164
165 /* We've been assigned a range on the "Low-density serial ports" major */
166 #define SERIAL_IMX_MAJOR 207
167 #define MINOR_START 16
168 #define DEV_NAME "ttymxc"
169
170 /*
171 * This determines how often we check the modem status signals
172 * for any change. They generally aren't connected to an IRQ
173 * so we have to poll them. We also check immediately before
174 * filling the TX fifo incase CTS has been dropped.
175 */
176 #define MCTRL_TIMEOUT (250*HZ/1000)
177
178 #define DRIVER_NAME "IMX-uart"
179
180 #define UART_NR 8
181
182 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
183 enum imx_uart_type {
184 IMX1_UART,
185 IMX21_UART,
186 IMX6Q_UART,
187 };
188
189 /* device type dependent stuff */
190 struct imx_uart_data {
191 unsigned uts_reg;
192 enum imx_uart_type devtype;
193 };
194
195 struct imx_port {
196 struct uart_port port;
197 struct timer_list timer;
198 unsigned int old_status;
199 unsigned int have_rtscts:1;
200 unsigned int dte_mode:1;
201 unsigned int irda_inv_rx:1;
202 unsigned int irda_inv_tx:1;
203 unsigned short trcv_delay; /* transceiver delay */
204 struct clk *clk_ipg;
205 struct clk *clk_per;
206 const struct imx_uart_data *devdata;
207
208 /* DMA fields */
209 unsigned int dma_is_inited:1;
210 unsigned int dma_is_enabled:1;
211 unsigned int dma_is_rxing:1;
212 unsigned int dma_is_txing:1;
213 struct dma_chan *dma_chan_rx, *dma_chan_tx;
214 struct scatterlist rx_sgl, tx_sgl[2];
215 void *rx_buf;
216 unsigned int tx_bytes;
217 unsigned int dma_tx_nents;
218 wait_queue_head_t dma_wait;
219 };
220
221 struct imx_port_ucrs {
222 unsigned int ucr1;
223 unsigned int ucr2;
224 unsigned int ucr3;
225 };
226
227 static struct imx_uart_data imx_uart_devdata[] = {
228 [IMX1_UART] = {
229 .uts_reg = IMX1_UTS,
230 .devtype = IMX1_UART,
231 },
232 [IMX21_UART] = {
233 .uts_reg = IMX21_UTS,
234 .devtype = IMX21_UART,
235 },
236 [IMX6Q_UART] = {
237 .uts_reg = IMX21_UTS,
238 .devtype = IMX6Q_UART,
239 },
240 };
241
242 static const struct platform_device_id imx_uart_devtype[] = {
243 {
244 .name = "imx1-uart",
245 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
246 }, {
247 .name = "imx21-uart",
248 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
249 }, {
250 .name = "imx6q-uart",
251 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
252 }, {
253 /* sentinel */
254 }
255 };
256 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
257
258 static const struct of_device_id imx_uart_dt_ids[] = {
259 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
260 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
261 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
262 { /* sentinel */ }
263 };
264 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
265
266 static inline unsigned uts_reg(struct imx_port *sport)
267 {
268 return sport->devdata->uts_reg;
269 }
270
271 static inline int is_imx1_uart(struct imx_port *sport)
272 {
273 return sport->devdata->devtype == IMX1_UART;
274 }
275
276 static inline int is_imx21_uart(struct imx_port *sport)
277 {
278 return sport->devdata->devtype == IMX21_UART;
279 }
280
281 static inline int is_imx6q_uart(struct imx_port *sport)
282 {
283 return sport->devdata->devtype == IMX6Q_UART;
284 }
285 /*
286 * Save and restore functions for UCR1, UCR2 and UCR3 registers
287 */
288 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
289 static void imx_port_ucrs_save(struct uart_port *port,
290 struct imx_port_ucrs *ucr)
291 {
292 /* save control registers */
293 ucr->ucr1 = readl(port->membase + UCR1);
294 ucr->ucr2 = readl(port->membase + UCR2);
295 ucr->ucr3 = readl(port->membase + UCR3);
296 }
297
298 static void imx_port_ucrs_restore(struct uart_port *port,
299 struct imx_port_ucrs *ucr)
300 {
301 /* restore control registers */
302 writel(ucr->ucr1, port->membase + UCR1);
303 writel(ucr->ucr2, port->membase + UCR2);
304 writel(ucr->ucr3, port->membase + UCR3);
305 }
306 #endif
307
308 /*
309 * Handle any change of modem status signal since we were last called.
310 */
311 static void imx_mctrl_check(struct imx_port *sport)
312 {
313 unsigned int status, changed;
314
315 status = sport->port.ops->get_mctrl(&sport->port);
316 changed = status ^ sport->old_status;
317
318 if (changed == 0)
319 return;
320
321 sport->old_status = status;
322
323 if (changed & TIOCM_RI)
324 sport->port.icount.rng++;
325 if (changed & TIOCM_DSR)
326 sport->port.icount.dsr++;
327 if (changed & TIOCM_CAR)
328 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
329 if (changed & TIOCM_CTS)
330 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
331
332 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
333 }
334
335 /*
336 * This is our per-port timeout handler, for checking the
337 * modem status signals.
338 */
339 static void imx_timeout(unsigned long data)
340 {
341 struct imx_port *sport = (struct imx_port *)data;
342 unsigned long flags;
343
344 if (sport->port.state) {
345 spin_lock_irqsave(&sport->port.lock, flags);
346 imx_mctrl_check(sport);
347 spin_unlock_irqrestore(&sport->port.lock, flags);
348
349 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
350 }
351 }
352
353 /*
354 * interrupts disabled on entry
355 */
356 static void imx_stop_tx(struct uart_port *port)
357 {
358 struct imx_port *sport = (struct imx_port *)port;
359 unsigned long temp;
360
361 /*
362 * We are maybe in the SMP context, so if the DMA TX thread is running
363 * on other cpu, we have to wait for it to finish.
364 */
365 if (sport->dma_is_enabled && sport->dma_is_txing)
366 return;
367
368 temp = readl(port->membase + UCR1);
369 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
370
371 /* in rs485 mode disable transmitter if shifter is empty */
372 if (port->rs485.flags & SER_RS485_ENABLED &&
373 readl(port->membase + USR2) & USR2_TXDC) {
374 temp = readl(port->membase + UCR2);
375 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
376 temp &= ~UCR2_CTS;
377 else
378 temp |= UCR2_CTS;
379 writel(temp, port->membase + UCR2);
380
381 temp = readl(port->membase + UCR4);
382 temp &= ~UCR4_TCEN;
383 writel(temp, port->membase + UCR4);
384 }
385 }
386
387 /*
388 * interrupts disabled on entry
389 */
390 static void imx_stop_rx(struct uart_port *port)
391 {
392 struct imx_port *sport = (struct imx_port *)port;
393 unsigned long temp;
394
395 if (sport->dma_is_enabled && sport->dma_is_rxing) {
396 if (sport->port.suspended) {
397 dmaengine_terminate_all(sport->dma_chan_rx);
398 sport->dma_is_rxing = 0;
399 } else {
400 return;
401 }
402 }
403
404 temp = readl(sport->port.membase + UCR2);
405 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
406
407 /* disable the `Receiver Ready Interrrupt` */
408 temp = readl(sport->port.membase + UCR1);
409 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
410 }
411
412 /*
413 * Set the modem control timer to fire immediately.
414 */
415 static void imx_enable_ms(struct uart_port *port)
416 {
417 struct imx_port *sport = (struct imx_port *)port;
418
419 mod_timer(&sport->timer, jiffies);
420 }
421
422 static void imx_dma_tx(struct imx_port *sport);
423 static inline void imx_transmit_buffer(struct imx_port *sport)
424 {
425 struct circ_buf *xmit = &sport->port.state->xmit;
426 unsigned long temp;
427
428 if (sport->port.x_char) {
429 /* Send next char */
430 writel(sport->port.x_char, sport->port.membase + URTX0);
431 sport->port.icount.tx++;
432 sport->port.x_char = 0;
433 return;
434 }
435
436 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
437 imx_stop_tx(&sport->port);
438 return;
439 }
440
441 if (sport->dma_is_enabled) {
442 /*
443 * We've just sent a X-char Ensure the TX DMA is enabled
444 * and the TX IRQ is disabled.
445 **/
446 temp = readl(sport->port.membase + UCR1);
447 temp &= ~UCR1_TXMPTYEN;
448 if (sport->dma_is_txing) {
449 temp |= UCR1_TDMAEN;
450 writel(temp, sport->port.membase + UCR1);
451 } else {
452 writel(temp, sport->port.membase + UCR1);
453 imx_dma_tx(sport);
454 }
455 }
456
457 while (!uart_circ_empty(xmit) &&
458 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
459 /* send xmit->buf[xmit->tail]
460 * out the port here */
461 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
462 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
463 sport->port.icount.tx++;
464 }
465
466 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
467 uart_write_wakeup(&sport->port);
468
469 if (uart_circ_empty(xmit))
470 imx_stop_tx(&sport->port);
471 }
472
473 static void dma_tx_callback(void *data)
474 {
475 struct imx_port *sport = data;
476 struct scatterlist *sgl = &sport->tx_sgl[0];
477 struct circ_buf *xmit = &sport->port.state->xmit;
478 unsigned long flags;
479 unsigned long temp;
480
481 spin_lock_irqsave(&sport->port.lock, flags);
482
483 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
484
485 temp = readl(sport->port.membase + UCR1);
486 temp &= ~UCR1_TDMAEN;
487 writel(temp, sport->port.membase + UCR1);
488
489 /* update the stat */
490 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
491 sport->port.icount.tx += sport->tx_bytes;
492
493 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
494
495 sport->dma_is_txing = 0;
496
497 spin_unlock_irqrestore(&sport->port.lock, flags);
498
499 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
500 uart_write_wakeup(&sport->port);
501
502 if (waitqueue_active(&sport->dma_wait)) {
503 wake_up(&sport->dma_wait);
504 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
505 return;
506 }
507
508 spin_lock_irqsave(&sport->port.lock, flags);
509 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
510 imx_dma_tx(sport);
511 spin_unlock_irqrestore(&sport->port.lock, flags);
512 }
513
514 static void imx_dma_tx(struct imx_port *sport)
515 {
516 struct circ_buf *xmit = &sport->port.state->xmit;
517 struct scatterlist *sgl = sport->tx_sgl;
518 struct dma_async_tx_descriptor *desc;
519 struct dma_chan *chan = sport->dma_chan_tx;
520 struct device *dev = sport->port.dev;
521 unsigned long temp;
522 int ret;
523
524 if (sport->dma_is_txing)
525 return;
526
527 sport->tx_bytes = uart_circ_chars_pending(xmit);
528
529 if (xmit->tail < xmit->head) {
530 sport->dma_tx_nents = 1;
531 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
532 } else {
533 sport->dma_tx_nents = 2;
534 sg_init_table(sgl, 2);
535 sg_set_buf(sgl, xmit->buf + xmit->tail,
536 UART_XMIT_SIZE - xmit->tail);
537 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
538 }
539
540 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
541 if (ret == 0) {
542 dev_err(dev, "DMA mapping error for TX.\n");
543 return;
544 }
545 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
546 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
547 if (!desc) {
548 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
549 DMA_TO_DEVICE);
550 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
551 return;
552 }
553 desc->callback = dma_tx_callback;
554 desc->callback_param = sport;
555
556 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
557 uart_circ_chars_pending(xmit));
558
559 temp = readl(sport->port.membase + UCR1);
560 temp |= UCR1_TDMAEN;
561 writel(temp, sport->port.membase + UCR1);
562
563 /* fire it */
564 sport->dma_is_txing = 1;
565 dmaengine_submit(desc);
566 dma_async_issue_pending(chan);
567 return;
568 }
569
570 /*
571 * interrupts disabled on entry
572 */
573 static void imx_start_tx(struct uart_port *port)
574 {
575 struct imx_port *sport = (struct imx_port *)port;
576 unsigned long temp;
577
578 if (port->rs485.flags & SER_RS485_ENABLED) {
579 /* enable transmitter and shifter empty irq */
580 temp = readl(port->membase + UCR2);
581 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
582 temp &= ~UCR2_CTS;
583 else
584 temp |= UCR2_CTS;
585 writel(temp, port->membase + UCR2);
586
587 temp = readl(port->membase + UCR4);
588 temp |= UCR4_TCEN;
589 writel(temp, port->membase + UCR4);
590 }
591
592 if (!sport->dma_is_enabled) {
593 temp = readl(sport->port.membase + UCR1);
594 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
595 }
596
597 if (sport->dma_is_enabled) {
598 if (sport->port.x_char) {
599 /* We have X-char to send, so enable TX IRQ and
600 * disable TX DMA to let TX interrupt to send X-char */
601 temp = readl(sport->port.membase + UCR1);
602 temp &= ~UCR1_TDMAEN;
603 temp |= UCR1_TXMPTYEN;
604 writel(temp, sport->port.membase + UCR1);
605 return;
606 }
607
608 if (!uart_circ_empty(&port->state->xmit) &&
609 !uart_tx_stopped(port))
610 imx_dma_tx(sport);
611 return;
612 }
613 }
614
615 static irqreturn_t imx_rtsint(int irq, void *dev_id)
616 {
617 struct imx_port *sport = dev_id;
618 unsigned int val;
619 unsigned long flags;
620
621 spin_lock_irqsave(&sport->port.lock, flags);
622
623 writel(USR1_RTSD, sport->port.membase + USR1);
624 val = readl(sport->port.membase + USR1) & USR1_RTSS;
625 uart_handle_cts_change(&sport->port, !!val);
626 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
627
628 spin_unlock_irqrestore(&sport->port.lock, flags);
629 return IRQ_HANDLED;
630 }
631
632 static irqreturn_t imx_txint(int irq, void *dev_id)
633 {
634 struct imx_port *sport = dev_id;
635 unsigned long flags;
636
637 spin_lock_irqsave(&sport->port.lock, flags);
638 imx_transmit_buffer(sport);
639 spin_unlock_irqrestore(&sport->port.lock, flags);
640 return IRQ_HANDLED;
641 }
642
643 static irqreturn_t imx_rxint(int irq, void *dev_id)
644 {
645 struct imx_port *sport = dev_id;
646 unsigned int rx, flg, ignored = 0;
647 struct tty_port *port = &sport->port.state->port;
648 unsigned long flags, temp;
649
650 spin_lock_irqsave(&sport->port.lock, flags);
651
652 while (readl(sport->port.membase + USR2) & USR2_RDR) {
653 flg = TTY_NORMAL;
654 sport->port.icount.rx++;
655
656 rx = readl(sport->port.membase + URXD0);
657
658 temp = readl(sport->port.membase + USR2);
659 if (temp & USR2_BRCD) {
660 writel(USR2_BRCD, sport->port.membase + USR2);
661 if (uart_handle_break(&sport->port))
662 continue;
663 }
664
665 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
666 continue;
667
668 if (unlikely(rx & URXD_ERR)) {
669 if (rx & URXD_BRK)
670 sport->port.icount.brk++;
671 else if (rx & URXD_PRERR)
672 sport->port.icount.parity++;
673 else if (rx & URXD_FRMERR)
674 sport->port.icount.frame++;
675 if (rx & URXD_OVRRUN)
676 sport->port.icount.overrun++;
677
678 if (rx & sport->port.ignore_status_mask) {
679 if (++ignored > 100)
680 goto out;
681 continue;
682 }
683
684 rx &= (sport->port.read_status_mask | 0xFF);
685
686 if (rx & URXD_BRK)
687 flg = TTY_BREAK;
688 else if (rx & URXD_PRERR)
689 flg = TTY_PARITY;
690 else if (rx & URXD_FRMERR)
691 flg = TTY_FRAME;
692 if (rx & URXD_OVRRUN)
693 flg = TTY_OVERRUN;
694
695 #ifdef SUPPORT_SYSRQ
696 sport->port.sysrq = 0;
697 #endif
698 }
699
700 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
701 goto out;
702
703 tty_insert_flip_char(port, rx, flg);
704 }
705
706 out:
707 spin_unlock_irqrestore(&sport->port.lock, flags);
708 tty_flip_buffer_push(port);
709 return IRQ_HANDLED;
710 }
711
712 static int start_rx_dma(struct imx_port *sport);
713 /*
714 * If the RXFIFO is filled with some data, and then we
715 * arise a DMA operation to receive them.
716 */
717 static void imx_dma_rxint(struct imx_port *sport)
718 {
719 unsigned long temp;
720 unsigned long flags;
721
722 spin_lock_irqsave(&sport->port.lock, flags);
723
724 temp = readl(sport->port.membase + USR2);
725 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
726 sport->dma_is_rxing = 1;
727
728 /* disable the `Recerver Ready Interrrupt` */
729 temp = readl(sport->port.membase + UCR1);
730 temp &= ~(UCR1_RRDYEN);
731 writel(temp, sport->port.membase + UCR1);
732
733 /* tell the DMA to receive the data. */
734 start_rx_dma(sport);
735 }
736
737 spin_unlock_irqrestore(&sport->port.lock, flags);
738 }
739
740 static irqreturn_t imx_int(int irq, void *dev_id)
741 {
742 struct imx_port *sport = dev_id;
743 unsigned int sts;
744 unsigned int sts2;
745
746 sts = readl(sport->port.membase + USR1);
747 sts2 = readl(sport->port.membase + USR2);
748
749 if (sts & USR1_RRDY) {
750 if (sport->dma_is_enabled)
751 imx_dma_rxint(sport);
752 else
753 imx_rxint(irq, dev_id);
754 }
755
756 if ((sts & USR1_TRDY &&
757 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
758 (sts2 & USR2_TXDC &&
759 readl(sport->port.membase + UCR4) & UCR4_TCEN))
760 imx_txint(irq, dev_id);
761
762 if (sts & USR1_RTSD)
763 imx_rtsint(irq, dev_id);
764
765 if (sts & USR1_AWAKE)
766 writel(USR1_AWAKE, sport->port.membase + USR1);
767
768 if (sts2 & USR2_ORE) {
769 dev_err(sport->port.dev, "Rx FIFO overrun\n");
770 sport->port.icount.overrun++;
771 writel(USR2_ORE, sport->port.membase + USR2);
772 }
773
774 return IRQ_HANDLED;
775 }
776
777 /*
778 * Return TIOCSER_TEMT when transmitter is not busy.
779 */
780 static unsigned int imx_tx_empty(struct uart_port *port)
781 {
782 struct imx_port *sport = (struct imx_port *)port;
783 unsigned int ret;
784
785 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
786
787 /* If the TX DMA is working, return 0. */
788 if (sport->dma_is_enabled && sport->dma_is_txing)
789 ret = 0;
790
791 return ret;
792 }
793
794 /*
795 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
796 */
797 static unsigned int imx_get_mctrl(struct uart_port *port)
798 {
799 struct imx_port *sport = (struct imx_port *)port;
800 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
801
802 if (readl(sport->port.membase + USR1) & USR1_RTSS)
803 tmp |= TIOCM_CTS;
804
805 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
806 tmp |= TIOCM_RTS;
807
808 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
809 tmp |= TIOCM_LOOP;
810
811 return tmp;
812 }
813
814 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
815 {
816 struct imx_port *sport = (struct imx_port *)port;
817 unsigned long temp;
818
819 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
820 temp = readl(sport->port.membase + UCR2);
821 temp &= ~(UCR2_CTS | UCR2_CTSC);
822 if (mctrl & TIOCM_RTS)
823 temp |= UCR2_CTS | UCR2_CTSC;
824 writel(temp, sport->port.membase + UCR2);
825 }
826
827 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
828 if (mctrl & TIOCM_LOOP)
829 temp |= UTS_LOOP;
830 writel(temp, sport->port.membase + uts_reg(sport));
831 }
832
833 /*
834 * Interrupts always disabled.
835 */
836 static void imx_break_ctl(struct uart_port *port, int break_state)
837 {
838 struct imx_port *sport = (struct imx_port *)port;
839 unsigned long flags, temp;
840
841 spin_lock_irqsave(&sport->port.lock, flags);
842
843 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
844
845 if (break_state != 0)
846 temp |= UCR1_SNDBRK;
847
848 writel(temp, sport->port.membase + UCR1);
849
850 spin_unlock_irqrestore(&sport->port.lock, flags);
851 }
852
853 #define TXTL 2 /* reset default */
854 #define RXTL 1 /* reset default */
855
856 static void imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
857 {
858 unsigned int val;
859
860 /* set receiver / transmitter trigger level */
861 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
862 val |= TXTL << UFCR_TXTL_SHF | RXTL;
863 writel(val, sport->port.membase + UFCR);
864 }
865
866 #define RX_BUF_SIZE (PAGE_SIZE)
867 static void imx_rx_dma_done(struct imx_port *sport)
868 {
869 unsigned long temp;
870 unsigned long flags;
871
872 spin_lock_irqsave(&sport->port.lock, flags);
873
874 /* Enable this interrupt when the RXFIFO is empty. */
875 temp = readl(sport->port.membase + UCR1);
876 temp |= UCR1_RRDYEN;
877 writel(temp, sport->port.membase + UCR1);
878
879 sport->dma_is_rxing = 0;
880
881 /* Is the shutdown waiting for us? */
882 if (waitqueue_active(&sport->dma_wait))
883 wake_up(&sport->dma_wait);
884
885 spin_unlock_irqrestore(&sport->port.lock, flags);
886 }
887
888 /*
889 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
890 * [1] the RX DMA buffer is full.
891 * [2] the Aging timer expires(wait for 8 bytes long)
892 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
893 *
894 * The [2] is trigger when a character was been sitting in the FIFO
895 * meanwhile [3] can wait for 32 bytes long when the RX line is
896 * on IDLE state and RxFIFO is empty.
897 */
898 static void dma_rx_callback(void *data)
899 {
900 struct imx_port *sport = data;
901 struct dma_chan *chan = sport->dma_chan_rx;
902 struct scatterlist *sgl = &sport->rx_sgl;
903 struct tty_port *port = &sport->port.state->port;
904 struct dma_tx_state state;
905 enum dma_status status;
906 unsigned int count;
907
908 /* unmap it first */
909 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
910
911 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
912 count = RX_BUF_SIZE - state.residue;
913
914 if (readl(sport->port.membase + USR2) & USR2_IDLE) {
915 /* In condition [3] the SDMA counted up too early */
916 count--;
917
918 writel(USR2_IDLE, sport->port.membase + USR2);
919 }
920
921 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
922
923 if (count) {
924 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ))
925 tty_insert_flip_string(port, sport->rx_buf, count);
926 tty_flip_buffer_push(port);
927
928 start_rx_dma(sport);
929 } else if (readl(sport->port.membase + USR2) & USR2_RDR) {
930 /*
931 * start rx_dma directly once data in RXFIFO, more efficient
932 * than before:
933 * 1. call imx_rx_dma_done to stop dma if no data received
934 * 2. wait next RDR interrupt to start dma transfer.
935 */
936 start_rx_dma(sport);
937 } else {
938 /*
939 * stop dma to prevent too many IDLE event trigged if no data
940 * in RXFIFO
941 */
942 imx_rx_dma_done(sport);
943 }
944 }
945
946 static int start_rx_dma(struct imx_port *sport)
947 {
948 struct scatterlist *sgl = &sport->rx_sgl;
949 struct dma_chan *chan = sport->dma_chan_rx;
950 struct device *dev = sport->port.dev;
951 struct dma_async_tx_descriptor *desc;
952 int ret;
953
954 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
955 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
956 if (ret == 0) {
957 dev_err(dev, "DMA mapping error for RX.\n");
958 return -EINVAL;
959 }
960 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
961 DMA_PREP_INTERRUPT);
962 if (!desc) {
963 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
964 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
965 return -EINVAL;
966 }
967 desc->callback = dma_rx_callback;
968 desc->callback_param = sport;
969
970 dev_dbg(dev, "RX: prepare for the DMA.\n");
971 dmaengine_submit(desc);
972 dma_async_issue_pending(chan);
973 return 0;
974 }
975
976 static void imx_uart_dma_exit(struct imx_port *sport)
977 {
978 if (sport->dma_chan_rx) {
979 dma_release_channel(sport->dma_chan_rx);
980 sport->dma_chan_rx = NULL;
981
982 kfree(sport->rx_buf);
983 sport->rx_buf = NULL;
984 }
985
986 if (sport->dma_chan_tx) {
987 dma_release_channel(sport->dma_chan_tx);
988 sport->dma_chan_tx = NULL;
989 }
990
991 sport->dma_is_inited = 0;
992 }
993
994 static int imx_uart_dma_init(struct imx_port *sport)
995 {
996 struct dma_slave_config slave_config = {};
997 struct device *dev = sport->port.dev;
998 int ret;
999
1000 /* Prepare for RX : */
1001 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1002 if (!sport->dma_chan_rx) {
1003 dev_dbg(dev, "cannot get the DMA channel.\n");
1004 ret = -EINVAL;
1005 goto err;
1006 }
1007
1008 slave_config.direction = DMA_DEV_TO_MEM;
1009 slave_config.src_addr = sport->port.mapbase + URXD0;
1010 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1011 slave_config.src_maxburst = RXTL;
1012 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1013 if (ret) {
1014 dev_err(dev, "error in RX dma configuration.\n");
1015 goto err;
1016 }
1017
1018 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1019 if (!sport->rx_buf) {
1020 ret = -ENOMEM;
1021 goto err;
1022 }
1023
1024 /* Prepare for TX : */
1025 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1026 if (!sport->dma_chan_tx) {
1027 dev_err(dev, "cannot get the TX DMA channel!\n");
1028 ret = -EINVAL;
1029 goto err;
1030 }
1031
1032 slave_config.direction = DMA_MEM_TO_DEV;
1033 slave_config.dst_addr = sport->port.mapbase + URTX0;
1034 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1035 slave_config.dst_maxburst = TXTL;
1036 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1037 if (ret) {
1038 dev_err(dev, "error in TX dma configuration.");
1039 goto err;
1040 }
1041
1042 sport->dma_is_inited = 1;
1043
1044 return 0;
1045 err:
1046 imx_uart_dma_exit(sport);
1047 return ret;
1048 }
1049
1050 static void imx_enable_dma(struct imx_port *sport)
1051 {
1052 unsigned long temp;
1053
1054 init_waitqueue_head(&sport->dma_wait);
1055
1056 /* set UCR1 */
1057 temp = readl(sport->port.membase + UCR1);
1058 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1059 /* wait for 32 idle frames for IDDMA interrupt */
1060 UCR1_ICD_REG(3);
1061 writel(temp, sport->port.membase + UCR1);
1062
1063 /* set UCR4 */
1064 temp = readl(sport->port.membase + UCR4);
1065 temp |= UCR4_IDDMAEN;
1066 writel(temp, sport->port.membase + UCR4);
1067
1068 sport->dma_is_enabled = 1;
1069 }
1070
1071 static void imx_disable_dma(struct imx_port *sport)
1072 {
1073 unsigned long temp;
1074
1075 /* clear UCR1 */
1076 temp = readl(sport->port.membase + UCR1);
1077 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1078 writel(temp, sport->port.membase + UCR1);
1079
1080 /* clear UCR2 */
1081 temp = readl(sport->port.membase + UCR2);
1082 temp &= ~(UCR2_CTSC | UCR2_CTS);
1083 writel(temp, sport->port.membase + UCR2);
1084
1085 /* clear UCR4 */
1086 temp = readl(sport->port.membase + UCR4);
1087 temp &= ~UCR4_IDDMAEN;
1088 writel(temp, sport->port.membase + UCR4);
1089
1090 sport->dma_is_enabled = 0;
1091 }
1092
1093 /* half the RX buffer size */
1094 #define CTSTL 16
1095
1096 static int imx_startup(struct uart_port *port)
1097 {
1098 struct imx_port *sport = (struct imx_port *)port;
1099 int retval, i;
1100 unsigned long flags, temp;
1101
1102 retval = clk_prepare_enable(sport->clk_per);
1103 if (retval)
1104 return retval;
1105 retval = clk_prepare_enable(sport->clk_ipg);
1106 if (retval) {
1107 clk_disable_unprepare(sport->clk_per);
1108 return retval;
1109 }
1110
1111 imx_setup_ufcr(sport, 0);
1112
1113 /* disable the DREN bit (Data Ready interrupt enable) before
1114 * requesting IRQs
1115 */
1116 temp = readl(sport->port.membase + UCR4);
1117
1118 /* set the trigger level for CTS */
1119 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1120 temp |= CTSTL << UCR4_CTSTL_SHF;
1121
1122 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1123
1124 /* Can we enable the DMA support? */
1125 if (is_imx6q_uart(sport) && !uart_console(port) &&
1126 !sport->dma_is_inited)
1127 imx_uart_dma_init(sport);
1128
1129 spin_lock_irqsave(&sport->port.lock, flags);
1130 /* Reset fifo's and state machines */
1131 i = 100;
1132
1133 temp = readl(sport->port.membase + UCR2);
1134 temp &= ~UCR2_SRST;
1135 writel(temp, sport->port.membase + UCR2);
1136
1137 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1138 udelay(1);
1139
1140 /*
1141 * Finally, clear and enable interrupts
1142 */
1143 writel(USR1_RTSD, sport->port.membase + USR1);
1144 writel(USR2_ORE, sport->port.membase + USR2);
1145
1146 if (sport->dma_is_inited && !sport->dma_is_enabled)
1147 imx_enable_dma(sport);
1148
1149 temp = readl(sport->port.membase + UCR1);
1150 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1151
1152 writel(temp, sport->port.membase + UCR1);
1153
1154 temp = readl(sport->port.membase + UCR4);
1155 temp |= UCR4_OREN;
1156 writel(temp, sport->port.membase + UCR4);
1157
1158 temp = readl(sport->port.membase + UCR2);
1159 temp |= (UCR2_RXEN | UCR2_TXEN);
1160 if (!sport->have_rtscts)
1161 temp |= UCR2_IRTS;
1162 writel(temp, sport->port.membase + UCR2);
1163
1164 if (!is_imx1_uart(sport)) {
1165 temp = readl(sport->port.membase + UCR3);
1166 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1167 writel(temp, sport->port.membase + UCR3);
1168 }
1169
1170 /*
1171 * Enable modem status interrupts
1172 */
1173 imx_enable_ms(&sport->port);
1174 spin_unlock_irqrestore(&sport->port.lock, flags);
1175
1176 return 0;
1177 }
1178
1179 static void imx_shutdown(struct uart_port *port)
1180 {
1181 struct imx_port *sport = (struct imx_port *)port;
1182 unsigned long temp;
1183 unsigned long flags;
1184
1185 if (sport->dma_is_enabled) {
1186 int ret;
1187
1188 /* We have to wait for the DMA to finish. */
1189 ret = wait_event_interruptible(sport->dma_wait,
1190 !sport->dma_is_rxing && !sport->dma_is_txing);
1191 if (ret != 0) {
1192 sport->dma_is_rxing = 0;
1193 sport->dma_is_txing = 0;
1194 dmaengine_terminate_all(sport->dma_chan_tx);
1195 dmaengine_terminate_all(sport->dma_chan_rx);
1196 }
1197 spin_lock_irqsave(&sport->port.lock, flags);
1198 imx_stop_tx(port);
1199 imx_stop_rx(port);
1200 imx_disable_dma(sport);
1201 spin_unlock_irqrestore(&sport->port.lock, flags);
1202 imx_uart_dma_exit(sport);
1203 }
1204
1205 spin_lock_irqsave(&sport->port.lock, flags);
1206 temp = readl(sport->port.membase + UCR2);
1207 temp &= ~(UCR2_TXEN);
1208 writel(temp, sport->port.membase + UCR2);
1209 spin_unlock_irqrestore(&sport->port.lock, flags);
1210
1211 /*
1212 * Stop our timer.
1213 */
1214 del_timer_sync(&sport->timer);
1215
1216 /*
1217 * Disable all interrupts, port and break condition.
1218 */
1219
1220 spin_lock_irqsave(&sport->port.lock, flags);
1221 temp = readl(sport->port.membase + UCR1);
1222 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1223
1224 writel(temp, sport->port.membase + UCR1);
1225 spin_unlock_irqrestore(&sport->port.lock, flags);
1226
1227 clk_disable_unprepare(sport->clk_per);
1228 clk_disable_unprepare(sport->clk_ipg);
1229 }
1230
1231 static void imx_flush_buffer(struct uart_port *port)
1232 {
1233 struct imx_port *sport = (struct imx_port *)port;
1234 struct scatterlist *sgl = &sport->tx_sgl[0];
1235 unsigned long temp;
1236 int i = 100, ubir, ubmr, uts;
1237
1238 if (!sport->dma_chan_tx)
1239 return;
1240
1241 sport->tx_bytes = 0;
1242 dmaengine_terminate_all(sport->dma_chan_tx);
1243 if (sport->dma_is_txing) {
1244 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1245 DMA_TO_DEVICE);
1246 temp = readl(sport->port.membase + UCR1);
1247 temp &= ~UCR1_TDMAEN;
1248 writel(temp, sport->port.membase + UCR1);
1249 sport->dma_is_txing = false;
1250 }
1251
1252 /*
1253 * According to the Reference Manual description of the UART SRST bit:
1254 * "Reset the transmit and receive state machines,
1255 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1256 * and UTS[6-3]". As we don't need to restore the old values from
1257 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1258 */
1259 ubir = readl(sport->port.membase + UBIR);
1260 ubmr = readl(sport->port.membase + UBMR);
1261 uts = readl(sport->port.membase + IMX21_UTS);
1262
1263 temp = readl(sport->port.membase + UCR2);
1264 temp &= ~UCR2_SRST;
1265 writel(temp, sport->port.membase + UCR2);
1266
1267 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1268 udelay(1);
1269
1270 /* Restore the registers */
1271 writel(ubir, sport->port.membase + UBIR);
1272 writel(ubmr, sport->port.membase + UBMR);
1273 writel(uts, sport->port.membase + IMX21_UTS);
1274 }
1275
1276 static void
1277 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1278 struct ktermios *old)
1279 {
1280 struct imx_port *sport = (struct imx_port *)port;
1281 unsigned long flags;
1282 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1283 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1284 unsigned int div, ufcr;
1285 unsigned long num, denom;
1286 uint64_t tdiv64;
1287
1288 /*
1289 * We only support CS7 and CS8.
1290 */
1291 while ((termios->c_cflag & CSIZE) != CS7 &&
1292 (termios->c_cflag & CSIZE) != CS8) {
1293 termios->c_cflag &= ~CSIZE;
1294 termios->c_cflag |= old_csize;
1295 old_csize = CS8;
1296 }
1297
1298 if ((termios->c_cflag & CSIZE) == CS8)
1299 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1300 else
1301 ucr2 = UCR2_SRST | UCR2_IRTS;
1302
1303 if (termios->c_cflag & CRTSCTS) {
1304 if (sport->have_rtscts) {
1305 ucr2 &= ~UCR2_IRTS;
1306
1307 if (port->rs485.flags & SER_RS485_ENABLED) {
1308 /*
1309 * RTS is mandatory for rs485 operation, so keep
1310 * it under manual control and keep transmitter
1311 * disabled.
1312 */
1313 if (!(port->rs485.flags &
1314 SER_RS485_RTS_AFTER_SEND))
1315 ucr2 |= UCR2_CTS;
1316 } else {
1317 ucr2 |= UCR2_CTSC;
1318 }
1319 } else {
1320 termios->c_cflag &= ~CRTSCTS;
1321 }
1322 } else if (port->rs485.flags & SER_RS485_ENABLED)
1323 /* disable transmitter */
1324 if (!(port->rs485.flags & SER_RS485_RTS_AFTER_SEND))
1325 ucr2 |= UCR2_CTS;
1326
1327 if (termios->c_cflag & CSTOPB)
1328 ucr2 |= UCR2_STPB;
1329 if (termios->c_cflag & PARENB) {
1330 ucr2 |= UCR2_PREN;
1331 if (termios->c_cflag & PARODD)
1332 ucr2 |= UCR2_PROE;
1333 }
1334
1335 del_timer_sync(&sport->timer);
1336
1337 /*
1338 * Ask the core to calculate the divisor for us.
1339 */
1340 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1341 quot = uart_get_divisor(port, baud);
1342
1343 spin_lock_irqsave(&sport->port.lock, flags);
1344
1345 sport->port.read_status_mask = 0;
1346 if (termios->c_iflag & INPCK)
1347 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1348 if (termios->c_iflag & (BRKINT | PARMRK))
1349 sport->port.read_status_mask |= URXD_BRK;
1350
1351 /*
1352 * Characters to ignore
1353 */
1354 sport->port.ignore_status_mask = 0;
1355 if (termios->c_iflag & IGNPAR)
1356 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1357 if (termios->c_iflag & IGNBRK) {
1358 sport->port.ignore_status_mask |= URXD_BRK;
1359 /*
1360 * If we're ignoring parity and break indicators,
1361 * ignore overruns too (for real raw support).
1362 */
1363 if (termios->c_iflag & IGNPAR)
1364 sport->port.ignore_status_mask |= URXD_OVRRUN;
1365 }
1366
1367 if ((termios->c_cflag & CREAD) == 0)
1368 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1369
1370 /*
1371 * Update the per-port timeout.
1372 */
1373 uart_update_timeout(port, termios->c_cflag, baud);
1374
1375 /*
1376 * disable interrupts and drain transmitter
1377 */
1378 old_ucr1 = readl(sport->port.membase + UCR1);
1379 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1380 sport->port.membase + UCR1);
1381
1382 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1383 barrier();
1384
1385 /* then, disable everything */
1386 old_txrxen = readl(sport->port.membase + UCR2);
1387 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1388 sport->port.membase + UCR2);
1389 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1390
1391 /* custom-baudrate handling */
1392 div = sport->port.uartclk / (baud * 16);
1393 if (baud == 38400 && quot != div)
1394 baud = sport->port.uartclk / (quot * 16);
1395
1396 div = sport->port.uartclk / (baud * 16);
1397 if (div > 7)
1398 div = 7;
1399 if (!div)
1400 div = 1;
1401
1402 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1403 1 << 16, 1 << 16, &num, &denom);
1404
1405 tdiv64 = sport->port.uartclk;
1406 tdiv64 *= num;
1407 do_div(tdiv64, denom * 16 * div);
1408 tty_termios_encode_baud_rate(termios,
1409 (speed_t)tdiv64, (speed_t)tdiv64);
1410
1411 num -= 1;
1412 denom -= 1;
1413
1414 ufcr = readl(sport->port.membase + UFCR);
1415 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1416 if (sport->dte_mode)
1417 ufcr |= UFCR_DCEDTE;
1418 writel(ufcr, sport->port.membase + UFCR);
1419
1420 writel(num, sport->port.membase + UBIR);
1421 writel(denom, sport->port.membase + UBMR);
1422
1423 if (!is_imx1_uart(sport))
1424 writel(sport->port.uartclk / div / 1000,
1425 sport->port.membase + IMX21_ONEMS);
1426
1427 writel(old_ucr1, sport->port.membase + UCR1);
1428
1429 /* set the parity, stop bits and data size */
1430 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1431
1432 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1433 imx_enable_ms(&sport->port);
1434
1435 spin_unlock_irqrestore(&sport->port.lock, flags);
1436 }
1437
1438 static const char *imx_type(struct uart_port *port)
1439 {
1440 struct imx_port *sport = (struct imx_port *)port;
1441
1442 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1443 }
1444
1445 /*
1446 * Configure/autoconfigure the port.
1447 */
1448 static void imx_config_port(struct uart_port *port, int flags)
1449 {
1450 struct imx_port *sport = (struct imx_port *)port;
1451
1452 if (flags & UART_CONFIG_TYPE)
1453 sport->port.type = PORT_IMX;
1454 }
1455
1456 /*
1457 * Verify the new serial_struct (for TIOCSSERIAL).
1458 * The only change we allow are to the flags and type, and
1459 * even then only between PORT_IMX and PORT_UNKNOWN
1460 */
1461 static int
1462 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1463 {
1464 struct imx_port *sport = (struct imx_port *)port;
1465 int ret = 0;
1466
1467 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1468 ret = -EINVAL;
1469 if (sport->port.irq != ser->irq)
1470 ret = -EINVAL;
1471 if (ser->io_type != UPIO_MEM)
1472 ret = -EINVAL;
1473 if (sport->port.uartclk / 16 != ser->baud_base)
1474 ret = -EINVAL;
1475 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1476 ret = -EINVAL;
1477 if (sport->port.iobase != ser->port)
1478 ret = -EINVAL;
1479 if (ser->hub6 != 0)
1480 ret = -EINVAL;
1481 return ret;
1482 }
1483
1484 #if defined(CONFIG_CONSOLE_POLL)
1485
1486 static int imx_poll_init(struct uart_port *port)
1487 {
1488 struct imx_port *sport = (struct imx_port *)port;
1489 unsigned long flags;
1490 unsigned long temp;
1491 int retval;
1492
1493 retval = clk_prepare_enable(sport->clk_ipg);
1494 if (retval)
1495 return retval;
1496 retval = clk_prepare_enable(sport->clk_per);
1497 if (retval)
1498 clk_disable_unprepare(sport->clk_ipg);
1499
1500 imx_setup_ufcr(sport, 0);
1501
1502 spin_lock_irqsave(&sport->port.lock, flags);
1503
1504 temp = readl(sport->port.membase + UCR1);
1505 if (is_imx1_uart(sport))
1506 temp |= IMX1_UCR1_UARTCLKEN;
1507 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1508 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1509 writel(temp, sport->port.membase + UCR1);
1510
1511 temp = readl(sport->port.membase + UCR2);
1512 temp |= UCR2_RXEN;
1513 writel(temp, sport->port.membase + UCR2);
1514
1515 spin_unlock_irqrestore(&sport->port.lock, flags);
1516
1517 return 0;
1518 }
1519
1520 static int imx_poll_get_char(struct uart_port *port)
1521 {
1522 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1523 return NO_POLL_CHAR;
1524
1525 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1526 }
1527
1528 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1529 {
1530 unsigned int status;
1531
1532 /* drain */
1533 do {
1534 status = readl_relaxed(port->membase + USR1);
1535 } while (~status & USR1_TRDY);
1536
1537 /* write */
1538 writel_relaxed(c, port->membase + URTX0);
1539
1540 /* flush */
1541 do {
1542 status = readl_relaxed(port->membase + USR2);
1543 } while (~status & USR2_TXDC);
1544 }
1545 #endif
1546
1547 static int imx_rs485_config(struct uart_port *port,
1548 struct serial_rs485 *rs485conf)
1549 {
1550 struct imx_port *sport = (struct imx_port *)port;
1551
1552 /* unimplemented */
1553 rs485conf->delay_rts_before_send = 0;
1554 rs485conf->delay_rts_after_send = 0;
1555 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1556
1557 /* RTS is required to control the transmitter */
1558 if (!sport->have_rtscts)
1559 rs485conf->flags &= ~SER_RS485_ENABLED;
1560
1561 if (rs485conf->flags & SER_RS485_ENABLED) {
1562 unsigned long temp;
1563
1564 /* disable transmitter */
1565 temp = readl(sport->port.membase + UCR2);
1566 temp &= ~UCR2_CTSC;
1567 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1568 temp &= ~UCR2_CTS;
1569 else
1570 temp |= UCR2_CTS;
1571 writel(temp, sport->port.membase + UCR2);
1572 }
1573
1574 port->rs485 = *rs485conf;
1575
1576 return 0;
1577 }
1578
1579 static struct uart_ops imx_pops = {
1580 .tx_empty = imx_tx_empty,
1581 .set_mctrl = imx_set_mctrl,
1582 .get_mctrl = imx_get_mctrl,
1583 .stop_tx = imx_stop_tx,
1584 .start_tx = imx_start_tx,
1585 .stop_rx = imx_stop_rx,
1586 .enable_ms = imx_enable_ms,
1587 .break_ctl = imx_break_ctl,
1588 .startup = imx_startup,
1589 .shutdown = imx_shutdown,
1590 .flush_buffer = imx_flush_buffer,
1591 .set_termios = imx_set_termios,
1592 .type = imx_type,
1593 .config_port = imx_config_port,
1594 .verify_port = imx_verify_port,
1595 #if defined(CONFIG_CONSOLE_POLL)
1596 .poll_init = imx_poll_init,
1597 .poll_get_char = imx_poll_get_char,
1598 .poll_put_char = imx_poll_put_char,
1599 #endif
1600 };
1601
1602 static struct imx_port *imx_ports[UART_NR];
1603
1604 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1605 static void imx_console_putchar(struct uart_port *port, int ch)
1606 {
1607 struct imx_port *sport = (struct imx_port *)port;
1608
1609 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1610 barrier();
1611
1612 writel(ch, sport->port.membase + URTX0);
1613 }
1614
1615 /*
1616 * Interrupts are disabled on entering
1617 */
1618 static void
1619 imx_console_write(struct console *co, const char *s, unsigned int count)
1620 {
1621 struct imx_port *sport = imx_ports[co->index];
1622 struct imx_port_ucrs old_ucr;
1623 unsigned int ucr1;
1624 unsigned long flags = 0;
1625 int locked = 1;
1626 int retval;
1627
1628 retval = clk_enable(sport->clk_per);
1629 if (retval)
1630 return;
1631 retval = clk_enable(sport->clk_ipg);
1632 if (retval) {
1633 clk_disable(sport->clk_per);
1634 return;
1635 }
1636
1637 if (sport->port.sysrq)
1638 locked = 0;
1639 else if (oops_in_progress)
1640 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1641 else
1642 spin_lock_irqsave(&sport->port.lock, flags);
1643
1644 /*
1645 * First, save UCR1/2/3 and then disable interrupts
1646 */
1647 imx_port_ucrs_save(&sport->port, &old_ucr);
1648 ucr1 = old_ucr.ucr1;
1649
1650 if (is_imx1_uart(sport))
1651 ucr1 |= IMX1_UCR1_UARTCLKEN;
1652 ucr1 |= UCR1_UARTEN;
1653 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1654
1655 writel(ucr1, sport->port.membase + UCR1);
1656
1657 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1658
1659 uart_console_write(&sport->port, s, count, imx_console_putchar);
1660
1661 /*
1662 * Finally, wait for transmitter to become empty
1663 * and restore UCR1/2/3
1664 */
1665 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1666
1667 imx_port_ucrs_restore(&sport->port, &old_ucr);
1668
1669 if (locked)
1670 spin_unlock_irqrestore(&sport->port.lock, flags);
1671
1672 clk_disable(sport->clk_ipg);
1673 clk_disable(sport->clk_per);
1674 }
1675
1676 /*
1677 * If the port was already initialised (eg, by a boot loader),
1678 * try to determine the current setup.
1679 */
1680 static void __init
1681 imx_console_get_options(struct imx_port *sport, int *baud,
1682 int *parity, int *bits)
1683 {
1684
1685 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1686 /* ok, the port was enabled */
1687 unsigned int ucr2, ubir, ubmr, uartclk;
1688 unsigned int baud_raw;
1689 unsigned int ucfr_rfdiv;
1690
1691 ucr2 = readl(sport->port.membase + UCR2);
1692
1693 *parity = 'n';
1694 if (ucr2 & UCR2_PREN) {
1695 if (ucr2 & UCR2_PROE)
1696 *parity = 'o';
1697 else
1698 *parity = 'e';
1699 }
1700
1701 if (ucr2 & UCR2_WS)
1702 *bits = 8;
1703 else
1704 *bits = 7;
1705
1706 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1707 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1708
1709 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1710 if (ucfr_rfdiv == 6)
1711 ucfr_rfdiv = 7;
1712 else
1713 ucfr_rfdiv = 6 - ucfr_rfdiv;
1714
1715 uartclk = clk_get_rate(sport->clk_per);
1716 uartclk /= ucfr_rfdiv;
1717
1718 { /*
1719 * The next code provides exact computation of
1720 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1721 * without need of float support or long long division,
1722 * which would be required to prevent 32bit arithmetic overflow
1723 */
1724 unsigned int mul = ubir + 1;
1725 unsigned int div = 16 * (ubmr + 1);
1726 unsigned int rem = uartclk % div;
1727
1728 baud_raw = (uartclk / div) * mul;
1729 baud_raw += (rem * mul + div / 2) / div;
1730 *baud = (baud_raw + 50) / 100 * 100;
1731 }
1732
1733 if (*baud != baud_raw)
1734 pr_info("Console IMX rounded baud rate from %d to %d\n",
1735 baud_raw, *baud);
1736 }
1737 }
1738
1739 static int __init
1740 imx_console_setup(struct console *co, char *options)
1741 {
1742 struct imx_port *sport;
1743 int baud = 9600;
1744 int bits = 8;
1745 int parity = 'n';
1746 int flow = 'n';
1747 int retval;
1748
1749 /*
1750 * Check whether an invalid uart number has been specified, and
1751 * if so, search for the first available port that does have
1752 * console support.
1753 */
1754 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1755 co->index = 0;
1756 sport = imx_ports[co->index];
1757 if (sport == NULL)
1758 return -ENODEV;
1759
1760 /* For setting the registers, we only need to enable the ipg clock. */
1761 retval = clk_prepare_enable(sport->clk_ipg);
1762 if (retval)
1763 goto error_console;
1764
1765 if (options)
1766 uart_parse_options(options, &baud, &parity, &bits, &flow);
1767 else
1768 imx_console_get_options(sport, &baud, &parity, &bits);
1769
1770 imx_setup_ufcr(sport, 0);
1771
1772 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1773
1774 clk_disable(sport->clk_ipg);
1775 if (retval) {
1776 clk_unprepare(sport->clk_ipg);
1777 goto error_console;
1778 }
1779
1780 retval = clk_prepare(sport->clk_per);
1781 if (retval)
1782 clk_disable_unprepare(sport->clk_ipg);
1783
1784 error_console:
1785 return retval;
1786 }
1787
1788 static struct uart_driver imx_reg;
1789 static struct console imx_console = {
1790 .name = DEV_NAME,
1791 .write = imx_console_write,
1792 .device = uart_console_device,
1793 .setup = imx_console_setup,
1794 .flags = CON_PRINTBUFFER,
1795 .index = -1,
1796 .data = &imx_reg,
1797 };
1798
1799 #define IMX_CONSOLE &imx_console
1800 #else
1801 #define IMX_CONSOLE NULL
1802 #endif
1803
1804 static struct uart_driver imx_reg = {
1805 .owner = THIS_MODULE,
1806 .driver_name = DRIVER_NAME,
1807 .dev_name = DEV_NAME,
1808 .major = SERIAL_IMX_MAJOR,
1809 .minor = MINOR_START,
1810 .nr = ARRAY_SIZE(imx_ports),
1811 .cons = IMX_CONSOLE,
1812 };
1813
1814 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1815 {
1816 struct imx_port *sport = platform_get_drvdata(dev);
1817 unsigned int val;
1818
1819 /* enable wakeup from i.MX UART */
1820 val = readl(sport->port.membase + UCR3);
1821 val |= UCR3_AWAKEN;
1822 writel(val, sport->port.membase + UCR3);
1823
1824 uart_suspend_port(&imx_reg, &sport->port);
1825
1826 return 0;
1827 }
1828
1829 static int serial_imx_resume(struct platform_device *dev)
1830 {
1831 struct imx_port *sport = platform_get_drvdata(dev);
1832 unsigned int val;
1833
1834 /* disable wakeup from i.MX UART */
1835 val = readl(sport->port.membase + UCR3);
1836 val &= ~UCR3_AWAKEN;
1837 writel(val, sport->port.membase + UCR3);
1838
1839 uart_resume_port(&imx_reg, &sport->port);
1840
1841 return 0;
1842 }
1843
1844 #ifdef CONFIG_OF
1845 /*
1846 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1847 * could successfully get all information from dt or a negative errno.
1848 */
1849 static int serial_imx_probe_dt(struct imx_port *sport,
1850 struct platform_device *pdev)
1851 {
1852 struct device_node *np = pdev->dev.of_node;
1853 const struct of_device_id *of_id =
1854 of_match_device(imx_uart_dt_ids, &pdev->dev);
1855 int ret;
1856
1857 if (!np)
1858 /* no device tree device */
1859 return 1;
1860
1861 ret = of_alias_get_id(np, "serial");
1862 if (ret < 0) {
1863 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1864 return ret;
1865 }
1866 sport->port.line = ret;
1867
1868 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1869 sport->have_rtscts = 1;
1870
1871 if (of_get_property(np, "fsl,dte-mode", NULL))
1872 sport->dte_mode = 1;
1873
1874 sport->devdata = of_id->data;
1875
1876 return 0;
1877 }
1878 #else
1879 static inline int serial_imx_probe_dt(struct imx_port *sport,
1880 struct platform_device *pdev)
1881 {
1882 return 1;
1883 }
1884 #endif
1885
1886 static void serial_imx_probe_pdata(struct imx_port *sport,
1887 struct platform_device *pdev)
1888 {
1889 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1890
1891 sport->port.line = pdev->id;
1892 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1893
1894 if (!pdata)
1895 return;
1896
1897 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1898 sport->have_rtscts = 1;
1899 }
1900
1901 static int serial_imx_probe(struct platform_device *pdev)
1902 {
1903 struct imx_port *sport;
1904 void __iomem *base;
1905 int ret = 0;
1906 struct resource *res;
1907 int txirq, rxirq, rtsirq;
1908
1909 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1910 if (!sport)
1911 return -ENOMEM;
1912
1913 ret = serial_imx_probe_dt(sport, pdev);
1914 if (ret > 0)
1915 serial_imx_probe_pdata(sport, pdev);
1916 else if (ret < 0)
1917 return ret;
1918
1919 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1920 base = devm_ioremap_resource(&pdev->dev, res);
1921 if (IS_ERR(base))
1922 return PTR_ERR(base);
1923
1924 rxirq = platform_get_irq(pdev, 0);
1925 txirq = platform_get_irq(pdev, 1);
1926 rtsirq = platform_get_irq(pdev, 2);
1927
1928 sport->port.dev = &pdev->dev;
1929 sport->port.mapbase = res->start;
1930 sport->port.membase = base;
1931 sport->port.type = PORT_IMX,
1932 sport->port.iotype = UPIO_MEM;
1933 sport->port.irq = rxirq;
1934 sport->port.fifosize = 32;
1935 sport->port.ops = &imx_pops;
1936 sport->port.rs485_config = imx_rs485_config;
1937 sport->port.rs485.flags =
1938 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
1939 sport->port.flags = UPF_BOOT_AUTOCONF;
1940 init_timer(&sport->timer);
1941 sport->timer.function = imx_timeout;
1942 sport->timer.data = (unsigned long)sport;
1943
1944 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1945 if (IS_ERR(sport->clk_ipg)) {
1946 ret = PTR_ERR(sport->clk_ipg);
1947 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1948 return ret;
1949 }
1950
1951 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1952 if (IS_ERR(sport->clk_per)) {
1953 ret = PTR_ERR(sport->clk_per);
1954 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1955 return ret;
1956 }
1957
1958 sport->port.uartclk = clk_get_rate(sport->clk_per);
1959
1960 /*
1961 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1962 * chips only have one interrupt.
1963 */
1964 if (txirq > 0) {
1965 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
1966 dev_name(&pdev->dev), sport);
1967 if (ret)
1968 return ret;
1969
1970 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
1971 dev_name(&pdev->dev), sport);
1972 if (ret)
1973 return ret;
1974 } else {
1975 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
1976 dev_name(&pdev->dev), sport);
1977 if (ret)
1978 return ret;
1979 }
1980
1981 imx_ports[sport->port.line] = sport;
1982
1983 platform_set_drvdata(pdev, sport);
1984
1985 return uart_add_one_port(&imx_reg, &sport->port);
1986 }
1987
1988 static int serial_imx_remove(struct platform_device *pdev)
1989 {
1990 struct imx_port *sport = platform_get_drvdata(pdev);
1991
1992 return uart_remove_one_port(&imx_reg, &sport->port);
1993 }
1994
1995 static struct platform_driver serial_imx_driver = {
1996 .probe = serial_imx_probe,
1997 .remove = serial_imx_remove,
1998
1999 .suspend = serial_imx_suspend,
2000 .resume = serial_imx_resume,
2001 .id_table = imx_uart_devtype,
2002 .driver = {
2003 .name = "imx-uart",
2004 .of_match_table = imx_uart_dt_ids,
2005 },
2006 };
2007
2008 static int __init imx_serial_init(void)
2009 {
2010 int ret = uart_register_driver(&imx_reg);
2011
2012 if (ret)
2013 return ret;
2014
2015 ret = platform_driver_register(&serial_imx_driver);
2016 if (ret != 0)
2017 uart_unregister_driver(&imx_reg);
2018
2019 return ret;
2020 }
2021
2022 static void __exit imx_serial_exit(void)
2023 {
2024 platform_driver_unregister(&serial_imx_driver);
2025 uart_unregister_driver(&imx_reg);
2026 }
2027
2028 module_init(imx_serial_init);
2029 module_exit(imx_serial_exit);
2030
2031 MODULE_AUTHOR("Sascha Hauer");
2032 MODULE_DESCRIPTION("IMX generic serial port driver");
2033 MODULE_LICENSE("GPL");
2034 MODULE_ALIAS("platform:imx-uart");
Linux with added FPC-III support