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ARM: ep93xx: move timer to its own file
[linux/fpc-iii.git] / drivers / tty / serial / omap-serial.c
blob7a2172b5e93cd296674c9b78a5fd31594db0f492
1 /*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
26
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
36 #include <linux/io.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/pm_wakeirq.h>
42 #include <linux/of.h>
43 #include <linux/of_irq.h>
44 #include <linux/gpio.h>
45 #include <linux/of_gpio.h>
46 #include <linux/platform_data/serial-omap.h>
47
48 #include <dt-bindings/gpio/gpio.h>
49
50 #define OMAP_MAX_HSUART_PORTS 10
51
52 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
53
54 #define OMAP_UART_REV_42 0x0402
55 #define OMAP_UART_REV_46 0x0406
56 #define OMAP_UART_REV_52 0x0502
57 #define OMAP_UART_REV_63 0x0603
58
59 #define OMAP_UART_TX_WAKEUP_EN BIT(7)
60
61 /* Feature flags */
62 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
63
64 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
65 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
66
67 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
68
69 /* SCR register bitmasks */
70 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
71 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
72 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
73
74 /* FCR register bitmasks */
75 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
76 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
77
78 /* MVR register bitmasks */
79 #define OMAP_UART_MVR_SCHEME_SHIFT 30
80
81 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
82 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
83 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
84
85 #define OMAP_UART_MVR_MAJ_MASK 0x700
86 #define OMAP_UART_MVR_MAJ_SHIFT 8
87 #define OMAP_UART_MVR_MIN_MASK 0x3f
88
89 #define OMAP_UART_DMA_CH_FREE -1
90
91 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
92 #define OMAP_MODE13X_SPEED 230400
93
94 /* WER = 0x7F
95 * Enable module level wakeup in WER reg
96 */
97 #define OMAP_UART_WER_MOD_WKUP 0x7F
98
99 /* Enable XON/XOFF flow control on output */
100 #define OMAP_UART_SW_TX 0x08
101
102 /* Enable XON/XOFF flow control on input */
103 #define OMAP_UART_SW_RX 0x02
104
105 #define OMAP_UART_SW_CLR 0xF0
106
107 #define OMAP_UART_TCR_TRIG 0x0F
108
109 struct uart_omap_dma {
110 u8 uart_dma_tx;
111 u8 uart_dma_rx;
112 int rx_dma_channel;
113 int tx_dma_channel;
114 dma_addr_t rx_buf_dma_phys;
115 dma_addr_t tx_buf_dma_phys;
116 unsigned int uart_base;
117 /*
118 * Buffer for rx dma. It is not required for tx because the buffer
119 * comes from port structure.
120 */
121 unsigned char *rx_buf;
122 unsigned int prev_rx_dma_pos;
123 int tx_buf_size;
124 int tx_dma_used;
125 int rx_dma_used;
126 spinlock_t tx_lock;
127 spinlock_t rx_lock;
128 /* timer to poll activity on rx dma */
129 struct timer_list rx_timer;
130 unsigned int rx_buf_size;
131 unsigned int rx_poll_rate;
132 unsigned int rx_timeout;
133 };
134
135 struct uart_omap_port {
136 struct uart_port port;
137 struct uart_omap_dma uart_dma;
138 struct device *dev;
139 int wakeirq;
140
141 unsigned char ier;
142 unsigned char lcr;
143 unsigned char mcr;
144 unsigned char fcr;
145 unsigned char efr;
146 unsigned char dll;
147 unsigned char dlh;
148 unsigned char mdr1;
149 unsigned char scr;
150 unsigned char wer;
151
152 int use_dma;
153 /*
154 * Some bits in registers are cleared on a read, so they must
155 * be saved whenever the register is read, but the bits will not
156 * be immediately processed.
157 */
158 unsigned int lsr_break_flag;
159 unsigned char msr_saved_flags;
160 char name[20];
161 unsigned long port_activity;
162 int context_loss_cnt;
163 u32 errata;
164 u32 features;
165
166 int rts_gpio;
167
168 struct pm_qos_request pm_qos_request;
169 u32 latency;
170 u32 calc_latency;
171 struct work_struct qos_work;
172 bool is_suspending;
173 };
174
175 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
176
177 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
178
179 /* Forward declaration of functions */
180 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
181
182 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
183 {
184 offset <<= up->port.regshift;
185 return readw(up->port.membase + offset);
186 }
187
188 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
189 {
190 offset <<= up->port.regshift;
191 writew(value, up->port.membase + offset);
192 }
193
194 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
195 {
196 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
197 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
198 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
199 serial_out(up, UART_FCR, 0);
200 }
201
202 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
203 {
204 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
205
206 if (!pdata || !pdata->get_context_loss_count)
207 return -EINVAL;
208
209 return pdata->get_context_loss_count(up->dev);
210 }
211
212 /* REVISIT: Remove this when omap3 boots in device tree only mode */
213 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
214 {
215 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
216
217 if (!pdata || !pdata->enable_wakeup)
218 return;
219
220 pdata->enable_wakeup(up->dev, enable);
221 }
222
223 /*
224 * Calculate the absolute difference between the desired and actual baud
225 * rate for the given mode.
226 */
227 static inline int calculate_baud_abs_diff(struct uart_port *port,
228 unsigned int baud, unsigned int mode)
229 {
230 unsigned int n = port->uartclk / (mode * baud);
231 int abs_diff;
232
233 if (n == 0)
234 n = 1;
235
236 abs_diff = baud - (port->uartclk / (mode * n));
237 if (abs_diff < 0)
238 abs_diff = -abs_diff;
239
240 return abs_diff;
241 }
242
243 /*
244 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
245 * @port: uart port info
246 * @baud: baudrate for which mode needs to be determined
247 *
248 * Returns true if baud rate is MODE16X and false if MODE13X
249 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
250 * and Error Rates" determines modes not for all common baud rates.
251 * E.g. for 1000000 baud rate mode must be 16x, but according to that
252 * table it's determined as 13x.
253 */
254 static bool
255 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
256 {
257 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
258 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
259
260 return (abs_diff_13 >= abs_diff_16);
261 }
262
263 /*
264 * serial_omap_get_divisor - calculate divisor value
265 * @port: uart port info
266 * @baud: baudrate for which divisor needs to be calculated.
267 */
268 static unsigned int
269 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
270 {
271 unsigned int mode;
272
273 if (!serial_omap_baud_is_mode16(port, baud))
274 mode = 13;
275 else
276 mode = 16;
277 return port->uartclk/(mode * baud);
278 }
279
280 static void serial_omap_enable_ms(struct uart_port *port)
281 {
282 struct uart_omap_port *up = to_uart_omap_port(port);
283
284 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
285
286 pm_runtime_get_sync(up->dev);
287 up->ier |= UART_IER_MSI;
288 serial_out(up, UART_IER, up->ier);
289 pm_runtime_mark_last_busy(up->dev);
290 pm_runtime_put_autosuspend(up->dev);
291 }
292
293 static void serial_omap_stop_tx(struct uart_port *port)
294 {
295 struct uart_omap_port *up = to_uart_omap_port(port);
296 int res;
297
298 pm_runtime_get_sync(up->dev);
299
300 /* Handle RS-485 */
301 if (port->rs485.flags & SER_RS485_ENABLED) {
302 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
303 /* THR interrupt is fired when both TX FIFO and TX
304 * shift register are empty. This means there's nothing
305 * left to transmit now, so make sure the THR interrupt
306 * is fired when TX FIFO is below the trigger level,
307 * disable THR interrupts and toggle the RS-485 GPIO
308 * data direction pin if needed.
309 */
310 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
311 serial_out(up, UART_OMAP_SCR, up->scr);
312 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
313 1 : 0;
314 if (gpio_get_value(up->rts_gpio) != res) {
315 if (port->rs485.delay_rts_after_send > 0)
316 mdelay(
317 port->rs485.delay_rts_after_send);
318 gpio_set_value(up->rts_gpio, res);
319 }
320 } else {
321 /* We're asked to stop, but there's still stuff in the
322 * UART FIFO, so make sure the THR interrupt is fired
323 * when both TX FIFO and TX shift register are empty.
324 * The next THR interrupt (if no transmission is started
325 * in the meantime) will indicate the end of a
326 * transmission. Therefore we _don't_ disable THR
327 * interrupts in this situation.
328 */
329 up->scr |= OMAP_UART_SCR_TX_EMPTY;
330 serial_out(up, UART_OMAP_SCR, up->scr);
331 return;
332 }
333 }
334
335 if (up->ier & UART_IER_THRI) {
336 up->ier &= ~UART_IER_THRI;
337 serial_out(up, UART_IER, up->ier);
338 }
339
340 if ((port->rs485.flags & SER_RS485_ENABLED) &&
341 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
342 /*
343 * Empty the RX FIFO, we are not interested in anything
344 * received during the half-duplex transmission.
345 */
346 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
347 /* Re-enable RX interrupts */
348 up->ier |= UART_IER_RLSI | UART_IER_RDI;
349 up->port.read_status_mask |= UART_LSR_DR;
350 serial_out(up, UART_IER, up->ier);
351 }
352
353 pm_runtime_mark_last_busy(up->dev);
354 pm_runtime_put_autosuspend(up->dev);
355 }
356
357 static void serial_omap_stop_rx(struct uart_port *port)
358 {
359 struct uart_omap_port *up = to_uart_omap_port(port);
360
361 pm_runtime_get_sync(up->dev);
362 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
363 up->port.read_status_mask &= ~UART_LSR_DR;
364 serial_out(up, UART_IER, up->ier);
365 pm_runtime_mark_last_busy(up->dev);
366 pm_runtime_put_autosuspend(up->dev);
367 }
368
369 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
370 {
371 struct circ_buf *xmit = &up->port.state->xmit;
372 int count;
373
374 if (up->port.x_char) {
375 serial_out(up, UART_TX, up->port.x_char);
376 up->port.icount.tx++;
377 up->port.x_char = 0;
378 return;
379 }
380 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
381 serial_omap_stop_tx(&up->port);
382 return;
383 }
384 count = up->port.fifosize / 4;
385 do {
386 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
387 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
388 up->port.icount.tx++;
389 if (uart_circ_empty(xmit))
390 break;
391 } while (--count > 0);
392
393 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
394 uart_write_wakeup(&up->port);
395
396 if (uart_circ_empty(xmit))
397 serial_omap_stop_tx(&up->port);
398 }
399
400 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
401 {
402 if (!(up->ier & UART_IER_THRI)) {
403 up->ier |= UART_IER_THRI;
404 serial_out(up, UART_IER, up->ier);
405 }
406 }
407
408 static void serial_omap_start_tx(struct uart_port *port)
409 {
410 struct uart_omap_port *up = to_uart_omap_port(port);
411 int res;
412
413 pm_runtime_get_sync(up->dev);
414
415 /* Handle RS-485 */
416 if (port->rs485.flags & SER_RS485_ENABLED) {
417 /* Fire THR interrupts when FIFO is below trigger level */
418 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
419 serial_out(up, UART_OMAP_SCR, up->scr);
420
421 /* if rts not already enabled */
422 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
423 if (gpio_get_value(up->rts_gpio) != res) {
424 gpio_set_value(up->rts_gpio, res);
425 if (port->rs485.delay_rts_before_send > 0)
426 mdelay(port->rs485.delay_rts_before_send);
427 }
428 }
429
430 if ((port->rs485.flags & SER_RS485_ENABLED) &&
431 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
432 serial_omap_stop_rx(port);
433
434 serial_omap_enable_ier_thri(up);
435 pm_runtime_mark_last_busy(up->dev);
436 pm_runtime_put_autosuspend(up->dev);
437 }
438
439 static void serial_omap_throttle(struct uart_port *port)
440 {
441 struct uart_omap_port *up = to_uart_omap_port(port);
442 unsigned long flags;
443
444 pm_runtime_get_sync(up->dev);
445 spin_lock_irqsave(&up->port.lock, flags);
446 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
447 serial_out(up, UART_IER, up->ier);
448 spin_unlock_irqrestore(&up->port.lock, flags);
449 pm_runtime_mark_last_busy(up->dev);
450 pm_runtime_put_autosuspend(up->dev);
451 }
452
453 static void serial_omap_unthrottle(struct uart_port *port)
454 {
455 struct uart_omap_port *up = to_uart_omap_port(port);
456 unsigned long flags;
457
458 pm_runtime_get_sync(up->dev);
459 spin_lock_irqsave(&up->port.lock, flags);
460 up->ier |= UART_IER_RLSI | UART_IER_RDI;
461 serial_out(up, UART_IER, up->ier);
462 spin_unlock_irqrestore(&up->port.lock, flags);
463 pm_runtime_mark_last_busy(up->dev);
464 pm_runtime_put_autosuspend(up->dev);
465 }
466
467 static unsigned int check_modem_status(struct uart_omap_port *up)
468 {
469 unsigned int status;
470
471 status = serial_in(up, UART_MSR);
472 status |= up->msr_saved_flags;
473 up->msr_saved_flags = 0;
474 if ((status & UART_MSR_ANY_DELTA) == 0)
475 return status;
476
477 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
478 up->port.state != NULL) {
479 if (status & UART_MSR_TERI)
480 up->port.icount.rng++;
481 if (status & UART_MSR_DDSR)
482 up->port.icount.dsr++;
483 if (status & UART_MSR_DDCD)
484 uart_handle_dcd_change
485 (&up->port, status & UART_MSR_DCD);
486 if (status & UART_MSR_DCTS)
487 uart_handle_cts_change
488 (&up->port, status & UART_MSR_CTS);
489 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
490 }
491
492 return status;
493 }
494
495 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
496 {
497 unsigned int flag;
498 unsigned char ch = 0;
499
500 if (likely(lsr & UART_LSR_DR))
501 ch = serial_in(up, UART_RX);
502
503 up->port.icount.rx++;
504 flag = TTY_NORMAL;
505
506 if (lsr & UART_LSR_BI) {
507 flag = TTY_BREAK;
508 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
509 up->port.icount.brk++;
510 /*
511 * We do the SysRQ and SAK checking
512 * here because otherwise the break
513 * may get masked by ignore_status_mask
514 * or read_status_mask.
515 */
516 if (uart_handle_break(&up->port))
517 return;
518
519 }
520
521 if (lsr & UART_LSR_PE) {
522 flag = TTY_PARITY;
523 up->port.icount.parity++;
524 }
525
526 if (lsr & UART_LSR_FE) {
527 flag = TTY_FRAME;
528 up->port.icount.frame++;
529 }
530
531 if (lsr & UART_LSR_OE)
532 up->port.icount.overrun++;
533
534 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
535 if (up->port.line == up->port.cons->index) {
536 /* Recover the break flag from console xmit */
537 lsr |= up->lsr_break_flag;
538 }
539 #endif
540 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
541 }
542
543 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
544 {
545 unsigned char ch = 0;
546 unsigned int flag;
547
548 if (!(lsr & UART_LSR_DR))
549 return;
550
551 ch = serial_in(up, UART_RX);
552 flag = TTY_NORMAL;
553 up->port.icount.rx++;
554
555 if (uart_handle_sysrq_char(&up->port, ch))
556 return;
557
558 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
559 }
560
561 /**
562 * serial_omap_irq() - This handles the interrupt from one port
563 * @irq: uart port irq number
564 * @dev_id: uart port info
565 */
566 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
567 {
568 struct uart_omap_port *up = dev_id;
569 unsigned int iir, lsr;
570 unsigned int type;
571 irqreturn_t ret = IRQ_NONE;
572 int max_count = 256;
573
574 spin_lock(&up->port.lock);
575 pm_runtime_get_sync(up->dev);
576
577 do {
578 iir = serial_in(up, UART_IIR);
579 if (iir & UART_IIR_NO_INT)
580 break;
581
582 ret = IRQ_HANDLED;
583 lsr = serial_in(up, UART_LSR);
584
585 /* extract IRQ type from IIR register */
586 type = iir & 0x3e;
587
588 switch (type) {
589 case UART_IIR_MSI:
590 check_modem_status(up);
591 break;
592 case UART_IIR_THRI:
593 transmit_chars(up, lsr);
594 break;
595 case UART_IIR_RX_TIMEOUT:
596 /* FALLTHROUGH */
597 case UART_IIR_RDI:
598 serial_omap_rdi(up, lsr);
599 break;
600 case UART_IIR_RLSI:
601 serial_omap_rlsi(up, lsr);
602 break;
603 case UART_IIR_CTS_RTS_DSR:
604 /* simply try again */
605 break;
606 case UART_IIR_XOFF:
607 /* FALLTHROUGH */
608 default:
609 break;
610 }
611 } while (!(iir & UART_IIR_NO_INT) && max_count--);
612
613 spin_unlock(&up->port.lock);
614
615 tty_flip_buffer_push(&up->port.state->port);
616
617 pm_runtime_mark_last_busy(up->dev);
618 pm_runtime_put_autosuspend(up->dev);
619 up->port_activity = jiffies;
620
621 return ret;
622 }
623
624 static unsigned int serial_omap_tx_empty(struct uart_port *port)
625 {
626 struct uart_omap_port *up = to_uart_omap_port(port);
627 unsigned long flags = 0;
628 unsigned int ret = 0;
629
630 pm_runtime_get_sync(up->dev);
631 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
632 spin_lock_irqsave(&up->port.lock, flags);
633 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
634 spin_unlock_irqrestore(&up->port.lock, flags);
635 pm_runtime_mark_last_busy(up->dev);
636 pm_runtime_put_autosuspend(up->dev);
637 return ret;
638 }
639
640 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
641 {
642 struct uart_omap_port *up = to_uart_omap_port(port);
643 unsigned int status;
644 unsigned int ret = 0;
645
646 pm_runtime_get_sync(up->dev);
647 status = check_modem_status(up);
648 pm_runtime_mark_last_busy(up->dev);
649 pm_runtime_put_autosuspend(up->dev);
650
651 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
652
653 if (status & UART_MSR_DCD)
654 ret |= TIOCM_CAR;
655 if (status & UART_MSR_RI)
656 ret |= TIOCM_RNG;
657 if (status & UART_MSR_DSR)
658 ret |= TIOCM_DSR;
659 if (status & UART_MSR_CTS)
660 ret |= TIOCM_CTS;
661 return ret;
662 }
663
664 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
665 {
666 struct uart_omap_port *up = to_uart_omap_port(port);
667 unsigned char mcr = 0, old_mcr, lcr;
668
669 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
670 if (mctrl & TIOCM_RTS)
671 mcr |= UART_MCR_RTS;
672 if (mctrl & TIOCM_DTR)
673 mcr |= UART_MCR_DTR;
674 if (mctrl & TIOCM_OUT1)
675 mcr |= UART_MCR_OUT1;
676 if (mctrl & TIOCM_OUT2)
677 mcr |= UART_MCR_OUT2;
678 if (mctrl & TIOCM_LOOP)
679 mcr |= UART_MCR_LOOP;
680
681 pm_runtime_get_sync(up->dev);
682 old_mcr = serial_in(up, UART_MCR);
683 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
684 UART_MCR_DTR | UART_MCR_RTS);
685 up->mcr = old_mcr | mcr;
686 serial_out(up, UART_MCR, up->mcr);
687
688 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
689 lcr = serial_in(up, UART_LCR);
690 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
691 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
692 up->efr |= UART_EFR_RTS;
693 else
694 up->efr &= UART_EFR_RTS;
695 serial_out(up, UART_EFR, up->efr);
696 serial_out(up, UART_LCR, lcr);
697
698 pm_runtime_mark_last_busy(up->dev);
699 pm_runtime_put_autosuspend(up->dev);
700 }
701
702 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
703 {
704 struct uart_omap_port *up = to_uart_omap_port(port);
705 unsigned long flags = 0;
706
707 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
708 pm_runtime_get_sync(up->dev);
709 spin_lock_irqsave(&up->port.lock, flags);
710 if (break_state == -1)
711 up->lcr |= UART_LCR_SBC;
712 else
713 up->lcr &= ~UART_LCR_SBC;
714 serial_out(up, UART_LCR, up->lcr);
715 spin_unlock_irqrestore(&up->port.lock, flags);
716 pm_runtime_mark_last_busy(up->dev);
717 pm_runtime_put_autosuspend(up->dev);
718 }
719
720 static int serial_omap_startup(struct uart_port *port)
721 {
722 struct uart_omap_port *up = to_uart_omap_port(port);
723 unsigned long flags = 0;
724 int retval;
725
726 /*
727 * Allocate the IRQ
728 */
729 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
730 up->name, up);
731 if (retval)
732 return retval;
733
734 /* Optional wake-up IRQ */
735 if (up->wakeirq) {
736 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
737 if (retval) {
738 free_irq(up->port.irq, up);
739 return retval;
740 }
741 }
742
743 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
744
745 pm_runtime_get_sync(up->dev);
746 /*
747 * Clear the FIFO buffers and disable them.
748 * (they will be reenabled in set_termios())
749 */
750 serial_omap_clear_fifos(up);
751
752 /*
753 * Clear the interrupt registers.
754 */
755 (void) serial_in(up, UART_LSR);
756 if (serial_in(up, UART_LSR) & UART_LSR_DR)
757 (void) serial_in(up, UART_RX);
758 (void) serial_in(up, UART_IIR);
759 (void) serial_in(up, UART_MSR);
760
761 /*
762 * Now, initialize the UART
763 */
764 serial_out(up, UART_LCR, UART_LCR_WLEN8);
765 spin_lock_irqsave(&up->port.lock, flags);
766 /*
767 * Most PC uarts need OUT2 raised to enable interrupts.
768 */
769 up->port.mctrl |= TIOCM_OUT2;
770 serial_omap_set_mctrl(&up->port, up->port.mctrl);
771 spin_unlock_irqrestore(&up->port.lock, flags);
772
773 up->msr_saved_flags = 0;
774 /*
775 * Finally, enable interrupts. Note: Modem status interrupts
776 * are set via set_termios(), which will be occurring imminently
777 * anyway, so we don't enable them here.
778 */
779 up->ier = UART_IER_RLSI | UART_IER_RDI;
780 serial_out(up, UART_IER, up->ier);
781
782 /* Enable module level wake up */
783 up->wer = OMAP_UART_WER_MOD_WKUP;
784 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
785 up->wer |= OMAP_UART_TX_WAKEUP_EN;
786
787 serial_out(up, UART_OMAP_WER, up->wer);
788
789 pm_runtime_mark_last_busy(up->dev);
790 pm_runtime_put_autosuspend(up->dev);
791 up->port_activity = jiffies;
792 return 0;
793 }
794
795 static void serial_omap_shutdown(struct uart_port *port)
796 {
797 struct uart_omap_port *up = to_uart_omap_port(port);
798 unsigned long flags = 0;
799
800 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
801
802 pm_runtime_get_sync(up->dev);
803 /*
804 * Disable interrupts from this port
805 */
806 up->ier = 0;
807 serial_out(up, UART_IER, 0);
808
809 spin_lock_irqsave(&up->port.lock, flags);
810 up->port.mctrl &= ~TIOCM_OUT2;
811 serial_omap_set_mctrl(&up->port, up->port.mctrl);
812 spin_unlock_irqrestore(&up->port.lock, flags);
813
814 /*
815 * Disable break condition and FIFOs
816 */
817 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
818 serial_omap_clear_fifos(up);
819
820 /*
821 * Read data port to reset things, and then free the irq
822 */
823 if (serial_in(up, UART_LSR) & UART_LSR_DR)
824 (void) serial_in(up, UART_RX);
825
826 pm_runtime_mark_last_busy(up->dev);
827 pm_runtime_put_autosuspend(up->dev);
828 free_irq(up->port.irq, up);
829 dev_pm_clear_wake_irq(up->dev);
830 }
831
832 static void serial_omap_uart_qos_work(struct work_struct *work)
833 {
834 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
835 qos_work);
836
837 pm_qos_update_request(&up->pm_qos_request, up->latency);
838 }
839
840 static void
841 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
842 struct ktermios *old)
843 {
844 struct uart_omap_port *up = to_uart_omap_port(port);
845 unsigned char cval = 0;
846 unsigned long flags = 0;
847 unsigned int baud, quot;
848
849 switch (termios->c_cflag & CSIZE) {
850 case CS5:
851 cval = UART_LCR_WLEN5;
852 break;
853 case CS6:
854 cval = UART_LCR_WLEN6;
855 break;
856 case CS7:
857 cval = UART_LCR_WLEN7;
858 break;
859 default:
860 case CS8:
861 cval = UART_LCR_WLEN8;
862 break;
863 }
864
865 if (termios->c_cflag & CSTOPB)
866 cval |= UART_LCR_STOP;
867 if (termios->c_cflag & PARENB)
868 cval |= UART_LCR_PARITY;
869 if (!(termios->c_cflag & PARODD))
870 cval |= UART_LCR_EPAR;
871 if (termios->c_cflag & CMSPAR)
872 cval |= UART_LCR_SPAR;
873
874 /*
875 * Ask the core to calculate the divisor for us.
876 */
877
878 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
879 quot = serial_omap_get_divisor(port, baud);
880
881 /* calculate wakeup latency constraint */
882 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
883 up->latency = up->calc_latency;
884 schedule_work(&up->qos_work);
885
886 up->dll = quot & 0xff;
887 up->dlh = quot >> 8;
888 up->mdr1 = UART_OMAP_MDR1_DISABLE;
889
890 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
891 UART_FCR_ENABLE_FIFO;
892
893 /*
894 * Ok, we're now changing the port state. Do it with
895 * interrupts disabled.
896 */
897 pm_runtime_get_sync(up->dev);
898 spin_lock_irqsave(&up->port.lock, flags);
899
900 /*
901 * Update the per-port timeout.
902 */
903 uart_update_timeout(port, termios->c_cflag, baud);
904
905 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
906 if (termios->c_iflag & INPCK)
907 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
908 if (termios->c_iflag & (BRKINT | PARMRK))
909 up->port.read_status_mask |= UART_LSR_BI;
910
911 /*
912 * Characters to ignore
913 */
914 up->port.ignore_status_mask = 0;
915 if (termios->c_iflag & IGNPAR)
916 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
917 if (termios->c_iflag & IGNBRK) {
918 up->port.ignore_status_mask |= UART_LSR_BI;
919 /*
920 * If we're ignoring parity and break indicators,
921 * ignore overruns too (for real raw support).
922 */
923 if (termios->c_iflag & IGNPAR)
924 up->port.ignore_status_mask |= UART_LSR_OE;
925 }
926
927 /*
928 * ignore all characters if CREAD is not set
929 */
930 if ((termios->c_cflag & CREAD) == 0)
931 up->port.ignore_status_mask |= UART_LSR_DR;
932
933 /*
934 * Modem status interrupts
935 */
936 up->ier &= ~UART_IER_MSI;
937 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
938 up->ier |= UART_IER_MSI;
939 serial_out(up, UART_IER, up->ier);
940 serial_out(up, UART_LCR, cval); /* reset DLAB */
941 up->lcr = cval;
942 up->scr = 0;
943
944 /* FIFOs and DMA Settings */
945
946 /* FCR can be changed only when the
947 * baud clock is not running
948 * DLL_REG and DLH_REG set to 0.
949 */
950 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
951 serial_out(up, UART_DLL, 0);
952 serial_out(up, UART_DLM, 0);
953 serial_out(up, UART_LCR, 0);
954
955 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
956
957 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
958 up->efr &= ~UART_EFR_SCD;
959 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
960
961 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
962 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
963 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
964 /* FIFO ENABLE, DMA MODE */
965
966 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
967 /*
968 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
969 * sets Enables the granularity of 1 for TRIGGER RX
970 * level. Along with setting RX FIFO trigger level
971 * to 1 (as noted below, 16 characters) and TLR[3:0]
972 * to zero this will result RX FIFO threshold level
973 * to 1 character, instead of 16 as noted in comment
974 * below.
975 */
976
977 /* Set receive FIFO threshold to 16 characters and
978 * transmit FIFO threshold to 32 spaces
979 */
980 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
981 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
982 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
983 UART_FCR_ENABLE_FIFO;
984
985 serial_out(up, UART_FCR, up->fcr);
986 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
987
988 serial_out(up, UART_OMAP_SCR, up->scr);
989
990 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
991 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
992 serial_out(up, UART_MCR, up->mcr);
993 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
994 serial_out(up, UART_EFR, up->efr);
995 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
996
997 /* Protocol, Baud Rate, and Interrupt Settings */
998
999 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1000 serial_omap_mdr1_errataset(up, up->mdr1);
1001 else
1002 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1003
1004 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1005 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1006
1007 serial_out(up, UART_LCR, 0);
1008 serial_out(up, UART_IER, 0);
1009 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1010
1011 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1012 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1013
1014 serial_out(up, UART_LCR, 0);
1015 serial_out(up, UART_IER, up->ier);
1016 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1017
1018 serial_out(up, UART_EFR, up->efr);
1019 serial_out(up, UART_LCR, cval);
1020
1021 if (!serial_omap_baud_is_mode16(port, baud))
1022 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1023 else
1024 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1025
1026 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1027 serial_omap_mdr1_errataset(up, up->mdr1);
1028 else
1029 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1030
1031 /* Configure flow control */
1032 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1033
1034 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1035 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1036 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1037
1038 /* Enable access to TCR/TLR */
1039 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1040 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1041 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1042
1043 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1044
1045 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1046
1047 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1048 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
1049 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1050 up->efr |= UART_EFR_CTS;
1051 } else {
1052 /* Disable AUTORTS and AUTOCTS */
1053 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1054 }
1055
1056 if (up->port.flags & UPF_SOFT_FLOW) {
1057 /* clear SW control mode bits */
1058 up->efr &= OMAP_UART_SW_CLR;
1059
1060 /*
1061 * IXON Flag:
1062 * Enable XON/XOFF flow control on input.
1063 * Receiver compares XON1, XOFF1.
1064 */
1065 if (termios->c_iflag & IXON)
1066 up->efr |= OMAP_UART_SW_RX;
1067
1068 /*
1069 * IXOFF Flag:
1070 * Enable XON/XOFF flow control on output.
1071 * Transmit XON1, XOFF1
1072 */
1073 if (termios->c_iflag & IXOFF) {
1074 up->port.status |= UPSTAT_AUTOXOFF;
1075 up->efr |= OMAP_UART_SW_TX;
1076 }
1077
1078 /*
1079 * IXANY Flag:
1080 * Enable any character to restart output.
1081 * Operation resumes after receiving any
1082 * character after recognition of the XOFF character
1083 */
1084 if (termios->c_iflag & IXANY)
1085 up->mcr |= UART_MCR_XONANY;
1086 else
1087 up->mcr &= ~UART_MCR_XONANY;
1088 }
1089 serial_out(up, UART_MCR, up->mcr);
1090 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1091 serial_out(up, UART_EFR, up->efr);
1092 serial_out(up, UART_LCR, up->lcr);
1093
1094 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1095
1096 spin_unlock_irqrestore(&up->port.lock, flags);
1097 pm_runtime_mark_last_busy(up->dev);
1098 pm_runtime_put_autosuspend(up->dev);
1099 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1100 }
1101
1102 static void
1103 serial_omap_pm(struct uart_port *port, unsigned int state,
1104 unsigned int oldstate)
1105 {
1106 struct uart_omap_port *up = to_uart_omap_port(port);
1107 unsigned char efr;
1108
1109 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1110
1111 pm_runtime_get_sync(up->dev);
1112 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1113 efr = serial_in(up, UART_EFR);
1114 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1115 serial_out(up, UART_LCR, 0);
1116
1117 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1118 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1119 serial_out(up, UART_EFR, efr);
1120 serial_out(up, UART_LCR, 0);
1121
1122 pm_runtime_mark_last_busy(up->dev);
1123 pm_runtime_put_autosuspend(up->dev);
1124 }
1125
1126 static void serial_omap_release_port(struct uart_port *port)
1127 {
1128 dev_dbg(port->dev, "serial_omap_release_port+\n");
1129 }
1130
1131 static int serial_omap_request_port(struct uart_port *port)
1132 {
1133 dev_dbg(port->dev, "serial_omap_request_port+\n");
1134 return 0;
1135 }
1136
1137 static void serial_omap_config_port(struct uart_port *port, int flags)
1138 {
1139 struct uart_omap_port *up = to_uart_omap_port(port);
1140
1141 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1142 up->port.line);
1143 up->port.type = PORT_OMAP;
1144 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1145 }
1146
1147 static int
1148 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1149 {
1150 /* we don't want the core code to modify any port params */
1151 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1152 return -EINVAL;
1153 }
1154
1155 static const char *
1156 serial_omap_type(struct uart_port *port)
1157 {
1158 struct uart_omap_port *up = to_uart_omap_port(port);
1159
1160 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1161 return up->name;
1162 }
1163
1164 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1165
1166 static inline void wait_for_xmitr(struct uart_omap_port *up)
1167 {
1168 unsigned int status, tmout = 10000;
1169
1170 /* Wait up to 10ms for the character(s) to be sent. */
1171 do {
1172 status = serial_in(up, UART_LSR);
1173
1174 if (status & UART_LSR_BI)
1175 up->lsr_break_flag = UART_LSR_BI;
1176
1177 if (--tmout == 0)
1178 break;
1179 udelay(1);
1180 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1181
1182 /* Wait up to 1s for flow control if necessary */
1183 if (up->port.flags & UPF_CONS_FLOW) {
1184 tmout = 1000000;
1185 for (tmout = 1000000; tmout; tmout--) {
1186 unsigned int msr = serial_in(up, UART_MSR);
1187
1188 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1189 if (msr & UART_MSR_CTS)
1190 break;
1191
1192 udelay(1);
1193 }
1194 }
1195 }
1196
1197 #ifdef CONFIG_CONSOLE_POLL
1198
1199 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1200 {
1201 struct uart_omap_port *up = to_uart_omap_port(port);
1202
1203 pm_runtime_get_sync(up->dev);
1204 wait_for_xmitr(up);
1205 serial_out(up, UART_TX, ch);
1206 pm_runtime_mark_last_busy(up->dev);
1207 pm_runtime_put_autosuspend(up->dev);
1208 }
1209
1210 static int serial_omap_poll_get_char(struct uart_port *port)
1211 {
1212 struct uart_omap_port *up = to_uart_omap_port(port);
1213 unsigned int status;
1214
1215 pm_runtime_get_sync(up->dev);
1216 status = serial_in(up, UART_LSR);
1217 if (!(status & UART_LSR_DR)) {
1218 status = NO_POLL_CHAR;
1219 goto out;
1220 }
1221
1222 status = serial_in(up, UART_RX);
1223
1224 out:
1225 pm_runtime_mark_last_busy(up->dev);
1226 pm_runtime_put_autosuspend(up->dev);
1227
1228 return status;
1229 }
1230
1231 #endif /* CONFIG_CONSOLE_POLL */
1232
1233 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1234
1235 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1236
1237 static struct uart_driver serial_omap_reg;
1238
1239 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1240 {
1241 struct uart_omap_port *up = to_uart_omap_port(port);
1242
1243 wait_for_xmitr(up);
1244 serial_out(up, UART_TX, ch);
1245 }
1246
1247 static void
1248 serial_omap_console_write(struct console *co, const char *s,
1249 unsigned int count)
1250 {
1251 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1252 unsigned long flags;
1253 unsigned int ier;
1254 int locked = 1;
1255
1256 pm_runtime_get_sync(up->dev);
1257
1258 local_irq_save(flags);
1259 if (up->port.sysrq)
1260 locked = 0;
1261 else if (oops_in_progress)
1262 locked = spin_trylock(&up->port.lock);
1263 else
1264 spin_lock(&up->port.lock);
1265
1266 /*
1267 * First save the IER then disable the interrupts
1268 */
1269 ier = serial_in(up, UART_IER);
1270 serial_out(up, UART_IER, 0);
1271
1272 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1273
1274 /*
1275 * Finally, wait for transmitter to become empty
1276 * and restore the IER
1277 */
1278 wait_for_xmitr(up);
1279 serial_out(up, UART_IER, ier);
1280 /*
1281 * The receive handling will happen properly because the
1282 * receive ready bit will still be set; it is not cleared
1283 * on read. However, modem control will not, we must
1284 * call it if we have saved something in the saved flags
1285 * while processing with interrupts off.
1286 */
1287 if (up->msr_saved_flags)
1288 check_modem_status(up);
1289
1290 pm_runtime_mark_last_busy(up->dev);
1291 pm_runtime_put_autosuspend(up->dev);
1292 if (locked)
1293 spin_unlock(&up->port.lock);
1294 local_irq_restore(flags);
1295 }
1296
1297 static int __init
1298 serial_omap_console_setup(struct console *co, char *options)
1299 {
1300 struct uart_omap_port *up;
1301 int baud = 115200;
1302 int bits = 8;
1303 int parity = 'n';
1304 int flow = 'n';
1305
1306 if (serial_omap_console_ports[co->index] == NULL)
1307 return -ENODEV;
1308 up = serial_omap_console_ports[co->index];
1309
1310 if (options)
1311 uart_parse_options(options, &baud, &parity, &bits, &flow);
1312
1313 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1314 }
1315
1316 static struct console serial_omap_console = {
1317 .name = OMAP_SERIAL_NAME,
1318 .write = serial_omap_console_write,
1319 .device = uart_console_device,
1320 .setup = serial_omap_console_setup,
1321 .flags = CON_PRINTBUFFER,
1322 .index = -1,
1323 .data = &serial_omap_reg,
1324 };
1325
1326 static void serial_omap_add_console_port(struct uart_omap_port *up)
1327 {
1328 serial_omap_console_ports[up->port.line] = up;
1329 }
1330
1331 #define OMAP_CONSOLE (&serial_omap_console)
1332
1333 #else
1334
1335 #define OMAP_CONSOLE NULL
1336
1337 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1338 {}
1339
1340 #endif
1341
1342 /* Enable or disable the rs485 support */
1343 static int
1344 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1345 {
1346 struct uart_omap_port *up = to_uart_omap_port(port);
1347 unsigned int mode;
1348 int val;
1349
1350 pm_runtime_get_sync(up->dev);
1351
1352 /* Disable interrupts from this port */
1353 mode = up->ier;
1354 up->ier = 0;
1355 serial_out(up, UART_IER, 0);
1356
1357 /* store new config */
1358 port->rs485 = *rs485conf;
1359
1360 /*
1361 * Just as a precaution, only allow rs485
1362 * to be enabled if the gpio pin is valid
1363 */
1364 if (gpio_is_valid(up->rts_gpio)) {
1365 /* enable / disable rts */
1366 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1367 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1368 val = (port->rs485.flags & val) ? 1 : 0;
1369 gpio_set_value(up->rts_gpio, val);
1370 } else
1371 port->rs485.flags &= ~SER_RS485_ENABLED;
1372
1373 /* Enable interrupts */
1374 up->ier = mode;
1375 serial_out(up, UART_IER, up->ier);
1376
1377 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1378 * TX FIFO is below the trigger level.
1379 */
1380 if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1381 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1382 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1383 serial_out(up, UART_OMAP_SCR, up->scr);
1384 }
1385
1386 pm_runtime_mark_last_busy(up->dev);
1387 pm_runtime_put_autosuspend(up->dev);
1388
1389 return 0;
1390 }
1391
1392 static struct uart_ops serial_omap_pops = {
1393 .tx_empty = serial_omap_tx_empty,
1394 .set_mctrl = serial_omap_set_mctrl,
1395 .get_mctrl = serial_omap_get_mctrl,
1396 .stop_tx = serial_omap_stop_tx,
1397 .start_tx = serial_omap_start_tx,
1398 .throttle = serial_omap_throttle,
1399 .unthrottle = serial_omap_unthrottle,
1400 .stop_rx = serial_omap_stop_rx,
1401 .enable_ms = serial_omap_enable_ms,
1402 .break_ctl = serial_omap_break_ctl,
1403 .startup = serial_omap_startup,
1404 .shutdown = serial_omap_shutdown,
1405 .set_termios = serial_omap_set_termios,
1406 .pm = serial_omap_pm,
1407 .type = serial_omap_type,
1408 .release_port = serial_omap_release_port,
1409 .request_port = serial_omap_request_port,
1410 .config_port = serial_omap_config_port,
1411 .verify_port = serial_omap_verify_port,
1412 #ifdef CONFIG_CONSOLE_POLL
1413 .poll_put_char = serial_omap_poll_put_char,
1414 .poll_get_char = serial_omap_poll_get_char,
1415 #endif
1416 };
1417
1418 static struct uart_driver serial_omap_reg = {
1419 .owner = THIS_MODULE,
1420 .driver_name = "OMAP-SERIAL",
1421 .dev_name = OMAP_SERIAL_NAME,
1422 .nr = OMAP_MAX_HSUART_PORTS,
1423 .cons = OMAP_CONSOLE,
1424 };
1425
1426 #ifdef CONFIG_PM_SLEEP
1427 static int serial_omap_prepare(struct device *dev)
1428 {
1429 struct uart_omap_port *up = dev_get_drvdata(dev);
1430
1431 up->is_suspending = true;
1432
1433 return 0;
1434 }
1435
1436 static void serial_omap_complete(struct device *dev)
1437 {
1438 struct uart_omap_port *up = dev_get_drvdata(dev);
1439
1440 up->is_suspending = false;
1441 }
1442
1443 static int serial_omap_suspend(struct device *dev)
1444 {
1445 struct uart_omap_port *up = dev_get_drvdata(dev);
1446
1447 uart_suspend_port(&serial_omap_reg, &up->port);
1448 flush_work(&up->qos_work);
1449
1450 if (device_may_wakeup(dev))
1451 serial_omap_enable_wakeup(up, true);
1452 else
1453 serial_omap_enable_wakeup(up, false);
1454
1455 return 0;
1456 }
1457
1458 static int serial_omap_resume(struct device *dev)
1459 {
1460 struct uart_omap_port *up = dev_get_drvdata(dev);
1461
1462 if (device_may_wakeup(dev))
1463 serial_omap_enable_wakeup(up, false);
1464
1465 uart_resume_port(&serial_omap_reg, &up->port);
1466
1467 return 0;
1468 }
1469 #else
1470 #define serial_omap_prepare NULL
1471 #define serial_omap_complete NULL
1472 #endif /* CONFIG_PM_SLEEP */
1473
1474 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1475 {
1476 u32 mvr, scheme;
1477 u16 revision, major, minor;
1478
1479 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1480
1481 /* Check revision register scheme */
1482 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1483
1484 switch (scheme) {
1485 case 0: /* Legacy Scheme: OMAP2/3 */
1486 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1487 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1488 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1489 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1490 break;
1491 case 1:
1492 /* New Scheme: OMAP4+ */
1493 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1494 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1495 OMAP_UART_MVR_MAJ_SHIFT;
1496 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1497 break;
1498 default:
1499 dev_warn(up->dev,
1500 "Unknown %s revision, defaulting to highest\n",
1501 up->name);
1502 /* highest possible revision */
1503 major = 0xff;
1504 minor = 0xff;
1505 }
1506
1507 /* normalize revision for the driver */
1508 revision = UART_BUILD_REVISION(major, minor);
1509
1510 switch (revision) {
1511 case OMAP_UART_REV_46:
1512 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1513 UART_ERRATA_i291_DMA_FORCEIDLE);
1514 break;
1515 case OMAP_UART_REV_52:
1516 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1517 UART_ERRATA_i291_DMA_FORCEIDLE);
1518 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1519 break;
1520 case OMAP_UART_REV_63:
1521 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1522 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1523 break;
1524 default:
1525 break;
1526 }
1527 }
1528
1529 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1530 {
1531 struct omap_uart_port_info *omap_up_info;
1532
1533 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1534 if (!omap_up_info)
1535 return NULL; /* out of memory */
1536
1537 of_property_read_u32(dev->of_node, "clock-frequency",
1538 &omap_up_info->uartclk);
1539 return omap_up_info;
1540 }
1541
1542 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1543 struct device_node *np)
1544 {
1545 struct serial_rs485 *rs485conf = &up->port.rs485;
1546 u32 rs485_delay[2];
1547 enum of_gpio_flags flags;
1548 int ret;
1549
1550 rs485conf->flags = 0;
1551 up->rts_gpio = -EINVAL;
1552
1553 if (!np)
1554 return 0;
1555
1556 if (of_property_read_bool(np, "rs485-rts-active-high"))
1557 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1558 else
1559 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1560
1561 /* check for tx enable gpio */
1562 up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1563 if (gpio_is_valid(up->rts_gpio)) {
1564 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
1565 if (ret < 0)
1566 return ret;
1567 ret = gpio_direction_output(up->rts_gpio,
1568 flags & SER_RS485_RTS_AFTER_SEND);
1569 if (ret < 0)
1570 return ret;
1571 } else if (up->rts_gpio == -EPROBE_DEFER) {
1572 return -EPROBE_DEFER;
1573 } else {
1574 up->rts_gpio = -EINVAL;
1575 }
1576
1577 if (of_property_read_u32_array(np, "rs485-rts-delay",
1578 rs485_delay, 2) == 0) {
1579 rs485conf->delay_rts_before_send = rs485_delay[0];
1580 rs485conf->delay_rts_after_send = rs485_delay[1];
1581 }
1582
1583 if (of_property_read_bool(np, "rs485-rx-during-tx"))
1584 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1585
1586 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1587 rs485conf->flags |= SER_RS485_ENABLED;
1588
1589 return 0;
1590 }
1591
1592 static int serial_omap_probe(struct platform_device *pdev)
1593 {
1594 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1595 struct uart_omap_port *up;
1596 struct resource *mem;
1597 void __iomem *base;
1598 int uartirq = 0;
1599 int wakeirq = 0;
1600 int ret;
1601
1602 /* The optional wakeirq may be specified in the board dts file */
1603 if (pdev->dev.of_node) {
1604 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1605 if (!uartirq)
1606 return -EPROBE_DEFER;
1607 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1608 omap_up_info = of_get_uart_port_info(&pdev->dev);
1609 pdev->dev.platform_data = omap_up_info;
1610 } else {
1611 uartirq = platform_get_irq(pdev, 0);
1612 if (uartirq < 0)
1613 return -EPROBE_DEFER;
1614 }
1615
1616 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1617 if (!up)
1618 return -ENOMEM;
1619
1620 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1621 base = devm_ioremap_resource(&pdev->dev, mem);
1622 if (IS_ERR(base))
1623 return PTR_ERR(base);
1624
1625 up->dev = &pdev->dev;
1626 up->port.dev = &pdev->dev;
1627 up->port.type = PORT_OMAP;
1628 up->port.iotype = UPIO_MEM;
1629 up->port.irq = uartirq;
1630 up->port.regshift = 2;
1631 up->port.fifosize = 64;
1632 up->port.ops = &serial_omap_pops;
1633
1634 if (pdev->dev.of_node)
1635 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1636 else
1637 ret = pdev->id;
1638
1639 if (ret < 0) {
1640 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1641 ret);
1642 goto err_port_line;
1643 }
1644 up->port.line = ret;
1645
1646 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1647 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1648 OMAP_MAX_HSUART_PORTS);
1649 ret = -ENXIO;
1650 goto err_port_line;
1651 }
1652
1653 up->wakeirq = wakeirq;
1654 if (!up->wakeirq)
1655 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1656 up->port.line);
1657
1658 ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1659 if (ret < 0)
1660 goto err_rs485;
1661
1662 sprintf(up->name, "OMAP UART%d", up->port.line);
1663 up->port.mapbase = mem->start;
1664 up->port.membase = base;
1665 up->port.flags = omap_up_info->flags;
1666 up->port.uartclk = omap_up_info->uartclk;
1667 up->port.rs485_config = serial_omap_config_rs485;
1668 if (!up->port.uartclk) {
1669 up->port.uartclk = DEFAULT_CLK_SPEED;
1670 dev_warn(&pdev->dev,
1671 "No clock speed specified: using default: %d\n",
1672 DEFAULT_CLK_SPEED);
1673 }
1674
1675 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1676 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1677 pm_qos_add_request(&up->pm_qos_request,
1678 PM_QOS_CPU_DMA_LATENCY, up->latency);
1679 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1680
1681 platform_set_drvdata(pdev, up);
1682 if (omap_up_info->autosuspend_timeout == 0)
1683 omap_up_info->autosuspend_timeout = -1;
1684
1685 device_init_wakeup(up->dev, true);
1686 pm_runtime_use_autosuspend(&pdev->dev);
1687 pm_runtime_set_autosuspend_delay(&pdev->dev,
1688 omap_up_info->autosuspend_timeout);
1689
1690 pm_runtime_irq_safe(&pdev->dev);
1691 pm_runtime_enable(&pdev->dev);
1692
1693 pm_runtime_get_sync(&pdev->dev);
1694
1695 omap_serial_fill_features_erratas(up);
1696
1697 ui[up->port.line] = up;
1698 serial_omap_add_console_port(up);
1699
1700 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1701 if (ret != 0)
1702 goto err_add_port;
1703
1704 pm_runtime_mark_last_busy(up->dev);
1705 pm_runtime_put_autosuspend(up->dev);
1706 return 0;
1707
1708 err_add_port:
1709 pm_runtime_put(&pdev->dev);
1710 pm_runtime_disable(&pdev->dev);
1711 pm_qos_remove_request(&up->pm_qos_request);
1712 device_init_wakeup(up->dev, false);
1713 err_rs485:
1714 err_port_line:
1715 return ret;
1716 }
1717
1718 static int serial_omap_remove(struct platform_device *dev)
1719 {
1720 struct uart_omap_port *up = platform_get_drvdata(dev);
1721
1722 pm_runtime_put_sync(up->dev);
1723 pm_runtime_disable(up->dev);
1724 uart_remove_one_port(&serial_omap_reg, &up->port);
1725 pm_qos_remove_request(&up->pm_qos_request);
1726 device_init_wakeup(&dev->dev, false);
1727
1728 return 0;
1729 }
1730
1731 /*
1732 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1733 * The access to uart register after MDR1 Access
1734 * causes UART to corrupt data.
1735 *
1736 * Need a delay =
1737 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1738 * give 10 times as much
1739 */
1740 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1741 {
1742 u8 timeout = 255;
1743
1744 serial_out(up, UART_OMAP_MDR1, mdr1);
1745 udelay(2);
1746 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1747 UART_FCR_CLEAR_RCVR);
1748 /*
1749 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1750 * TX_FIFO_E bit is 1.
1751 */
1752 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1753 (UART_LSR_THRE | UART_LSR_DR))) {
1754 timeout--;
1755 if (!timeout) {
1756 /* Should *never* happen. we warn and carry on */
1757 dev_crit(up->dev, "Errata i202: timedout %x\n",
1758 serial_in(up, UART_LSR));
1759 break;
1760 }
1761 udelay(1);
1762 }
1763 }
1764
1765 #ifdef CONFIG_PM
1766 static void serial_omap_restore_context(struct uart_omap_port *up)
1767 {
1768 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1769 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1770 else
1771 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1772
1773 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1774 serial_out(up, UART_EFR, UART_EFR_ECB);
1775 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1776 serial_out(up, UART_IER, 0x0);
1777 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1778 serial_out(up, UART_DLL, up->dll);
1779 serial_out(up, UART_DLM, up->dlh);
1780 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1781 serial_out(up, UART_IER, up->ier);
1782 serial_out(up, UART_FCR, up->fcr);
1783 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1784 serial_out(up, UART_MCR, up->mcr);
1785 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1786 serial_out(up, UART_OMAP_SCR, up->scr);
1787 serial_out(up, UART_EFR, up->efr);
1788 serial_out(up, UART_LCR, up->lcr);
1789 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1790 serial_omap_mdr1_errataset(up, up->mdr1);
1791 else
1792 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1793 serial_out(up, UART_OMAP_WER, up->wer);
1794 }
1795
1796 static int serial_omap_runtime_suspend(struct device *dev)
1797 {
1798 struct uart_omap_port *up = dev_get_drvdata(dev);
1799
1800 if (!up)
1801 return -EINVAL;
1802
1803 /*
1804 * When using 'no_console_suspend', the console UART must not be
1805 * suspended. Since driver suspend is managed by runtime suspend,
1806 * preventing runtime suspend (by returning error) will keep device
1807 * active during suspend.
1808 */
1809 if (up->is_suspending && !console_suspend_enabled &&
1810 uart_console(&up->port))
1811 return -EBUSY;
1812
1813 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1814
1815 serial_omap_enable_wakeup(up, true);
1816
1817 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1818 schedule_work(&up->qos_work);
1819
1820 return 0;
1821 }
1822
1823 static int serial_omap_runtime_resume(struct device *dev)
1824 {
1825 struct uart_omap_port *up = dev_get_drvdata(dev);
1826
1827 int loss_cnt = serial_omap_get_context_loss_count(up);
1828
1829 serial_omap_enable_wakeup(up, false);
1830
1831 if (loss_cnt < 0) {
1832 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1833 loss_cnt);
1834 serial_omap_restore_context(up);
1835 } else if (up->context_loss_cnt != loss_cnt) {
1836 serial_omap_restore_context(up);
1837 }
1838 up->latency = up->calc_latency;
1839 schedule_work(&up->qos_work);
1840
1841 return 0;
1842 }
1843 #endif
1844
1845 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1846 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1847 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1848 serial_omap_runtime_resume, NULL)
1849 .prepare = serial_omap_prepare,
1850 .complete = serial_omap_complete,
1851 };
1852
1853 #if defined(CONFIG_OF)
1854 static const struct of_device_id omap_serial_of_match[] = {
1855 { .compatible = "ti,omap2-uart" },
1856 { .compatible = "ti,omap3-uart" },
1857 { .compatible = "ti,omap4-uart" },
1858 {},
1859 };
1860 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1861 #endif
1862
1863 static struct platform_driver serial_omap_driver = {
1864 .probe = serial_omap_probe,
1865 .remove = serial_omap_remove,
1866 .driver = {
1867 .name = DRIVER_NAME,
1868 .pm = &serial_omap_dev_pm_ops,
1869 .of_match_table = of_match_ptr(omap_serial_of_match),
1870 },
1871 };
1872
1873 static int __init serial_omap_init(void)
1874 {
1875 int ret;
1876
1877 ret = uart_register_driver(&serial_omap_reg);
1878 if (ret != 0)
1879 return ret;
1880 ret = platform_driver_register(&serial_omap_driver);
1881 if (ret != 0)
1882 uart_unregister_driver(&serial_omap_reg);
1883 return ret;
1884 }
1885
1886 static void __exit serial_omap_exit(void)
1887 {
1888 platform_driver_unregister(&serial_omap_driver);
1889 uart_unregister_driver(&serial_omap_reg);
1890 }
1891
1892 module_init(serial_omap_init);
1893 module_exit(serial_omap_exit);
1894
1895 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1896 MODULE_LICENSE("GPL");
1897 MODULE_AUTHOR("Texas Instruments Inc");
Linux with added FPC-III support