?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
media: vimc: free vimc_cap_device when the last user disappears
[linux/fpc-iii.git] / drivers / spi / spi-omap2-mcspi.c
blob8be3043796285294bf4278ccbdc88fc985d2d92f
1 /*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/err.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/slab.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/gcd.h>
36 #include <linux/iopoll.h>
37
38 #include <linux/spi/spi.h>
39 #include <linux/gpio.h>
40
41 #include <linux/platform_data/spi-omap2-mcspi.h>
42
43 #define OMAP2_MCSPI_MAX_FREQ 48000000
44 #define OMAP2_MCSPI_MAX_DIVIDER 4096
45 #define OMAP2_MCSPI_MAX_FIFODEPTH 64
46 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
47 #define SPI_AUTOSUSPEND_TIMEOUT 2000
48
49 #define OMAP2_MCSPI_REVISION 0x00
50 #define OMAP2_MCSPI_SYSSTATUS 0x14
51 #define OMAP2_MCSPI_IRQSTATUS 0x18
52 #define OMAP2_MCSPI_IRQENABLE 0x1c
53 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
54 #define OMAP2_MCSPI_SYST 0x24
55 #define OMAP2_MCSPI_MODULCTRL 0x28
56 #define OMAP2_MCSPI_XFERLEVEL 0x7c
57
58 /* per-channel banks, 0x14 bytes each, first is: */
59 #define OMAP2_MCSPI_CHCONF0 0x2c
60 #define OMAP2_MCSPI_CHSTAT0 0x30
61 #define OMAP2_MCSPI_CHCTRL0 0x34
62 #define OMAP2_MCSPI_TX0 0x38
63 #define OMAP2_MCSPI_RX0 0x3c
64
65 /* per-register bitmasks: */
66 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
67
68 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
69 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
70 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
71
72 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
73 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
74 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
75 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
76 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
77 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
78 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
79 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
80 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
81 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
82 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
83 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
84 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
85 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
86 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
87 #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
88 #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
89 #define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
90
91 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
92 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
93 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
94 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
95
96 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
97 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
98
99 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
100
101 /* We have 2 DMA channels per CS, one for RX and one for TX */
102 struct omap2_mcspi_dma {
103 struct dma_chan *dma_tx;
104 struct dma_chan *dma_rx;
105
106 struct completion dma_tx_completion;
107 struct completion dma_rx_completion;
108
109 char dma_rx_ch_name[14];
110 char dma_tx_ch_name[14];
111 };
112
113 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
114 * cache operations; better heuristics consider wordsize and bitrate.
115 */
116 #define DMA_MIN_BYTES 160
117
118
119 /*
120 * Used for context save and restore, structure members to be updated whenever
121 * corresponding registers are modified.
122 */
123 struct omap2_mcspi_regs {
124 u32 modulctrl;
125 u32 wakeupenable;
126 struct list_head cs;
127 };
128
129 struct omap2_mcspi {
130 struct completion txdone;
131 struct spi_master *master;
132 /* Virtual base address of the controller */
133 void __iomem *base;
134 unsigned long phys;
135 /* SPI1 has 4 channels, while SPI2 has 2 */
136 struct omap2_mcspi_dma *dma_channels;
137 struct device *dev;
138 struct omap2_mcspi_regs ctx;
139 int fifo_depth;
140 bool slave_aborted;
141 unsigned int pin_dir:1;
142 };
143
144 struct omap2_mcspi_cs {
145 void __iomem *base;
146 unsigned long phys;
147 int word_len;
148 u16 mode;
149 struct list_head node;
150 /* Context save and restore shadow register */
151 u32 chconf0, chctrl0;
152 };
153
154 static inline void mcspi_write_reg(struct spi_master *master,
155 int idx, u32 val)
156 {
157 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
158
159 writel_relaxed(val, mcspi->base + idx);
160 }
161
162 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
163 {
164 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
165
166 return readl_relaxed(mcspi->base + idx);
167 }
168
169 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
170 int idx, u32 val)
171 {
172 struct omap2_mcspi_cs *cs = spi->controller_state;
173
174 writel_relaxed(val, cs->base + idx);
175 }
176
177 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
178 {
179 struct omap2_mcspi_cs *cs = spi->controller_state;
180
181 return readl_relaxed(cs->base + idx);
182 }
183
184 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
185 {
186 struct omap2_mcspi_cs *cs = spi->controller_state;
187
188 return cs->chconf0;
189 }
190
191 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
192 {
193 struct omap2_mcspi_cs *cs = spi->controller_state;
194
195 cs->chconf0 = val;
196 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
197 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
198 }
199
200 static inline int mcspi_bytes_per_word(int word_len)
201 {
202 if (word_len <= 8)
203 return 1;
204 else if (word_len <= 16)
205 return 2;
206 else /* word_len <= 32 */
207 return 4;
208 }
209
210 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
211 int is_read, int enable)
212 {
213 u32 l, rw;
214
215 l = mcspi_cached_chconf0(spi);
216
217 if (is_read) /* 1 is read, 0 write */
218 rw = OMAP2_MCSPI_CHCONF_DMAR;
219 else
220 rw = OMAP2_MCSPI_CHCONF_DMAW;
221
222 if (enable)
223 l |= rw;
224 else
225 l &= ~rw;
226
227 mcspi_write_chconf0(spi, l);
228 }
229
230 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
231 {
232 struct omap2_mcspi_cs *cs = spi->controller_state;
233 u32 l;
234
235 l = cs->chctrl0;
236 if (enable)
237 l |= OMAP2_MCSPI_CHCTRL_EN;
238 else
239 l &= ~OMAP2_MCSPI_CHCTRL_EN;
240 cs->chctrl0 = l;
241 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
242 /* Flash post-writes */
243 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
244 }
245
246 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
247 {
248 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
249 u32 l;
250
251 /* The controller handles the inverted chip selects
252 * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
253 * the inversion from the core spi_set_cs function.
254 */
255 if (spi->mode & SPI_CS_HIGH)
256 enable = !enable;
257
258 if (spi->controller_state) {
259 int err = pm_runtime_get_sync(mcspi->dev);
260 if (err < 0) {
261 pm_runtime_put_noidle(mcspi->dev);
262 dev_err(mcspi->dev, "failed to get sync: %d\n", err);
263 return;
264 }
265
266 l = mcspi_cached_chconf0(spi);
267
268 if (enable)
269 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
270 else
271 l |= OMAP2_MCSPI_CHCONF_FORCE;
272
273 mcspi_write_chconf0(spi, l);
274
275 pm_runtime_mark_last_busy(mcspi->dev);
276 pm_runtime_put_autosuspend(mcspi->dev);
277 }
278 }
279
280 static void omap2_mcspi_set_mode(struct spi_master *master)
281 {
282 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
283 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
284 u32 l;
285
286 /*
287 * Choose master or slave mode
288 */
289 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
290 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST);
291 if (spi_controller_is_slave(master)) {
292 l |= (OMAP2_MCSPI_MODULCTRL_MS);
293 } else {
294 l &= ~(OMAP2_MCSPI_MODULCTRL_MS);
295 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
296 }
297 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
298
299 ctx->modulctrl = l;
300 }
301
302 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
303 struct spi_transfer *t, int enable)
304 {
305 struct spi_master *master = spi->master;
306 struct omap2_mcspi_cs *cs = spi->controller_state;
307 struct omap2_mcspi *mcspi;
308 unsigned int wcnt;
309 int max_fifo_depth, bytes_per_word;
310 u32 chconf, xferlevel;
311
312 mcspi = spi_master_get_devdata(master);
313
314 chconf = mcspi_cached_chconf0(spi);
315 if (enable) {
316 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
317 if (t->len % bytes_per_word != 0)
318 goto disable_fifo;
319
320 if (t->rx_buf != NULL && t->tx_buf != NULL)
321 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
322 else
323 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
324
325 wcnt = t->len / bytes_per_word;
326 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
327 goto disable_fifo;
328
329 xferlevel = wcnt << 16;
330 if (t->rx_buf != NULL) {
331 chconf |= OMAP2_MCSPI_CHCONF_FFER;
332 xferlevel |= (bytes_per_word - 1) << 8;
333 }
334
335 if (t->tx_buf != NULL) {
336 chconf |= OMAP2_MCSPI_CHCONF_FFET;
337 xferlevel |= bytes_per_word - 1;
338 }
339
340 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
341 mcspi_write_chconf0(spi, chconf);
342 mcspi->fifo_depth = max_fifo_depth;
343
344 return;
345 }
346
347 disable_fifo:
348 if (t->rx_buf != NULL)
349 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
350
351 if (t->tx_buf != NULL)
352 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
353
354 mcspi_write_chconf0(spi, chconf);
355 mcspi->fifo_depth = 0;
356 }
357
358 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
359 {
360 u32 val;
361
362 return readl_poll_timeout(reg, val, val & bit, 1, MSEC_PER_SEC);
363 }
364
365 static int mcspi_wait_for_completion(struct omap2_mcspi *mcspi,
366 struct completion *x)
367 {
368 if (spi_controller_is_slave(mcspi->master)) {
369 if (wait_for_completion_interruptible(x) ||
370 mcspi->slave_aborted)
371 return -EINTR;
372 } else {
373 wait_for_completion(x);
374 }
375
376 return 0;
377 }
378
379 static void omap2_mcspi_rx_callback(void *data)
380 {
381 struct spi_device *spi = data;
382 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
383 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
384
385 /* We must disable the DMA RX request */
386 omap2_mcspi_set_dma_req(spi, 1, 0);
387
388 complete(&mcspi_dma->dma_rx_completion);
389 }
390
391 static void omap2_mcspi_tx_callback(void *data)
392 {
393 struct spi_device *spi = data;
394 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
395 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
396
397 /* We must disable the DMA TX request */
398 omap2_mcspi_set_dma_req(spi, 0, 0);
399
400 complete(&mcspi_dma->dma_tx_completion);
401 }
402
403 static void omap2_mcspi_tx_dma(struct spi_device *spi,
404 struct spi_transfer *xfer,
405 struct dma_slave_config cfg)
406 {
407 struct omap2_mcspi *mcspi;
408 struct omap2_mcspi_dma *mcspi_dma;
409
410 mcspi = spi_master_get_devdata(spi->master);
411 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
412
413 if (mcspi_dma->dma_tx) {
414 struct dma_async_tx_descriptor *tx;
415
416 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
417
418 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
419 xfer->tx_sg.nents,
420 DMA_MEM_TO_DEV,
421 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
422 if (tx) {
423 tx->callback = omap2_mcspi_tx_callback;
424 tx->callback_param = spi;
425 dmaengine_submit(tx);
426 } else {
427 /* FIXME: fall back to PIO? */
428 }
429 }
430 dma_async_issue_pending(mcspi_dma->dma_tx);
431 omap2_mcspi_set_dma_req(spi, 0, 1);
432
433 }
434
435 static unsigned
436 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
437 struct dma_slave_config cfg,
438 unsigned es)
439 {
440 struct omap2_mcspi *mcspi;
441 struct omap2_mcspi_dma *mcspi_dma;
442 unsigned int count, transfer_reduction = 0;
443 struct scatterlist *sg_out[2];
444 int nb_sizes = 0, out_mapped_nents[2], ret, x;
445 size_t sizes[2];
446 u32 l;
447 int elements = 0;
448 int word_len, element_count;
449 struct omap2_mcspi_cs *cs = spi->controller_state;
450 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
451
452 mcspi = spi_master_get_devdata(spi->master);
453 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
454 count = xfer->len;
455
456 /*
457 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
458 * it mentions reducing DMA transfer length by one element in master
459 * normal mode.
460 */
461 if (mcspi->fifo_depth == 0)
462 transfer_reduction = es;
463
464 word_len = cs->word_len;
465 l = mcspi_cached_chconf0(spi);
466
467 if (word_len <= 8)
468 element_count = count;
469 else if (word_len <= 16)
470 element_count = count >> 1;
471 else /* word_len <= 32 */
472 element_count = count >> 2;
473
474 if (mcspi_dma->dma_rx) {
475 struct dma_async_tx_descriptor *tx;
476
477 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
478
479 /*
480 * Reduce DMA transfer length by one more if McSPI is
481 * configured in turbo mode.
482 */
483 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
484 transfer_reduction += es;
485
486 if (transfer_reduction) {
487 /* Split sgl into two. The second sgl won't be used. */
488 sizes[0] = count - transfer_reduction;
489 sizes[1] = transfer_reduction;
490 nb_sizes = 2;
491 } else {
492 /*
493 * Don't bother splitting the sgl. This essentially
494 * clones the original sgl.
495 */
496 sizes[0] = count;
497 nb_sizes = 1;
498 }
499
500 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents,
501 0, nb_sizes,
502 sizes,
503 sg_out, out_mapped_nents,
504 GFP_KERNEL);
505
506 if (ret < 0) {
507 dev_err(&spi->dev, "sg_split failed\n");
508 return 0;
509 }
510
511 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx,
512 sg_out[0],
513 out_mapped_nents[0],
514 DMA_DEV_TO_MEM,
515 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
516 if (tx) {
517 tx->callback = omap2_mcspi_rx_callback;
518 tx->callback_param = spi;
519 dmaengine_submit(tx);
520 } else {
521 /* FIXME: fall back to PIO? */
522 }
523 }
524
525 dma_async_issue_pending(mcspi_dma->dma_rx);
526 omap2_mcspi_set_dma_req(spi, 1, 1);
527
528 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
529 if (ret || mcspi->slave_aborted) {
530 dmaengine_terminate_sync(mcspi_dma->dma_rx);
531 omap2_mcspi_set_dma_req(spi, 1, 0);
532 return 0;
533 }
534
535 for (x = 0; x < nb_sizes; x++)
536 kfree(sg_out[x]);
537
538 if (mcspi->fifo_depth > 0)
539 return count;
540
541 /*
542 * Due to the DMA transfer length reduction the missing bytes must
543 * be read manually to receive all of the expected data.
544 */
545 omap2_mcspi_set_enable(spi, 0);
546
547 elements = element_count - 1;
548
549 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
550 elements--;
551
552 if (!mcspi_wait_for_reg_bit(chstat_reg,
553 OMAP2_MCSPI_CHSTAT_RXS)) {
554 u32 w;
555
556 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
557 if (word_len <= 8)
558 ((u8 *)xfer->rx_buf)[elements++] = w;
559 else if (word_len <= 16)
560 ((u16 *)xfer->rx_buf)[elements++] = w;
561 else /* word_len <= 32 */
562 ((u32 *)xfer->rx_buf)[elements++] = w;
563 } else {
564 int bytes_per_word = mcspi_bytes_per_word(word_len);
565 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
566 count -= (bytes_per_word << 1);
567 omap2_mcspi_set_enable(spi, 1);
568 return count;
569 }
570 }
571 if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
572 u32 w;
573
574 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
575 if (word_len <= 8)
576 ((u8 *)xfer->rx_buf)[elements] = w;
577 else if (word_len <= 16)
578 ((u16 *)xfer->rx_buf)[elements] = w;
579 else /* word_len <= 32 */
580 ((u32 *)xfer->rx_buf)[elements] = w;
581 } else {
582 dev_err(&spi->dev, "DMA RX last word empty\n");
583 count -= mcspi_bytes_per_word(word_len);
584 }
585 omap2_mcspi_set_enable(spi, 1);
586 return count;
587 }
588
589 static unsigned
590 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
591 {
592 struct omap2_mcspi *mcspi;
593 struct omap2_mcspi_cs *cs = spi->controller_state;
594 struct omap2_mcspi_dma *mcspi_dma;
595 unsigned int count;
596 u8 *rx;
597 const u8 *tx;
598 struct dma_slave_config cfg;
599 enum dma_slave_buswidth width;
600 unsigned es;
601 void __iomem *chstat_reg;
602 void __iomem *irqstat_reg;
603 int wait_res;
604
605 mcspi = spi_master_get_devdata(spi->master);
606 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
607
608 if (cs->word_len <= 8) {
609 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
610 es = 1;
611 } else if (cs->word_len <= 16) {
612 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
613 es = 2;
614 } else {
615 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
616 es = 4;
617 }
618
619 count = xfer->len;
620
621 memset(&cfg, 0, sizeof(cfg));
622 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
623 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
624 cfg.src_addr_width = width;
625 cfg.dst_addr_width = width;
626 cfg.src_maxburst = 1;
627 cfg.dst_maxburst = 1;
628
629 rx = xfer->rx_buf;
630 tx = xfer->tx_buf;
631
632 mcspi->slave_aborted = false;
633 reinit_completion(&mcspi_dma->dma_tx_completion);
634 reinit_completion(&mcspi_dma->dma_rx_completion);
635 reinit_completion(&mcspi->txdone);
636 if (tx) {
637 /* Enable EOW IRQ to know end of tx in slave mode */
638 if (spi_controller_is_slave(spi->master))
639 mcspi_write_reg(spi->master,
640 OMAP2_MCSPI_IRQENABLE,
641 OMAP2_MCSPI_IRQSTATUS_EOW);
642 omap2_mcspi_tx_dma(spi, xfer, cfg);
643 }
644
645 if (rx != NULL)
646 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
647
648 if (tx != NULL) {
649 int ret;
650
651 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
652 if (ret || mcspi->slave_aborted) {
653 dmaengine_terminate_sync(mcspi_dma->dma_tx);
654 omap2_mcspi_set_dma_req(spi, 0, 0);
655 return 0;
656 }
657
658 if (spi_controller_is_slave(mcspi->master)) {
659 ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
660 if (ret || mcspi->slave_aborted)
661 return 0;
662 }
663
664 if (mcspi->fifo_depth > 0) {
665 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
666
667 if (mcspi_wait_for_reg_bit(irqstat_reg,
668 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
669 dev_err(&spi->dev, "EOW timed out\n");
670
671 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
672 OMAP2_MCSPI_IRQSTATUS_EOW);
673 }
674
675 /* for TX_ONLY mode, be sure all words have shifted out */
676 if (rx == NULL) {
677 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
678 if (mcspi->fifo_depth > 0) {
679 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
680 OMAP2_MCSPI_CHSTAT_TXFFE);
681 if (wait_res < 0)
682 dev_err(&spi->dev, "TXFFE timed out\n");
683 } else {
684 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
685 OMAP2_MCSPI_CHSTAT_TXS);
686 if (wait_res < 0)
687 dev_err(&spi->dev, "TXS timed out\n");
688 }
689 if (wait_res >= 0 &&
690 (mcspi_wait_for_reg_bit(chstat_reg,
691 OMAP2_MCSPI_CHSTAT_EOT) < 0))
692 dev_err(&spi->dev, "EOT timed out\n");
693 }
694 }
695 return count;
696 }
697
698 static unsigned
699 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
700 {
701 struct omap2_mcspi_cs *cs = spi->controller_state;
702 unsigned int count, c;
703 u32 l;
704 void __iomem *base = cs->base;
705 void __iomem *tx_reg;
706 void __iomem *rx_reg;
707 void __iomem *chstat_reg;
708 int word_len;
709
710 count = xfer->len;
711 c = count;
712 word_len = cs->word_len;
713
714 l = mcspi_cached_chconf0(spi);
715
716 /* We store the pre-calculated register addresses on stack to speed
717 * up the transfer loop. */
718 tx_reg = base + OMAP2_MCSPI_TX0;
719 rx_reg = base + OMAP2_MCSPI_RX0;
720 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
721
722 if (c < (word_len>>3))
723 return 0;
724
725 if (word_len <= 8) {
726 u8 *rx;
727 const u8 *tx;
728
729 rx = xfer->rx_buf;
730 tx = xfer->tx_buf;
731
732 do {
733 c -= 1;
734 if (tx != NULL) {
735 if (mcspi_wait_for_reg_bit(chstat_reg,
736 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
737 dev_err(&spi->dev, "TXS timed out\n");
738 goto out;
739 }
740 dev_vdbg(&spi->dev, "write-%d %02x\n",
741 word_len, *tx);
742 writel_relaxed(*tx++, tx_reg);
743 }
744 if (rx != NULL) {
745 if (mcspi_wait_for_reg_bit(chstat_reg,
746 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
747 dev_err(&spi->dev, "RXS timed out\n");
748 goto out;
749 }
750
751 if (c == 1 && tx == NULL &&
752 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
753 omap2_mcspi_set_enable(spi, 0);
754 *rx++ = readl_relaxed(rx_reg);
755 dev_vdbg(&spi->dev, "read-%d %02x\n",
756 word_len, *(rx - 1));
757 if (mcspi_wait_for_reg_bit(chstat_reg,
758 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
759 dev_err(&spi->dev,
760 "RXS timed out\n");
761 goto out;
762 }
763 c = 0;
764 } else if (c == 0 && tx == NULL) {
765 omap2_mcspi_set_enable(spi, 0);
766 }
767
768 *rx++ = readl_relaxed(rx_reg);
769 dev_vdbg(&spi->dev, "read-%d %02x\n",
770 word_len, *(rx - 1));
771 }
772 } while (c);
773 } else if (word_len <= 16) {
774 u16 *rx;
775 const u16 *tx;
776
777 rx = xfer->rx_buf;
778 tx = xfer->tx_buf;
779 do {
780 c -= 2;
781 if (tx != NULL) {
782 if (mcspi_wait_for_reg_bit(chstat_reg,
783 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
784 dev_err(&spi->dev, "TXS timed out\n");
785 goto out;
786 }
787 dev_vdbg(&spi->dev, "write-%d %04x\n",
788 word_len, *tx);
789 writel_relaxed(*tx++, tx_reg);
790 }
791 if (rx != NULL) {
792 if (mcspi_wait_for_reg_bit(chstat_reg,
793 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
794 dev_err(&spi->dev, "RXS timed out\n");
795 goto out;
796 }
797
798 if (c == 2 && tx == NULL &&
799 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
800 omap2_mcspi_set_enable(spi, 0);
801 *rx++ = readl_relaxed(rx_reg);
802 dev_vdbg(&spi->dev, "read-%d %04x\n",
803 word_len, *(rx - 1));
804 if (mcspi_wait_for_reg_bit(chstat_reg,
805 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
806 dev_err(&spi->dev,
807 "RXS timed out\n");
808 goto out;
809 }
810 c = 0;
811 } else if (c == 0 && tx == NULL) {
812 omap2_mcspi_set_enable(spi, 0);
813 }
814
815 *rx++ = readl_relaxed(rx_reg);
816 dev_vdbg(&spi->dev, "read-%d %04x\n",
817 word_len, *(rx - 1));
818 }
819 } while (c >= 2);
820 } else if (word_len <= 32) {
821 u32 *rx;
822 const u32 *tx;
823
824 rx = xfer->rx_buf;
825 tx = xfer->tx_buf;
826 do {
827 c -= 4;
828 if (tx != NULL) {
829 if (mcspi_wait_for_reg_bit(chstat_reg,
830 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
831 dev_err(&spi->dev, "TXS timed out\n");
832 goto out;
833 }
834 dev_vdbg(&spi->dev, "write-%d %08x\n",
835 word_len, *tx);
836 writel_relaxed(*tx++, tx_reg);
837 }
838 if (rx != NULL) {
839 if (mcspi_wait_for_reg_bit(chstat_reg,
840 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
841 dev_err(&spi->dev, "RXS timed out\n");
842 goto out;
843 }
844
845 if (c == 4 && tx == NULL &&
846 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
847 omap2_mcspi_set_enable(spi, 0);
848 *rx++ = readl_relaxed(rx_reg);
849 dev_vdbg(&spi->dev, "read-%d %08x\n",
850 word_len, *(rx - 1));
851 if (mcspi_wait_for_reg_bit(chstat_reg,
852 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
853 dev_err(&spi->dev,
854 "RXS timed out\n");
855 goto out;
856 }
857 c = 0;
858 } else if (c == 0 && tx == NULL) {
859 omap2_mcspi_set_enable(spi, 0);
860 }
861
862 *rx++ = readl_relaxed(rx_reg);
863 dev_vdbg(&spi->dev, "read-%d %08x\n",
864 word_len, *(rx - 1));
865 }
866 } while (c >= 4);
867 }
868
869 /* for TX_ONLY mode, be sure all words have shifted out */
870 if (xfer->rx_buf == NULL) {
871 if (mcspi_wait_for_reg_bit(chstat_reg,
872 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
873 dev_err(&spi->dev, "TXS timed out\n");
874 } else if (mcspi_wait_for_reg_bit(chstat_reg,
875 OMAP2_MCSPI_CHSTAT_EOT) < 0)
876 dev_err(&spi->dev, "EOT timed out\n");
877
878 /* disable chan to purge rx datas received in TX_ONLY transfer,
879 * otherwise these rx datas will affect the direct following
880 * RX_ONLY transfer.
881 */
882 omap2_mcspi_set_enable(spi, 0);
883 }
884 out:
885 omap2_mcspi_set_enable(spi, 1);
886 return count - c;
887 }
888
889 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
890 {
891 u32 div;
892
893 for (div = 0; div < 15; div++)
894 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
895 return div;
896
897 return 15;
898 }
899
900 /* called only when no transfer is active to this device */
901 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
902 struct spi_transfer *t)
903 {
904 struct omap2_mcspi_cs *cs = spi->controller_state;
905 struct omap2_mcspi *mcspi;
906 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
907 u8 word_len = spi->bits_per_word;
908 u32 speed_hz = spi->max_speed_hz;
909
910 mcspi = spi_master_get_devdata(spi->master);
911
912 if (t != NULL && t->bits_per_word)
913 word_len = t->bits_per_word;
914
915 cs->word_len = word_len;
916
917 if (t && t->speed_hz)
918 speed_hz = t->speed_hz;
919
920 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
921 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
922 clkd = omap2_mcspi_calc_divisor(speed_hz);
923 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
924 clkg = 0;
925 } else {
926 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
927 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
928 clkd = (div - 1) & 0xf;
929 extclk = (div - 1) >> 4;
930 clkg = OMAP2_MCSPI_CHCONF_CLKG;
931 }
932
933 l = mcspi_cached_chconf0(spi);
934
935 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
936 * REVISIT: this controller could support SPI_3WIRE mode.
937 */
938 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
939 l &= ~OMAP2_MCSPI_CHCONF_IS;
940 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
941 l |= OMAP2_MCSPI_CHCONF_DPE0;
942 } else {
943 l |= OMAP2_MCSPI_CHCONF_IS;
944 l |= OMAP2_MCSPI_CHCONF_DPE1;
945 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
946 }
947
948 /* wordlength */
949 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
950 l |= (word_len - 1) << 7;
951
952 /* set chipselect polarity; manage with FORCE */
953 if (!(spi->mode & SPI_CS_HIGH))
954 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
955 else
956 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
957
958 /* set clock divisor */
959 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
960 l |= clkd << 2;
961
962 /* set clock granularity */
963 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
964 l |= clkg;
965 if (clkg) {
966 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
967 cs->chctrl0 |= extclk << 8;
968 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
969 }
970
971 /* set SPI mode 0..3 */
972 if (spi->mode & SPI_CPOL)
973 l |= OMAP2_MCSPI_CHCONF_POL;
974 else
975 l &= ~OMAP2_MCSPI_CHCONF_POL;
976 if (spi->mode & SPI_CPHA)
977 l |= OMAP2_MCSPI_CHCONF_PHA;
978 else
979 l &= ~OMAP2_MCSPI_CHCONF_PHA;
980
981 mcspi_write_chconf0(spi, l);
982
983 cs->mode = spi->mode;
984
985 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
986 speed_hz,
987 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
988 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
989
990 return 0;
991 }
992
993 /*
994 * Note that we currently allow DMA only if we get a channel
995 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
996 */
997 static int omap2_mcspi_request_dma(struct spi_device *spi)
998 {
999 struct spi_master *master = spi->master;
1000 struct omap2_mcspi *mcspi;
1001 struct omap2_mcspi_dma *mcspi_dma;
1002 int ret = 0;
1003
1004 mcspi = spi_master_get_devdata(master);
1005 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1006
1007 init_completion(&mcspi_dma->dma_rx_completion);
1008 init_completion(&mcspi_dma->dma_tx_completion);
1009
1010 mcspi_dma->dma_rx = dma_request_chan(&master->dev,
1011 mcspi_dma->dma_rx_ch_name);
1012 if (IS_ERR(mcspi_dma->dma_rx)) {
1013 ret = PTR_ERR(mcspi_dma->dma_rx);
1014 mcspi_dma->dma_rx = NULL;
1015 goto no_dma;
1016 }
1017
1018 mcspi_dma->dma_tx = dma_request_chan(&master->dev,
1019 mcspi_dma->dma_tx_ch_name);
1020 if (IS_ERR(mcspi_dma->dma_tx)) {
1021 ret = PTR_ERR(mcspi_dma->dma_tx);
1022 mcspi_dma->dma_tx = NULL;
1023 dma_release_channel(mcspi_dma->dma_rx);
1024 mcspi_dma->dma_rx = NULL;
1025 }
1026
1027 no_dma:
1028 return ret;
1029 }
1030
1031 static int omap2_mcspi_setup(struct spi_device *spi)
1032 {
1033 int ret;
1034 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1035 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1036 struct omap2_mcspi_dma *mcspi_dma;
1037 struct omap2_mcspi_cs *cs = spi->controller_state;
1038
1039 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1040
1041 if (!cs) {
1042 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1043 if (!cs)
1044 return -ENOMEM;
1045 cs->base = mcspi->base + spi->chip_select * 0x14;
1046 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1047 cs->mode = 0;
1048 cs->chconf0 = 0;
1049 cs->chctrl0 = 0;
1050 spi->controller_state = cs;
1051 /* Link this to context save list */
1052 list_add_tail(&cs->node, &ctx->cs);
1053
1054 if (gpio_is_valid(spi->cs_gpio)) {
1055 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1056 if (ret) {
1057 dev_err(&spi->dev, "failed to request gpio\n");
1058 return ret;
1059 }
1060 gpio_direction_output(spi->cs_gpio,
1061 !(spi->mode & SPI_CS_HIGH));
1062 }
1063 }
1064
1065 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1066 ret = omap2_mcspi_request_dma(spi);
1067 if (ret)
1068 dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
1069 ret);
1070 }
1071
1072 ret = pm_runtime_get_sync(mcspi->dev);
1073 if (ret < 0) {
1074 pm_runtime_put_noidle(mcspi->dev);
1075
1076 return ret;
1077 }
1078
1079 ret = omap2_mcspi_setup_transfer(spi, NULL);
1080 pm_runtime_mark_last_busy(mcspi->dev);
1081 pm_runtime_put_autosuspend(mcspi->dev);
1082
1083 return ret;
1084 }
1085
1086 static void omap2_mcspi_cleanup(struct spi_device *spi)
1087 {
1088 struct omap2_mcspi *mcspi;
1089 struct omap2_mcspi_dma *mcspi_dma;
1090 struct omap2_mcspi_cs *cs;
1091
1092 mcspi = spi_master_get_devdata(spi->master);
1093
1094 if (spi->controller_state) {
1095 /* Unlink controller state from context save list */
1096 cs = spi->controller_state;
1097 list_del(&cs->node);
1098
1099 kfree(cs);
1100 }
1101
1102 if (spi->chip_select < spi->master->num_chipselect) {
1103 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1104
1105 if (mcspi_dma->dma_rx) {
1106 dma_release_channel(mcspi_dma->dma_rx);
1107 mcspi_dma->dma_rx = NULL;
1108 }
1109 if (mcspi_dma->dma_tx) {
1110 dma_release_channel(mcspi_dma->dma_tx);
1111 mcspi_dma->dma_tx = NULL;
1112 }
1113 }
1114
1115 if (gpio_is_valid(spi->cs_gpio))
1116 gpio_free(spi->cs_gpio);
1117 }
1118
1119 static irqreturn_t omap2_mcspi_irq_handler(int irq, void *data)
1120 {
1121 struct omap2_mcspi *mcspi = data;
1122 u32 irqstat;
1123
1124 irqstat = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS);
1125 if (!irqstat)
1126 return IRQ_NONE;
1127
1128 /* Disable IRQ and wakeup slave xfer task */
1129 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0);
1130 if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW)
1131 complete(&mcspi->txdone);
1132
1133 return IRQ_HANDLED;
1134 }
1135
1136 static int omap2_mcspi_slave_abort(struct spi_master *master)
1137 {
1138 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1139 struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
1140
1141 mcspi->slave_aborted = true;
1142 complete(&mcspi_dma->dma_rx_completion);
1143 complete(&mcspi_dma->dma_tx_completion);
1144 complete(&mcspi->txdone);
1145
1146 return 0;
1147 }
1148
1149 static int omap2_mcspi_transfer_one(struct spi_master *master,
1150 struct spi_device *spi,
1151 struct spi_transfer *t)
1152 {
1153
1154 /* We only enable one channel at a time -- the one whose message is
1155 * -- although this controller would gladly
1156 * arbitrate among multiple channels. This corresponds to "single
1157 * channel" master mode. As a side effect, we need to manage the
1158 * chipselect with the FORCE bit ... CS != channel enable.
1159 */
1160
1161 struct omap2_mcspi *mcspi;
1162 struct omap2_mcspi_dma *mcspi_dma;
1163 struct omap2_mcspi_cs *cs;
1164 struct omap2_mcspi_device_config *cd;
1165 int par_override = 0;
1166 int status = 0;
1167 u32 chconf;
1168
1169 mcspi = spi_master_get_devdata(master);
1170 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1171 cs = spi->controller_state;
1172 cd = spi->controller_data;
1173
1174 /*
1175 * The slave driver could have changed spi->mode in which case
1176 * it will be different from cs->mode (the current hardware setup).
1177 * If so, set par_override (even though its not a parity issue) so
1178 * omap2_mcspi_setup_transfer will be called to configure the hardware
1179 * with the correct mode on the first iteration of the loop below.
1180 */
1181 if (spi->mode != cs->mode)
1182 par_override = 1;
1183
1184 omap2_mcspi_set_enable(spi, 0);
1185
1186 if (gpio_is_valid(spi->cs_gpio))
1187 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1188
1189 if (par_override ||
1190 (t->speed_hz != spi->max_speed_hz) ||
1191 (t->bits_per_word != spi->bits_per_word)) {
1192 par_override = 1;
1193 status = omap2_mcspi_setup_transfer(spi, t);
1194 if (status < 0)
1195 goto out;
1196 if (t->speed_hz == spi->max_speed_hz &&
1197 t->bits_per_word == spi->bits_per_word)
1198 par_override = 0;
1199 }
1200 if (cd && cd->cs_per_word) {
1201 chconf = mcspi->ctx.modulctrl;
1202 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1203 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1204 mcspi->ctx.modulctrl =
1205 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1206 }
1207
1208 chconf = mcspi_cached_chconf0(spi);
1209 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1210 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1211
1212 if (t->tx_buf == NULL)
1213 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1214 else if (t->rx_buf == NULL)
1215 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1216
1217 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1218 /* Turbo mode is for more than one word */
1219 if (t->len > ((cs->word_len + 7) >> 3))
1220 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1221 }
1222
1223 mcspi_write_chconf0(spi, chconf);
1224
1225 if (t->len) {
1226 unsigned count;
1227
1228 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1229 master->cur_msg_mapped &&
1230 master->can_dma(master, spi, t))
1231 omap2_mcspi_set_fifo(spi, t, 1);
1232
1233 omap2_mcspi_set_enable(spi, 1);
1234
1235 /* RX_ONLY mode needs dummy data in TX reg */
1236 if (t->tx_buf == NULL)
1237 writel_relaxed(0, cs->base
1238 + OMAP2_MCSPI_TX0);
1239
1240 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1241 master->cur_msg_mapped &&
1242 master->can_dma(master, spi, t))
1243 count = omap2_mcspi_txrx_dma(spi, t);
1244 else
1245 count = omap2_mcspi_txrx_pio(spi, t);
1246
1247 if (count != t->len) {
1248 status = -EIO;
1249 goto out;
1250 }
1251 }
1252
1253 omap2_mcspi_set_enable(spi, 0);
1254
1255 if (mcspi->fifo_depth > 0)
1256 omap2_mcspi_set_fifo(spi, t, 0);
1257
1258 out:
1259 /* Restore defaults if they were overriden */
1260 if (par_override) {
1261 par_override = 0;
1262 status = omap2_mcspi_setup_transfer(spi, NULL);
1263 }
1264
1265 if (cd && cd->cs_per_word) {
1266 chconf = mcspi->ctx.modulctrl;
1267 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1268 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1269 mcspi->ctx.modulctrl =
1270 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1271 }
1272
1273 omap2_mcspi_set_enable(spi, 0);
1274
1275 if (gpio_is_valid(spi->cs_gpio))
1276 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1277
1278 if (mcspi->fifo_depth > 0 && t)
1279 omap2_mcspi_set_fifo(spi, t, 0);
1280
1281 return status;
1282 }
1283
1284 static int omap2_mcspi_prepare_message(struct spi_master *master,
1285 struct spi_message *msg)
1286 {
1287 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1288 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1289 struct omap2_mcspi_cs *cs;
1290
1291 /* Only a single channel can have the FORCE bit enabled
1292 * in its chconf0 register.
1293 * Scan all channels and disable them except the current one.
1294 * A FORCE can remain from a last transfer having cs_change enabled
1295 */
1296 list_for_each_entry(cs, &ctx->cs, node) {
1297 if (msg->spi->controller_state == cs)
1298 continue;
1299
1300 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1301 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1302 writel_relaxed(cs->chconf0,
1303 cs->base + OMAP2_MCSPI_CHCONF0);
1304 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1305 }
1306 }
1307
1308 return 0;
1309 }
1310
1311 static bool omap2_mcspi_can_dma(struct spi_master *master,
1312 struct spi_device *spi,
1313 struct spi_transfer *xfer)
1314 {
1315 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1316 struct omap2_mcspi_dma *mcspi_dma =
1317 &mcspi->dma_channels[spi->chip_select];
1318
1319 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
1320 return false;
1321
1322 if (spi_controller_is_slave(master))
1323 return true;
1324
1325 return (xfer->len >= DMA_MIN_BYTES);
1326 }
1327
1328 static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
1329 {
1330 struct spi_master *master = mcspi->master;
1331 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1332 int ret = 0;
1333
1334 ret = pm_runtime_get_sync(mcspi->dev);
1335 if (ret < 0) {
1336 pm_runtime_put_noidle(mcspi->dev);
1337
1338 return ret;
1339 }
1340
1341 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1342 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1343 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1344
1345 omap2_mcspi_set_mode(master);
1346 pm_runtime_mark_last_busy(mcspi->dev);
1347 pm_runtime_put_autosuspend(mcspi->dev);
1348 return 0;
1349 }
1350
1351 /*
1352 * When SPI wake up from off-mode, CS is in activate state. If it was in
1353 * inactive state when driver was suspend, then force it to inactive state at
1354 * wake up.
1355 */
1356 static int omap_mcspi_runtime_resume(struct device *dev)
1357 {
1358 struct spi_master *master = dev_get_drvdata(dev);
1359 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1360 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1361 struct omap2_mcspi_cs *cs;
1362
1363 /* McSPI: context restore */
1364 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
1365 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
1366
1367 list_for_each_entry(cs, &ctx->cs, node) {
1368 /*
1369 * We need to toggle CS state for OMAP take this
1370 * change in account.
1371 */
1372 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1373 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1374 writel_relaxed(cs->chconf0,
1375 cs->base + OMAP2_MCSPI_CHCONF0);
1376 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1377 writel_relaxed(cs->chconf0,
1378 cs->base + OMAP2_MCSPI_CHCONF0);
1379 } else {
1380 writel_relaxed(cs->chconf0,
1381 cs->base + OMAP2_MCSPI_CHCONF0);
1382 }
1383 }
1384
1385 return 0;
1386 }
1387
1388 static struct omap2_mcspi_platform_config omap2_pdata = {
1389 .regs_offset = 0,
1390 };
1391
1392 static struct omap2_mcspi_platform_config omap4_pdata = {
1393 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1394 };
1395
1396 static const struct of_device_id omap_mcspi_of_match[] = {
1397 {
1398 .compatible = "ti,omap2-mcspi",
1399 .data = &omap2_pdata,
1400 },
1401 {
1402 .compatible = "ti,omap4-mcspi",
1403 .data = &omap4_pdata,
1404 },
1405 { },
1406 };
1407 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1408
1409 static int omap2_mcspi_probe(struct platform_device *pdev)
1410 {
1411 struct spi_master *master;
1412 const struct omap2_mcspi_platform_config *pdata;
1413 struct omap2_mcspi *mcspi;
1414 struct resource *r;
1415 int status = 0, i;
1416 u32 regs_offset = 0;
1417 struct device_node *node = pdev->dev.of_node;
1418 const struct of_device_id *match;
1419
1420 if (of_property_read_bool(node, "spi-slave"))
1421 master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi));
1422 else
1423 master = spi_alloc_master(&pdev->dev, sizeof(*mcspi));
1424 if (!master)
1425 return -ENOMEM;
1426
1427 /* the spi->mode bits understood by this driver: */
1428 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1429 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1430 master->setup = omap2_mcspi_setup;
1431 master->auto_runtime_pm = true;
1432 master->prepare_message = omap2_mcspi_prepare_message;
1433 master->can_dma = omap2_mcspi_can_dma;
1434 master->transfer_one = omap2_mcspi_transfer_one;
1435 master->set_cs = omap2_mcspi_set_cs;
1436 master->cleanup = omap2_mcspi_cleanup;
1437 master->slave_abort = omap2_mcspi_slave_abort;
1438 master->dev.of_node = node;
1439 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1440 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1441
1442 platform_set_drvdata(pdev, master);
1443
1444 mcspi = spi_master_get_devdata(master);
1445 mcspi->master = master;
1446
1447 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1448 if (match) {
1449 u32 num_cs = 1; /* default number of chipselect */
1450 pdata = match->data;
1451
1452 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1453 master->num_chipselect = num_cs;
1454 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1455 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1456 } else {
1457 pdata = dev_get_platdata(&pdev->dev);
1458 master->num_chipselect = pdata->num_cs;
1459 mcspi->pin_dir = pdata->pin_dir;
1460 }
1461 regs_offset = pdata->regs_offset;
1462
1463 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1464 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1465 if (IS_ERR(mcspi->base)) {
1466 status = PTR_ERR(mcspi->base);
1467 goto free_master;
1468 }
1469 mcspi->phys = r->start + regs_offset;
1470 mcspi->base += regs_offset;
1471
1472 mcspi->dev = &pdev->dev;
1473
1474 INIT_LIST_HEAD(&mcspi->ctx.cs);
1475
1476 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1477 sizeof(struct omap2_mcspi_dma),
1478 GFP_KERNEL);
1479 if (mcspi->dma_channels == NULL) {
1480 status = -ENOMEM;
1481 goto free_master;
1482 }
1483
1484 for (i = 0; i < master->num_chipselect; i++) {
1485 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1486 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1487 }
1488
1489 status = platform_get_irq(pdev, 0);
1490 if (status == -EPROBE_DEFER)
1491 goto free_master;
1492 if (status < 0) {
1493 dev_err(&pdev->dev, "no irq resource found\n");
1494 goto free_master;
1495 }
1496 init_completion(&mcspi->txdone);
1497 status = devm_request_irq(&pdev->dev, status,
1498 omap2_mcspi_irq_handler, 0, pdev->name,
1499 mcspi);
1500 if (status) {
1501 dev_err(&pdev->dev, "Cannot request IRQ");
1502 goto free_master;
1503 }
1504
1505 pm_runtime_use_autosuspend(&pdev->dev);
1506 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1507 pm_runtime_enable(&pdev->dev);
1508
1509 status = omap2_mcspi_controller_setup(mcspi);
1510 if (status < 0)
1511 goto disable_pm;
1512
1513 status = devm_spi_register_controller(&pdev->dev, master);
1514 if (status < 0)
1515 goto disable_pm;
1516
1517 return status;
1518
1519 disable_pm:
1520 pm_runtime_dont_use_autosuspend(&pdev->dev);
1521 pm_runtime_put_sync(&pdev->dev);
1522 pm_runtime_disable(&pdev->dev);
1523 free_master:
1524 spi_master_put(master);
1525 return status;
1526 }
1527
1528 static int omap2_mcspi_remove(struct platform_device *pdev)
1529 {
1530 struct spi_master *master = platform_get_drvdata(pdev);
1531 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1532
1533 pm_runtime_dont_use_autosuspend(mcspi->dev);
1534 pm_runtime_put_sync(mcspi->dev);
1535 pm_runtime_disable(&pdev->dev);
1536
1537 return 0;
1538 }
1539
1540 /* work with hotplug and coldplug */
1541 MODULE_ALIAS("platform:omap2_mcspi");
1542
1543 static int __maybe_unused omap2_mcspi_suspend(struct device *dev)
1544 {
1545 struct spi_master *master = dev_get_drvdata(dev);
1546 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1547 int error;
1548
1549 error = pinctrl_pm_select_sleep_state(dev);
1550 if (error)
1551 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1552 __func__, error);
1553
1554 error = spi_master_suspend(master);
1555 if (error)
1556 dev_warn(mcspi->dev, "%s: master suspend failed: %i\n",
1557 __func__, error);
1558
1559 return pm_runtime_force_suspend(dev);
1560 }
1561
1562 static int __maybe_unused omap2_mcspi_resume(struct device *dev)
1563 {
1564 struct spi_master *master = dev_get_drvdata(dev);
1565 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1566 int error;
1567
1568 error = pinctrl_pm_select_default_state(dev);
1569 if (error)
1570 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1571 __func__, error);
1572
1573 error = spi_master_resume(master);
1574 if (error)
1575 dev_warn(mcspi->dev, "%s: master resume failed: %i\n",
1576 __func__, error);
1577
1578 return pm_runtime_force_resume(dev);
1579 }
1580
1581 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1582 SET_SYSTEM_SLEEP_PM_OPS(omap2_mcspi_suspend,
1583 omap2_mcspi_resume)
1584 .runtime_resume = omap_mcspi_runtime_resume,
1585 };
1586
1587 static struct platform_driver omap2_mcspi_driver = {
1588 .driver = {
1589 .name = "omap2_mcspi",
1590 .pm = &omap2_mcspi_pm_ops,
1591 .of_match_table = omap_mcspi_of_match,
1592 },
1593 .probe = omap2_mcspi_probe,
1594 .remove = omap2_mcspi_remove,
1595 };
1596
1597 module_platform_driver(omap2_mcspi_driver);
1598 MODULE_LICENSE("GPL");
Linux with added FPC-III support