arch/arm/mach-shmobile/pm-rcar-gen2.c

   1 /*
   2  * R-Car Generation 2 Power management support
   3  *
   4  * Copyright (C) 2013 - 2015  Renesas Electronics Corporation
   5  * Copyright (C) 2011  Renesas Solutions Corp.
   6  * Copyright (C) 2011  Magnus Damm
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/ioport.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/smp.h>
  18 #include <linux/soc/renesas/rcar-sysc.h>
  19 #include <asm/io.h>
  20 #include <asm/cputype.h>
  21 #include "common.h"
  22 #include "rcar-gen2.h"
  23
  24 /* RST */
  25 #define RST             0xe6160000
  26
  27 #define CA15BAR         0x0020          /* CA15 Boot Address Register */
  28 #define CA7BAR          0x0030          /* CA7 Boot Address Register */
  29 #define CA15RESCNT      0x0040          /* CA15 Reset Control Register */
  30 #define CA7RESCNT       0x0044          /* CA7 Reset Control Register */
  31
  32 /* SYS Boot Address Register */
  33 #define SBAR_BAREN      BIT(4)          /* SBAR is valid */
  34
  35 /* Reset Control Registers */
  36 #define CA15RESCNT_CODE 0xa5a50000
  37 #define CA15RESCNT_CPUS 0xf             /* CPU0-3 */
  38 #define CA7RESCNT_CODE  0x5a5a0000
  39 #define CA7RESCNT_CPUS  0xf             /* CPU0-3 */
  40
  41 /* On-chip RAM */
  42 #define ICRAM1          0xe63c0000      /* Inter Connect RAM1 (4 KiB) */
  43
  44 static inline u32 phys_to_sbar(phys_addr_t addr)
  45 {
  46         return (addr >> 8) & 0xfffffc00;
  47 }
  48
  49 /* SYSC */
  50 #define SYSCIER 0x0c
  51 #define SYSCIMR 0x10
  52
  53 #if defined(CONFIG_SMP)
  54
  55 static void __init rcar_gen2_sysc_init(u32 syscier)
  56 {
  57         rcar_sysc_init(0xe6180000, syscier);
  58 }
  59
  60 #else /* CONFIG_SMP */
  61
  62 static inline void rcar_gen2_sysc_init(u32 syscier) {}
  63
  64 #endif /* CONFIG_SMP */
  65
  66 void __init rcar_gen2_pm_init(void)
  67 {
  68         void __iomem *p;
  69         u32 bar;
  70         static int once;
  71         struct device_node *np, *cpus;
  72         bool has_a7 = false;
  73         bool has_a15 = false;
  74         struct resource res;
  75         u32 syscier = 0;
  76         int error;
  77
  78         if (once++)
  79                 return;
  80
  81         cpus = of_find_node_by_path("/cpus");
  82         if (!cpus)
  83                 return;
  84
  85         for_each_child_of_node(cpus, np) {
  86                 if (of_device_is_compatible(np, "arm,cortex-a15"))
  87                         has_a15 = true;
  88                 else if (of_device_is_compatible(np, "arm,cortex-a7"))
  89                         has_a7 = true;
  90         }
  91
  92         if (of_machine_is_compatible("renesas,r8a7790"))
  93                 syscier = 0x013111ef;
  94         else if (of_machine_is_compatible("renesas,r8a7791"))
  95                 syscier = 0x00111003;
  96
  97         np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
  98         if (!np) {
  99                 /* No smp-sram in DT, fall back to hardcoded address */
 100                 res = (struct resource)DEFINE_RES_MEM(ICRAM1,
 101                                                       shmobile_boot_size);
 102                 goto map;
 103         }
 104
 105         error = of_address_to_resource(np, 0, &res);
 106         if (error) {
 107                 pr_err("Failed to get smp-sram address: %d\n", error);
 108                 return;
 109         }
 110
 111 map:
 112         /* RAM for jump stub, because BAR requires 256KB aligned address */
 113         if (res.start & (256 * 1024 - 1) ||
 114             resource_size(&res) < shmobile_boot_size) {
 115                 pr_err("Invalid smp-sram region\n");
 116                 return;
 117         }
 118
 119         p = ioremap(res.start, resource_size(&res));
 120         if (!p)
 121                 return;
 122         /*
 123          * install the reset vector, use the largest version if we have enough
 124          * memory available
 125          */
 126         if (resource_size(&res) >= shmobile_boot_size_gen2) {
 127                 shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
 128                 memcpy_toio(p, shmobile_boot_vector_gen2,
 129                             shmobile_boot_size_gen2);
 130         } else {
 131                 memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
 132         }
 133         iounmap(p);
 134
 135         /* setup reset vectors */
 136         p = ioremap_nocache(RST, 0x63);
 137         bar = phys_to_sbar(res.start);
 138         if (has_a15) {
 139                 writel_relaxed(bar, p + CA15BAR);
 140                 writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
 141
 142                 /* de-assert reset for CA15 CPUs */
 143                 writel_relaxed((readl_relaxed(p + CA15RESCNT) &
 144                                 ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
 145                                p + CA15RESCNT);
 146         }
 147         if (has_a7) {
 148                 writel_relaxed(bar, p + CA7BAR);
 149                 writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
 150
 151                 /* de-assert reset for CA7 CPUs */
 152                 writel_relaxed((readl_relaxed(p + CA7RESCNT) &
 153                                 ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
 154                                p + CA7RESCNT);
 155         }
 156         iounmap(p);
 157
 158         rcar_gen2_sysc_init(syscier);
 159         shmobile_smp_apmu_suspend_init();
 160 }