6 perf-c2c - Shared Data C2C/HITM Analyzer.
11 'perf c2c record' [<options>] <command>
12 'perf c2c record' [<options>] -- [<record command options>] <command>
13 'perf c2c report' [<options>]
17 C2C stands for Cache To Cache.
19 The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
20 you to track down the cacheline contentions.
22 On x86, the tool is based on load latency and precise store facility events
23 provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
24 with thresholding feature.
27 - memory address of the access
28 - type of the access (load and store details)
29 - latency (in cycles) of the load access
31 The c2c tool provide means to record this data and report back access details
32 for cachelines with highest contention - highest number of HITM accesses.
34 The basic workflow with this tool follows the standard record/report phase.
35 User uses the record command to record events data and report command to
43 Select the PMU event. Use 'perf mem record -e list'
44 to list available events.
48 Be more verbose (show counter open errors, etc).
52 Configure mem-loads latency. (x86 only)
56 Configure all used events to run in kernel space.
60 Configure all used events to run in user space.
70 Be more verbose (show counter open errors, etc).
74 Specify the input file to process.
78 Show extra node info in report (see NODE INFO section)
82 Specify sorting fields for single cacheline display.
83 Following fields are available: tid,pid,iaddr,dso
88 Setup callchains parameters.
89 Please refer to perf-report man page for details.
92 Force the stdio output (see STDIO OUTPUT)
95 Display only statistic tables and force stdio mode.
98 Display full length of symbols.
101 Do not display Source:Line column.
104 Show all captured HITM lines, with no regard to HITM % 0.0005 limit.
108 Don't do ownership validation.
112 Switch to HITM type (rmt, lcl) to display and sort on. Total HITMs as default.
116 The perf c2c record command setup options related to HITM cacheline analysis
117 and calls standard perf record command.
119 Following perf record options are configured by default:
120 (check perf record man page for details)
122 -W,-d,--phys-data,--sample-cpu
124 Unless specified otherwise with '-e' option, following events are monitored by
127 cpu/mem-loads,ldlat=30/P
130 and following on PowerPC:
135 User can pass any 'perf record' option behind '--' mark, like (to enable
136 callchains and system wide monitoring):
138 $ perf c2c record -- -g -a
140 Please check RECORD OPTIONS section for specific c2c record options.
144 The perf c2c report command displays shared data analysis. It comes in two
145 display modes: stdio and tui (default).
147 The report command workflow is following:
148 - sort all the data based on the cacheline address
149 - store access details for each cacheline
150 - sort all cachelines based on user settings
153 In general perf report output consist of 2 basic views:
154 1) most expensive cachelines list
155 2) offsets details for each cacheline
157 For each cacheline in the 1) list we display following data:
158 (Both stdio and TUI modes follow the same fields output)
161 - zero based index to identify the cacheline
164 - cacheline address (hex number)
167 - sum of all cachelines accesses
170 - cacheline percentage of all Remote/Local HITM accesses
172 LLC Load Hitm - Total, Lcl, Rmt
173 - count of Total/Local/Remote load HITMs
175 Store Reference - Total, L1Hit, L1Miss
176 Total - all store accesses
177 L1Hit - store accesses that hit L1
178 L1Hit - store accesses that missed L1
181 - count of local and remote DRAM accesses
184 - count of all accesses that missed LLC
187 - sum of all load accesses
189 Core Load Hit - FB, L1, L2
190 - count of load hits in FB (Fill Buffer), L1 and L2 cache
192 LLC Load Hit - Llc, Rmt
193 - count of LLC and Remote load hits
195 For each offset in the 2) list we display following data:
198 - % of Remote/Local HITM accesses for given offset within cacheline
200 Store Refs - L1 Hit, L1 Miss
201 - % of store accesses that hit/missed L1 for given offset within cacheline
203 Data address - Offset
207 - pid of the process responsible for the accesses
210 - tid of the process responsible for the accesses
213 - code address responsible for the accesses
215 cycles - rmt hitm, lcl hitm, load
216 - sum of cycles for given accesses - Remote/Local HITM and generic load
219 - number of cpus that participated on the access
222 - code symbol related to the 'Code address' value
225 - shared object name related to the 'Code address' value
228 - source information related to the 'Code address' value
231 - nodes participating on the access (see NODE INFO section)
235 The 'Node' field displays nodes that accesses given cacheline
236 offset. Its output comes in 3 flavors:
237 - node IDs separated by ','
238 - node IDs with stats for each ID, in following format:
239 Node{cpus %hitms %stores}
240 - node IDs with list of affected CPUs in following format:
243 User can switch between above flavors with -N option or
244 use 'n' key to interactively switch in TUI mode.
248 User can specify how to sort offsets for cacheline.
250 Following fields are available and governs the final
251 output fields set for caheline offsets output:
253 tid - coalesced by process TIDs
254 pid - coalesced by process PIDs
255 iaddr - coalesced by code address, following fields are displayed:
256 Code address, Code symbol, Shared Object, Source line
257 dso - coalesced by shared object
259 By default the coalescing is setup with 'pid,iaddr'.
263 The stdio output displays data on standard output.
265 Following tables are displayed:
266 Trace Event Information
267 - overall statistics of memory accesses
269 Global Shared Cache Line Event Information
270 - overall statistics on shared cachelines
272 Shared Data Cache Line Table
273 - list of most expensive cachelines
275 Shared Cache Line Distribution Pareto
276 - list of all accessed offsets for each cacheline
280 The TUI output provides interactive interface to navigate
281 through cachelines list and to display offset details.
283 For details please refer to the help window by pressing '?' key.
287 Although Don Zickus, Dick Fowles and Joe Mario worked together
288 to get this implemented, we got lots of early help from Arnaldo
289 Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.
293 Check Joe's blog on c2c tool for detailed use case explanation:
294 https://joemario.github.io/blog/2016/09/01/c2c-blog/
298 linkperf:perf-record[1], linkperf:perf-mem[1]