sound/soc/codecs/rt5677-spi.c

   1 /*
   2  * rt5677-spi.c  --  RT5677 ALSA SoC audio codec driver
   3  *
   4  * Copyright 2013 Realtek Semiconductor Corp.
   5  * Author: Oder Chiou <oder_chiou@realtek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/input.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/device.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/slab.h>
  21 #include <linux/gpio.h>
  22 #include <linux/sched.h>
  23 #include <linux/kthread.h>
  24 #include <linux/uaccess.h>
  25 #include <linux/miscdevice.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/pm_qos.h>
  28 #include <linux/sysfs.h>
  29 #include <linux/clk.h>
  30 #include <linux/firmware.h>
  31
  32 #include "rt5677-spi.h"
  33
  34 #define RT5677_SPI_BURST_LEN    240
  35 #define RT5677_SPI_HEADER       5
  36 #define RT5677_SPI_FREQ         6000000
  37
  38 /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire.
  39  * DataPhase word size of 16-bit commands is 2 bytes.
  40  * DataPhase word size of 32-bit commands is 4 bytes.
  41  * DataPhase word size of burst commands is 8 bytes.
  42  * The DSP CPU is little-endian.
  43  */
  44 #define RT5677_SPI_WRITE_BURST  0x5
  45 #define RT5677_SPI_READ_BURST   0x4
  46 #define RT5677_SPI_WRITE_32     0x3
  47 #define RT5677_SPI_READ_32      0x2
  48 #define RT5677_SPI_WRITE_16     0x1
  49 #define RT5677_SPI_READ_16      0x0
  50
  51 static struct spi_device *g_spi;
  52 static DEFINE_MUTEX(spi_mutex);
  53
  54 /* Select a suitable transfer command for the next transfer to ensure
  55  * the transfer address is always naturally aligned while minimizing
  56  * the total number of transfers required.
  57  *
  58  * 3 transfer commands are available:
  59  * RT5677_SPI_READ/WRITE_16:    Transfer 2 bytes
  60  * RT5677_SPI_READ/WRITE_32:    Transfer 4 bytes
  61  * RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes
  62  *
  63  * For example, reading 260 bytes at 0x60030002 uses the following commands:
  64  * 0x60030002 RT5677_SPI_READ_16        2 bytes
  65  * 0x60030004 RT5677_SPI_READ_32        4 bytes
  66  * 0x60030008 RT5677_SPI_READ_BURST     240 bytes
  67  * 0x600300F8 RT5677_SPI_READ_BURST     8 bytes
  68  * 0x60030100 RT5677_SPI_READ_32        4 bytes
  69  * 0x60030104 RT5677_SPI_READ_16        2 bytes
  70  *
  71  * Input:
  72  * @read: true for read commands; false for write commands
  73  * @align: alignment of the next transfer address
  74  * @remain: number of bytes remaining to transfer
  75  *
  76  * Output:
  77  * @len: number of bytes to transfer with the selected command
  78  * Returns the selected command
  79  */
  80 static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len)
  81 {
  82         u8 cmd;
  83
  84         if (align == 2 || align == 6 || remain == 2) {
  85                 cmd = RT5677_SPI_READ_16;
  86                 *len = 2;
  87         } else if (align == 4 || remain <= 6) {
  88                 cmd = RT5677_SPI_READ_32;
  89                 *len = 4;
  90         } else {
  91                 cmd = RT5677_SPI_READ_BURST;
  92                 *len = min_t(u32, remain & ~7, RT5677_SPI_BURST_LEN);
  93         }
  94         return read ? cmd : cmd + 1;
  95 }
  96
  97 /* Copy dstlen bytes from src to dst, while reversing byte order for each word.
  98  * If srclen < dstlen, zeros are padded.
  99  */
 100 static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen)
 101 {
 102         u32 w, i, si;
 103         u32 word_size = min_t(u32, dstlen, 8);
 104
 105         for (w = 0; w < dstlen; w += word_size) {
 106                 for (i = 0; i < word_size; i++) {
 107                         si = w + word_size - i - 1;
 108                         dst[w + i] = si < srclen ? src[si] : 0;
 109                 }
 110         }
 111 }
 112
 113 /* Read DSP address space using SPI. addr and len have to be 2-byte aligned. */
 114 int rt5677_spi_read(u32 addr, void *rxbuf, size_t len)
 115 {
 116         u32 offset;
 117         int status = 0;
 118         struct spi_transfer t[2];
 119         struct spi_message m;
 120         /* +4 bytes is for the DummyPhase following the AddressPhase */
 121         u8 header[RT5677_SPI_HEADER + 4];
 122         u8 body[RT5677_SPI_BURST_LEN];
 123         u8 spi_cmd;
 124         u8 *cb = rxbuf;
 125
 126         if (!g_spi)
 127                 return -ENODEV;
 128
 129         if ((addr & 1) || (len & 1)) {
 130                 dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len);
 131                 return -EACCES;
 132         }
 133
 134         memset(t, 0, sizeof(t));
 135         t[0].tx_buf = header;
 136         t[0].len = sizeof(header);
 137         t[0].speed_hz = RT5677_SPI_FREQ;
 138         t[1].rx_buf = body;
 139         t[1].speed_hz = RT5677_SPI_FREQ;
 140         spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
 141
 142         for (offset = 0; offset < len; offset += t[1].len) {
 143                 spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7,
 144                                 len - offset, &t[1].len);
 145
 146                 /* Construct SPI message header */
 147                 header[0] = spi_cmd;
 148                 header[1] = ((addr + offset) & 0xff000000) >> 24;
 149                 header[2] = ((addr + offset) & 0x00ff0000) >> 16;
 150                 header[3] = ((addr + offset) & 0x0000ff00) >> 8;
 151                 header[4] = ((addr + offset) & 0x000000ff) >> 0;
 152
 153                 mutex_lock(&spi_mutex);
 154                 status |= spi_sync(g_spi, &m);
 155                 mutex_unlock(&spi_mutex);
 156
 157                 /* Copy data back to caller buffer */
 158                 rt5677_spi_reverse(cb + offset, t[1].len, body, t[1].len);
 159         }
 160         return status;
 161 }
 162 EXPORT_SYMBOL_GPL(rt5677_spi_read);
 163
 164 /* Write DSP address space using SPI. addr has to be 2-byte aligned.
 165  * If len is not 2-byte aligned, an extra byte of zero is written at the end
 166  * as padding.
 167  */
 168 int rt5677_spi_write(u32 addr, const void *txbuf, size_t len)
 169 {
 170         u32 offset, len_with_pad = len;
 171         int status = 0;
 172         struct spi_transfer t;
 173         struct spi_message m;
 174         /* +1 byte is for the DummyPhase following the DataPhase */
 175         u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1];
 176         u8 *body = buf + RT5677_SPI_HEADER;
 177         u8 spi_cmd;
 178         const u8 *cb = txbuf;
 179
 180         if (!g_spi)
 181                 return -ENODEV;
 182
 183         if (addr & 1) {
 184                 dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len);
 185                 return -EACCES;
 186         }
 187
 188         if (len & 1)
 189                 len_with_pad = len + 1;
 190
 191         memset(&t, 0, sizeof(t));
 192         t.tx_buf = buf;
 193         t.speed_hz = RT5677_SPI_FREQ;
 194         spi_message_init_with_transfers(&m, &t, 1);
 195
 196         for (offset = 0; offset < len_with_pad;) {
 197                 spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7,
 198                                 len_with_pad - offset, &t.len);
 199
 200                 /* Construct SPI message header */
 201                 buf[0] = spi_cmd;
 202                 buf[1] = ((addr + offset) & 0xff000000) >> 24;
 203                 buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
 204                 buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
 205                 buf[4] = ((addr + offset) & 0x000000ff) >> 0;
 206
 207                 /* Fetch data from caller buffer */
 208                 rt5677_spi_reverse(body, t.len, cb + offset, len - offset);
 209                 offset += t.len;
 210                 t.len += RT5677_SPI_HEADER + 1;
 211
 212                 mutex_lock(&spi_mutex);
 213                 status |= spi_sync(g_spi, &m);
 214                 mutex_unlock(&spi_mutex);
 215         }
 216         return status;
 217 }
 218 EXPORT_SYMBOL_GPL(rt5677_spi_write);
 219
 220 int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw)
 221 {
 222         return rt5677_spi_write(addr, fw->data, fw->size);
 223 }
 224 EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware);
 225
 226 static int rt5677_spi_probe(struct spi_device *spi)
 227 {
 228         g_spi = spi;
 229         return 0;
 230 }
 231
 232 static struct spi_driver rt5677_spi_driver = {
 233         .driver = {
 234                 .name = "rt5677",
 235         },
 236         .probe = rt5677_spi_probe,
 237 };
 238 module_spi_driver(rt5677_spi_driver);
 239
 240 MODULE_DESCRIPTION("ASoC RT5677 SPI driver");
 241 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
 242 MODULE_LICENSE("GPL v2");