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driver core: bus: use to_subsys_private and to_device_private_bus
[linux/fpc-iii.git] / sound / soc / fsl / fsl_sai.c
blobfef264d27fd3378d726a77209647ccc8098ec6a0
1 /*
2 * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
3 *
4 * Copyright 2012-2015 Freescale Semiconductor, Inc.
5 *
6 * This program is free software, you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation, either version 2 of the License, or(at your
9 * option) any later version.
10 *
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <sound/core.h>
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/pcm_params.h>
23
24 #include "fsl_sai.h"
25 #include "imx-pcm.h"
26
27 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
28 FSL_SAI_CSR_FEIE)
29
30 static const unsigned int fsl_sai_rates[] = {
31 8000, 11025, 12000, 16000, 22050,
32 24000, 32000, 44100, 48000, 64000,
33 88200, 96000, 176400, 192000
34 };
35
36 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
37 .count = ARRAY_SIZE(fsl_sai_rates),
38 .list = fsl_sai_rates,
39 };
40
41 static irqreturn_t fsl_sai_isr(int irq, void *devid)
42 {
43 struct fsl_sai *sai = (struct fsl_sai *)devid;
44 struct device *dev = &sai->pdev->dev;
45 u32 flags, xcsr, mask;
46 bool irq_none = true;
47
48 /*
49 * Both IRQ status bits and IRQ mask bits are in the xCSR but
50 * different shifts. And we here create a mask only for those
51 * IRQs that we activated.
52 */
53 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
54
55 /* Tx IRQ */
56 regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
57 flags = xcsr & mask;
58
59 if (flags)
60 irq_none = false;
61 else
62 goto irq_rx;
63
64 if (flags & FSL_SAI_CSR_WSF)
65 dev_dbg(dev, "isr: Start of Tx word detected\n");
66
67 if (flags & FSL_SAI_CSR_SEF)
68 dev_warn(dev, "isr: Tx Frame sync error detected\n");
69
70 if (flags & FSL_SAI_CSR_FEF) {
71 dev_warn(dev, "isr: Transmit underrun detected\n");
72 /* FIFO reset for safety */
73 xcsr |= FSL_SAI_CSR_FR;
74 }
75
76 if (flags & FSL_SAI_CSR_FWF)
77 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
78
79 if (flags & FSL_SAI_CSR_FRF)
80 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
81
82 flags &= FSL_SAI_CSR_xF_W_MASK;
83 xcsr &= ~FSL_SAI_CSR_xF_MASK;
84
85 if (flags)
86 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
87
88 irq_rx:
89 /* Rx IRQ */
90 regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
91 flags = xcsr & mask;
92
93 if (flags)
94 irq_none = false;
95 else
96 goto out;
97
98 if (flags & FSL_SAI_CSR_WSF)
99 dev_dbg(dev, "isr: Start of Rx word detected\n");
100
101 if (flags & FSL_SAI_CSR_SEF)
102 dev_warn(dev, "isr: Rx Frame sync error detected\n");
103
104 if (flags & FSL_SAI_CSR_FEF) {
105 dev_warn(dev, "isr: Receive overflow detected\n");
106 /* FIFO reset for safety */
107 xcsr |= FSL_SAI_CSR_FR;
108 }
109
110 if (flags & FSL_SAI_CSR_FWF)
111 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
112
113 if (flags & FSL_SAI_CSR_FRF)
114 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
115
116 flags &= FSL_SAI_CSR_xF_W_MASK;
117 xcsr &= ~FSL_SAI_CSR_xF_MASK;
118
119 if (flags)
120 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
121
122 out:
123 if (irq_none)
124 return IRQ_NONE;
125 else
126 return IRQ_HANDLED;
127 }
128
129 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
130 u32 rx_mask, int slots, int slot_width)
131 {
132 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
133
134 sai->slots = slots;
135 sai->slot_width = slot_width;
136
137 return 0;
138 }
139
140 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
141 int clk_id, unsigned int freq, int fsl_dir)
142 {
143 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
144 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
145 u32 val_cr2 = 0;
146
147 switch (clk_id) {
148 case FSL_SAI_CLK_BUS:
149 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
150 break;
151 case FSL_SAI_CLK_MAST1:
152 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
153 break;
154 case FSL_SAI_CLK_MAST2:
155 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
156 break;
157 case FSL_SAI_CLK_MAST3:
158 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
159 break;
160 default:
161 return -EINVAL;
162 }
163
164 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
165 FSL_SAI_CR2_MSEL_MASK, val_cr2);
166
167 return 0;
168 }
169
170 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
171 int clk_id, unsigned int freq, int dir)
172 {
173 int ret;
174
175 if (dir == SND_SOC_CLOCK_IN)
176 return 0;
177
178 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
179 FSL_FMT_TRANSMITTER);
180 if (ret) {
181 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
182 return ret;
183 }
184
185 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
186 FSL_FMT_RECEIVER);
187 if (ret)
188 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
189
190 return ret;
191 }
192
193 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
194 unsigned int fmt, int fsl_dir)
195 {
196 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
197 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
198 u32 val_cr2 = 0, val_cr4 = 0;
199
200 if (!sai->is_lsb_first)
201 val_cr4 |= FSL_SAI_CR4_MF;
202
203 /* DAI mode */
204 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
205 case SND_SOC_DAIFMT_I2S:
206 /*
207 * Frame low, 1clk before data, one word length for frame sync,
208 * frame sync starts one serial clock cycle earlier,
209 * that is, together with the last bit of the previous
210 * data word.
211 */
212 val_cr2 |= FSL_SAI_CR2_BCP;
213 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
214 break;
215 case SND_SOC_DAIFMT_LEFT_J:
216 /*
217 * Frame high, one word length for frame sync,
218 * frame sync asserts with the first bit of the frame.
219 */
220 val_cr2 |= FSL_SAI_CR2_BCP;
221 break;
222 case SND_SOC_DAIFMT_DSP_A:
223 /*
224 * Frame high, 1clk before data, one bit for frame sync,
225 * frame sync starts one serial clock cycle earlier,
226 * that is, together with the last bit of the previous
227 * data word.
228 */
229 val_cr2 |= FSL_SAI_CR2_BCP;
230 val_cr4 |= FSL_SAI_CR4_FSE;
231 sai->is_dsp_mode = true;
232 break;
233 case SND_SOC_DAIFMT_DSP_B:
234 /*
235 * Frame high, one bit for frame sync,
236 * frame sync asserts with the first bit of the frame.
237 */
238 val_cr2 |= FSL_SAI_CR2_BCP;
239 sai->is_dsp_mode = true;
240 break;
241 case SND_SOC_DAIFMT_RIGHT_J:
242 /* To be done */
243 default:
244 return -EINVAL;
245 }
246
247 /* DAI clock inversion */
248 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
249 case SND_SOC_DAIFMT_IB_IF:
250 /* Invert both clocks */
251 val_cr2 ^= FSL_SAI_CR2_BCP;
252 val_cr4 ^= FSL_SAI_CR4_FSP;
253 break;
254 case SND_SOC_DAIFMT_IB_NF:
255 /* Invert bit clock */
256 val_cr2 ^= FSL_SAI_CR2_BCP;
257 break;
258 case SND_SOC_DAIFMT_NB_IF:
259 /* Invert frame clock */
260 val_cr4 ^= FSL_SAI_CR4_FSP;
261 break;
262 case SND_SOC_DAIFMT_NB_NF:
263 /* Nothing to do for both normal cases */
264 break;
265 default:
266 return -EINVAL;
267 }
268
269 /* DAI clock master masks */
270 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
271 case SND_SOC_DAIFMT_CBS_CFS:
272 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
273 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
274 break;
275 case SND_SOC_DAIFMT_CBM_CFM:
276 sai->is_slave_mode = true;
277 break;
278 case SND_SOC_DAIFMT_CBS_CFM:
279 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
280 break;
281 case SND_SOC_DAIFMT_CBM_CFS:
282 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
283 sai->is_slave_mode = true;
284 break;
285 default:
286 return -EINVAL;
287 }
288
289 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
290 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
291 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
292 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
293 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
294
295 return 0;
296 }
297
298 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
299 {
300 int ret;
301
302 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
303 if (ret) {
304 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
305 return ret;
306 }
307
308 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
309 if (ret)
310 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
311
312 return ret;
313 }
314
315 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
316 {
317 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
318 unsigned long clk_rate;
319 u32 savediv = 0, ratio, savesub = freq;
320 u32 id;
321 int ret = 0;
322
323 /* Don't apply to slave mode */
324 if (sai->is_slave_mode)
325 return 0;
326
327 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
328 clk_rate = clk_get_rate(sai->mclk_clk[id]);
329 if (!clk_rate)
330 continue;
331
332 ratio = clk_rate / freq;
333
334 ret = clk_rate - ratio * freq;
335
336 /*
337 * Drop the source that can not be
338 * divided into the required rate.
339 */
340 if (ret != 0 && clk_rate / ret < 1000)
341 continue;
342
343 dev_dbg(dai->dev,
344 "ratio %d for freq %dHz based on clock %ldHz\n",
345 ratio, freq, clk_rate);
346
347 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
348 ratio /= 2;
349 else
350 continue;
351
352 if (ret < savesub) {
353 savediv = ratio;
354 sai->mclk_id[tx] = id;
355 savesub = ret;
356 }
357
358 if (ret == 0)
359 break;
360 }
361
362 if (savediv == 0) {
363 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
364 tx ? 'T' : 'R', freq);
365 return -EINVAL;
366 }
367
368 /*
369 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
370 * set TCR2 register for playback.
371 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
372 * and capture.
373 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
374 * and capture.
375 * 4) For Tx and Rx are both Synchronous with another SAI, we just
376 * ignore it.
377 */
378 if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
379 (!tx && !sai->synchronous[RX])) {
380 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
381 FSL_SAI_CR2_MSEL_MASK,
382 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
383 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
384 FSL_SAI_CR2_DIV_MASK, savediv - 1);
385 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
386 (tx && !sai->synchronous[TX])) {
387 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
388 FSL_SAI_CR2_MSEL_MASK,
389 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
390 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
391 FSL_SAI_CR2_DIV_MASK, savediv - 1);
392 }
393
394 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
395 sai->mclk_id[tx], savediv, savesub);
396
397 return 0;
398 }
399
400 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
401 struct snd_pcm_hw_params *params,
402 struct snd_soc_dai *cpu_dai)
403 {
404 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
405 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
406 unsigned int channels = params_channels(params);
407 u32 word_width = params_width(params);
408 u32 val_cr4 = 0, val_cr5 = 0;
409 u32 slots = (channels == 1) ? 2 : channels;
410 u32 slot_width = word_width;
411 int ret;
412
413 if (sai->slots)
414 slots = sai->slots;
415
416 if (sai->slot_width)
417 slot_width = sai->slot_width;
418
419 if (!sai->is_slave_mode) {
420 ret = fsl_sai_set_bclk(cpu_dai, tx,
421 slots * slot_width * params_rate(params));
422 if (ret)
423 return ret;
424
425 /* Do not enable the clock if it is already enabled */
426 if (!(sai->mclk_streams & BIT(substream->stream))) {
427 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
428 if (ret)
429 return ret;
430
431 sai->mclk_streams |= BIT(substream->stream);
432 }
433 }
434
435 if (!sai->is_dsp_mode)
436 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
437
438 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
439 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
440
441 if (sai->is_lsb_first)
442 val_cr5 |= FSL_SAI_CR5_FBT(0);
443 else
444 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
445
446 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
447
448 /*
449 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
450 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
451 * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
452 * error.
453 */
454
455 if (!sai->is_slave_mode) {
456 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
457 regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
458 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
459 val_cr4);
460 regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
461 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
462 FSL_SAI_CR5_FBT_MASK, val_cr5);
463 regmap_write(sai->regmap, FSL_SAI_TMR,
464 ~0UL - ((1 << channels) - 1));
465 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
466 regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
467 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
468 val_cr4);
469 regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
470 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
471 FSL_SAI_CR5_FBT_MASK, val_cr5);
472 regmap_write(sai->regmap, FSL_SAI_RMR,
473 ~0UL - ((1 << channels) - 1));
474 }
475 }
476
477 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
478 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
479 val_cr4);
480 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
481 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
482 FSL_SAI_CR5_FBT_MASK, val_cr5);
483 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
484
485 return 0;
486 }
487
488 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
489 struct snd_soc_dai *cpu_dai)
490 {
491 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
492 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
493
494 if (!sai->is_slave_mode &&
495 sai->mclk_streams & BIT(substream->stream)) {
496 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
497 sai->mclk_streams &= ~BIT(substream->stream);
498 }
499
500 return 0;
501 }
502
503
504 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
505 struct snd_soc_dai *cpu_dai)
506 {
507 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
508 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
509 u32 xcsr, count = 100;
510
511 /*
512 * Asynchronous mode: Clear SYNC for both Tx and Rx.
513 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
514 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
515 */
516 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
517 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
518 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
519 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
520
521 /*
522 * It is recommended that the transmitter is the last enabled
523 * and the first disabled.
524 */
525 switch (cmd) {
526 case SNDRV_PCM_TRIGGER_START:
527 case SNDRV_PCM_TRIGGER_RESUME:
528 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
529 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
530 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
531
532 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
533 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
534 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
535 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
536
537 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
538 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
539 break;
540 case SNDRV_PCM_TRIGGER_STOP:
541 case SNDRV_PCM_TRIGGER_SUSPEND:
542 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
543 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
544 FSL_SAI_CSR_FRDE, 0);
545 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
546 FSL_SAI_CSR_xIE_MASK, 0);
547
548 /* Check if the opposite FRDE is also disabled */
549 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
550 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
551 /* Disable both directions and reset their FIFOs */
552 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
553 FSL_SAI_CSR_TERE, 0);
554 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
555 FSL_SAI_CSR_TERE, 0);
556
557 /* TERE will remain set till the end of current frame */
558 do {
559 udelay(10);
560 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
561 } while (--count && xcsr & FSL_SAI_CSR_TERE);
562
563 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
564 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
565 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
566 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
567
568 /*
569 * For sai master mode, after several open/close sai,
570 * there will be no frame clock, and can't recover
571 * anymore. Add software reset to fix this issue.
572 * This is a hardware bug, and will be fix in the
573 * next sai version.
574 */
575 if (!sai->is_slave_mode) {
576 /* Software Reset for both Tx and Rx */
577 regmap_write(sai->regmap,
578 FSL_SAI_TCSR, FSL_SAI_CSR_SR);
579 regmap_write(sai->regmap,
580 FSL_SAI_RCSR, FSL_SAI_CSR_SR);
581 /* Clear SR bit to finish the reset */
582 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
583 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
584 }
585 }
586 break;
587 default:
588 return -EINVAL;
589 }
590
591 return 0;
592 }
593
594 static int fsl_sai_startup(struct snd_pcm_substream *substream,
595 struct snd_soc_dai *cpu_dai)
596 {
597 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
598 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
599 struct device *dev = &sai->pdev->dev;
600 int ret;
601
602 ret = clk_prepare_enable(sai->bus_clk);
603 if (ret) {
604 dev_err(dev, "failed to enable bus clock: %d\n", ret);
605 return ret;
606 }
607
608 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
609 FSL_SAI_CR3_TRCE);
610
611 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
612 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
613
614 return ret;
615 }
616
617 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
618 struct snd_soc_dai *cpu_dai)
619 {
620 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
621 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
622
623 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
624
625 clk_disable_unprepare(sai->bus_clk);
626 }
627
628 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
629 .set_sysclk = fsl_sai_set_dai_sysclk,
630 .set_fmt = fsl_sai_set_dai_fmt,
631 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
632 .hw_params = fsl_sai_hw_params,
633 .hw_free = fsl_sai_hw_free,
634 .trigger = fsl_sai_trigger,
635 .startup = fsl_sai_startup,
636 .shutdown = fsl_sai_shutdown,
637 };
638
639 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
640 {
641 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
642
643 /* Software Reset for both Tx and Rx */
644 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
645 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
646 /* Clear SR bit to finish the reset */
647 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
648 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
649
650 regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
651 FSL_SAI_MAXBURST_TX * 2);
652 regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
653 FSL_SAI_MAXBURST_RX - 1);
654
655 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
656 &sai->dma_params_rx);
657
658 snd_soc_dai_set_drvdata(cpu_dai, sai);
659
660 return 0;
661 }
662
663 static struct snd_soc_dai_driver fsl_sai_dai = {
664 .probe = fsl_sai_dai_probe,
665 .playback = {
666 .stream_name = "CPU-Playback",
667 .channels_min = 1,
668 .channels_max = 2,
669 .rate_min = 8000,
670 .rate_max = 192000,
671 .rates = SNDRV_PCM_RATE_KNOT,
672 .formats = FSL_SAI_FORMATS,
673 },
674 .capture = {
675 .stream_name = "CPU-Capture",
676 .channels_min = 1,
677 .channels_max = 2,
678 .rate_min = 8000,
679 .rate_max = 192000,
680 .rates = SNDRV_PCM_RATE_KNOT,
681 .formats = FSL_SAI_FORMATS,
682 },
683 .ops = &fsl_sai_pcm_dai_ops,
684 };
685
686 static const struct snd_soc_component_driver fsl_component = {
687 .name = "fsl-sai",
688 };
689
690 static struct reg_default fsl_sai_reg_defaults[] = {
691 {FSL_SAI_TCR1, 0},
692 {FSL_SAI_TCR2, 0},
693 {FSL_SAI_TCR3, 0},
694 {FSL_SAI_TCR4, 0},
695 {FSL_SAI_TCR5, 0},
696 {FSL_SAI_TDR, 0},
697 {FSL_SAI_TMR, 0},
698 {FSL_SAI_RCR1, 0},
699 {FSL_SAI_RCR2, 0},
700 {FSL_SAI_RCR3, 0},
701 {FSL_SAI_RCR4, 0},
702 {FSL_SAI_RCR5, 0},
703 {FSL_SAI_RMR, 0},
704 };
705
706 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
707 {
708 switch (reg) {
709 case FSL_SAI_TCSR:
710 case FSL_SAI_TCR1:
711 case FSL_SAI_TCR2:
712 case FSL_SAI_TCR3:
713 case FSL_SAI_TCR4:
714 case FSL_SAI_TCR5:
715 case FSL_SAI_TFR:
716 case FSL_SAI_TMR:
717 case FSL_SAI_RCSR:
718 case FSL_SAI_RCR1:
719 case FSL_SAI_RCR2:
720 case FSL_SAI_RCR3:
721 case FSL_SAI_RCR4:
722 case FSL_SAI_RCR5:
723 case FSL_SAI_RDR:
724 case FSL_SAI_RFR:
725 case FSL_SAI_RMR:
726 return true;
727 default:
728 return false;
729 }
730 }
731
732 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
733 {
734 switch (reg) {
735 case FSL_SAI_TCSR:
736 case FSL_SAI_RCSR:
737 case FSL_SAI_TFR:
738 case FSL_SAI_RFR:
739 case FSL_SAI_RDR:
740 return true;
741 default:
742 return false;
743 }
744 }
745
746 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
747 {
748 switch (reg) {
749 case FSL_SAI_TCSR:
750 case FSL_SAI_TCR1:
751 case FSL_SAI_TCR2:
752 case FSL_SAI_TCR3:
753 case FSL_SAI_TCR4:
754 case FSL_SAI_TCR5:
755 case FSL_SAI_TDR:
756 case FSL_SAI_TMR:
757 case FSL_SAI_RCSR:
758 case FSL_SAI_RCR1:
759 case FSL_SAI_RCR2:
760 case FSL_SAI_RCR3:
761 case FSL_SAI_RCR4:
762 case FSL_SAI_RCR5:
763 case FSL_SAI_RMR:
764 return true;
765 default:
766 return false;
767 }
768 }
769
770 static const struct regmap_config fsl_sai_regmap_config = {
771 .reg_bits = 32,
772 .reg_stride = 4,
773 .val_bits = 32,
774
775 .max_register = FSL_SAI_RMR,
776 .reg_defaults = fsl_sai_reg_defaults,
777 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults),
778 .readable_reg = fsl_sai_readable_reg,
779 .volatile_reg = fsl_sai_volatile_reg,
780 .writeable_reg = fsl_sai_writeable_reg,
781 .cache_type = REGCACHE_FLAT,
782 };
783
784 static int fsl_sai_probe(struct platform_device *pdev)
785 {
786 struct device_node *np = pdev->dev.of_node;
787 struct fsl_sai *sai;
788 struct resource *res;
789 void __iomem *base;
790 char tmp[8];
791 int irq, ret, i;
792
793 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
794 if (!sai)
795 return -ENOMEM;
796
797 sai->pdev = pdev;
798
799 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
800 sai->sai_on_imx = true;
801
802 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
803
804 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
805 base = devm_ioremap_resource(&pdev->dev, res);
806 if (IS_ERR(base))
807 return PTR_ERR(base);
808
809 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
810 "bus", base, &fsl_sai_regmap_config);
811
812 /* Compatible with old DTB cases */
813 if (IS_ERR(sai->regmap))
814 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
815 "sai", base, &fsl_sai_regmap_config);
816 if (IS_ERR(sai->regmap)) {
817 dev_err(&pdev->dev, "regmap init failed\n");
818 return PTR_ERR(sai->regmap);
819 }
820
821 /* No error out for old DTB cases but only mark the clock NULL */
822 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
823 if (IS_ERR(sai->bus_clk)) {
824 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
825 PTR_ERR(sai->bus_clk));
826 sai->bus_clk = NULL;
827 }
828
829 sai->mclk_clk[0] = sai->bus_clk;
830 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
831 sprintf(tmp, "mclk%d", i);
832 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
833 if (IS_ERR(sai->mclk_clk[i])) {
834 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
835 i + 1, PTR_ERR(sai->mclk_clk[i]));
836 sai->mclk_clk[i] = NULL;
837 }
838 }
839
840 irq = platform_get_irq(pdev, 0);
841 if (irq < 0) {
842 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
843 return irq;
844 }
845
846 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
847 if (ret) {
848 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
849 return ret;
850 }
851
852 /* Sync Tx with Rx as default by following old DT binding */
853 sai->synchronous[RX] = true;
854 sai->synchronous[TX] = false;
855 fsl_sai_dai.symmetric_rates = 1;
856 fsl_sai_dai.symmetric_channels = 1;
857 fsl_sai_dai.symmetric_samplebits = 1;
858
859 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
860 of_find_property(np, "fsl,sai-asynchronous", NULL)) {
861 /* error out if both synchronous and asynchronous are present */
862 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
863 return -EINVAL;
864 }
865
866 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
867 /* Sync Rx with Tx */
868 sai->synchronous[RX] = false;
869 sai->synchronous[TX] = true;
870 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
871 /* Discard all settings for asynchronous mode */
872 sai->synchronous[RX] = false;
873 sai->synchronous[TX] = false;
874 fsl_sai_dai.symmetric_rates = 0;
875 fsl_sai_dai.symmetric_channels = 0;
876 fsl_sai_dai.symmetric_samplebits = 0;
877 }
878
879 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
880 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
881 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
882 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
883
884 platform_set_drvdata(pdev, sai);
885
886 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
887 &fsl_sai_dai, 1);
888 if (ret)
889 return ret;
890
891 if (sai->sai_on_imx)
892 return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
893 else
894 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
895 }
896
897 static const struct of_device_id fsl_sai_ids[] = {
898 { .compatible = "fsl,vf610-sai", },
899 { .compatible = "fsl,imx6sx-sai", },
900 { /* sentinel */ }
901 };
902 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
903
904 #ifdef CONFIG_PM_SLEEP
905 static int fsl_sai_suspend(struct device *dev)
906 {
907 struct fsl_sai *sai = dev_get_drvdata(dev);
908
909 regcache_cache_only(sai->regmap, true);
910 regcache_mark_dirty(sai->regmap);
911
912 return 0;
913 }
914
915 static int fsl_sai_resume(struct device *dev)
916 {
917 struct fsl_sai *sai = dev_get_drvdata(dev);
918
919 regcache_cache_only(sai->regmap, false);
920 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
921 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
922 msleep(1);
923 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
924 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
925 return regcache_sync(sai->regmap);
926 }
927 #endif /* CONFIG_PM_SLEEP */
928
929 static const struct dev_pm_ops fsl_sai_pm_ops = {
930 SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume)
931 };
932
933 static struct platform_driver fsl_sai_driver = {
934 .probe = fsl_sai_probe,
935 .driver = {
936 .name = "fsl-sai",
937 .pm = &fsl_sai_pm_ops,
938 .of_match_table = fsl_sai_ids,
939 },
940 };
941 module_platform_driver(fsl_sai_driver);
942
943 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
944 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
945 MODULE_ALIAS("platform:fsl-sai");
946 MODULE_LICENSE("GPL");
Linux with added FPC-III support