sound/soc/intel/skylake/skl-sst-cldma.h

   1 /*
   2  * Intel Code Loader DMA support
   3  *
   4  * Copyright (C) 2015, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as version 2, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  */
  15
  16 #ifndef SKL_SST_CLDMA_H_
  17 #define SKL_SST_CLDMA_H_
  18
  19 #define FW_CL_STREAM_NUMBER             0x1
  20
  21 #define DMA_ADDRESS_128_BITS_ALIGNMENT  7
  22 #define BDL_ALIGN(x)                    (x >> DMA_ADDRESS_128_BITS_ALIGNMENT)
  23
  24 #define SKL_ADSPIC_CL_DMA                       0x2
  25 #define SKL_ADSPIS_CL_DMA                       0x2
  26 #define SKL_CL_DMA_SD_INT_DESC_ERR              0x10 /* Descriptor error interrupt */
  27 #define SKL_CL_DMA_SD_INT_FIFO_ERR              0x08 /* FIFO error interrupt */
  28 #define SKL_CL_DMA_SD_INT_COMPLETE              0x04 /* Buffer completion interrupt */
  29
  30 /* Intel HD Audio Code Loader DMA Registers */
  31
  32 #define HDA_ADSP_LOADER_BASE            0x80
  33
  34 /* Stream Registers */
  35 #define SKL_ADSP_REG_CL_SD_CTL                  (HDA_ADSP_LOADER_BASE + 0x00)
  36 #define SKL_ADSP_REG_CL_SD_STS                  (HDA_ADSP_LOADER_BASE + 0x03)
  37 #define SKL_ADSP_REG_CL_SD_LPIB                 (HDA_ADSP_LOADER_BASE + 0x04)
  38 #define SKL_ADSP_REG_CL_SD_CBL                  (HDA_ADSP_LOADER_BASE + 0x08)
  39 #define SKL_ADSP_REG_CL_SD_LVI                  (HDA_ADSP_LOADER_BASE + 0x0c)
  40 #define SKL_ADSP_REG_CL_SD_FIFOW                (HDA_ADSP_LOADER_BASE + 0x0e)
  41 #define SKL_ADSP_REG_CL_SD_FIFOSIZE             (HDA_ADSP_LOADER_BASE + 0x10)
  42 #define SKL_ADSP_REG_CL_SD_FORMAT               (HDA_ADSP_LOADER_BASE + 0x12)
  43 #define SKL_ADSP_REG_CL_SD_FIFOL                (HDA_ADSP_LOADER_BASE + 0x14)
  44 #define SKL_ADSP_REG_CL_SD_BDLPL                (HDA_ADSP_LOADER_BASE + 0x18)
  45 #define SKL_ADSP_REG_CL_SD_BDLPU                (HDA_ADSP_LOADER_BASE + 0x1c)
  46
  47 /* CL: Software Position Based FIFO Capability Registers */
  48 #define SKL_ADSP_REG_CL_SPBFIFO                 (HDA_ADSP_LOADER_BASE + 0x20)
  49 #define SKL_ADSP_REG_CL_SPBFIFO_SPBFCH          (SKL_ADSP_REG_CL_SPBFIFO + 0x0)
  50 #define SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL        (SKL_ADSP_REG_CL_SPBFIFO + 0x4)
  51 #define SKL_ADSP_REG_CL_SPBFIFO_SPIB            (SKL_ADSP_REG_CL_SPBFIFO + 0x8)
  52 #define SKL_ADSP_REG_CL_SPBFIFO_MAXFIFOS        (SKL_ADSP_REG_CL_SPBFIFO + 0xc)
  53
  54 /* CL: Stream Descriptor x Control */
  55
  56 /* Stream Reset */
  57 #define CL_SD_CTL_SRST_SHIFT            0
  58 #define CL_SD_CTL_SRST_MASK             (1 << CL_SD_CTL_SRST_SHIFT)
  59 #define CL_SD_CTL_SRST(x)               \
  60                         ((x << CL_SD_CTL_SRST_SHIFT) & CL_SD_CTL_SRST_MASK)
  61
  62 /* Stream Run */
  63 #define CL_SD_CTL_RUN_SHIFT             1
  64 #define CL_SD_CTL_RUN_MASK              (1 << CL_SD_CTL_RUN_SHIFT)
  65 #define CL_SD_CTL_RUN(x)                \
  66                         ((x << CL_SD_CTL_RUN_SHIFT) & CL_SD_CTL_RUN_MASK)
  67
  68 /* Interrupt On Completion Enable */
  69 #define CL_SD_CTL_IOCE_SHIFT            2
  70 #define CL_SD_CTL_IOCE_MASK             (1 << CL_SD_CTL_IOCE_SHIFT)
  71 #define CL_SD_CTL_IOCE(x)               \
  72                         ((x << CL_SD_CTL_IOCE_SHIFT) & CL_SD_CTL_IOCE_MASK)
  73
  74 /* FIFO Error Interrupt Enable */
  75 #define CL_SD_CTL_FEIE_SHIFT            3
  76 #define CL_SD_CTL_FEIE_MASK             (1 << CL_SD_CTL_FEIE_SHIFT)
  77 #define CL_SD_CTL_FEIE(x)               \
  78                         ((x << CL_SD_CTL_FEIE_SHIFT) & CL_SD_CTL_FEIE_MASK)
  79
  80 /* Descriptor Error Interrupt Enable */
  81 #define CL_SD_CTL_DEIE_SHIFT            4
  82 #define CL_SD_CTL_DEIE_MASK             (1 << CL_SD_CTL_DEIE_SHIFT)
  83 #define CL_SD_CTL_DEIE(x)               \
  84                         ((x << CL_SD_CTL_DEIE_SHIFT) & CL_SD_CTL_DEIE_MASK)
  85
  86 /* FIFO Limit Change */
  87 #define CL_SD_CTL_FIFOLC_SHIFT          5
  88 #define CL_SD_CTL_FIFOLC_MASK           (1 << CL_SD_CTL_FIFOLC_SHIFT)
  89 #define CL_SD_CTL_FIFOLC(x)             \
  90                         ((x << CL_SD_CTL_FIFOLC_SHIFT) & CL_SD_CTL_FIFOLC_MASK)
  91
  92 /* Stripe Control */
  93 #define CL_SD_CTL_STRIPE_SHIFT          16
  94 #define CL_SD_CTL_STRIPE_MASK           (0x3 << CL_SD_CTL_STRIPE_SHIFT)
  95 #define CL_SD_CTL_STRIPE(x)             \
  96                         ((x << CL_SD_CTL_STRIPE_SHIFT) & CL_SD_CTL_STRIPE_MASK)
  97
  98 /* Traffic Priority */
  99 #define CL_SD_CTL_TP_SHIFT              18
 100 #define CL_SD_CTL_TP_MASK               (1 << CL_SD_CTL_TP_SHIFT)
 101 #define CL_SD_CTL_TP(x)                 \
 102                         ((x << CL_SD_CTL_TP_SHIFT) & CL_SD_CTL_TP_MASK)
 103
 104 /* Bidirectional Direction Control */
 105 #define CL_SD_CTL_DIR_SHIFT             19
 106 #define CL_SD_CTL_DIR_MASK              (1 << CL_SD_CTL_DIR_SHIFT)
 107 #define CL_SD_CTL_DIR(x)                \
 108                         ((x << CL_SD_CTL_DIR_SHIFT) & CL_SD_CTL_DIR_MASK)
 109
 110 /* Stream Number */
 111 #define CL_SD_CTL_STRM_SHIFT            20
 112 #define CL_SD_CTL_STRM_MASK             (0xf << CL_SD_CTL_STRM_SHIFT)
 113 #define CL_SD_CTL_STRM(x)               \
 114                         ((x << CL_SD_CTL_STRM_SHIFT) & CL_SD_CTL_STRM_MASK)
 115
 116 /* CL: Stream Descriptor x Status */
 117
 118 /* Buffer Completion Interrupt Status */
 119 #define CL_SD_STS_BCIS(x)               CL_SD_CTL_IOCE(x)
 120
 121 /* FIFO Error */
 122 #define CL_SD_STS_FIFOE(x)              CL_SD_CTL_FEIE(x)
 123
 124 /* Descriptor Error */
 125 #define CL_SD_STS_DESE(x)               CL_SD_CTL_DEIE(x)
 126
 127 /* FIFO Ready */
 128 #define CL_SD_STS_FIFORDY(x)    CL_SD_CTL_FIFOLC(x)
 129
 130
 131 /* CL: Stream Descriptor x Last Valid Index */
 132 #define CL_SD_LVI_SHIFT                 0
 133 #define CL_SD_LVI_MASK                  (0xff << CL_SD_LVI_SHIFT)
 134 #define CL_SD_LVI(x)                    ((x << CL_SD_LVI_SHIFT) & CL_SD_LVI_MASK)
 135
 136 /* CL: Stream Descriptor x FIFO Eviction Watermark */
 137 #define CL_SD_FIFOW_SHIFT               0
 138 #define CL_SD_FIFOW_MASK                (0x7 << CL_SD_FIFOW_SHIFT)
 139 #define CL_SD_FIFOW(x)                  \
 140                         ((x << CL_SD_FIFOW_SHIFT) & CL_SD_FIFOW_MASK)
 141
 142 /* CL: Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address */
 143
 144 /* Protect Bits */
 145 #define CL_SD_BDLPLBA_PROT_SHIFT        0
 146 #define CL_SD_BDLPLBA_PROT_MASK         (1 << CL_SD_BDLPLBA_PROT_SHIFT)
 147 #define CL_SD_BDLPLBA_PROT(x)           \
 148                 ((x << CL_SD_BDLPLBA_PROT_SHIFT) & CL_SD_BDLPLBA_PROT_MASK)
 149
 150 /* Buffer Descriptor List Lower Base Address */
 151 #define CL_SD_BDLPLBA_SHIFT             7
 152 #define CL_SD_BDLPLBA_MASK              (0x1ffffff << CL_SD_BDLPLBA_SHIFT)
 153 #define CL_SD_BDLPLBA(x)                \
 154         ((BDL_ALIGN(lower_32_bits(x)) << CL_SD_BDLPLBA_SHIFT) & CL_SD_BDLPLBA_MASK)
 155
 156 /* Buffer Descriptor List Upper Base Address */
 157 #define CL_SD_BDLPUBA_SHIFT             0
 158 #define CL_SD_BDLPUBA_MASK              (0xffffffff << CL_SD_BDLPUBA_SHIFT)
 159 #define CL_SD_BDLPUBA(x)                \
 160                 ((upper_32_bits(x) << CL_SD_BDLPUBA_SHIFT) & CL_SD_BDLPUBA_MASK)
 161
 162 /*
 163  * Code Loader - Software Position Based FIFO
 164  * Capability Registers x Software Position Based FIFO Header
 165  */
 166
 167 /* Next Capability Pointer */
 168 #define CL_SPBFIFO_SPBFCH_PTR_SHIFT     0
 169 #define CL_SPBFIFO_SPBFCH_PTR_MASK      (0xff << CL_SPBFIFO_SPBFCH_PTR_SHIFT)
 170 #define CL_SPBFIFO_SPBFCH_PTR(x)        \
 171                 ((x << CL_SPBFIFO_SPBFCH_PTR_SHIFT) & CL_SPBFIFO_SPBFCH_PTR_MASK)
 172
 173 /* Capability Identifier */
 174 #define CL_SPBFIFO_SPBFCH_ID_SHIFT      16
 175 #define CL_SPBFIFO_SPBFCH_ID_MASK       (0xfff << CL_SPBFIFO_SPBFCH_ID_SHIFT)
 176 #define CL_SPBFIFO_SPBFCH_ID(x)         \
 177                 ((x << CL_SPBFIFO_SPBFCH_ID_SHIFT) & CL_SPBFIFO_SPBFCH_ID_MASK)
 178
 179 /* Capability Version */
 180 #define CL_SPBFIFO_SPBFCH_VER_SHIFT     28
 181 #define CL_SPBFIFO_SPBFCH_VER_MASK      (0xf << CL_SPBFIFO_SPBFCH_VER_SHIFT)
 182 #define CL_SPBFIFO_SPBFCH_VER(x)        \
 183         ((x << CL_SPBFIFO_SPBFCH_VER_SHIFT) & CL_SPBFIFO_SPBFCH_VER_MASK)
 184
 185 /* Software Position in Buffer Enable */
 186 #define CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT 0
 187 #define CL_SPBFIFO_SPBFCCTL_SPIBE_MASK  (1 << CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT)
 188 #define CL_SPBFIFO_SPBFCCTL_SPIBE(x)    \
 189         ((x << CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT) & CL_SPBFIFO_SPBFCCTL_SPIBE_MASK)
 190
 191 /* SST IPC SKL defines */
 192 #define SKL_WAIT_TIMEOUT                500     /* 500 msec */
 193 #define SKL_MAX_BUFFER_SIZE             (32 * PAGE_SIZE)
 194
 195 enum skl_cl_dma_wake_states {
 196         SKL_CL_DMA_STATUS_NONE = 0,
 197         SKL_CL_DMA_BUF_COMPLETE,
 198         SKL_CL_DMA_ERR, /* TODO: Expand the error states */
 199 };
 200
 201 struct sst_dsp;
 202
 203 struct skl_cl_dev_ops {
 204         void (*cl_setup_bdle)(struct sst_dsp *ctx,
 205                         struct snd_dma_buffer *dmab_data,
 206                         u32 **bdlp, int size, int with_ioc);
 207         void (*cl_setup_controller)(struct sst_dsp *ctx,
 208                         struct snd_dma_buffer *dmab_bdl,
 209                         unsigned int max_size, u32 page_count);
 210         void (*cl_setup_spb)(struct sst_dsp  *ctx,
 211                         unsigned int size, bool enable);
 212         void (*cl_cleanup_spb)(struct sst_dsp  *ctx);
 213         void (*cl_trigger)(struct sst_dsp  *ctx, bool enable);
 214         void (*cl_cleanup_controller)(struct sst_dsp  *ctx);
 215         int (*cl_copy_to_dmabuf)(struct sst_dsp *ctx,
 216                         const void *bin, u32 size);
 217         void (*cl_stop_dma)(struct sst_dsp *ctx);
 218 };
 219
 220 /**
 221  * skl_cl_dev - holds information for code loader dma transfer
 222  *
 223  * @dmab_data: buffer pointer
 224  * @dmab_bdl: buffer descriptor list
 225  * @bufsize: ring buffer size
 226  * @frags: Last valid buffer descriptor index in the BDL
 227  * @curr_spib_pos: Current position in ring buffer
 228  * @dma_buffer_offset: dma buffer offset
 229  * @ops: operations supported on CL dma
 230  * @wait_queue: wait queue to wake for wake event
 231  * @wake_status: DMA wake status
 232  * @wait_condition: condition to wait on wait queue
 233  * @cl_dma_lock: for synchronized access to cldma
 234  */
 235 struct skl_cl_dev {
 236         struct snd_dma_buffer dmab_data;
 237         struct snd_dma_buffer dmab_bdl;
 238
 239         unsigned int bufsize;
 240         unsigned int frags;
 241
 242         unsigned int curr_spib_pos;
 243         unsigned int dma_buffer_offset;
 244         struct skl_cl_dev_ops ops;
 245
 246         wait_queue_head_t wait_queue;
 247         int wake_status;
 248         bool wait_condition;
 249 };
 250
 251 #endif /* SKL_SST_CLDMA_H_ */