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drm/radeon: add a dpm quirk for all R7 370 parts
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / si_dpm.c
blob42b2baf0e6d731877804a92db3ac29c25bf0230e
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "drmP.h"
25 #include "radeon.h"
26 #include "sid.h"
27 #include "r600_dpm.h"
28 #include "si_dpm.h"
29 #include "atom.h"
30 #include <linux/math64.h>
31 #include <linux/seq_file.h>
32
33 #define MC_CG_ARB_FREQ_F0 0x0a
34 #define MC_CG_ARB_FREQ_F1 0x0b
35 #define MC_CG_ARB_FREQ_F2 0x0c
36 #define MC_CG_ARB_FREQ_F3 0x0d
37
38 #define SMC_RAM_END 0x20000
39
40 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
41
42 static const struct si_cac_config_reg cac_weights_tahiti[] =
43 {
44 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
45 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
46 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
48 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
49 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
55 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
57 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
58 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
60 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
62 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
63 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
64 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
66 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
67 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
76 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
79 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
80 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
82 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
83 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
85 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
104 { 0xFFFFFFFF }
105 };
106
107 static const struct si_cac_config_reg lcac_tahiti[] =
108 {
109 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
110 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
111 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
113 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
115 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
117 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
119 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
121 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
123 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
125 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
127 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
129 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
131 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
133 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
135 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
137 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
139 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
141 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
143 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
145 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
147 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
149 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
151 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
153 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
155 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
157 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
159 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
161 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
163 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
165 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
167 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
169 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
171 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
173 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
175 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
177 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
179 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
181 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
183 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
185 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
187 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
189 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
191 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
193 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
195 { 0xFFFFFFFF }
196
197 };
198
199 static const struct si_cac_config_reg cac_override_tahiti[] =
200 {
201 { 0xFFFFFFFF }
202 };
203
204 static const struct si_powertune_data powertune_data_tahiti =
205 {
206 ((1 << 16) | 27027),
207 6,
208 0,
209 4,
210 95,
211 {
212 0UL,
213 0UL,
214 4521550UL,
215 309631529UL,
216 -1270850L,
217 4513710L,
218 40
219 },
220 595000000UL,
221 12,
222 {
223 0,
224 0,
225 0,
226 0,
227 0,
228 0,
229 0,
230 0
231 },
232 true
233 };
234
235 static const struct si_dte_data dte_data_tahiti =
236 {
237 { 1159409, 0, 0, 0, 0 },
238 { 777, 0, 0, 0, 0 },
239 2,
240 54000,
241 127000,
242 25,
243 2,
244 10,
245 13,
246 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
247 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
248 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
249 85,
250 false
251 };
252
253 static const struct si_dte_data dte_data_tahiti_le =
254 {
255 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
256 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
257 0x5,
258 0xAFC8,
259 0x64,
260 0x32,
261 1,
262 0,
263 0x10,
264 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
265 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
266 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
267 85,
268 true
269 };
270
271 static const struct si_dte_data dte_data_tahiti_pro =
272 {
273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
274 { 0x0, 0x0, 0x0, 0x0, 0x0 },
275 5,
276 45000,
277 100,
278 0xA,
279 1,
280 0,
281 0x10,
282 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
284 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
285 90,
286 true
287 };
288
289 static const struct si_dte_data dte_data_new_zealand =
290 {
291 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
292 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
293 0x5,
294 0xAFC8,
295 0x69,
296 0x32,
297 1,
298 0,
299 0x10,
300 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
301 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
302 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
303 85,
304 true
305 };
306
307 static const struct si_dte_data dte_data_aruba_pro =
308 {
309 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
310 { 0x0, 0x0, 0x0, 0x0, 0x0 },
311 5,
312 45000,
313 100,
314 0xA,
315 1,
316 0,
317 0x10,
318 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
319 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
320 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
321 90,
322 true
323 };
324
325 static const struct si_dte_data dte_data_malta =
326 {
327 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
328 { 0x0, 0x0, 0x0, 0x0, 0x0 },
329 5,
330 45000,
331 100,
332 0xA,
333 1,
334 0,
335 0x10,
336 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
337 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
338 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
339 90,
340 true
341 };
342
343 struct si_cac_config_reg cac_weights_pitcairn[] =
344 {
345 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
346 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
347 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
349 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
350 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
352 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
354 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
356 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
358 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
359 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
363 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
364 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
365 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
367 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
368 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
371 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
373 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
377 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
378 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
380 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
381 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
383 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
384 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
405 { 0xFFFFFFFF }
406 };
407
408 static const struct si_cac_config_reg lcac_pitcairn[] =
409 {
410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
414 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
416 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
418 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
420 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
422 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
424 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
426 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
428 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
430 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
432 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
434 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
436 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
438 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
440 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
442 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
444 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
446 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
448 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
450 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
452 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
454 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
456 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
458 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
460 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
462 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
464 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
466 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
468 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
470 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
472 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
474 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
476 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
478 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
480 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
482 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
484 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
486 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
488 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
490 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
492 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
494 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
496 { 0xFFFFFFFF }
497 };
498
499 static const struct si_cac_config_reg cac_override_pitcairn[] =
500 {
501 { 0xFFFFFFFF }
502 };
503
504 static const struct si_powertune_data powertune_data_pitcairn =
505 {
506 ((1 << 16) | 27027),
507 5,
508 0,
509 6,
510 100,
511 {
512 51600000UL,
513 1800000UL,
514 7194395UL,
515 309631529UL,
516 -1270850L,
517 4513710L,
518 100
519 },
520 117830498UL,
521 12,
522 {
523 0,
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 0
531 },
532 true
533 };
534
535 static const struct si_dte_data dte_data_pitcairn =
536 {
537 { 0, 0, 0, 0, 0 },
538 { 0, 0, 0, 0, 0 },
539 0,
540 0,
541 0,
542 0,
543 0,
544 0,
545 0,
546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 0,
550 false
551 };
552
553 static const struct si_dte_data dte_data_curacao_xt =
554 {
555 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
556 { 0x0, 0x0, 0x0, 0x0, 0x0 },
557 5,
558 45000,
559 100,
560 0xA,
561 1,
562 0,
563 0x10,
564 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
565 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
566 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
567 90,
568 true
569 };
570
571 static const struct si_dte_data dte_data_curacao_pro =
572 {
573 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
574 { 0x0, 0x0, 0x0, 0x0, 0x0 },
575 5,
576 45000,
577 100,
578 0xA,
579 1,
580 0,
581 0x10,
582 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
583 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
584 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
585 90,
586 true
587 };
588
589 static const struct si_dte_data dte_data_neptune_xt =
590 {
591 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
592 { 0x0, 0x0, 0x0, 0x0, 0x0 },
593 5,
594 45000,
595 100,
596 0xA,
597 1,
598 0,
599 0x10,
600 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
601 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
602 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
603 90,
604 true
605 };
606
607 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
608 {
609 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
610 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
611 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
613 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
614 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
616 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
618 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
620 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
622 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
623 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
625 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
627 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
628 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
629 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
631 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
632 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
635 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
637 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
641 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
642 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
645 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
647 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
648 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
650 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
651 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
669 { 0xFFFFFFFF }
670 };
671
672 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
673 {
674 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
675 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
676 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
678 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
679 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
681 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
683 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
685 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
687 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
688 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
690 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
692 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
693 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
694 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
696 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
697 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
700 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
702 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
706 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
707 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
710 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
712 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
713 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
715 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
716 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
734 { 0xFFFFFFFF }
735 };
736
737 static const struct si_cac_config_reg cac_weights_heathrow[] =
738 {
739 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
740 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
741 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
743 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
746 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
748 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
750 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
752 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
753 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
755 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
757 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
758 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
759 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
761 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
762 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
765 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
767 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
771 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
772 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
775 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
777 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
778 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
780 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
781 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
799 { 0xFFFFFFFF }
800 };
801
802 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
803 {
804 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
805 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
806 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
808 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
811 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
813 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
815 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
817 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
818 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
820 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
822 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
823 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
824 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
826 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
827 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
830 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
832 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
836 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
837 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
840 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
842 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
843 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
845 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
846 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
864 { 0xFFFFFFFF }
865 };
866
867 static const struct si_cac_config_reg cac_weights_cape_verde[] =
868 {
869 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
870 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
871 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
873 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
876 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
878 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
880 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
882 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
883 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
885 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
887 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
888 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
889 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
891 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
892 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
895 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
897 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
901 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
902 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
905 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
907 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
908 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
910 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
911 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
929 { 0xFFFFFFFF }
930 };
931
932 static const struct si_cac_config_reg lcac_cape_verde[] =
933 {
934 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
935 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
936 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
938 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
940 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
942 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
944 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
948 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
950 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
952 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
954 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
960 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
962 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
964 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
966 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
968 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
970 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
972 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
974 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
976 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
980 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0xFFFFFFFF }
989 };
990
991 static const struct si_cac_config_reg cac_override_cape_verde[] =
992 {
993 { 0xFFFFFFFF }
994 };
995
996 static const struct si_powertune_data powertune_data_cape_verde =
997 {
998 ((1 << 16) | 0x6993),
999 5,
1000 0,
1001 7,
1002 105,
1003 {
1004 0UL,
1005 0UL,
1006 7194395UL,
1007 309631529UL,
1008 -1270850L,
1009 4513710L,
1010 100
1011 },
1012 117830498UL,
1013 12,
1014 {
1015 0,
1016 0,
1017 0,
1018 0,
1019 0,
1020 0,
1021 0,
1022 0
1023 },
1024 true
1025 };
1026
1027 static const struct si_dte_data dte_data_cape_verde =
1028 {
1029 { 0, 0, 0, 0, 0 },
1030 { 0, 0, 0, 0, 0 },
1031 0,
1032 0,
1033 0,
1034 0,
1035 0,
1036 0,
1037 0,
1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 0,
1042 false
1043 };
1044
1045 static const struct si_dte_data dte_data_venus_xtx =
1046 {
1047 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1048 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1049 5,
1050 55000,
1051 0x69,
1052 0xA,
1053 1,
1054 0,
1055 0x3,
1056 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1057 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 90,
1060 true
1061 };
1062
1063 static const struct si_dte_data dte_data_venus_xt =
1064 {
1065 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1066 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1067 5,
1068 55000,
1069 0x69,
1070 0xA,
1071 1,
1072 0,
1073 0x3,
1074 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1075 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 90,
1078 true
1079 };
1080
1081 static const struct si_dte_data dte_data_venus_pro =
1082 {
1083 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1084 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1085 5,
1086 55000,
1087 0x69,
1088 0xA,
1089 1,
1090 0,
1091 0x3,
1092 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1093 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 90,
1096 true
1097 };
1098
1099 struct si_cac_config_reg cac_weights_oland[] =
1100 {
1101 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1102 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1103 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1105 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1106 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1108 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1110 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1112 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1114 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1115 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1117 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1119 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1120 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1121 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1123 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1124 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1127 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1129 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1133 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1134 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1137 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1139 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1140 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1142 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1161 { 0xFFFFFFFF }
1162 };
1163
1164 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1165 {
1166 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1167 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1168 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1170 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1171 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1173 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1175 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1177 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1179 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1180 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1182 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1184 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1185 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1186 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1188 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1189 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1192 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1194 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1196 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1198 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1199 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1202 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1204 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1205 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1207 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1226 { 0xFFFFFFFF }
1227 };
1228
1229 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1230 {
1231 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1232 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1233 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1235 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1238 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1240 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1242 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1244 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1245 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1247 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1249 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1250 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1251 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1253 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1254 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1257 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1259 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1261 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1263 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1264 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1267 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1269 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1270 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1272 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1291 { 0xFFFFFFFF }
1292 };
1293
1294 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1295 {
1296 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1297 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1298 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1300 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1303 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1305 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1307 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1309 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1310 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1312 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1314 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1315 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1316 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1318 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1319 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1322 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1324 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1326 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1328 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1329 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1332 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1334 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1335 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1337 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1356 { 0xFFFFFFFF }
1357 };
1358
1359 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1360 {
1361 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1362 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1363 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1365 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1368 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1370 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1372 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1374 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1375 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1377 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1379 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1380 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1381 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1383 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1384 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1387 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1389 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1391 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1393 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1394 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1397 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1399 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1400 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1402 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1421 { 0xFFFFFFFF }
1422 };
1423
1424 static const struct si_cac_config_reg lcac_oland[] =
1425 {
1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0xFFFFFFFF }
1469 };
1470
1471 static const struct si_cac_config_reg lcac_mars_pro[] =
1472 {
1473 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1474 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1475 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1477 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1479 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1489 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1503 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0xFFFFFFFF }
1516 };
1517
1518 static const struct si_cac_config_reg cac_override_oland[] =
1519 {
1520 { 0xFFFFFFFF }
1521 };
1522
1523 static const struct si_powertune_data powertune_data_oland =
1524 {
1525 ((1 << 16) | 0x6993),
1526 5,
1527 0,
1528 7,
1529 105,
1530 {
1531 0UL,
1532 0UL,
1533 7194395UL,
1534 309631529UL,
1535 -1270850L,
1536 4513710L,
1537 100
1538 },
1539 117830498UL,
1540 12,
1541 {
1542 0,
1543 0,
1544 0,
1545 0,
1546 0,
1547 0,
1548 0,
1549 0
1550 },
1551 true
1552 };
1553
1554 static const struct si_powertune_data powertune_data_mars_pro =
1555 {
1556 ((1 << 16) | 0x6993),
1557 5,
1558 0,
1559 7,
1560 105,
1561 {
1562 0UL,
1563 0UL,
1564 7194395UL,
1565 309631529UL,
1566 -1270850L,
1567 4513710L,
1568 100
1569 },
1570 117830498UL,
1571 12,
1572 {
1573 0,
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 0
1581 },
1582 true
1583 };
1584
1585 static const struct si_dte_data dte_data_oland =
1586 {
1587 { 0, 0, 0, 0, 0 },
1588 { 0, 0, 0, 0, 0 },
1589 0,
1590 0,
1591 0,
1592 0,
1593 0,
1594 0,
1595 0,
1596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 0,
1600 false
1601 };
1602
1603 static const struct si_dte_data dte_data_mars_pro =
1604 {
1605 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1606 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1607 5,
1608 55000,
1609 105,
1610 0xA,
1611 1,
1612 0,
1613 0x10,
1614 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1615 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1616 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1617 90,
1618 true
1619 };
1620
1621 static const struct si_dte_data dte_data_sun_xt =
1622 {
1623 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1624 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1625 5,
1626 55000,
1627 105,
1628 0xA,
1629 1,
1630 0,
1631 0x10,
1632 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1633 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1634 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1635 90,
1636 true
1637 };
1638
1639
1640 static const struct si_cac_config_reg cac_weights_hainan[] =
1641 {
1642 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1643 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1644 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1646 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1647 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1649 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1653 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1655 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1656 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1658 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1660 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1661 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1662 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1664 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1665 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1667 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1668 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1674 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1677 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1678 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1680 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1683 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1684 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1702 { 0xFFFFFFFF }
1703 };
1704
1705 static const struct si_powertune_data powertune_data_hainan =
1706 {
1707 ((1 << 16) | 0x6993),
1708 5,
1709 0,
1710 9,
1711 105,
1712 {
1713 0UL,
1714 0UL,
1715 7194395UL,
1716 309631529UL,
1717 -1270850L,
1718 4513710L,
1719 100
1720 },
1721 117830498UL,
1722 12,
1723 {
1724 0,
1725 0,
1726 0,
1727 0,
1728 0,
1729 0,
1730 0,
1731 0
1732 },
1733 true
1734 };
1735
1736 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1737 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1738 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1739 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1740
1741 extern int si_mc_load_microcode(struct radeon_device *rdev);
1742
1743 static int si_populate_voltage_value(struct radeon_device *rdev,
1744 const struct atom_voltage_table *table,
1745 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1746 static int si_get_std_voltage_value(struct radeon_device *rdev,
1747 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1748 u16 *std_voltage);
1749 static int si_write_smc_soft_register(struct radeon_device *rdev,
1750 u16 reg_offset, u32 value);
1751 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1752 struct rv7xx_pl *pl,
1753 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1754 static int si_calculate_sclk_params(struct radeon_device *rdev,
1755 u32 engine_clock,
1756 SISLANDS_SMC_SCLK_VALUE *sclk);
1757
1758 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1759 {
1760 struct si_power_info *pi = rdev->pm.dpm.priv;
1761
1762 return pi;
1763 }
1764
1765 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1766 u16 v, s32 t, u32 ileakage, u32 *leakage)
1767 {
1768 s64 kt, kv, leakage_w, i_leakage, vddc;
1769 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1770 s64 tmp;
1771
1772 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1773 vddc = div64_s64(drm_int2fixp(v), 1000);
1774 temperature = div64_s64(drm_int2fixp(t), 1000);
1775
1776 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1777 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1778 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1779 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1780 t_ref = drm_int2fixp(coeff->t_ref);
1781
1782 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1783 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1784 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1785 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1786
1787 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1788
1789 *leakage = drm_fixp2int(leakage_w * 1000);
1790 }
1791
1792 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1793 const struct ni_leakage_coeffients *coeff,
1794 u16 v,
1795 s32 t,
1796 u32 i_leakage,
1797 u32 *leakage)
1798 {
1799 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1800 }
1801
1802 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1803 const u32 fixed_kt, u16 v,
1804 u32 ileakage, u32 *leakage)
1805 {
1806 s64 kt, kv, leakage_w, i_leakage, vddc;
1807
1808 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1809 vddc = div64_s64(drm_int2fixp(v), 1000);
1810
1811 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1812 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1813 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1814
1815 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1816
1817 *leakage = drm_fixp2int(leakage_w * 1000);
1818 }
1819
1820 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1821 const struct ni_leakage_coeffients *coeff,
1822 const u32 fixed_kt,
1823 u16 v,
1824 u32 i_leakage,
1825 u32 *leakage)
1826 {
1827 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1828 }
1829
1830
1831 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1832 struct si_dte_data *dte_data)
1833 {
1834 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1835 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1836 u32 k = dte_data->k;
1837 u32 t_max = dte_data->max_t;
1838 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1839 u32 t_0 = dte_data->t0;
1840 u32 i;
1841
1842 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1843 dte_data->tdep_count = 3;
1844
1845 for (i = 0; i < k; i++) {
1846 dte_data->r[i] =
1847 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1848 (p_limit2 * (u32)100);
1849 }
1850
1851 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1852
1853 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1854 dte_data->tdep_r[i] = dte_data->r[4];
1855 }
1856 } else {
1857 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1858 }
1859 }
1860
1861 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1862 {
1863 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1864 struct si_power_info *si_pi = si_get_pi(rdev);
1865 bool update_dte_from_pl2 = false;
1866
1867 if (rdev->family == CHIP_TAHITI) {
1868 si_pi->cac_weights = cac_weights_tahiti;
1869 si_pi->lcac_config = lcac_tahiti;
1870 si_pi->cac_override = cac_override_tahiti;
1871 si_pi->powertune_data = &powertune_data_tahiti;
1872 si_pi->dte_data = dte_data_tahiti;
1873
1874 switch (rdev->pdev->device) {
1875 case 0x6798:
1876 si_pi->dte_data.enable_dte_by_default = true;
1877 break;
1878 case 0x6799:
1879 si_pi->dte_data = dte_data_new_zealand;
1880 break;
1881 case 0x6790:
1882 case 0x6791:
1883 case 0x6792:
1884 case 0x679E:
1885 si_pi->dte_data = dte_data_aruba_pro;
1886 update_dte_from_pl2 = true;
1887 break;
1888 case 0x679B:
1889 si_pi->dte_data = dte_data_malta;
1890 update_dte_from_pl2 = true;
1891 break;
1892 case 0x679A:
1893 si_pi->dte_data = dte_data_tahiti_pro;
1894 update_dte_from_pl2 = true;
1895 break;
1896 default:
1897 if (si_pi->dte_data.enable_dte_by_default == true)
1898 DRM_ERROR("DTE is not enabled!\n");
1899 break;
1900 }
1901 } else if (rdev->family == CHIP_PITCAIRN) {
1902 switch (rdev->pdev->device) {
1903 case 0x6810:
1904 case 0x6818:
1905 si_pi->cac_weights = cac_weights_pitcairn;
1906 si_pi->lcac_config = lcac_pitcairn;
1907 si_pi->cac_override = cac_override_pitcairn;
1908 si_pi->powertune_data = &powertune_data_pitcairn;
1909 si_pi->dte_data = dte_data_curacao_xt;
1910 update_dte_from_pl2 = true;
1911 break;
1912 case 0x6819:
1913 case 0x6811:
1914 si_pi->cac_weights = cac_weights_pitcairn;
1915 si_pi->lcac_config = lcac_pitcairn;
1916 si_pi->cac_override = cac_override_pitcairn;
1917 si_pi->powertune_data = &powertune_data_pitcairn;
1918 si_pi->dte_data = dte_data_curacao_pro;
1919 update_dte_from_pl2 = true;
1920 break;
1921 case 0x6800:
1922 case 0x6806:
1923 si_pi->cac_weights = cac_weights_pitcairn;
1924 si_pi->lcac_config = lcac_pitcairn;
1925 si_pi->cac_override = cac_override_pitcairn;
1926 si_pi->powertune_data = &powertune_data_pitcairn;
1927 si_pi->dte_data = dte_data_neptune_xt;
1928 update_dte_from_pl2 = true;
1929 break;
1930 default:
1931 si_pi->cac_weights = cac_weights_pitcairn;
1932 si_pi->lcac_config = lcac_pitcairn;
1933 si_pi->cac_override = cac_override_pitcairn;
1934 si_pi->powertune_data = &powertune_data_pitcairn;
1935 si_pi->dte_data = dte_data_pitcairn;
1936 break;
1937 }
1938 } else if (rdev->family == CHIP_VERDE) {
1939 si_pi->lcac_config = lcac_cape_verde;
1940 si_pi->cac_override = cac_override_cape_verde;
1941 si_pi->powertune_data = &powertune_data_cape_verde;
1942
1943 switch (rdev->pdev->device) {
1944 case 0x683B:
1945 case 0x683F:
1946 case 0x6829:
1947 case 0x6835:
1948 si_pi->cac_weights = cac_weights_cape_verde_pro;
1949 si_pi->dte_data = dte_data_cape_verde;
1950 break;
1951 case 0x682C:
1952 si_pi->cac_weights = cac_weights_cape_verde_pro;
1953 si_pi->dte_data = dte_data_sun_xt;
1954 break;
1955 case 0x6825:
1956 case 0x6827:
1957 si_pi->cac_weights = cac_weights_heathrow;
1958 si_pi->dte_data = dte_data_cape_verde;
1959 break;
1960 case 0x6824:
1961 case 0x682D:
1962 si_pi->cac_weights = cac_weights_chelsea_xt;
1963 si_pi->dte_data = dte_data_cape_verde;
1964 break;
1965 case 0x682F:
1966 si_pi->cac_weights = cac_weights_chelsea_pro;
1967 si_pi->dte_data = dte_data_cape_verde;
1968 break;
1969 case 0x6820:
1970 si_pi->cac_weights = cac_weights_heathrow;
1971 si_pi->dte_data = dte_data_venus_xtx;
1972 break;
1973 case 0x6821:
1974 si_pi->cac_weights = cac_weights_heathrow;
1975 si_pi->dte_data = dte_data_venus_xt;
1976 break;
1977 case 0x6823:
1978 case 0x682B:
1979 case 0x6822:
1980 case 0x682A:
1981 si_pi->cac_weights = cac_weights_chelsea_pro;
1982 si_pi->dte_data = dte_data_venus_pro;
1983 break;
1984 default:
1985 si_pi->cac_weights = cac_weights_cape_verde;
1986 si_pi->dte_data = dte_data_cape_verde;
1987 break;
1988 }
1989 } else if (rdev->family == CHIP_OLAND) {
1990 switch (rdev->pdev->device) {
1991 case 0x6601:
1992 case 0x6621:
1993 case 0x6603:
1994 case 0x6605:
1995 si_pi->cac_weights = cac_weights_mars_pro;
1996 si_pi->lcac_config = lcac_mars_pro;
1997 si_pi->cac_override = cac_override_oland;
1998 si_pi->powertune_data = &powertune_data_mars_pro;
1999 si_pi->dte_data = dte_data_mars_pro;
2000 update_dte_from_pl2 = true;
2001 break;
2002 case 0x6600:
2003 case 0x6606:
2004 case 0x6620:
2005 case 0x6604:
2006 si_pi->cac_weights = cac_weights_mars_xt;
2007 si_pi->lcac_config = lcac_mars_pro;
2008 si_pi->cac_override = cac_override_oland;
2009 si_pi->powertune_data = &powertune_data_mars_pro;
2010 si_pi->dte_data = dte_data_mars_pro;
2011 update_dte_from_pl2 = true;
2012 break;
2013 case 0x6611:
2014 case 0x6613:
2015 case 0x6608:
2016 si_pi->cac_weights = cac_weights_oland_pro;
2017 si_pi->lcac_config = lcac_mars_pro;
2018 si_pi->cac_override = cac_override_oland;
2019 si_pi->powertune_data = &powertune_data_mars_pro;
2020 si_pi->dte_data = dte_data_mars_pro;
2021 update_dte_from_pl2 = true;
2022 break;
2023 case 0x6610:
2024 si_pi->cac_weights = cac_weights_oland_xt;
2025 si_pi->lcac_config = lcac_mars_pro;
2026 si_pi->cac_override = cac_override_oland;
2027 si_pi->powertune_data = &powertune_data_mars_pro;
2028 si_pi->dte_data = dte_data_mars_pro;
2029 update_dte_from_pl2 = true;
2030 break;
2031 default:
2032 si_pi->cac_weights = cac_weights_oland;
2033 si_pi->lcac_config = lcac_oland;
2034 si_pi->cac_override = cac_override_oland;
2035 si_pi->powertune_data = &powertune_data_oland;
2036 si_pi->dte_data = dte_data_oland;
2037 break;
2038 }
2039 } else if (rdev->family == CHIP_HAINAN) {
2040 si_pi->cac_weights = cac_weights_hainan;
2041 si_pi->lcac_config = lcac_oland;
2042 si_pi->cac_override = cac_override_oland;
2043 si_pi->powertune_data = &powertune_data_hainan;
2044 si_pi->dte_data = dte_data_sun_xt;
2045 update_dte_from_pl2 = true;
2046 } else {
2047 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2048 return;
2049 }
2050
2051 ni_pi->enable_power_containment = false;
2052 ni_pi->enable_cac = false;
2053 ni_pi->enable_sq_ramping = false;
2054 si_pi->enable_dte = false;
2055
2056 if (si_pi->powertune_data->enable_powertune_by_default) {
2057 ni_pi->enable_power_containment= true;
2058 ni_pi->enable_cac = true;
2059 if (si_pi->dte_data.enable_dte_by_default) {
2060 si_pi->enable_dte = true;
2061 if (update_dte_from_pl2)
2062 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2063
2064 }
2065 ni_pi->enable_sq_ramping = true;
2066 }
2067
2068 ni_pi->driver_calculate_cac_leakage = true;
2069 ni_pi->cac_configuration_required = true;
2070
2071 if (ni_pi->cac_configuration_required) {
2072 ni_pi->support_cac_long_term_average = true;
2073 si_pi->dyn_powertune_data.l2_lta_window_size =
2074 si_pi->powertune_data->l2_lta_window_size_default;
2075 si_pi->dyn_powertune_data.lts_truncate =
2076 si_pi->powertune_data->lts_truncate_default;
2077 } else {
2078 ni_pi->support_cac_long_term_average = false;
2079 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2080 si_pi->dyn_powertune_data.lts_truncate = 0;
2081 }
2082
2083 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2084 }
2085
2086 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2087 {
2088 return 1;
2089 }
2090
2091 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2092 {
2093 u32 xclk;
2094 u32 wintime;
2095 u32 cac_window;
2096 u32 cac_window_size;
2097
2098 xclk = radeon_get_xclk(rdev);
2099
2100 if (xclk == 0)
2101 return 0;
2102
2103 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2104 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2105
2106 wintime = (cac_window_size * 100) / xclk;
2107
2108 return wintime;
2109 }
2110
2111 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2112 {
2113 return power_in_watts;
2114 }
2115
2116 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2117 bool adjust_polarity,
2118 u32 tdp_adjustment,
2119 u32 *tdp_limit,
2120 u32 *near_tdp_limit)
2121 {
2122 u32 adjustment_delta, max_tdp_limit;
2123
2124 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2125 return -EINVAL;
2126
2127 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2128
2129 if (adjust_polarity) {
2130 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2131 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2132 } else {
2133 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2134 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2135 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2136 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2137 else
2138 *near_tdp_limit = 0;
2139 }
2140
2141 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2142 return -EINVAL;
2143 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2144 return -EINVAL;
2145
2146 return 0;
2147 }
2148
2149 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2150 struct radeon_ps *radeon_state)
2151 {
2152 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2153 struct si_power_info *si_pi = si_get_pi(rdev);
2154
2155 if (ni_pi->enable_power_containment) {
2156 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2157 PP_SIslands_PAPMParameters *papm_parm;
2158 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2159 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2160 u32 tdp_limit;
2161 u32 near_tdp_limit;
2162 int ret;
2163
2164 if (scaling_factor == 0)
2165 return -EINVAL;
2166
2167 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2168
2169 ret = si_calculate_adjusted_tdp_limits(rdev,
2170 false, /* ??? */
2171 rdev->pm.dpm.tdp_adjustment,
2172 &tdp_limit,
2173 &near_tdp_limit);
2174 if (ret)
2175 return ret;
2176
2177 smc_table->dpm2Params.TDPLimit =
2178 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2179 smc_table->dpm2Params.NearTDPLimit =
2180 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2181 smc_table->dpm2Params.SafePowerLimit =
2182 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2183
2184 ret = si_copy_bytes_to_smc(rdev,
2185 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2186 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2187 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2188 sizeof(u32) * 3,
2189 si_pi->sram_end);
2190 if (ret)
2191 return ret;
2192
2193 if (si_pi->enable_ppm) {
2194 papm_parm = &si_pi->papm_parm;
2195 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2196 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2197 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2198 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2199 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2200 papm_parm->PlatformPowerLimit = 0xffffffff;
2201 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2202
2203 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2204 (u8 *)papm_parm,
2205 sizeof(PP_SIslands_PAPMParameters),
2206 si_pi->sram_end);
2207 if (ret)
2208 return ret;
2209 }
2210 }
2211 return 0;
2212 }
2213
2214 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2215 struct radeon_ps *radeon_state)
2216 {
2217 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2218 struct si_power_info *si_pi = si_get_pi(rdev);
2219
2220 if (ni_pi->enable_power_containment) {
2221 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2222 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2223 int ret;
2224
2225 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2226
2227 smc_table->dpm2Params.NearTDPLimit =
2228 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2229 smc_table->dpm2Params.SafePowerLimit =
2230 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2231
2232 ret = si_copy_bytes_to_smc(rdev,
2233 (si_pi->state_table_start +
2234 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2235 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2236 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2237 sizeof(u32) * 2,
2238 si_pi->sram_end);
2239 if (ret)
2240 return ret;
2241 }
2242
2243 return 0;
2244 }
2245
2246 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2247 const u16 prev_std_vddc,
2248 const u16 curr_std_vddc)
2249 {
2250 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2251 u64 prev_vddc = (u64)prev_std_vddc;
2252 u64 curr_vddc = (u64)curr_std_vddc;
2253 u64 pwr_efficiency_ratio, n, d;
2254
2255 if ((prev_vddc == 0) || (curr_vddc == 0))
2256 return 0;
2257
2258 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2259 d = prev_vddc * prev_vddc;
2260 pwr_efficiency_ratio = div64_u64(n, d);
2261
2262 if (pwr_efficiency_ratio > (u64)0xFFFF)
2263 return 0;
2264
2265 return (u16)pwr_efficiency_ratio;
2266 }
2267
2268 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2269 struct radeon_ps *radeon_state)
2270 {
2271 struct si_power_info *si_pi = si_get_pi(rdev);
2272
2273 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2274 radeon_state->vclk && radeon_state->dclk)
2275 return true;
2276
2277 return false;
2278 }
2279
2280 static int si_populate_power_containment_values(struct radeon_device *rdev,
2281 struct radeon_ps *radeon_state,
2282 SISLANDS_SMC_SWSTATE *smc_state)
2283 {
2284 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2285 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2286 struct ni_ps *state = ni_get_ps(radeon_state);
2287 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2288 u32 prev_sclk;
2289 u32 max_sclk;
2290 u32 min_sclk;
2291 u16 prev_std_vddc;
2292 u16 curr_std_vddc;
2293 int i;
2294 u16 pwr_efficiency_ratio;
2295 u8 max_ps_percent;
2296 bool disable_uvd_power_tune;
2297 int ret;
2298
2299 if (ni_pi->enable_power_containment == false)
2300 return 0;
2301
2302 if (state->performance_level_count == 0)
2303 return -EINVAL;
2304
2305 if (smc_state->levelCount != state->performance_level_count)
2306 return -EINVAL;
2307
2308 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2309
2310 smc_state->levels[0].dpm2.MaxPS = 0;
2311 smc_state->levels[0].dpm2.NearTDPDec = 0;
2312 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2313 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2314 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2315
2316 for (i = 1; i < state->performance_level_count; i++) {
2317 prev_sclk = state->performance_levels[i-1].sclk;
2318 max_sclk = state->performance_levels[i].sclk;
2319 if (i == 1)
2320 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2321 else
2322 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2323
2324 if (prev_sclk > max_sclk)
2325 return -EINVAL;
2326
2327 if ((max_ps_percent == 0) ||
2328 (prev_sclk == max_sclk) ||
2329 disable_uvd_power_tune) {
2330 min_sclk = max_sclk;
2331 } else if (i == 1) {
2332 min_sclk = prev_sclk;
2333 } else {
2334 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2335 }
2336
2337 if (min_sclk < state->performance_levels[0].sclk)
2338 min_sclk = state->performance_levels[0].sclk;
2339
2340 if (min_sclk == 0)
2341 return -EINVAL;
2342
2343 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2344 state->performance_levels[i-1].vddc, &vddc);
2345 if (ret)
2346 return ret;
2347
2348 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2349 if (ret)
2350 return ret;
2351
2352 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2353 state->performance_levels[i].vddc, &vddc);
2354 if (ret)
2355 return ret;
2356
2357 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2358 if (ret)
2359 return ret;
2360
2361 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2362 prev_std_vddc, curr_std_vddc);
2363
2364 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2365 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2366 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2367 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2368 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2369 }
2370
2371 return 0;
2372 }
2373
2374 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2375 struct radeon_ps *radeon_state,
2376 SISLANDS_SMC_SWSTATE *smc_state)
2377 {
2378 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2379 struct ni_ps *state = ni_get_ps(radeon_state);
2380 u32 sq_power_throttle, sq_power_throttle2;
2381 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2382 int i;
2383
2384 if (state->performance_level_count == 0)
2385 return -EINVAL;
2386
2387 if (smc_state->levelCount != state->performance_level_count)
2388 return -EINVAL;
2389
2390 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2391 return -EINVAL;
2392
2393 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2394 enable_sq_ramping = false;
2395
2396 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2397 enable_sq_ramping = false;
2398
2399 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2400 enable_sq_ramping = false;
2401
2402 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2403 enable_sq_ramping = false;
2404
2405 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2406 enable_sq_ramping = false;
2407
2408 for (i = 0; i < state->performance_level_count; i++) {
2409 sq_power_throttle = 0;
2410 sq_power_throttle2 = 0;
2411
2412 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2413 enable_sq_ramping) {
2414 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2415 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2416 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2417 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2418 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2419 } else {
2420 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2421 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2422 }
2423
2424 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2425 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2426 }
2427
2428 return 0;
2429 }
2430
2431 static int si_enable_power_containment(struct radeon_device *rdev,
2432 struct radeon_ps *radeon_new_state,
2433 bool enable)
2434 {
2435 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2436 PPSMC_Result smc_result;
2437 int ret = 0;
2438
2439 if (ni_pi->enable_power_containment) {
2440 if (enable) {
2441 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2442 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2443 if (smc_result != PPSMC_Result_OK) {
2444 ret = -EINVAL;
2445 ni_pi->pc_enabled = false;
2446 } else {
2447 ni_pi->pc_enabled = true;
2448 }
2449 }
2450 } else {
2451 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2452 if (smc_result != PPSMC_Result_OK)
2453 ret = -EINVAL;
2454 ni_pi->pc_enabled = false;
2455 }
2456 }
2457
2458 return ret;
2459 }
2460
2461 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2462 {
2463 struct si_power_info *si_pi = si_get_pi(rdev);
2464 int ret = 0;
2465 struct si_dte_data *dte_data = &si_pi->dte_data;
2466 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2467 u32 table_size;
2468 u8 tdep_count;
2469 u32 i;
2470
2471 if (dte_data == NULL)
2472 si_pi->enable_dte = false;
2473
2474 if (si_pi->enable_dte == false)
2475 return 0;
2476
2477 if (dte_data->k <= 0)
2478 return -EINVAL;
2479
2480 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2481 if (dte_tables == NULL) {
2482 si_pi->enable_dte = false;
2483 return -ENOMEM;
2484 }
2485
2486 table_size = dte_data->k;
2487
2488 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2489 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2490
2491 tdep_count = dte_data->tdep_count;
2492 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2493 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2494
2495 dte_tables->K = cpu_to_be32(table_size);
2496 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2497 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2498 dte_tables->WindowSize = dte_data->window_size;
2499 dte_tables->temp_select = dte_data->temp_select;
2500 dte_tables->DTE_mode = dte_data->dte_mode;
2501 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2502
2503 if (tdep_count > 0)
2504 table_size--;
2505
2506 for (i = 0; i < table_size; i++) {
2507 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2508 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2509 }
2510
2511 dte_tables->Tdep_count = tdep_count;
2512
2513 for (i = 0; i < (u32)tdep_count; i++) {
2514 dte_tables->T_limits[i] = dte_data->t_limits[i];
2515 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2516 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2517 }
2518
2519 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2520 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2521 kfree(dte_tables);
2522
2523 return ret;
2524 }
2525
2526 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2527 u16 *max, u16 *min)
2528 {
2529 struct si_power_info *si_pi = si_get_pi(rdev);
2530 struct radeon_cac_leakage_table *table =
2531 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2532 u32 i;
2533 u32 v0_loadline;
2534
2535
2536 if (table == NULL)
2537 return -EINVAL;
2538
2539 *max = 0;
2540 *min = 0xFFFF;
2541
2542 for (i = 0; i < table->count; i++) {
2543 if (table->entries[i].vddc > *max)
2544 *max = table->entries[i].vddc;
2545 if (table->entries[i].vddc < *min)
2546 *min = table->entries[i].vddc;
2547 }
2548
2549 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2550 return -EINVAL;
2551
2552 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2553
2554 if (v0_loadline > 0xFFFFUL)
2555 return -EINVAL;
2556
2557 *min = (u16)v0_loadline;
2558
2559 if ((*min > *max) || (*max == 0) || (*min == 0))
2560 return -EINVAL;
2561
2562 return 0;
2563 }
2564
2565 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2566 {
2567 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2568 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2569 }
2570
2571 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2572 PP_SIslands_CacConfig *cac_tables,
2573 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2574 u16 t0, u16 t_step)
2575 {
2576 struct si_power_info *si_pi = si_get_pi(rdev);
2577 u32 leakage;
2578 unsigned int i, j;
2579 s32 t;
2580 u32 smc_leakage;
2581 u32 scaling_factor;
2582 u16 voltage;
2583
2584 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2585
2586 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2587 t = (1000 * (i * t_step + t0));
2588
2589 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2590 voltage = vddc_max - (vddc_step * j);
2591
2592 si_calculate_leakage_for_v_and_t(rdev,
2593 &si_pi->powertune_data->leakage_coefficients,
2594 voltage,
2595 t,
2596 si_pi->dyn_powertune_data.cac_leakage,
2597 &leakage);
2598
2599 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2600
2601 if (smc_leakage > 0xFFFF)
2602 smc_leakage = 0xFFFF;
2603
2604 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2605 cpu_to_be16((u16)smc_leakage);
2606 }
2607 }
2608 return 0;
2609 }
2610
2611 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2612 PP_SIslands_CacConfig *cac_tables,
2613 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2614 {
2615 struct si_power_info *si_pi = si_get_pi(rdev);
2616 u32 leakage;
2617 unsigned int i, j;
2618 u32 smc_leakage;
2619 u32 scaling_factor;
2620 u16 voltage;
2621
2622 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2623
2624 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2625 voltage = vddc_max - (vddc_step * j);
2626
2627 si_calculate_leakage_for_v(rdev,
2628 &si_pi->powertune_data->leakage_coefficients,
2629 si_pi->powertune_data->fixed_kt,
2630 voltage,
2631 si_pi->dyn_powertune_data.cac_leakage,
2632 &leakage);
2633
2634 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2635
2636 if (smc_leakage > 0xFFFF)
2637 smc_leakage = 0xFFFF;
2638
2639 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2640 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2641 cpu_to_be16((u16)smc_leakage);
2642 }
2643 return 0;
2644 }
2645
2646 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2647 {
2648 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2649 struct si_power_info *si_pi = si_get_pi(rdev);
2650 PP_SIslands_CacConfig *cac_tables = NULL;
2651 u16 vddc_max, vddc_min, vddc_step;
2652 u16 t0, t_step;
2653 u32 load_line_slope, reg;
2654 int ret = 0;
2655 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2656
2657 if (ni_pi->enable_cac == false)
2658 return 0;
2659
2660 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2661 if (!cac_tables)
2662 return -ENOMEM;
2663
2664 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2665 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2666 WREG32(CG_CAC_CTRL, reg);
2667
2668 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2669 si_pi->dyn_powertune_data.dc_pwr_value =
2670 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2671 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2672 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2673
2674 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2675
2676 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2677 if (ret)
2678 goto done_free;
2679
2680 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2681 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2682 t_step = 4;
2683 t0 = 60;
2684
2685 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2686 ret = si_init_dte_leakage_table(rdev, cac_tables,
2687 vddc_max, vddc_min, vddc_step,
2688 t0, t_step);
2689 else
2690 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2691 vddc_max, vddc_min, vddc_step);
2692 if (ret)
2693 goto done_free;
2694
2695 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2696
2697 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2698 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2699 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2700 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2701 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2702 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2703 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2704 cac_tables->calculation_repeats = cpu_to_be32(2);
2705 cac_tables->dc_cac = cpu_to_be32(0);
2706 cac_tables->log2_PG_LKG_SCALE = 12;
2707 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2708 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2709 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2710
2711 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2712 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2713
2714 if (ret)
2715 goto done_free;
2716
2717 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2718
2719 done_free:
2720 if (ret) {
2721 ni_pi->enable_cac = false;
2722 ni_pi->enable_power_containment = false;
2723 }
2724
2725 kfree(cac_tables);
2726
2727 return 0;
2728 }
2729
2730 static int si_program_cac_config_registers(struct radeon_device *rdev,
2731 const struct si_cac_config_reg *cac_config_regs)
2732 {
2733 const struct si_cac_config_reg *config_regs = cac_config_regs;
2734 u32 data = 0, offset;
2735
2736 if (!config_regs)
2737 return -EINVAL;
2738
2739 while (config_regs->offset != 0xFFFFFFFF) {
2740 switch (config_regs->type) {
2741 case SISLANDS_CACCONFIG_CGIND:
2742 offset = SMC_CG_IND_START + config_regs->offset;
2743 if (offset < SMC_CG_IND_END)
2744 data = RREG32_SMC(offset);
2745 break;
2746 default:
2747 data = RREG32(config_regs->offset << 2);
2748 break;
2749 }
2750
2751 data &= ~config_regs->mask;
2752 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2753
2754 switch (config_regs->type) {
2755 case SISLANDS_CACCONFIG_CGIND:
2756 offset = SMC_CG_IND_START + config_regs->offset;
2757 if (offset < SMC_CG_IND_END)
2758 WREG32_SMC(offset, data);
2759 break;
2760 default:
2761 WREG32(config_regs->offset << 2, data);
2762 break;
2763 }
2764 config_regs++;
2765 }
2766 return 0;
2767 }
2768
2769 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2770 {
2771 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2772 struct si_power_info *si_pi = si_get_pi(rdev);
2773 int ret;
2774
2775 if ((ni_pi->enable_cac == false) ||
2776 (ni_pi->cac_configuration_required == false))
2777 return 0;
2778
2779 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2780 if (ret)
2781 return ret;
2782 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2783 if (ret)
2784 return ret;
2785 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2786 if (ret)
2787 return ret;
2788
2789 return 0;
2790 }
2791
2792 static int si_enable_smc_cac(struct radeon_device *rdev,
2793 struct radeon_ps *radeon_new_state,
2794 bool enable)
2795 {
2796 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2797 struct si_power_info *si_pi = si_get_pi(rdev);
2798 PPSMC_Result smc_result;
2799 int ret = 0;
2800
2801 if (ni_pi->enable_cac) {
2802 if (enable) {
2803 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2804 if (ni_pi->support_cac_long_term_average) {
2805 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2806 if (smc_result != PPSMC_Result_OK)
2807 ni_pi->support_cac_long_term_average = false;
2808 }
2809
2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2811 if (smc_result != PPSMC_Result_OK) {
2812 ret = -EINVAL;
2813 ni_pi->cac_enabled = false;
2814 } else {
2815 ni_pi->cac_enabled = true;
2816 }
2817
2818 if (si_pi->enable_dte) {
2819 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2820 if (smc_result != PPSMC_Result_OK)
2821 ret = -EINVAL;
2822 }
2823 }
2824 } else if (ni_pi->cac_enabled) {
2825 if (si_pi->enable_dte)
2826 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2827
2828 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2829
2830 ni_pi->cac_enabled = false;
2831
2832 if (ni_pi->support_cac_long_term_average)
2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2834 }
2835 }
2836 return ret;
2837 }
2838
2839 static int si_init_smc_spll_table(struct radeon_device *rdev)
2840 {
2841 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2842 struct si_power_info *si_pi = si_get_pi(rdev);
2843 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2844 SISLANDS_SMC_SCLK_VALUE sclk_params;
2845 u32 fb_div, p_div;
2846 u32 clk_s, clk_v;
2847 u32 sclk = 0;
2848 int ret = 0;
2849 u32 tmp;
2850 int i;
2851
2852 if (si_pi->spll_table_start == 0)
2853 return -EINVAL;
2854
2855 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2856 if (spll_table == NULL)
2857 return -ENOMEM;
2858
2859 for (i = 0; i < 256; i++) {
2860 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2861 if (ret)
2862 break;
2863
2864 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2865 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2866 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2867 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2868
2869 fb_div &= ~0x00001FFF;
2870 fb_div >>= 1;
2871 clk_v >>= 6;
2872
2873 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2874 ret = -EINVAL;
2875 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2876 ret = -EINVAL;
2877 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2878 ret = -EINVAL;
2879 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2880 ret = -EINVAL;
2881
2882 if (ret)
2883 break;
2884
2885 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2886 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2887 spll_table->freq[i] = cpu_to_be32(tmp);
2888
2889 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2890 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2891 spll_table->ss[i] = cpu_to_be32(tmp);
2892
2893 sclk += 512;
2894 }
2895
2896
2897 if (!ret)
2898 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2899 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2900 si_pi->sram_end);
2901
2902 if (ret)
2903 ni_pi->enable_power_containment = false;
2904
2905 kfree(spll_table);
2906
2907 return ret;
2908 }
2909
2910 struct si_dpm_quirk {
2911 u32 chip_vendor;
2912 u32 chip_device;
2913 u32 subsys_vendor;
2914 u32 subsys_device;
2915 u32 max_sclk;
2916 u32 max_mclk;
2917 };
2918
2919 /* cards with dpm stability problems */
2920 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2921 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2922 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2923 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2924 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
2925 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2926 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2927 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2928 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
2929 { 0, 0, 0, 0 },
2930 };
2931
2932 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2933 struct radeon_ps *rps)
2934 {
2935 struct ni_ps *ps = ni_get_ps(rps);
2936 struct radeon_clock_and_voltage_limits *max_limits;
2937 bool disable_mclk_switching = false;
2938 bool disable_sclk_switching = false;
2939 u32 mclk, sclk;
2940 u16 vddc, vddci;
2941 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2942 u32 max_sclk = 0, max_mclk = 0;
2943 int i;
2944 struct si_dpm_quirk *p = si_dpm_quirk_list;
2945
2946 /* Apply dpm quirks */
2947 while (p && p->chip_device != 0) {
2948 if (rdev->pdev->vendor == p->chip_vendor &&
2949 rdev->pdev->device == p->chip_device &&
2950 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
2951 rdev->pdev->subsystem_device == p->subsys_device) {
2952 max_sclk = p->max_sclk;
2953 max_mclk = p->max_mclk;
2954 break;
2955 }
2956 ++p;
2957 }
2958
2959 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2960 ni_dpm_vblank_too_short(rdev))
2961 disable_mclk_switching = true;
2962
2963 if (rps->vclk || rps->dclk) {
2964 disable_mclk_switching = true;
2965 disable_sclk_switching = true;
2966 }
2967
2968 if (rdev->pm.dpm.ac_power)
2969 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2970 else
2971 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2972
2973 for (i = ps->performance_level_count - 2; i >= 0; i--) {
2974 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2975 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2976 }
2977 if (rdev->pm.dpm.ac_power == false) {
2978 for (i = 0; i < ps->performance_level_count; i++) {
2979 if (ps->performance_levels[i].mclk > max_limits->mclk)
2980 ps->performance_levels[i].mclk = max_limits->mclk;
2981 if (ps->performance_levels[i].sclk > max_limits->sclk)
2982 ps->performance_levels[i].sclk = max_limits->sclk;
2983 if (ps->performance_levels[i].vddc > max_limits->vddc)
2984 ps->performance_levels[i].vddc = max_limits->vddc;
2985 if (ps->performance_levels[i].vddci > max_limits->vddci)
2986 ps->performance_levels[i].vddci = max_limits->vddci;
2987 }
2988 }
2989
2990 /* limit clocks to max supported clocks based on voltage dependency tables */
2991 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2992 &max_sclk_vddc);
2993 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2994 &max_mclk_vddci);
2995 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2996 &max_mclk_vddc);
2997
2998 for (i = 0; i < ps->performance_level_count; i++) {
2999 if (max_sclk_vddc) {
3000 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3001 ps->performance_levels[i].sclk = max_sclk_vddc;
3002 }
3003 if (max_mclk_vddci) {
3004 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3005 ps->performance_levels[i].mclk = max_mclk_vddci;
3006 }
3007 if (max_mclk_vddc) {
3008 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3009 ps->performance_levels[i].mclk = max_mclk_vddc;
3010 }
3011 if (max_mclk) {
3012 if (ps->performance_levels[i].mclk > max_mclk)
3013 ps->performance_levels[i].mclk = max_mclk;
3014 }
3015 if (max_sclk) {
3016 if (ps->performance_levels[i].sclk > max_sclk)
3017 ps->performance_levels[i].sclk = max_sclk;
3018 }
3019 }
3020 /* limit mclk on all R7 370 parts for stability */
3021 if (rdev->pdev->device == 0x6811 &&
3022 rdev->pdev->revision == 0x81)
3023 max_mclk = 120000;
3024
3025 /* XXX validate the min clocks required for display */
3026
3027 if (disable_mclk_switching) {
3028 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3029 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3030 } else {
3031 mclk = ps->performance_levels[0].mclk;
3032 vddci = ps->performance_levels[0].vddci;
3033 }
3034
3035 if (disable_sclk_switching) {
3036 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3037 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3038 } else {
3039 sclk = ps->performance_levels[0].sclk;
3040 vddc = ps->performance_levels[0].vddc;
3041 }
3042
3043 /* adjusted low state */
3044 ps->performance_levels[0].sclk = sclk;
3045 ps->performance_levels[0].mclk = mclk;
3046 ps->performance_levels[0].vddc = vddc;
3047 ps->performance_levels[0].vddci = vddci;
3048
3049 if (disable_sclk_switching) {
3050 sclk = ps->performance_levels[0].sclk;
3051 for (i = 1; i < ps->performance_level_count; i++) {
3052 if (sclk < ps->performance_levels[i].sclk)
3053 sclk = ps->performance_levels[i].sclk;
3054 }
3055 for (i = 0; i < ps->performance_level_count; i++) {
3056 ps->performance_levels[i].sclk = sclk;
3057 ps->performance_levels[i].vddc = vddc;
3058 }
3059 } else {
3060 for (i = 1; i < ps->performance_level_count; i++) {
3061 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3062 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3063 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3064 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3065 }
3066 }
3067
3068 if (disable_mclk_switching) {
3069 mclk = ps->performance_levels[0].mclk;
3070 for (i = 1; i < ps->performance_level_count; i++) {
3071 if (mclk < ps->performance_levels[i].mclk)
3072 mclk = ps->performance_levels[i].mclk;
3073 }
3074 for (i = 0; i < ps->performance_level_count; i++) {
3075 ps->performance_levels[i].mclk = mclk;
3076 ps->performance_levels[i].vddci = vddci;
3077 }
3078 } else {
3079 for (i = 1; i < ps->performance_level_count; i++) {
3080 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3081 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3082 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3083 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3084 }
3085 }
3086
3087 for (i = 0; i < ps->performance_level_count; i++)
3088 btc_adjust_clock_combinations(rdev, max_limits,
3089 &ps->performance_levels[i]);
3090
3091 for (i = 0; i < ps->performance_level_count; i++) {
3092 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3093 ps->performance_levels[i].sclk,
3094 max_limits->vddc, &ps->performance_levels[i].vddc);
3095 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3096 ps->performance_levels[i].mclk,
3097 max_limits->vddci, &ps->performance_levels[i].vddci);
3098 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3099 ps->performance_levels[i].mclk,
3100 max_limits->vddc, &ps->performance_levels[i].vddc);
3101 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3102 rdev->clock.current_dispclk,
3103 max_limits->vddc, &ps->performance_levels[i].vddc);
3104 }
3105
3106 for (i = 0; i < ps->performance_level_count; i++) {
3107 btc_apply_voltage_delta_rules(rdev,
3108 max_limits->vddc, max_limits->vddci,
3109 &ps->performance_levels[i].vddc,
3110 &ps->performance_levels[i].vddci);
3111 }
3112
3113 ps->dc_compatible = true;
3114 for (i = 0; i < ps->performance_level_count; i++) {
3115 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3116 ps->dc_compatible = false;
3117 }
3118
3119 }
3120
3121 #if 0
3122 static int si_read_smc_soft_register(struct radeon_device *rdev,
3123 u16 reg_offset, u32 *value)
3124 {
3125 struct si_power_info *si_pi = si_get_pi(rdev);
3126
3127 return si_read_smc_sram_dword(rdev,
3128 si_pi->soft_regs_start + reg_offset, value,
3129 si_pi->sram_end);
3130 }
3131 #endif
3132
3133 static int si_write_smc_soft_register(struct radeon_device *rdev,
3134 u16 reg_offset, u32 value)
3135 {
3136 struct si_power_info *si_pi = si_get_pi(rdev);
3137
3138 return si_write_smc_sram_dword(rdev,
3139 si_pi->soft_regs_start + reg_offset,
3140 value, si_pi->sram_end);
3141 }
3142
3143 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3144 {
3145 bool ret = false;
3146 u32 tmp, width, row, column, bank, density;
3147 bool is_memory_gddr5, is_special;
3148
3149 tmp = RREG32(MC_SEQ_MISC0);
3150 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3151 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3152 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3153
3154 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3155 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3156
3157 tmp = RREG32(MC_ARB_RAMCFG);
3158 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3159 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3160 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3161
3162 density = (1 << (row + column - 20 + bank)) * width;
3163
3164 if ((rdev->pdev->device == 0x6819) &&
3165 is_memory_gddr5 && is_special && (density == 0x400))
3166 ret = true;
3167
3168 return ret;
3169 }
3170
3171 static void si_get_leakage_vddc(struct radeon_device *rdev)
3172 {
3173 struct si_power_info *si_pi = si_get_pi(rdev);
3174 u16 vddc, count = 0;
3175 int i, ret;
3176
3177 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3178 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3179
3180 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3181 si_pi->leakage_voltage.entries[count].voltage = vddc;
3182 si_pi->leakage_voltage.entries[count].leakage_index =
3183 SISLANDS_LEAKAGE_INDEX0 + i;
3184 count++;
3185 }
3186 }
3187 si_pi->leakage_voltage.count = count;
3188 }
3189
3190 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3191 u32 index, u16 *leakage_voltage)
3192 {
3193 struct si_power_info *si_pi = si_get_pi(rdev);
3194 int i;
3195
3196 if (leakage_voltage == NULL)
3197 return -EINVAL;
3198
3199 if ((index & 0xff00) != 0xff00)
3200 return -EINVAL;
3201
3202 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3203 return -EINVAL;
3204
3205 if (index < SISLANDS_LEAKAGE_INDEX0)
3206 return -EINVAL;
3207
3208 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3209 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3210 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3211 return 0;
3212 }
3213 }
3214 return -EAGAIN;
3215 }
3216
3217 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3218 {
3219 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3220 bool want_thermal_protection;
3221 enum radeon_dpm_event_src dpm_event_src;
3222
3223 switch (sources) {
3224 case 0:
3225 default:
3226 want_thermal_protection = false;
3227 break;
3228 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3229 want_thermal_protection = true;
3230 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3231 break;
3232 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3233 want_thermal_protection = true;
3234 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3235 break;
3236 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3237 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3238 want_thermal_protection = true;
3239 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3240 break;
3241 }
3242
3243 if (want_thermal_protection) {
3244 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3245 if (pi->thermal_protection)
3246 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3247 } else {
3248 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3249 }
3250 }
3251
3252 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3253 enum radeon_dpm_auto_throttle_src source,
3254 bool enable)
3255 {
3256 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3257
3258 if (enable) {
3259 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3260 pi->active_auto_throttle_sources |= 1 << source;
3261 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3262 }
3263 } else {
3264 if (pi->active_auto_throttle_sources & (1 << source)) {
3265 pi->active_auto_throttle_sources &= ~(1 << source);
3266 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3267 }
3268 }
3269 }
3270
3271 static void si_start_dpm(struct radeon_device *rdev)
3272 {
3273 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3274 }
3275
3276 static void si_stop_dpm(struct radeon_device *rdev)
3277 {
3278 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3279 }
3280
3281 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3282 {
3283 if (enable)
3284 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3285 else
3286 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3287
3288 }
3289
3290 #if 0
3291 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3292 u32 thermal_level)
3293 {
3294 PPSMC_Result ret;
3295
3296 if (thermal_level == 0) {
3297 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3298 if (ret == PPSMC_Result_OK)
3299 return 0;
3300 else
3301 return -EINVAL;
3302 }
3303 return 0;
3304 }
3305
3306 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3307 {
3308 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3309 }
3310 #endif
3311
3312 #if 0
3313 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3314 {
3315 if (ac_power)
3316 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3317 0 : -EINVAL;
3318
3319 return 0;
3320 }
3321 #endif
3322
3323 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3324 PPSMC_Msg msg, u32 parameter)
3325 {
3326 WREG32(SMC_SCRATCH0, parameter);
3327 return si_send_msg_to_smc(rdev, msg);
3328 }
3329
3330 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3331 {
3332 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3333 return -EINVAL;
3334
3335 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3336 0 : -EINVAL;
3337 }
3338
3339 int si_dpm_force_performance_level(struct radeon_device *rdev,
3340 enum radeon_dpm_forced_level level)
3341 {
3342 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3343 struct ni_ps *ps = ni_get_ps(rps);
3344 u32 levels = ps->performance_level_count;
3345
3346 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3347 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3348 return -EINVAL;
3349
3350 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3351 return -EINVAL;
3352 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3353 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3354 return -EINVAL;
3355
3356 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3357 return -EINVAL;
3358 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3359 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3360 return -EINVAL;
3361
3362 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3363 return -EINVAL;
3364 }
3365
3366 rdev->pm.dpm.forced_level = level;
3367
3368 return 0;
3369 }
3370
3371 static int si_set_boot_state(struct radeon_device *rdev)
3372 {
3373 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3374 0 : -EINVAL;
3375 }
3376
3377 static int si_set_sw_state(struct radeon_device *rdev)
3378 {
3379 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3380 0 : -EINVAL;
3381 }
3382
3383 static int si_halt_smc(struct radeon_device *rdev)
3384 {
3385 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3386 return -EINVAL;
3387
3388 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3389 0 : -EINVAL;
3390 }
3391
3392 static int si_resume_smc(struct radeon_device *rdev)
3393 {
3394 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3395 return -EINVAL;
3396
3397 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3398 0 : -EINVAL;
3399 }
3400
3401 static void si_dpm_start_smc(struct radeon_device *rdev)
3402 {
3403 si_program_jump_on_start(rdev);
3404 si_start_smc(rdev);
3405 si_start_smc_clock(rdev);
3406 }
3407
3408 static void si_dpm_stop_smc(struct radeon_device *rdev)
3409 {
3410 si_reset_smc(rdev);
3411 si_stop_smc_clock(rdev);
3412 }
3413
3414 static int si_process_firmware_header(struct radeon_device *rdev)
3415 {
3416 struct si_power_info *si_pi = si_get_pi(rdev);
3417 u32 tmp;
3418 int ret;
3419
3420 ret = si_read_smc_sram_dword(rdev,
3421 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3422 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3423 &tmp, si_pi->sram_end);
3424 if (ret)
3425 return ret;
3426
3427 si_pi->state_table_start = tmp;
3428
3429 ret = si_read_smc_sram_dword(rdev,
3430 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3431 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3432 &tmp, si_pi->sram_end);
3433 if (ret)
3434 return ret;
3435
3436 si_pi->soft_regs_start = tmp;
3437
3438 ret = si_read_smc_sram_dword(rdev,
3439 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3440 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3441 &tmp, si_pi->sram_end);
3442 if (ret)
3443 return ret;
3444
3445 si_pi->mc_reg_table_start = tmp;
3446
3447 ret = si_read_smc_sram_dword(rdev,
3448 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3449 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3450 &tmp, si_pi->sram_end);
3451 if (ret)
3452 return ret;
3453
3454 si_pi->arb_table_start = tmp;
3455
3456 ret = si_read_smc_sram_dword(rdev,
3457 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3458 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3459 &tmp, si_pi->sram_end);
3460 if (ret)
3461 return ret;
3462
3463 si_pi->cac_table_start = tmp;
3464
3465 ret = si_read_smc_sram_dword(rdev,
3466 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3467 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3468 &tmp, si_pi->sram_end);
3469 if (ret)
3470 return ret;
3471
3472 si_pi->dte_table_start = tmp;
3473
3474 ret = si_read_smc_sram_dword(rdev,
3475 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3476 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3477 &tmp, si_pi->sram_end);
3478 if (ret)
3479 return ret;
3480
3481 si_pi->spll_table_start = tmp;
3482
3483 ret = si_read_smc_sram_dword(rdev,
3484 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3485 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3486 &tmp, si_pi->sram_end);
3487 if (ret)
3488 return ret;
3489
3490 si_pi->papm_cfg_table_start = tmp;
3491
3492 return ret;
3493 }
3494
3495 static void si_read_clock_registers(struct radeon_device *rdev)
3496 {
3497 struct si_power_info *si_pi = si_get_pi(rdev);
3498
3499 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3500 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3501 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3502 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3503 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3504 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3505 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3506 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3507 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3508 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3509 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3510 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3511 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3512 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3513 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3514 }
3515
3516 static void si_enable_thermal_protection(struct radeon_device *rdev,
3517 bool enable)
3518 {
3519 if (enable)
3520 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3521 else
3522 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3523 }
3524
3525 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3526 {
3527 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3528 }
3529
3530 #if 0
3531 static int si_enter_ulp_state(struct radeon_device *rdev)
3532 {
3533 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3534
3535 udelay(25000);
3536
3537 return 0;
3538 }
3539
3540 static int si_exit_ulp_state(struct radeon_device *rdev)
3541 {
3542 int i;
3543
3544 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3545
3546 udelay(7000);
3547
3548 for (i = 0; i < rdev->usec_timeout; i++) {
3549 if (RREG32(SMC_RESP_0) == 1)
3550 break;
3551 udelay(1000);
3552 }
3553
3554 return 0;
3555 }
3556 #endif
3557
3558 static int si_notify_smc_display_change(struct radeon_device *rdev,
3559 bool has_display)
3560 {
3561 PPSMC_Msg msg = has_display ?
3562 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3563
3564 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3565 0 : -EINVAL;
3566 }
3567
3568 static void si_program_response_times(struct radeon_device *rdev)
3569 {
3570 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3571 u32 vddc_dly, acpi_dly, vbi_dly;
3572 u32 reference_clock;
3573
3574 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3575
3576 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3577 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3578
3579 if (voltage_response_time == 0)
3580 voltage_response_time = 1000;
3581
3582 acpi_delay_time = 15000;
3583 vbi_time_out = 100000;
3584
3585 reference_clock = radeon_get_xclk(rdev);
3586
3587 vddc_dly = (voltage_response_time * reference_clock) / 100;
3588 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3589 vbi_dly = (vbi_time_out * reference_clock) / 100;
3590
3591 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3592 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3593 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3594 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3595 }
3596
3597 static void si_program_ds_registers(struct radeon_device *rdev)
3598 {
3599 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3600 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3601
3602 if (eg_pi->sclk_deep_sleep) {
3603 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3604 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3605 ~AUTOSCALE_ON_SS_CLEAR);
3606 }
3607 }
3608
3609 static void si_program_display_gap(struct radeon_device *rdev)
3610 {
3611 u32 tmp, pipe;
3612 int i;
3613
3614 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3615 if (rdev->pm.dpm.new_active_crtc_count > 0)
3616 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3617 else
3618 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3619
3620 if (rdev->pm.dpm.new_active_crtc_count > 1)
3621 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3622 else
3623 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3624
3625 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3626
3627 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3628 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3629
3630 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3631 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3632 /* find the first active crtc */
3633 for (i = 0; i < rdev->num_crtc; i++) {
3634 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3635 break;
3636 }
3637 if (i == rdev->num_crtc)
3638 pipe = 0;
3639 else
3640 pipe = i;
3641
3642 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3643 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3644 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3645 }
3646
3647 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3648 * This can be a problem on PowerXpress systems or if you want to use the card
3649 * for offscreen rendering or compute if there are no crtcs enabled.
3650 */
3651 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3652 }
3653
3654 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3655 {
3656 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3657
3658 if (enable) {
3659 if (pi->sclk_ss)
3660 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3661 } else {
3662 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3663 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3664 }
3665 }
3666
3667 static void si_setup_bsp(struct radeon_device *rdev)
3668 {
3669 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3670 u32 xclk = radeon_get_xclk(rdev);
3671
3672 r600_calculate_u_and_p(pi->asi,
3673 xclk,
3674 16,
3675 &pi->bsp,
3676 &pi->bsu);
3677
3678 r600_calculate_u_and_p(pi->pasi,
3679 xclk,
3680 16,
3681 &pi->pbsp,
3682 &pi->pbsu);
3683
3684
3685 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3686 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3687
3688 WREG32(CG_BSP, pi->dsp);
3689 }
3690
3691 static void si_program_git(struct radeon_device *rdev)
3692 {
3693 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3694 }
3695
3696 static void si_program_tp(struct radeon_device *rdev)
3697 {
3698 int i;
3699 enum r600_td td = R600_TD_DFLT;
3700
3701 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3702 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3703
3704 if (td == R600_TD_AUTO)
3705 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3706 else
3707 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3708
3709 if (td == R600_TD_UP)
3710 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3711
3712 if (td == R600_TD_DOWN)
3713 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3714 }
3715
3716 static void si_program_tpp(struct radeon_device *rdev)
3717 {
3718 WREG32(CG_TPC, R600_TPC_DFLT);
3719 }
3720
3721 static void si_program_sstp(struct radeon_device *rdev)
3722 {
3723 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3724 }
3725
3726 static void si_enable_display_gap(struct radeon_device *rdev)
3727 {
3728 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3729
3730 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3731 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3732 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3733
3734 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3735 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3736 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3737 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3738 }
3739
3740 static void si_program_vc(struct radeon_device *rdev)
3741 {
3742 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3743
3744 WREG32(CG_FTV, pi->vrc);
3745 }
3746
3747 static void si_clear_vc(struct radeon_device *rdev)
3748 {
3749 WREG32(CG_FTV, 0);
3750 }
3751
3752 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3753 {
3754 u8 mc_para_index;
3755
3756 if (memory_clock < 10000)
3757 mc_para_index = 0;
3758 else if (memory_clock >= 80000)
3759 mc_para_index = 0x0f;
3760 else
3761 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3762 return mc_para_index;
3763 }
3764
3765 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3766 {
3767 u8 mc_para_index;
3768
3769 if (strobe_mode) {
3770 if (memory_clock < 12500)
3771 mc_para_index = 0x00;
3772 else if (memory_clock > 47500)
3773 mc_para_index = 0x0f;
3774 else
3775 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3776 } else {
3777 if (memory_clock < 65000)
3778 mc_para_index = 0x00;
3779 else if (memory_clock > 135000)
3780 mc_para_index = 0x0f;
3781 else
3782 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3783 }
3784 return mc_para_index;
3785 }
3786
3787 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3788 {
3789 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3790 bool strobe_mode = false;
3791 u8 result = 0;
3792
3793 if (mclk <= pi->mclk_strobe_mode_threshold)
3794 strobe_mode = true;
3795
3796 if (pi->mem_gddr5)
3797 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3798 else
3799 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3800
3801 if (strobe_mode)
3802 result |= SISLANDS_SMC_STROBE_ENABLE;
3803
3804 return result;
3805 }
3806
3807 static int si_upload_firmware(struct radeon_device *rdev)
3808 {
3809 struct si_power_info *si_pi = si_get_pi(rdev);
3810 int ret;
3811
3812 si_reset_smc(rdev);
3813 si_stop_smc_clock(rdev);
3814
3815 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3816
3817 return ret;
3818 }
3819
3820 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3821 const struct atom_voltage_table *table,
3822 const struct radeon_phase_shedding_limits_table *limits)
3823 {
3824 u32 data, num_bits, num_levels;
3825
3826 if ((table == NULL) || (limits == NULL))
3827 return false;
3828
3829 data = table->mask_low;
3830
3831 num_bits = hweight32(data);
3832
3833 if (num_bits == 0)
3834 return false;
3835
3836 num_levels = (1 << num_bits);
3837
3838 if (table->count != num_levels)
3839 return false;
3840
3841 if (limits->count != (num_levels - 1))
3842 return false;
3843
3844 return true;
3845 }
3846
3847 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3848 u32 max_voltage_steps,
3849 struct atom_voltage_table *voltage_table)
3850 {
3851 unsigned int i, diff;
3852
3853 if (voltage_table->count <= max_voltage_steps)
3854 return;
3855
3856 diff = voltage_table->count - max_voltage_steps;
3857
3858 for (i= 0; i < max_voltage_steps; i++)
3859 voltage_table->entries[i] = voltage_table->entries[i + diff];
3860
3861 voltage_table->count = max_voltage_steps;
3862 }
3863
3864 static int si_construct_voltage_tables(struct radeon_device *rdev)
3865 {
3866 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3867 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3868 struct si_power_info *si_pi = si_get_pi(rdev);
3869 int ret;
3870
3871 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3872 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3873 if (ret)
3874 return ret;
3875
3876 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3877 si_trim_voltage_table_to_fit_state_table(rdev,
3878 SISLANDS_MAX_NO_VREG_STEPS,
3879 &eg_pi->vddc_voltage_table);
3880
3881 if (eg_pi->vddci_control) {
3882 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3883 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3884 if (ret)
3885 return ret;
3886
3887 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3888 si_trim_voltage_table_to_fit_state_table(rdev,
3889 SISLANDS_MAX_NO_VREG_STEPS,
3890 &eg_pi->vddci_voltage_table);
3891 }
3892
3893 if (pi->mvdd_control) {
3894 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3895 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3896
3897 if (ret) {
3898 pi->mvdd_control = false;
3899 return ret;
3900 }
3901
3902 if (si_pi->mvdd_voltage_table.count == 0) {
3903 pi->mvdd_control = false;
3904 return -EINVAL;
3905 }
3906
3907 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3908 si_trim_voltage_table_to_fit_state_table(rdev,
3909 SISLANDS_MAX_NO_VREG_STEPS,
3910 &si_pi->mvdd_voltage_table);
3911 }
3912
3913 if (si_pi->vddc_phase_shed_control) {
3914 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3915 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3916 if (ret)
3917 si_pi->vddc_phase_shed_control = false;
3918
3919 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3920 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3921 si_pi->vddc_phase_shed_control = false;
3922 }
3923
3924 return 0;
3925 }
3926
3927 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3928 const struct atom_voltage_table *voltage_table,
3929 SISLANDS_SMC_STATETABLE *table)
3930 {
3931 unsigned int i;
3932
3933 for (i = 0; i < voltage_table->count; i++)
3934 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3935 }
3936
3937 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3938 SISLANDS_SMC_STATETABLE *table)
3939 {
3940 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3941 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3942 struct si_power_info *si_pi = si_get_pi(rdev);
3943 u8 i;
3944
3945 if (eg_pi->vddc_voltage_table.count) {
3946 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3947 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3948 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3949
3950 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3951 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3952 table->maxVDDCIndexInPPTable = i;
3953 break;
3954 }
3955 }
3956 }
3957
3958 if (eg_pi->vddci_voltage_table.count) {
3959 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
3960
3961 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
3962 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
3963 }
3964
3965
3966 if (si_pi->mvdd_voltage_table.count) {
3967 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
3968
3969 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
3970 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
3971 }
3972
3973 if (si_pi->vddc_phase_shed_control) {
3974 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
3975 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
3976 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
3977
3978 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3979 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
3980
3981 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
3982 (u32)si_pi->vddc_phase_shed_table.phase_delay);
3983 } else {
3984 si_pi->vddc_phase_shed_control = false;
3985 }
3986 }
3987
3988 return 0;
3989 }
3990
3991 static int si_populate_voltage_value(struct radeon_device *rdev,
3992 const struct atom_voltage_table *table,
3993 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3994 {
3995 unsigned int i;
3996
3997 for (i = 0; i < table->count; i++) {
3998 if (value <= table->entries[i].value) {
3999 voltage->index = (u8)i;
4000 voltage->value = cpu_to_be16(table->entries[i].value);
4001 break;
4002 }
4003 }
4004
4005 if (i >= table->count)
4006 return -EINVAL;
4007
4008 return 0;
4009 }
4010
4011 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4012 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4013 {
4014 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4015 struct si_power_info *si_pi = si_get_pi(rdev);
4016
4017 if (pi->mvdd_control) {
4018 if (mclk <= pi->mvdd_split_frequency)
4019 voltage->index = 0;
4020 else
4021 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4022
4023 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4024 }
4025 return 0;
4026 }
4027
4028 static int si_get_std_voltage_value(struct radeon_device *rdev,
4029 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4030 u16 *std_voltage)
4031 {
4032 u16 v_index;
4033 bool voltage_found = false;
4034 *std_voltage = be16_to_cpu(voltage->value);
4035
4036 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4037 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4038 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4039 return -EINVAL;
4040
4041 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4042 if (be16_to_cpu(voltage->value) ==
4043 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4044 voltage_found = true;
4045 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4046 *std_voltage =
4047 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4048 else
4049 *std_voltage =
4050 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4051 break;
4052 }
4053 }
4054
4055 if (!voltage_found) {
4056 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4057 if (be16_to_cpu(voltage->value) <=
4058 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4059 voltage_found = true;
4060 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4061 *std_voltage =
4062 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4063 else
4064 *std_voltage =
4065 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4066 break;
4067 }
4068 }
4069 }
4070 } else {
4071 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4072 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4073 }
4074 }
4075
4076 return 0;
4077 }
4078
4079 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4080 u16 value, u8 index,
4081 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4082 {
4083 voltage->index = index;
4084 voltage->value = cpu_to_be16(value);
4085
4086 return 0;
4087 }
4088
4089 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4090 const struct radeon_phase_shedding_limits_table *limits,
4091 u16 voltage, u32 sclk, u32 mclk,
4092 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4093 {
4094 unsigned int i;
4095
4096 for (i = 0; i < limits->count; i++) {
4097 if ((voltage <= limits->entries[i].voltage) &&
4098 (sclk <= limits->entries[i].sclk) &&
4099 (mclk <= limits->entries[i].mclk))
4100 break;
4101 }
4102
4103 smc_voltage->phase_settings = (u8)i;
4104
4105 return 0;
4106 }
4107
4108 static int si_init_arb_table_index(struct radeon_device *rdev)
4109 {
4110 struct si_power_info *si_pi = si_get_pi(rdev);
4111 u32 tmp;
4112 int ret;
4113
4114 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4115 if (ret)
4116 return ret;
4117
4118 tmp &= 0x00FFFFFF;
4119 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4120
4121 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4122 }
4123
4124 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4125 {
4126 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4127 }
4128
4129 static int si_reset_to_default(struct radeon_device *rdev)
4130 {
4131 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4132 0 : -EINVAL;
4133 }
4134
4135 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4136 {
4137 struct si_power_info *si_pi = si_get_pi(rdev);
4138 u32 tmp;
4139 int ret;
4140
4141 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4142 &tmp, si_pi->sram_end);
4143 if (ret)
4144 return ret;
4145
4146 tmp = (tmp >> 24) & 0xff;
4147
4148 if (tmp == MC_CG_ARB_FREQ_F0)
4149 return 0;
4150
4151 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4152 }
4153
4154 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4155 u32 engine_clock)
4156 {
4157 u32 dram_rows;
4158 u32 dram_refresh_rate;
4159 u32 mc_arb_rfsh_rate;
4160 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4161
4162 if (tmp >= 4)
4163 dram_rows = 16384;
4164 else
4165 dram_rows = 1 << (tmp + 10);
4166
4167 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4168 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4169
4170 return mc_arb_rfsh_rate;
4171 }
4172
4173 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4174 struct rv7xx_pl *pl,
4175 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4176 {
4177 u32 dram_timing;
4178 u32 dram_timing2;
4179 u32 burst_time;
4180
4181 arb_regs->mc_arb_rfsh_rate =
4182 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4183
4184 radeon_atom_set_engine_dram_timings(rdev,
4185 pl->sclk,
4186 pl->mclk);
4187
4188 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4189 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4190 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4191
4192 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4193 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4194 arb_regs->mc_arb_burst_time = (u8)burst_time;
4195
4196 return 0;
4197 }
4198
4199 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4200 struct radeon_ps *radeon_state,
4201 unsigned int first_arb_set)
4202 {
4203 struct si_power_info *si_pi = si_get_pi(rdev);
4204 struct ni_ps *state = ni_get_ps(radeon_state);
4205 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4206 int i, ret = 0;
4207
4208 for (i = 0; i < state->performance_level_count; i++) {
4209 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4210 if (ret)
4211 break;
4212 ret = si_copy_bytes_to_smc(rdev,
4213 si_pi->arb_table_start +
4214 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4215 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4216 (u8 *)&arb_regs,
4217 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4218 si_pi->sram_end);
4219 if (ret)
4220 break;
4221 }
4222
4223 return ret;
4224 }
4225
4226 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4227 struct radeon_ps *radeon_new_state)
4228 {
4229 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4230 SISLANDS_DRIVER_STATE_ARB_INDEX);
4231 }
4232
4233 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4234 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4235 {
4236 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4237 struct si_power_info *si_pi = si_get_pi(rdev);
4238
4239 if (pi->mvdd_control)
4240 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4241 si_pi->mvdd_bootup_value, voltage);
4242
4243 return 0;
4244 }
4245
4246 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4247 struct radeon_ps *radeon_initial_state,
4248 SISLANDS_SMC_STATETABLE *table)
4249 {
4250 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4251 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4252 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4253 struct si_power_info *si_pi = si_get_pi(rdev);
4254 u32 reg;
4255 int ret;
4256
4257 table->initialState.levels[0].mclk.vDLL_CNTL =
4258 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4259 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4260 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4261 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4262 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4263 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4264 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4265 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4266 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4267 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4268 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4269 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4270 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4271 table->initialState.levels[0].mclk.vMPLL_SS =
4272 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4273 table->initialState.levels[0].mclk.vMPLL_SS2 =
4274 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4275
4276 table->initialState.levels[0].mclk.mclk_value =
4277 cpu_to_be32(initial_state->performance_levels[0].mclk);
4278
4279 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4280 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4281 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4282 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4283 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4284 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4285 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4286 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4287 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4288 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4289 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4290 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4291
4292 table->initialState.levels[0].sclk.sclk_value =
4293 cpu_to_be32(initial_state->performance_levels[0].sclk);
4294
4295 table->initialState.levels[0].arbRefreshState =
4296 SISLANDS_INITIAL_STATE_ARB_INDEX;
4297
4298 table->initialState.levels[0].ACIndex = 0;
4299
4300 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4301 initial_state->performance_levels[0].vddc,
4302 &table->initialState.levels[0].vddc);
4303
4304 if (!ret) {
4305 u16 std_vddc;
4306
4307 ret = si_get_std_voltage_value(rdev,
4308 &table->initialState.levels[0].vddc,
4309 &std_vddc);
4310 if (!ret)
4311 si_populate_std_voltage_value(rdev, std_vddc,
4312 table->initialState.levels[0].vddc.index,
4313 &table->initialState.levels[0].std_vddc);
4314 }
4315
4316 if (eg_pi->vddci_control)
4317 si_populate_voltage_value(rdev,
4318 &eg_pi->vddci_voltage_table,
4319 initial_state->performance_levels[0].vddci,
4320 &table->initialState.levels[0].vddci);
4321
4322 if (si_pi->vddc_phase_shed_control)
4323 si_populate_phase_shedding_value(rdev,
4324 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4325 initial_state->performance_levels[0].vddc,
4326 initial_state->performance_levels[0].sclk,
4327 initial_state->performance_levels[0].mclk,
4328 &table->initialState.levels[0].vddc);
4329
4330 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4331
4332 reg = CG_R(0xffff) | CG_L(0);
4333 table->initialState.levels[0].aT = cpu_to_be32(reg);
4334
4335 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4336
4337 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4338
4339 if (pi->mem_gddr5) {
4340 table->initialState.levels[0].strobeMode =
4341 si_get_strobe_mode_settings(rdev,
4342 initial_state->performance_levels[0].mclk);
4343
4344 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4345 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4346 else
4347 table->initialState.levels[0].mcFlags = 0;
4348 }
4349
4350 table->initialState.levelCount = 1;
4351
4352 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4353
4354 table->initialState.levels[0].dpm2.MaxPS = 0;
4355 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4356 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4357 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4358 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4359
4360 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4361 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4362
4363 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4364 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4365
4366 return 0;
4367 }
4368
4369 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4370 SISLANDS_SMC_STATETABLE *table)
4371 {
4372 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4373 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4374 struct si_power_info *si_pi = si_get_pi(rdev);
4375 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4376 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4377 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4378 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4379 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4380 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4381 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4382 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4383 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4384 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4385 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4386 u32 reg;
4387 int ret;
4388
4389 table->ACPIState = table->initialState;
4390
4391 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4392
4393 if (pi->acpi_vddc) {
4394 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4395 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4396 if (!ret) {
4397 u16 std_vddc;
4398
4399 ret = si_get_std_voltage_value(rdev,
4400 &table->ACPIState.levels[0].vddc, &std_vddc);
4401 if (!ret)
4402 si_populate_std_voltage_value(rdev, std_vddc,
4403 table->ACPIState.levels[0].vddc.index,
4404 &table->ACPIState.levels[0].std_vddc);
4405 }
4406 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4407
4408 if (si_pi->vddc_phase_shed_control) {
4409 si_populate_phase_shedding_value(rdev,
4410 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4411 pi->acpi_vddc,
4412 0,
4413 0,
4414 &table->ACPIState.levels[0].vddc);
4415 }
4416 } else {
4417 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4418 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4419 if (!ret) {
4420 u16 std_vddc;
4421
4422 ret = si_get_std_voltage_value(rdev,
4423 &table->ACPIState.levels[0].vddc, &std_vddc);
4424
4425 if (!ret)
4426 si_populate_std_voltage_value(rdev, std_vddc,
4427 table->ACPIState.levels[0].vddc.index,
4428 &table->ACPIState.levels[0].std_vddc);
4429 }
4430 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4431 si_pi->sys_pcie_mask,
4432 si_pi->boot_pcie_gen,
4433 RADEON_PCIE_GEN1);
4434
4435 if (si_pi->vddc_phase_shed_control)
4436 si_populate_phase_shedding_value(rdev,
4437 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4438 pi->min_vddc_in_table,
4439 0,
4440 0,
4441 &table->ACPIState.levels[0].vddc);
4442 }
4443
4444 if (pi->acpi_vddc) {
4445 if (eg_pi->acpi_vddci)
4446 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4447 eg_pi->acpi_vddci,
4448 &table->ACPIState.levels[0].vddci);
4449 }
4450
4451 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4452 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4453
4454 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4455
4456 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4457 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4458
4459 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4460 cpu_to_be32(dll_cntl);
4461 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4462 cpu_to_be32(mclk_pwrmgt_cntl);
4463 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4464 cpu_to_be32(mpll_ad_func_cntl);
4465 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4466 cpu_to_be32(mpll_dq_func_cntl);
4467 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4468 cpu_to_be32(mpll_func_cntl);
4469 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4470 cpu_to_be32(mpll_func_cntl_1);
4471 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4472 cpu_to_be32(mpll_func_cntl_2);
4473 table->ACPIState.levels[0].mclk.vMPLL_SS =
4474 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4475 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4476 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4477
4478 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4479 cpu_to_be32(spll_func_cntl);
4480 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4481 cpu_to_be32(spll_func_cntl_2);
4482 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4483 cpu_to_be32(spll_func_cntl_3);
4484 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4485 cpu_to_be32(spll_func_cntl_4);
4486
4487 table->ACPIState.levels[0].mclk.mclk_value = 0;
4488 table->ACPIState.levels[0].sclk.sclk_value = 0;
4489
4490 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4491
4492 if (eg_pi->dynamic_ac_timing)
4493 table->ACPIState.levels[0].ACIndex = 0;
4494
4495 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4496 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4497 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4498 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4499 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4500
4501 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4502 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4503
4504 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4505 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4506
4507 return 0;
4508 }
4509
4510 static int si_populate_ulv_state(struct radeon_device *rdev,
4511 SISLANDS_SMC_SWSTATE *state)
4512 {
4513 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4514 struct si_power_info *si_pi = si_get_pi(rdev);
4515 struct si_ulv_param *ulv = &si_pi->ulv;
4516 u32 sclk_in_sr = 1350; /* ??? */
4517 int ret;
4518
4519 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4520 &state->levels[0]);
4521 if (!ret) {
4522 if (eg_pi->sclk_deep_sleep) {
4523 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4524 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4525 else
4526 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4527 }
4528 if (ulv->one_pcie_lane_in_ulv)
4529 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4530 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4531 state->levels[0].ACIndex = 1;
4532 state->levels[0].std_vddc = state->levels[0].vddc;
4533 state->levelCount = 1;
4534
4535 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4536 }
4537
4538 return ret;
4539 }
4540
4541 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4542 {
4543 struct si_power_info *si_pi = si_get_pi(rdev);
4544 struct si_ulv_param *ulv = &si_pi->ulv;
4545 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4546 int ret;
4547
4548 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4549 &arb_regs);
4550 if (ret)
4551 return ret;
4552
4553 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4554 ulv->volt_change_delay);
4555
4556 ret = si_copy_bytes_to_smc(rdev,
4557 si_pi->arb_table_start +
4558 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4559 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4560 (u8 *)&arb_regs,
4561 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4562 si_pi->sram_end);
4563
4564 return ret;
4565 }
4566
4567 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4568 {
4569 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4570
4571 pi->mvdd_split_frequency = 30000;
4572 }
4573
4574 static int si_init_smc_table(struct radeon_device *rdev)
4575 {
4576 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4577 struct si_power_info *si_pi = si_get_pi(rdev);
4578 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4579 const struct si_ulv_param *ulv = &si_pi->ulv;
4580 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4581 int ret;
4582 u32 lane_width;
4583 u32 vr_hot_gpio;
4584
4585 si_populate_smc_voltage_tables(rdev, table);
4586
4587 switch (rdev->pm.int_thermal_type) {
4588 case THERMAL_TYPE_SI:
4589 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4590 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4591 break;
4592 case THERMAL_TYPE_NONE:
4593 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4594 break;
4595 default:
4596 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4597 break;
4598 }
4599
4600 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4601 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4602
4603 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4604 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4605 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4606 }
4607
4608 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4609 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4610
4611 if (pi->mem_gddr5)
4612 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4613
4614 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4615 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4616
4617 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4618 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4619 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4620 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4621 vr_hot_gpio);
4622 }
4623
4624 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4625 if (ret)
4626 return ret;
4627
4628 ret = si_populate_smc_acpi_state(rdev, table);
4629 if (ret)
4630 return ret;
4631
4632 table->driverState = table->initialState;
4633
4634 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4635 SISLANDS_INITIAL_STATE_ARB_INDEX);
4636 if (ret)
4637 return ret;
4638
4639 if (ulv->supported && ulv->pl.vddc) {
4640 ret = si_populate_ulv_state(rdev, &table->ULVState);
4641 if (ret)
4642 return ret;
4643
4644 ret = si_program_ulv_memory_timing_parameters(rdev);
4645 if (ret)
4646 return ret;
4647
4648 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4649 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4650
4651 lane_width = radeon_get_pcie_lanes(rdev);
4652 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4653 } else {
4654 table->ULVState = table->initialState;
4655 }
4656
4657 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4658 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4659 si_pi->sram_end);
4660 }
4661
4662 static int si_calculate_sclk_params(struct radeon_device *rdev,
4663 u32 engine_clock,
4664 SISLANDS_SMC_SCLK_VALUE *sclk)
4665 {
4666 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4667 struct si_power_info *si_pi = si_get_pi(rdev);
4668 struct atom_clock_dividers dividers;
4669 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4670 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4671 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4672 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4673 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4674 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4675 u64 tmp;
4676 u32 reference_clock = rdev->clock.spll.reference_freq;
4677 u32 reference_divider;
4678 u32 fbdiv;
4679 int ret;
4680
4681 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4682 engine_clock, false, &dividers);
4683 if (ret)
4684 return ret;
4685
4686 reference_divider = 1 + dividers.ref_div;
4687
4688 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4689 do_div(tmp, reference_clock);
4690 fbdiv = (u32) tmp;
4691
4692 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4693 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4694 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4695
4696 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4697 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4698
4699 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4700 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4701 spll_func_cntl_3 |= SPLL_DITHEN;
4702
4703 if (pi->sclk_ss) {
4704 struct radeon_atom_ss ss;
4705 u32 vco_freq = engine_clock * dividers.post_div;
4706
4707 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4708 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4709 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4710 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4711
4712 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4713 cg_spll_spread_spectrum |= CLK_S(clk_s);
4714 cg_spll_spread_spectrum |= SSEN;
4715
4716 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4717 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4718 }
4719 }
4720
4721 sclk->sclk_value = engine_clock;
4722 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4723 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4724 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4725 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4726 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4727 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4728
4729 return 0;
4730 }
4731
4732 static int si_populate_sclk_value(struct radeon_device *rdev,
4733 u32 engine_clock,
4734 SISLANDS_SMC_SCLK_VALUE *sclk)
4735 {
4736 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4737 int ret;
4738
4739 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4740 if (!ret) {
4741 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4742 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4743 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4744 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4745 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4746 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4747 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4748 }
4749
4750 return ret;
4751 }
4752
4753 static int si_populate_mclk_value(struct radeon_device *rdev,
4754 u32 engine_clock,
4755 u32 memory_clock,
4756 SISLANDS_SMC_MCLK_VALUE *mclk,
4757 bool strobe_mode,
4758 bool dll_state_on)
4759 {
4760 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4761 struct si_power_info *si_pi = si_get_pi(rdev);
4762 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4763 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4764 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4765 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4766 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4767 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4768 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4769 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4770 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4771 struct atom_mpll_param mpll_param;
4772 int ret;
4773
4774 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4775 if (ret)
4776 return ret;
4777
4778 mpll_func_cntl &= ~BWCTRL_MASK;
4779 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4780
4781 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4782 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4783 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4784
4785 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4786 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4787
4788 if (pi->mem_gddr5) {
4789 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4790 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4791 YCLK_POST_DIV(mpll_param.post_div);
4792 }
4793
4794 if (pi->mclk_ss) {
4795 struct radeon_atom_ss ss;
4796 u32 freq_nom;
4797 u32 tmp;
4798 u32 reference_clock = rdev->clock.mpll.reference_freq;
4799
4800 if (pi->mem_gddr5)
4801 freq_nom = memory_clock * 4;
4802 else
4803 freq_nom = memory_clock * 2;
4804
4805 tmp = freq_nom / reference_clock;
4806 tmp = tmp * tmp;
4807 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4808 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4809 u32 clks = reference_clock * 5 / ss.rate;
4810 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4811
4812 mpll_ss1 &= ~CLKV_MASK;
4813 mpll_ss1 |= CLKV(clkv);
4814
4815 mpll_ss2 &= ~CLKS_MASK;
4816 mpll_ss2 |= CLKS(clks);
4817 }
4818 }
4819
4820 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4821 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4822
4823 if (dll_state_on)
4824 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4825 else
4826 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4827
4828 mclk->mclk_value = cpu_to_be32(memory_clock);
4829 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4830 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4831 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4832 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4833 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4834 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4835 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4836 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4837 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4838
4839 return 0;
4840 }
4841
4842 static void si_populate_smc_sp(struct radeon_device *rdev,
4843 struct radeon_ps *radeon_state,
4844 SISLANDS_SMC_SWSTATE *smc_state)
4845 {
4846 struct ni_ps *ps = ni_get_ps(radeon_state);
4847 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4848 int i;
4849
4850 for (i = 0; i < ps->performance_level_count - 1; i++)
4851 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4852
4853 smc_state->levels[ps->performance_level_count - 1].bSP =
4854 cpu_to_be32(pi->psp);
4855 }
4856
4857 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4858 struct rv7xx_pl *pl,
4859 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4860 {
4861 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4862 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4863 struct si_power_info *si_pi = si_get_pi(rdev);
4864 int ret;
4865 bool dll_state_on;
4866 u16 std_vddc;
4867 bool gmc_pg = false;
4868
4869 if (eg_pi->pcie_performance_request &&
4870 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4871 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4872 else
4873 level->gen2PCIE = (u8)pl->pcie_gen;
4874
4875 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4876 if (ret)
4877 return ret;
4878
4879 level->mcFlags = 0;
4880
4881 if (pi->mclk_stutter_mode_threshold &&
4882 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4883 !eg_pi->uvd_enabled &&
4884 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4885 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4886 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4887
4888 if (gmc_pg)
4889 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4890 }
4891
4892 if (pi->mem_gddr5) {
4893 if (pl->mclk > pi->mclk_edc_enable_threshold)
4894 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4895
4896 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4897 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4898
4899 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4900
4901 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4902 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4903 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4904 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4905 else
4906 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4907 } else {
4908 dll_state_on = false;
4909 }
4910 } else {
4911 level->strobeMode = si_get_strobe_mode_settings(rdev,
4912 pl->mclk);
4913
4914 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4915 }
4916
4917 ret = si_populate_mclk_value(rdev,
4918 pl->sclk,
4919 pl->mclk,
4920 &level->mclk,
4921 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4922 if (ret)
4923 return ret;
4924
4925 ret = si_populate_voltage_value(rdev,
4926 &eg_pi->vddc_voltage_table,
4927 pl->vddc, &level->vddc);
4928 if (ret)
4929 return ret;
4930
4931
4932 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4933 if (ret)
4934 return ret;
4935
4936 ret = si_populate_std_voltage_value(rdev, std_vddc,
4937 level->vddc.index, &level->std_vddc);
4938 if (ret)
4939 return ret;
4940
4941 if (eg_pi->vddci_control) {
4942 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4943 pl->vddci, &level->vddci);
4944 if (ret)
4945 return ret;
4946 }
4947
4948 if (si_pi->vddc_phase_shed_control) {
4949 ret = si_populate_phase_shedding_value(rdev,
4950 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4951 pl->vddc,
4952 pl->sclk,
4953 pl->mclk,
4954 &level->vddc);
4955 if (ret)
4956 return ret;
4957 }
4958
4959 level->MaxPoweredUpCU = si_pi->max_cu;
4960
4961 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
4962
4963 return ret;
4964 }
4965
4966 static int si_populate_smc_t(struct radeon_device *rdev,
4967 struct radeon_ps *radeon_state,
4968 SISLANDS_SMC_SWSTATE *smc_state)
4969 {
4970 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4971 struct ni_ps *state = ni_get_ps(radeon_state);
4972 u32 a_t;
4973 u32 t_l, t_h;
4974 u32 high_bsp;
4975 int i, ret;
4976
4977 if (state->performance_level_count >= 9)
4978 return -EINVAL;
4979
4980 if (state->performance_level_count < 2) {
4981 a_t = CG_R(0xffff) | CG_L(0);
4982 smc_state->levels[0].aT = cpu_to_be32(a_t);
4983 return 0;
4984 }
4985
4986 smc_state->levels[0].aT = cpu_to_be32(0);
4987
4988 for (i = 0; i <= state->performance_level_count - 2; i++) {
4989 ret = r600_calculate_at(
4990 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
4991 100 * R600_AH_DFLT,
4992 state->performance_levels[i + 1].sclk,
4993 state->performance_levels[i].sclk,
4994 &t_l,
4995 &t_h);
4996
4997 if (ret) {
4998 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
4999 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5000 }
5001
5002 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5003 a_t |= CG_R(t_l * pi->bsp / 20000);
5004 smc_state->levels[i].aT = cpu_to_be32(a_t);
5005
5006 high_bsp = (i == state->performance_level_count - 2) ?
5007 pi->pbsp : pi->bsp;
5008 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5009 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5010 }
5011
5012 return 0;
5013 }
5014
5015 static int si_disable_ulv(struct radeon_device *rdev)
5016 {
5017 struct si_power_info *si_pi = si_get_pi(rdev);
5018 struct si_ulv_param *ulv = &si_pi->ulv;
5019
5020 if (ulv->supported)
5021 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5022 0 : -EINVAL;
5023
5024 return 0;
5025 }
5026
5027 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5028 struct radeon_ps *radeon_state)
5029 {
5030 const struct si_power_info *si_pi = si_get_pi(rdev);
5031 const struct si_ulv_param *ulv = &si_pi->ulv;
5032 const struct ni_ps *state = ni_get_ps(radeon_state);
5033 int i;
5034
5035 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5036 return false;
5037
5038 /* XXX validate against display requirements! */
5039
5040 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5041 if (rdev->clock.current_dispclk <=
5042 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5043 if (ulv->pl.vddc <
5044 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5045 return false;
5046 }
5047 }
5048
5049 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5050 return false;
5051
5052 return true;
5053 }
5054
5055 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5056 struct radeon_ps *radeon_new_state)
5057 {
5058 const struct si_power_info *si_pi = si_get_pi(rdev);
5059 const struct si_ulv_param *ulv = &si_pi->ulv;
5060
5061 if (ulv->supported) {
5062 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5063 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5064 0 : -EINVAL;
5065 }
5066 return 0;
5067 }
5068
5069 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5070 struct radeon_ps *radeon_state,
5071 SISLANDS_SMC_SWSTATE *smc_state)
5072 {
5073 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5074 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5075 struct si_power_info *si_pi = si_get_pi(rdev);
5076 struct ni_ps *state = ni_get_ps(radeon_state);
5077 int i, ret;
5078 u32 threshold;
5079 u32 sclk_in_sr = 1350; /* ??? */
5080
5081 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5082 return -EINVAL;
5083
5084 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5085
5086 if (radeon_state->vclk && radeon_state->dclk) {
5087 eg_pi->uvd_enabled = true;
5088 if (eg_pi->smu_uvd_hs)
5089 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5090 } else {
5091 eg_pi->uvd_enabled = false;
5092 }
5093
5094 if (state->dc_compatible)
5095 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5096
5097 smc_state->levelCount = 0;
5098 for (i = 0; i < state->performance_level_count; i++) {
5099 if (eg_pi->sclk_deep_sleep) {
5100 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5101 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5102 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5103 else
5104 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5105 }
5106 }
5107
5108 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5109 &smc_state->levels[i]);
5110 smc_state->levels[i].arbRefreshState =
5111 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5112
5113 if (ret)
5114 return ret;
5115
5116 if (ni_pi->enable_power_containment)
5117 smc_state->levels[i].displayWatermark =
5118 (state->performance_levels[i].sclk < threshold) ?
5119 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5120 else
5121 smc_state->levels[i].displayWatermark = (i < 2) ?
5122 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5123
5124 if (eg_pi->dynamic_ac_timing)
5125 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5126 else
5127 smc_state->levels[i].ACIndex = 0;
5128
5129 smc_state->levelCount++;
5130 }
5131
5132 si_write_smc_soft_register(rdev,
5133 SI_SMC_SOFT_REGISTER_watermark_threshold,
5134 threshold / 512);
5135
5136 si_populate_smc_sp(rdev, radeon_state, smc_state);
5137
5138 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5139 if (ret)
5140 ni_pi->enable_power_containment = false;
5141
5142 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5143 if (ret)
5144 ni_pi->enable_sq_ramping = false;
5145
5146 return si_populate_smc_t(rdev, radeon_state, smc_state);
5147 }
5148
5149 static int si_upload_sw_state(struct radeon_device *rdev,
5150 struct radeon_ps *radeon_new_state)
5151 {
5152 struct si_power_info *si_pi = si_get_pi(rdev);
5153 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5154 int ret;
5155 u32 address = si_pi->state_table_start +
5156 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5157 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5158 ((new_state->performance_level_count - 1) *
5159 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5160 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5161
5162 memset(smc_state, 0, state_size);
5163
5164 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5165 if (ret)
5166 return ret;
5167
5168 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5169 state_size, si_pi->sram_end);
5170
5171 return ret;
5172 }
5173
5174 static int si_upload_ulv_state(struct radeon_device *rdev)
5175 {
5176 struct si_power_info *si_pi = si_get_pi(rdev);
5177 struct si_ulv_param *ulv = &si_pi->ulv;
5178 int ret = 0;
5179
5180 if (ulv->supported && ulv->pl.vddc) {
5181 u32 address = si_pi->state_table_start +
5182 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5183 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5184 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5185
5186 memset(smc_state, 0, state_size);
5187
5188 ret = si_populate_ulv_state(rdev, smc_state);
5189 if (!ret)
5190 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5191 state_size, si_pi->sram_end);
5192 }
5193
5194 return ret;
5195 }
5196
5197 static int si_upload_smc_data(struct radeon_device *rdev)
5198 {
5199 struct radeon_crtc *radeon_crtc = NULL;
5200 int i;
5201
5202 if (rdev->pm.dpm.new_active_crtc_count == 0)
5203 return 0;
5204
5205 for (i = 0; i < rdev->num_crtc; i++) {
5206 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5207 radeon_crtc = rdev->mode_info.crtcs[i];
5208 break;
5209 }
5210 }
5211
5212 if (radeon_crtc == NULL)
5213 return 0;
5214
5215 if (radeon_crtc->line_time <= 0)
5216 return 0;
5217
5218 if (si_write_smc_soft_register(rdev,
5219 SI_SMC_SOFT_REGISTER_crtc_index,
5220 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5221 return 0;
5222
5223 if (si_write_smc_soft_register(rdev,
5224 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5225 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5226 return 0;
5227
5228 if (si_write_smc_soft_register(rdev,
5229 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5230 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5231 return 0;
5232
5233 return 0;
5234 }
5235
5236 static int si_set_mc_special_registers(struct radeon_device *rdev,
5237 struct si_mc_reg_table *table)
5238 {
5239 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5240 u8 i, j, k;
5241 u32 temp_reg;
5242
5243 for (i = 0, j = table->last; i < table->last; i++) {
5244 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5245 return -EINVAL;
5246 switch (table->mc_reg_address[i].s1 << 2) {
5247 case MC_SEQ_MISC1:
5248 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5249 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5250 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5251 for (k = 0; k < table->num_entries; k++)
5252 table->mc_reg_table_entry[k].mc_data[j] =
5253 ((temp_reg & 0xffff0000)) |
5254 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5255 j++;
5256 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5257 return -EINVAL;
5258
5259 temp_reg = RREG32(MC_PMG_CMD_MRS);
5260 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5261 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5262 for (k = 0; k < table->num_entries; k++) {
5263 table->mc_reg_table_entry[k].mc_data[j] =
5264 (temp_reg & 0xffff0000) |
5265 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5266 if (!pi->mem_gddr5)
5267 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5268 }
5269 j++;
5270 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5271 return -EINVAL;
5272
5273 if (!pi->mem_gddr5) {
5274 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5275 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5276 for (k = 0; k < table->num_entries; k++)
5277 table->mc_reg_table_entry[k].mc_data[j] =
5278 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5279 j++;
5280 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5281 return -EINVAL;
5282 }
5283 break;
5284 case MC_SEQ_RESERVE_M:
5285 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5286 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5287 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5288 for(k = 0; k < table->num_entries; k++)
5289 table->mc_reg_table_entry[k].mc_data[j] =
5290 (temp_reg & 0xffff0000) |
5291 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5292 j++;
5293 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5294 return -EINVAL;
5295 break;
5296 default:
5297 break;
5298 }
5299 }
5300
5301 table->last = j;
5302
5303 return 0;
5304 }
5305
5306 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5307 {
5308 bool result = true;
5309
5310 switch (in_reg) {
5311 case MC_SEQ_RAS_TIMING >> 2:
5312 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5313 break;
5314 case MC_SEQ_CAS_TIMING >> 2:
5315 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5316 break;
5317 case MC_SEQ_MISC_TIMING >> 2:
5318 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5319 break;
5320 case MC_SEQ_MISC_TIMING2 >> 2:
5321 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5322 break;
5323 case MC_SEQ_RD_CTL_D0 >> 2:
5324 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5325 break;
5326 case MC_SEQ_RD_CTL_D1 >> 2:
5327 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5328 break;
5329 case MC_SEQ_WR_CTL_D0 >> 2:
5330 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5331 break;
5332 case MC_SEQ_WR_CTL_D1 >> 2:
5333 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5334 break;
5335 case MC_PMG_CMD_EMRS >> 2:
5336 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5337 break;
5338 case MC_PMG_CMD_MRS >> 2:
5339 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5340 break;
5341 case MC_PMG_CMD_MRS1 >> 2:
5342 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5343 break;
5344 case MC_SEQ_PMG_TIMING >> 2:
5345 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5346 break;
5347 case MC_PMG_CMD_MRS2 >> 2:
5348 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5349 break;
5350 case MC_SEQ_WR_CTL_2 >> 2:
5351 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5352 break;
5353 default:
5354 result = false;
5355 break;
5356 }
5357
5358 return result;
5359 }
5360
5361 static void si_set_valid_flag(struct si_mc_reg_table *table)
5362 {
5363 u8 i, j;
5364
5365 for (i = 0; i < table->last; i++) {
5366 for (j = 1; j < table->num_entries; j++) {
5367 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5368 table->valid_flag |= 1 << i;
5369 break;
5370 }
5371 }
5372 }
5373 }
5374
5375 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5376 {
5377 u32 i;
5378 u16 address;
5379
5380 for (i = 0; i < table->last; i++)
5381 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5382 address : table->mc_reg_address[i].s1;
5383
5384 }
5385
5386 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5387 struct si_mc_reg_table *si_table)
5388 {
5389 u8 i, j;
5390
5391 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5392 return -EINVAL;
5393 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5394 return -EINVAL;
5395
5396 for (i = 0; i < table->last; i++)
5397 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5398 si_table->last = table->last;
5399
5400 for (i = 0; i < table->num_entries; i++) {
5401 si_table->mc_reg_table_entry[i].mclk_max =
5402 table->mc_reg_table_entry[i].mclk_max;
5403 for (j = 0; j < table->last; j++) {
5404 si_table->mc_reg_table_entry[i].mc_data[j] =
5405 table->mc_reg_table_entry[i].mc_data[j];
5406 }
5407 }
5408 si_table->num_entries = table->num_entries;
5409
5410 return 0;
5411 }
5412
5413 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5414 {
5415 struct si_power_info *si_pi = si_get_pi(rdev);
5416 struct atom_mc_reg_table *table;
5417 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5418 u8 module_index = rv770_get_memory_module_index(rdev);
5419 int ret;
5420
5421 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5422 if (!table)
5423 return -ENOMEM;
5424
5425 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5426 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5427 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5428 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5429 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5430 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5431 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5432 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5433 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5434 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5435 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5436 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5437 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5438 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5439
5440 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5441 if (ret)
5442 goto init_mc_done;
5443
5444 ret = si_copy_vbios_mc_reg_table(table, si_table);
5445 if (ret)
5446 goto init_mc_done;
5447
5448 si_set_s0_mc_reg_index(si_table);
5449
5450 ret = si_set_mc_special_registers(rdev, si_table);
5451 if (ret)
5452 goto init_mc_done;
5453
5454 si_set_valid_flag(si_table);
5455
5456 init_mc_done:
5457 kfree(table);
5458
5459 return ret;
5460
5461 }
5462
5463 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5464 SMC_SIslands_MCRegisters *mc_reg_table)
5465 {
5466 struct si_power_info *si_pi = si_get_pi(rdev);
5467 u32 i, j;
5468
5469 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5470 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5471 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5472 break;
5473 mc_reg_table->address[i].s0 =
5474 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5475 mc_reg_table->address[i].s1 =
5476 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5477 i++;
5478 }
5479 }
5480 mc_reg_table->last = (u8)i;
5481 }
5482
5483 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5484 SMC_SIslands_MCRegisterSet *data,
5485 u32 num_entries, u32 valid_flag)
5486 {
5487 u32 i, j;
5488
5489 for(i = 0, j = 0; j < num_entries; j++) {
5490 if (valid_flag & (1 << j)) {
5491 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5492 i++;
5493 }
5494 }
5495 }
5496
5497 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5498 struct rv7xx_pl *pl,
5499 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5500 {
5501 struct si_power_info *si_pi = si_get_pi(rdev);
5502 u32 i = 0;
5503
5504 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5505 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5506 break;
5507 }
5508
5509 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5510 --i;
5511
5512 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5513 mc_reg_table_data, si_pi->mc_reg_table.last,
5514 si_pi->mc_reg_table.valid_flag);
5515 }
5516
5517 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5518 struct radeon_ps *radeon_state,
5519 SMC_SIslands_MCRegisters *mc_reg_table)
5520 {
5521 struct ni_ps *state = ni_get_ps(radeon_state);
5522 int i;
5523
5524 for (i = 0; i < state->performance_level_count; i++) {
5525 si_convert_mc_reg_table_entry_to_smc(rdev,
5526 &state->performance_levels[i],
5527 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5528 }
5529 }
5530
5531 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5532 struct radeon_ps *radeon_boot_state)
5533 {
5534 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5535 struct si_power_info *si_pi = si_get_pi(rdev);
5536 struct si_ulv_param *ulv = &si_pi->ulv;
5537 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5538
5539 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5540
5541 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5542
5543 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5544
5545 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5546 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5547
5548 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5549 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5550 si_pi->mc_reg_table.last,
5551 si_pi->mc_reg_table.valid_flag);
5552
5553 if (ulv->supported && ulv->pl.vddc != 0)
5554 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5555 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5556 else
5557 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5558 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5559 si_pi->mc_reg_table.last,
5560 si_pi->mc_reg_table.valid_flag);
5561
5562 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5563
5564 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5565 (u8 *)smc_mc_reg_table,
5566 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5567 }
5568
5569 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5570 struct radeon_ps *radeon_new_state)
5571 {
5572 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5573 struct si_power_info *si_pi = si_get_pi(rdev);
5574 u32 address = si_pi->mc_reg_table_start +
5575 offsetof(SMC_SIslands_MCRegisters,
5576 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5577 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5578
5579 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5580
5581 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5582
5583
5584 return si_copy_bytes_to_smc(rdev, address,
5585 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5586 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5587 si_pi->sram_end);
5588
5589 }
5590
5591 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5592 {
5593 if (enable)
5594 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5595 else
5596 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5597 }
5598
5599 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5600 struct radeon_ps *radeon_state)
5601 {
5602 struct ni_ps *state = ni_get_ps(radeon_state);
5603 int i;
5604 u16 pcie_speed, max_speed = 0;
5605
5606 for (i = 0; i < state->performance_level_count; i++) {
5607 pcie_speed = state->performance_levels[i].pcie_gen;
5608 if (max_speed < pcie_speed)
5609 max_speed = pcie_speed;
5610 }
5611 return max_speed;
5612 }
5613
5614 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5615 {
5616 u32 speed_cntl;
5617
5618 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5619 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5620
5621 return (u16)speed_cntl;
5622 }
5623
5624 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5625 struct radeon_ps *radeon_new_state,
5626 struct radeon_ps *radeon_current_state)
5627 {
5628 struct si_power_info *si_pi = si_get_pi(rdev);
5629 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5630 enum radeon_pcie_gen current_link_speed;
5631
5632 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5633 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5634 else
5635 current_link_speed = si_pi->force_pcie_gen;
5636
5637 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5638 si_pi->pspp_notify_required = false;
5639 if (target_link_speed > current_link_speed) {
5640 switch (target_link_speed) {
5641 #if defined(CONFIG_ACPI)
5642 case RADEON_PCIE_GEN3:
5643 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5644 break;
5645 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5646 if (current_link_speed == RADEON_PCIE_GEN2)
5647 break;
5648 case RADEON_PCIE_GEN2:
5649 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5650 break;
5651 #endif
5652 default:
5653 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5654 break;
5655 }
5656 } else {
5657 if (target_link_speed < current_link_speed)
5658 si_pi->pspp_notify_required = true;
5659 }
5660 }
5661
5662 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5663 struct radeon_ps *radeon_new_state,
5664 struct radeon_ps *radeon_current_state)
5665 {
5666 struct si_power_info *si_pi = si_get_pi(rdev);
5667 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5668 u8 request;
5669
5670 if (si_pi->pspp_notify_required) {
5671 if (target_link_speed == RADEON_PCIE_GEN3)
5672 request = PCIE_PERF_REQ_PECI_GEN3;
5673 else if (target_link_speed == RADEON_PCIE_GEN2)
5674 request = PCIE_PERF_REQ_PECI_GEN2;
5675 else
5676 request = PCIE_PERF_REQ_PECI_GEN1;
5677
5678 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5679 (si_get_current_pcie_speed(rdev) > 0))
5680 return;
5681
5682 #if defined(CONFIG_ACPI)
5683 radeon_acpi_pcie_performance_request(rdev, request, false);
5684 #endif
5685 }
5686 }
5687
5688 #if 0
5689 static int si_ds_request(struct radeon_device *rdev,
5690 bool ds_status_on, u32 count_write)
5691 {
5692 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5693
5694 if (eg_pi->sclk_deep_sleep) {
5695 if (ds_status_on)
5696 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5697 PPSMC_Result_OK) ?
5698 0 : -EINVAL;
5699 else
5700 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5701 PPSMC_Result_OK) ? 0 : -EINVAL;
5702 }
5703 return 0;
5704 }
5705 #endif
5706
5707 static void si_set_max_cu_value(struct radeon_device *rdev)
5708 {
5709 struct si_power_info *si_pi = si_get_pi(rdev);
5710
5711 if (rdev->family == CHIP_VERDE) {
5712 switch (rdev->pdev->device) {
5713 case 0x6820:
5714 case 0x6825:
5715 case 0x6821:
5716 case 0x6823:
5717 case 0x6827:
5718 si_pi->max_cu = 10;
5719 break;
5720 case 0x682D:
5721 case 0x6824:
5722 case 0x682F:
5723 case 0x6826:
5724 si_pi->max_cu = 8;
5725 break;
5726 case 0x6828:
5727 case 0x6830:
5728 case 0x6831:
5729 case 0x6838:
5730 case 0x6839:
5731 case 0x683D:
5732 si_pi->max_cu = 10;
5733 break;
5734 case 0x683B:
5735 case 0x683F:
5736 case 0x6829:
5737 si_pi->max_cu = 8;
5738 break;
5739 default:
5740 si_pi->max_cu = 0;
5741 break;
5742 }
5743 } else {
5744 si_pi->max_cu = 0;
5745 }
5746 }
5747
5748 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5749 struct radeon_clock_voltage_dependency_table *table)
5750 {
5751 u32 i;
5752 int j;
5753 u16 leakage_voltage;
5754
5755 if (table) {
5756 for (i = 0; i < table->count; i++) {
5757 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5758 table->entries[i].v,
5759 &leakage_voltage)) {
5760 case 0:
5761 table->entries[i].v = leakage_voltage;
5762 break;
5763 case -EAGAIN:
5764 return -EINVAL;
5765 case -EINVAL:
5766 default:
5767 break;
5768 }
5769 }
5770
5771 for (j = (table->count - 2); j >= 0; j--) {
5772 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5773 table->entries[j].v : table->entries[j + 1].v;
5774 }
5775 }
5776 return 0;
5777 }
5778
5779 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5780 {
5781 int ret = 0;
5782
5783 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5784 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5785 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5786 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5787 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5788 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5789 return ret;
5790 }
5791
5792 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5793 struct radeon_ps *radeon_new_state,
5794 struct radeon_ps *radeon_current_state)
5795 {
5796 u32 lane_width;
5797 u32 new_lane_width =
5798 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5799 u32 current_lane_width =
5800 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5801
5802 if (new_lane_width != current_lane_width) {
5803 radeon_set_pcie_lanes(rdev, new_lane_width);
5804 lane_width = radeon_get_pcie_lanes(rdev);
5805 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5806 }
5807 }
5808
5809 void si_dpm_setup_asic(struct radeon_device *rdev)
5810 {
5811 int r;
5812
5813 r = si_mc_load_microcode(rdev);
5814 if (r)
5815 DRM_ERROR("Failed to load MC firmware!\n");
5816 rv770_get_memory_type(rdev);
5817 si_read_clock_registers(rdev);
5818 si_enable_acpi_power_management(rdev);
5819 }
5820
5821 static int si_set_thermal_temperature_range(struct radeon_device *rdev,
5822 int min_temp, int max_temp)
5823 {
5824 int low_temp = 0 * 1000;
5825 int high_temp = 255 * 1000;
5826
5827 if (low_temp < min_temp)
5828 low_temp = min_temp;
5829 if (high_temp > max_temp)
5830 high_temp = max_temp;
5831 if (high_temp < low_temp) {
5832 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5833 return -EINVAL;
5834 }
5835
5836 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5837 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5838 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5839
5840 rdev->pm.dpm.thermal.min_temp = low_temp;
5841 rdev->pm.dpm.thermal.max_temp = high_temp;
5842
5843 return 0;
5844 }
5845
5846 int si_dpm_enable(struct radeon_device *rdev)
5847 {
5848 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5849 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5850 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5851 int ret;
5852
5853 if (si_is_smc_running(rdev))
5854 return -EINVAL;
5855 if (pi->voltage_control)
5856 si_enable_voltage_control(rdev, true);
5857 if (pi->mvdd_control)
5858 si_get_mvdd_configuration(rdev);
5859 if (pi->voltage_control) {
5860 ret = si_construct_voltage_tables(rdev);
5861 if (ret) {
5862 DRM_ERROR("si_construct_voltage_tables failed\n");
5863 return ret;
5864 }
5865 }
5866 if (eg_pi->dynamic_ac_timing) {
5867 ret = si_initialize_mc_reg_table(rdev);
5868 if (ret)
5869 eg_pi->dynamic_ac_timing = false;
5870 }
5871 if (pi->dynamic_ss)
5872 si_enable_spread_spectrum(rdev, true);
5873 if (pi->thermal_protection)
5874 si_enable_thermal_protection(rdev, true);
5875 si_setup_bsp(rdev);
5876 si_program_git(rdev);
5877 si_program_tp(rdev);
5878 si_program_tpp(rdev);
5879 si_program_sstp(rdev);
5880 si_enable_display_gap(rdev);
5881 si_program_vc(rdev);
5882 ret = si_upload_firmware(rdev);
5883 if (ret) {
5884 DRM_ERROR("si_upload_firmware failed\n");
5885 return ret;
5886 }
5887 ret = si_process_firmware_header(rdev);
5888 if (ret) {
5889 DRM_ERROR("si_process_firmware_header failed\n");
5890 return ret;
5891 }
5892 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
5893 if (ret) {
5894 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
5895 return ret;
5896 }
5897 ret = si_init_smc_table(rdev);
5898 if (ret) {
5899 DRM_ERROR("si_init_smc_table failed\n");
5900 return ret;
5901 }
5902 ret = si_init_smc_spll_table(rdev);
5903 if (ret) {
5904 DRM_ERROR("si_init_smc_spll_table failed\n");
5905 return ret;
5906 }
5907 ret = si_init_arb_table_index(rdev);
5908 if (ret) {
5909 DRM_ERROR("si_init_arb_table_index failed\n");
5910 return ret;
5911 }
5912 if (eg_pi->dynamic_ac_timing) {
5913 ret = si_populate_mc_reg_table(rdev, boot_ps);
5914 if (ret) {
5915 DRM_ERROR("si_populate_mc_reg_table failed\n");
5916 return ret;
5917 }
5918 }
5919 ret = si_initialize_smc_cac_tables(rdev);
5920 if (ret) {
5921 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
5922 return ret;
5923 }
5924 ret = si_initialize_hardware_cac_manager(rdev);
5925 if (ret) {
5926 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
5927 return ret;
5928 }
5929 ret = si_initialize_smc_dte_tables(rdev);
5930 if (ret) {
5931 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
5932 return ret;
5933 }
5934 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
5935 if (ret) {
5936 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
5937 return ret;
5938 }
5939 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
5940 if (ret) {
5941 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
5942 return ret;
5943 }
5944 si_program_response_times(rdev);
5945 si_program_ds_registers(rdev);
5946 si_dpm_start_smc(rdev);
5947 ret = si_notify_smc_display_change(rdev, false);
5948 if (ret) {
5949 DRM_ERROR("si_notify_smc_display_change failed\n");
5950 return ret;
5951 }
5952 si_enable_sclk_control(rdev, true);
5953 si_start_dpm(rdev);
5954
5955 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5956
5957 ni_update_current_ps(rdev, boot_ps);
5958
5959 return 0;
5960 }
5961
5962 int si_dpm_late_enable(struct radeon_device *rdev)
5963 {
5964 int ret;
5965
5966 if (rdev->irq.installed &&
5967 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
5968 PPSMC_Result result;
5969
5970 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5971 if (ret)
5972 return ret;
5973 rdev->irq.dpm_thermal = true;
5974 radeon_irq_set(rdev);
5975 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5976
5977 if (result != PPSMC_Result_OK)
5978 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5979 }
5980
5981 return 0;
5982 }
5983
5984 void si_dpm_disable(struct radeon_device *rdev)
5985 {
5986 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5987 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5988
5989 if (!si_is_smc_running(rdev))
5990 return;
5991 si_disable_ulv(rdev);
5992 si_clear_vc(rdev);
5993 if (pi->thermal_protection)
5994 si_enable_thermal_protection(rdev, false);
5995 si_enable_power_containment(rdev, boot_ps, false);
5996 si_enable_smc_cac(rdev, boot_ps, false);
5997 si_enable_spread_spectrum(rdev, false);
5998 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5999 si_stop_dpm(rdev);
6000 si_reset_to_default(rdev);
6001 si_dpm_stop_smc(rdev);
6002 si_force_switch_to_arb_f0(rdev);
6003
6004 ni_update_current_ps(rdev, boot_ps);
6005 }
6006
6007 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6008 {
6009 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6010 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6011 struct radeon_ps *new_ps = &requested_ps;
6012
6013 ni_update_requested_ps(rdev, new_ps);
6014
6015 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6016
6017 return 0;
6018 }
6019
6020 static int si_power_control_set_level(struct radeon_device *rdev)
6021 {
6022 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6023 int ret;
6024
6025 ret = si_restrict_performance_levels_before_switch(rdev);
6026 if (ret)
6027 return ret;
6028 ret = si_halt_smc(rdev);
6029 if (ret)
6030 return ret;
6031 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6032 if (ret)
6033 return ret;
6034 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6035 if (ret)
6036 return ret;
6037 ret = si_resume_smc(rdev);
6038 if (ret)
6039 return ret;
6040 ret = si_set_sw_state(rdev);
6041 if (ret)
6042 return ret;
6043 return 0;
6044 }
6045
6046 int si_dpm_set_power_state(struct radeon_device *rdev)
6047 {
6048 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6049 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6050 struct radeon_ps *old_ps = &eg_pi->current_rps;
6051 int ret;
6052
6053 ret = si_disable_ulv(rdev);
6054 if (ret) {
6055 DRM_ERROR("si_disable_ulv failed\n");
6056 return ret;
6057 }
6058 ret = si_restrict_performance_levels_before_switch(rdev);
6059 if (ret) {
6060 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6061 return ret;
6062 }
6063 if (eg_pi->pcie_performance_request)
6064 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6065 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6066 ret = si_enable_power_containment(rdev, new_ps, false);
6067 if (ret) {
6068 DRM_ERROR("si_enable_power_containment failed\n");
6069 return ret;
6070 }
6071 ret = si_enable_smc_cac(rdev, new_ps, false);
6072 if (ret) {
6073 DRM_ERROR("si_enable_smc_cac failed\n");
6074 return ret;
6075 }
6076 ret = si_halt_smc(rdev);
6077 if (ret) {
6078 DRM_ERROR("si_halt_smc failed\n");
6079 return ret;
6080 }
6081 ret = si_upload_sw_state(rdev, new_ps);
6082 if (ret) {
6083 DRM_ERROR("si_upload_sw_state failed\n");
6084 return ret;
6085 }
6086 ret = si_upload_smc_data(rdev);
6087 if (ret) {
6088 DRM_ERROR("si_upload_smc_data failed\n");
6089 return ret;
6090 }
6091 ret = si_upload_ulv_state(rdev);
6092 if (ret) {
6093 DRM_ERROR("si_upload_ulv_state failed\n");
6094 return ret;
6095 }
6096 if (eg_pi->dynamic_ac_timing) {
6097 ret = si_upload_mc_reg_table(rdev, new_ps);
6098 if (ret) {
6099 DRM_ERROR("si_upload_mc_reg_table failed\n");
6100 return ret;
6101 }
6102 }
6103 ret = si_program_memory_timing_parameters(rdev, new_ps);
6104 if (ret) {
6105 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6106 return ret;
6107 }
6108 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6109
6110 ret = si_resume_smc(rdev);
6111 if (ret) {
6112 DRM_ERROR("si_resume_smc failed\n");
6113 return ret;
6114 }
6115 ret = si_set_sw_state(rdev);
6116 if (ret) {
6117 DRM_ERROR("si_set_sw_state failed\n");
6118 return ret;
6119 }
6120 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6121 if (eg_pi->pcie_performance_request)
6122 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6123 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6124 if (ret) {
6125 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6126 return ret;
6127 }
6128 ret = si_enable_smc_cac(rdev, new_ps, true);
6129 if (ret) {
6130 DRM_ERROR("si_enable_smc_cac failed\n");
6131 return ret;
6132 }
6133 ret = si_enable_power_containment(rdev, new_ps, true);
6134 if (ret) {
6135 DRM_ERROR("si_enable_power_containment failed\n");
6136 return ret;
6137 }
6138
6139 ret = si_power_control_set_level(rdev);
6140 if (ret) {
6141 DRM_ERROR("si_power_control_set_level failed\n");
6142 return ret;
6143 }
6144
6145 return 0;
6146 }
6147
6148 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6149 {
6150 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6151 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6152
6153 ni_update_current_ps(rdev, new_ps);
6154 }
6155
6156
6157 void si_dpm_reset_asic(struct radeon_device *rdev)
6158 {
6159 si_restrict_performance_levels_before_switch(rdev);
6160 si_disable_ulv(rdev);
6161 si_set_boot_state(rdev);
6162 }
6163
6164 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6165 {
6166 si_program_display_gap(rdev);
6167 }
6168
6169 union power_info {
6170 struct _ATOM_POWERPLAY_INFO info;
6171 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6172 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6173 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6174 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6175 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6176 };
6177
6178 union pplib_clock_info {
6179 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6180 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6181 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6182 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6183 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6184 };
6185
6186 union pplib_power_state {
6187 struct _ATOM_PPLIB_STATE v1;
6188 struct _ATOM_PPLIB_STATE_V2 v2;
6189 };
6190
6191 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6192 struct radeon_ps *rps,
6193 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6194 u8 table_rev)
6195 {
6196 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6197 rps->class = le16_to_cpu(non_clock_info->usClassification);
6198 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6199
6200 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6201 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6202 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6203 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6204 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6205 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6206 } else {
6207 rps->vclk = 0;
6208 rps->dclk = 0;
6209 }
6210
6211 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6212 rdev->pm.dpm.boot_ps = rps;
6213 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6214 rdev->pm.dpm.uvd_ps = rps;
6215 }
6216
6217 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6218 struct radeon_ps *rps, int index,
6219 union pplib_clock_info *clock_info)
6220 {
6221 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6222 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6223 struct si_power_info *si_pi = si_get_pi(rdev);
6224 struct ni_ps *ps = ni_get_ps(rps);
6225 u16 leakage_voltage;
6226 struct rv7xx_pl *pl = &ps->performance_levels[index];
6227 int ret;
6228
6229 ps->performance_level_count = index + 1;
6230
6231 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6232 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6233 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6234 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6235
6236 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6237 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6238 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6239 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6240 si_pi->sys_pcie_mask,
6241 si_pi->boot_pcie_gen,
6242 clock_info->si.ucPCIEGen);
6243
6244 /* patch up vddc if necessary */
6245 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6246 &leakage_voltage);
6247 if (ret == 0)
6248 pl->vddc = leakage_voltage;
6249
6250 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6251 pi->acpi_vddc = pl->vddc;
6252 eg_pi->acpi_vddci = pl->vddci;
6253 si_pi->acpi_pcie_gen = pl->pcie_gen;
6254 }
6255
6256 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6257 index == 0) {
6258 /* XXX disable for A0 tahiti */
6259 si_pi->ulv.supported = false;
6260 si_pi->ulv.pl = *pl;
6261 si_pi->ulv.one_pcie_lane_in_ulv = false;
6262 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6263 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6264 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6265 }
6266
6267 if (pi->min_vddc_in_table > pl->vddc)
6268 pi->min_vddc_in_table = pl->vddc;
6269
6270 if (pi->max_vddc_in_table < pl->vddc)
6271 pi->max_vddc_in_table = pl->vddc;
6272
6273 /* patch up boot state */
6274 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6275 u16 vddc, vddci, mvdd;
6276 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6277 pl->mclk = rdev->clock.default_mclk;
6278 pl->sclk = rdev->clock.default_sclk;
6279 pl->vddc = vddc;
6280 pl->vddci = vddci;
6281 si_pi->mvdd_bootup_value = mvdd;
6282 }
6283
6284 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6285 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6286 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6287 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6288 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6289 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6290 }
6291 }
6292
6293 static int si_parse_power_table(struct radeon_device *rdev)
6294 {
6295 struct radeon_mode_info *mode_info = &rdev->mode_info;
6296 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6297 union pplib_power_state *power_state;
6298 int i, j, k, non_clock_array_index, clock_array_index;
6299 union pplib_clock_info *clock_info;
6300 struct _StateArray *state_array;
6301 struct _ClockInfoArray *clock_info_array;
6302 struct _NonClockInfoArray *non_clock_info_array;
6303 union power_info *power_info;
6304 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6305 u16 data_offset;
6306 u8 frev, crev;
6307 u8 *power_state_offset;
6308 struct ni_ps *ps;
6309
6310 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6311 &frev, &crev, &data_offset))
6312 return -EINVAL;
6313 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6314
6315 state_array = (struct _StateArray *)
6316 (mode_info->atom_context->bios + data_offset +
6317 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6318 clock_info_array = (struct _ClockInfoArray *)
6319 (mode_info->atom_context->bios + data_offset +
6320 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6321 non_clock_info_array = (struct _NonClockInfoArray *)
6322 (mode_info->atom_context->bios + data_offset +
6323 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6324
6325 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6326 state_array->ucNumEntries, GFP_KERNEL);
6327 if (!rdev->pm.dpm.ps)
6328 return -ENOMEM;
6329 power_state_offset = (u8 *)state_array->states;
6330 for (i = 0; i < state_array->ucNumEntries; i++) {
6331 u8 *idx;
6332 power_state = (union pplib_power_state *)power_state_offset;
6333 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6334 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6335 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6336 if (!rdev->pm.power_state[i].clock_info)
6337 return -EINVAL;
6338 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6339 if (ps == NULL) {
6340 kfree(rdev->pm.dpm.ps);
6341 return -ENOMEM;
6342 }
6343 rdev->pm.dpm.ps[i].ps_priv = ps;
6344 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6345 non_clock_info,
6346 non_clock_info_array->ucEntrySize);
6347 k = 0;
6348 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6349 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6350 clock_array_index = idx[j];
6351 if (clock_array_index >= clock_info_array->ucNumEntries)
6352 continue;
6353 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6354 break;
6355 clock_info = (union pplib_clock_info *)
6356 ((u8 *)&clock_info_array->clockInfo[0] +
6357 (clock_array_index * clock_info_array->ucEntrySize));
6358 si_parse_pplib_clock_info(rdev,
6359 &rdev->pm.dpm.ps[i], k,
6360 clock_info);
6361 k++;
6362 }
6363 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6364 }
6365 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6366 return 0;
6367 }
6368
6369 int si_dpm_init(struct radeon_device *rdev)
6370 {
6371 struct rv7xx_power_info *pi;
6372 struct evergreen_power_info *eg_pi;
6373 struct ni_power_info *ni_pi;
6374 struct si_power_info *si_pi;
6375 struct atom_clock_dividers dividers;
6376 int ret;
6377 u32 mask;
6378
6379 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6380 if (si_pi == NULL)
6381 return -ENOMEM;
6382 rdev->pm.dpm.priv = si_pi;
6383 ni_pi = &si_pi->ni;
6384 eg_pi = &ni_pi->eg;
6385 pi = &eg_pi->rv7xx;
6386
6387 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6388 if (ret)
6389 si_pi->sys_pcie_mask = 0;
6390 else
6391 si_pi->sys_pcie_mask = mask;
6392 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6393 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6394
6395 si_set_max_cu_value(rdev);
6396
6397 rv770_get_max_vddc(rdev);
6398 si_get_leakage_vddc(rdev);
6399 si_patch_dependency_tables_based_on_leakage(rdev);
6400
6401 pi->acpi_vddc = 0;
6402 eg_pi->acpi_vddci = 0;
6403 pi->min_vddc_in_table = 0;
6404 pi->max_vddc_in_table = 0;
6405
6406 ret = r600_get_platform_caps(rdev);
6407 if (ret)
6408 return ret;
6409
6410 ret = si_parse_power_table(rdev);
6411 if (ret)
6412 return ret;
6413 ret = r600_parse_extended_power_table(rdev);
6414 if (ret)
6415 return ret;
6416
6417 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6418 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6419 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6420 r600_free_extended_power_table(rdev);
6421 return -ENOMEM;
6422 }
6423 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6424 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6425 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6426 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6427 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6428 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6429 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6430 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6431 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6432
6433 if (rdev->pm.dpm.voltage_response_time == 0)
6434 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6435 if (rdev->pm.dpm.backbias_response_time == 0)
6436 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6437
6438 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6439 0, false, &dividers);
6440 if (ret)
6441 pi->ref_div = dividers.ref_div + 1;
6442 else
6443 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6444
6445 eg_pi->smu_uvd_hs = false;
6446
6447 pi->mclk_strobe_mode_threshold = 40000;
6448 if (si_is_special_1gb_platform(rdev))
6449 pi->mclk_stutter_mode_threshold = 0;
6450 else
6451 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6452 pi->mclk_edc_enable_threshold = 40000;
6453 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6454
6455 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6456
6457 pi->voltage_control =
6458 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT);
6459
6460 pi->mvdd_control =
6461 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT);
6462
6463 eg_pi->vddci_control =
6464 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT);
6465
6466 si_pi->vddc_phase_shed_control =
6467 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6468
6469 rv770_get_engine_memory_ss(rdev);
6470
6471 pi->asi = RV770_ASI_DFLT;
6472 pi->pasi = CYPRESS_HASI_DFLT;
6473 pi->vrc = SISLANDS_VRC_DFLT;
6474
6475 pi->gfx_clock_gating = true;
6476
6477 eg_pi->sclk_deep_sleep = true;
6478 si_pi->sclk_deep_sleep_above_low = false;
6479
6480 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6481 pi->thermal_protection = true;
6482 else
6483 pi->thermal_protection = false;
6484
6485 eg_pi->dynamic_ac_timing = true;
6486
6487 eg_pi->light_sleep = true;
6488 #if defined(CONFIG_ACPI)
6489 eg_pi->pcie_performance_request =
6490 radeon_acpi_is_pcie_performance_request_supported(rdev);
6491 #else
6492 eg_pi->pcie_performance_request = false;
6493 #endif
6494
6495 si_pi->sram_end = SMC_RAM_END;
6496
6497 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6498 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6499 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6500 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6501 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6502 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6503 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6504
6505 si_initialize_powertune_defaults(rdev);
6506
6507 /* make sure dc limits are valid */
6508 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6509 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6510 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6511 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6512
6513 return 0;
6514 }
6515
6516 void si_dpm_fini(struct radeon_device *rdev)
6517 {
6518 int i;
6519
6520 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6521 kfree(rdev->pm.dpm.ps[i].ps_priv);
6522 }
6523 kfree(rdev->pm.dpm.ps);
6524 kfree(rdev->pm.dpm.priv);
6525 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6526 r600_free_extended_power_table(rdev);
6527 }
6528
6529 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6530 struct seq_file *m)
6531 {
6532 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6533 struct radeon_ps *rps = &eg_pi->current_rps;
6534 struct ni_ps *ps = ni_get_ps(rps);
6535 struct rv7xx_pl *pl;
6536 u32 current_index =
6537 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6538 CURRENT_STATE_INDEX_SHIFT;
6539
6540 if (current_index >= ps->performance_level_count) {
6541 seq_printf(m, "invalid dpm profile %d\n", current_index);
6542 } else {
6543 pl = &ps->performance_levels[current_index];
6544 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6545 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6546 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6547 }
6548 }
Linux with added FPC-III support