| blob | b4c7db434654ebbcdb82e2375f70e2d7e406b3ec |
1 /*
2 * Low-level exception handling code
3 *
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
29 #include <asm/esr.h>
30 #include <asm/irq.h>
31 #include <asm/memory.h>
32 #include <asm/thread_info.h>
33 #include <asm/asm-uaccess.h>
34 #include <asm/unistd.h>
36 /*
37 * Context tracking subsystem. Used to instrument transitions
38 * between user and kernel mode.
39 */
40 .macro ct_user_exit, syscall = 0
41 #ifdef CONFIG_CONTEXT_TRACKING
42 bl context_tracking_user_exit
43 .if \syscall == 1
44 /*
45 * Save/restore needed during syscalls. Restore syscall arguments from
46 * the values already saved on stack during kernel_entry.
47 */
48 ldp x0, x1, [sp]
49 ldp x2, x3, [sp, #S_X2]
50 ldp x4, x5, [sp, #S_X4]
51 ldp x6, x7, [sp, #S_X6]
52 .endif
53 #endif
54 .endm
56 .macro ct_user_enter
57 #ifdef CONFIG_CONTEXT_TRACKING
58 bl context_tracking_user_enter
59 #endif
60 .endm
62 /*
63 * Bad Abort numbers
64 *-----------------
65 */
66 #define BAD_SYNC 0
67 #define BAD_IRQ 1
68 #define BAD_FIQ 2
69 #define BAD_ERROR 3
71 .macro kernel_entry, el, regsize = 64
72 sub sp, sp, #S_FRAME_SIZE
73 .if \regsize == 32
74 mov w0, w0 // zero upper 32 bits of x0
75 .endif
76 stp x0, x1, [sp, #16 * 0]
77 stp x2, x3, [sp, #16 * 1]
78 stp x4, x5, [sp, #16 * 2]
79 stp x6, x7, [sp, #16 * 3]
80 stp x8, x9, [sp, #16 * 4]
81 stp x10, x11, [sp, #16 * 5]
82 stp x12, x13, [sp, #16 * 6]
83 stp x14, x15, [sp, #16 * 7]
84 stp x16, x17, [sp, #16 * 8]
85 stp x18, x19, [sp, #16 * 9]
86 stp x20, x21, [sp, #16 * 10]
87 stp x22, x23, [sp, #16 * 11]
88 stp x24, x25, [sp, #16 * 12]
89 stp x26, x27, [sp, #16 * 13]
90 stp x28, x29, [sp, #16 * 14]
92 .if \el == 0
93 mrs x21, sp_el0
94 mov tsk, sp
95 and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear,
96 ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug
97 disable_step_tsk x19, x20 // exceptions when scheduling.
99 mov x29, xzr // fp pointed to user-space
100 .else
101 add x21, sp, #S_FRAME_SIZE
102 get_thread_info tsk
103 /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */
104 ldr x20, [tsk, #TI_ADDR_LIMIT]
105 str x20, [sp, #S_ORIG_ADDR_LIMIT]
106 mov x20, #TASK_SIZE_64
107 str x20, [tsk, #TI_ADDR_LIMIT]
108 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
109 .endif /* \el == 0 */
110 mrs x22, elr_el1
111 mrs x23, spsr_el1
112 stp lr, x21, [sp, #S_LR]
113 stp x22, x23, [sp, #S_PC]
115 /*
116 * Set syscallno to -1 by default (overridden later if real syscall).
117 */
118 .if \el == 0
119 mvn x21, xzr
120 str x21, [sp, #S_SYSCALLNO]
121 .endif
123 /*
124 * Set sp_el0 to current thread_info.
125 */
126 .if \el == 0
127 msr sp_el0, tsk
128 .endif
130 /*
131 * Registers that may be useful after this macro is invoked:
132 *
133 * x21 - aborted SP
134 * x22 - aborted PC
135 * x23 - aborted PSTATE
136 */
137 .endm
139 .macro kernel_exit, el
140 .if \el != 0
141 /* Restore the task's original addr_limit. */
142 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
143 str x20, [tsk, #TI_ADDR_LIMIT]
145 /* No need to restore UAO, it will be restored from SPSR_EL1 */
146 .endif
148 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
149 .if \el == 0
150 ct_user_enter
151 ldr x23, [sp, #S_SP] // load return stack pointer
152 msr sp_el0, x23
153 #ifdef CONFIG_ARM64_ERRATUM_845719
154 alternative_if ARM64_WORKAROUND_845719
155 tbz x22, #4, 1f
156 #ifdef CONFIG_PID_IN_CONTEXTIDR
157 mrs x29, contextidr_el1
158 msr contextidr_el1, x29
159 #else
160 msr contextidr_el1, xzr
161 #endif
162 1:
163 alternative_else_nop_endif
164 #endif
165 .endif
166 msr elr_el1, x21 // set up the return data
167 msr spsr_el1, x22
168 ldp x0, x1, [sp, #16 * 0]
169 ldp x2, x3, [sp, #16 * 1]
170 ldp x4, x5, [sp, #16 * 2]
171 ldp x6, x7, [sp, #16 * 3]
172 ldp x8, x9, [sp, #16 * 4]
173 ldp x10, x11, [sp, #16 * 5]
174 ldp x12, x13, [sp, #16 * 6]
175 ldp x14, x15, [sp, #16 * 7]
176 ldp x16, x17, [sp, #16 * 8]
177 ldp x18, x19, [sp, #16 * 9]
178 ldp x20, x21, [sp, #16 * 10]
179 ldp x22, x23, [sp, #16 * 11]
180 ldp x24, x25, [sp, #16 * 12]
181 ldp x26, x27, [sp, #16 * 13]
182 ldp x28, x29, [sp, #16 * 14]
183 ldr lr, [sp, #S_LR]
184 add sp, sp, #S_FRAME_SIZE // restore sp
185 eret // return to kernel
186 .endm
188 .macro get_thread_info, rd
189 mrs \rd, sp_el0
190 .endm
192 .macro irq_stack_entry
193 mov x19, sp // preserve the original sp
195 /*
196 * Compare sp with the current thread_info, if the top
197 * ~(THREAD_SIZE - 1) bits match, we are on a task stack, and
198 * should switch to the irq stack.
199 */
200 and x25, x19, #~(THREAD_SIZE - 1)
201 cmp x25, tsk
202 b.ne 9998f
204 this_cpu_ptr irq_stack, x25, x26
205 mov x26, #IRQ_STACK_START_SP
206 add x26, x25, x26
208 /* switch to the irq stack */
209 mov sp, x26
211 /*
212 * Add a dummy stack frame, this non-standard format is fixed up
213 * by unwind_frame()
214 */
215 stp x29, x19, [sp, #-16]!
216 mov x29, sp
218 9998:
219 .endm
221 /*
222 * x19 should be preserved between irq_stack_entry and
223 * irq_stack_exit.
224 */
225 .macro irq_stack_exit
226 mov sp, x19
227 .endm
229 /*
230 * These are the registers used in the syscall handler, and allow us to
231 * have in theory up to 7 arguments to a function - x0 to x6.
232 *
233 * x7 is reserved for the system call number in 32-bit mode.
234 */
235 sc_nr .req x25 // number of system calls
236 scno .req x26 // syscall number
237 stbl .req x27 // syscall table pointer
238 tsk .req x28 // current thread_info
240 /*
241 * Interrupt handling.
242 */
243 .macro irq_handler
244 ldr_l x1, handle_arch_irq
245 mov x0, sp
246 irq_stack_entry
247 blr x1
248 irq_stack_exit
249 .endm
251 .text
253 /*
254 * Exception vectors.
255 */
256 .pushsection ".entry.text", "ax"
258 .align 11
259 ENTRY(vectors)
260 ventry el1_sync_invalid // Synchronous EL1t
261 ventry el1_irq_invalid // IRQ EL1t
262 ventry el1_fiq_invalid // FIQ EL1t
263 ventry el1_error_invalid // Error EL1t
265 ventry el1_sync // Synchronous EL1h
266 ventry el1_irq // IRQ EL1h
267 ventry el1_fiq_invalid // FIQ EL1h
268 ventry el1_error_invalid // Error EL1h
270 ventry el0_sync // Synchronous 64-bit EL0
271 ventry el0_irq // IRQ 64-bit EL0
272 ventry el0_fiq_invalid // FIQ 64-bit EL0
273 ventry el0_error_invalid // Error 64-bit EL0
275 #ifdef CONFIG_COMPAT
276 ventry el0_sync_compat // Synchronous 32-bit EL0
277 ventry el0_irq_compat // IRQ 32-bit EL0
278 ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
279 ventry el0_error_invalid_compat // Error 32-bit EL0
280 #else
281 ventry el0_sync_invalid // Synchronous 32-bit EL0
282 ventry el0_irq_invalid // IRQ 32-bit EL0
283 ventry el0_fiq_invalid // FIQ 32-bit EL0
284 ventry el0_error_invalid // Error 32-bit EL0
285 #endif
286 END(vectors)
288 /*
289 * Invalid mode handlers
290 */
291 .macro inv_entry, el, reason, regsize = 64
292 kernel_entry \el, \regsize
293 mov x0, sp
294 mov x1, #\reason
295 mrs x2, esr_el1
296 b bad_mode
297 .endm
299 el0_sync_invalid:
300 inv_entry 0, BAD_SYNC
301 ENDPROC(el0_sync_invalid)
303 el0_irq_invalid:
304 inv_entry 0, BAD_IRQ
305 ENDPROC(el0_irq_invalid)
307 el0_fiq_invalid:
308 inv_entry 0, BAD_FIQ
309 ENDPROC(el0_fiq_invalid)
311 el0_error_invalid:
312 inv_entry 0, BAD_ERROR
313 ENDPROC(el0_error_invalid)
315 #ifdef CONFIG_COMPAT
316 el0_fiq_invalid_compat:
317 inv_entry 0, BAD_FIQ, 32
318 ENDPROC(el0_fiq_invalid_compat)
320 el0_error_invalid_compat:
321 inv_entry 0, BAD_ERROR, 32
322 ENDPROC(el0_error_invalid_compat)
323 #endif
325 el1_sync_invalid:
326 inv_entry 1, BAD_SYNC
327 ENDPROC(el1_sync_invalid)
329 el1_irq_invalid:
330 inv_entry 1, BAD_IRQ
331 ENDPROC(el1_irq_invalid)
333 el1_fiq_invalid:
334 inv_entry 1, BAD_FIQ
335 ENDPROC(el1_fiq_invalid)
337 el1_error_invalid:
338 inv_entry 1, BAD_ERROR
339 ENDPROC(el1_error_invalid)
341 /*
342 * EL1 mode handlers.
343 */
344 .align 6
345 el1_sync:
346 kernel_entry 1
347 mrs x1, esr_el1 // read the syndrome register
348 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
349 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
350 b.eq el1_da
351 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
352 b.eq el1_ia
353 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
354 b.eq el1_undef
355 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
356 b.eq el1_sp_pc
357 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
358 b.eq el1_sp_pc
359 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
360 b.eq el1_undef
361 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
362 b.ge el1_dbg
363 b el1_inv
365 el1_ia:
366 /*
367 * Fall through to the Data abort case
368 */
369 el1_da:
370 /*
371 * Data abort handling
372 */
373 mrs x3, far_el1
374 enable_dbg
375 // re-enable interrupts if they were enabled in the aborted context
376 tbnz x23, #7, 1f // PSR_I_BIT
377 enable_irq
378 1:
379 clear_address_tag x0, x3
380 mov x2, sp // struct pt_regs
381 bl do_mem_abort
383 // disable interrupts before pulling preserved data off the stack
384 disable_irq
385 kernel_exit 1
386 el1_sp_pc:
387 /*
388 * Stack or PC alignment exception handling
389 */
390 mrs x0, far_el1
391 enable_dbg
392 mov x2, sp
393 b do_sp_pc_abort
394 el1_undef:
395 /*
396 * Undefined instruction
397 */
398 enable_dbg
399 mov x0, sp
400 b do_undefinstr
401 el1_dbg:
402 /*
403 * Debug exception handling
404 */
405 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
406 cinc x24, x24, eq // set bit '0'
407 tbz x24, #0, el1_inv // EL1 only
408 mrs x0, far_el1
409 mov x2, sp // struct pt_regs
410 bl do_debug_exception
411 kernel_exit 1
412 el1_inv:
413 // TODO: add support for undefined instructions in kernel mode
414 enable_dbg
415 mov x0, sp
416 mov x2, x1
417 mov x1, #BAD_SYNC
418 b bad_mode
419 ENDPROC(el1_sync)
421 .align 6
422 el1_irq:
423 kernel_entry 1
424 enable_dbg
425 #ifdef CONFIG_TRACE_IRQFLAGS
426 bl trace_hardirqs_off
427 #endif
429 irq_handler
431 #ifdef CONFIG_PREEMPT
432 ldr w24, [tsk, #TI_PREEMPT] // get preempt count
433 cbnz w24, 1f // preempt count != 0
434 ldr x0, [tsk, #TI_FLAGS] // get flags
435 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
436 bl el1_preempt
437 1:
438 #endif
439 #ifdef CONFIG_TRACE_IRQFLAGS
440 bl trace_hardirqs_on
441 #endif
442 kernel_exit 1
443 ENDPROC(el1_irq)
445 #ifdef CONFIG_PREEMPT
446 el1_preempt:
447 mov x24, lr
448 1: bl preempt_schedule_irq // irq en/disable is done inside
449 ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
450 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
451 ret x24
452 #endif
454 /*
455 * EL0 mode handlers.
456 */
457 .align 6
458 el0_sync:
459 kernel_entry 0
460 mrs x25, esr_el1 // read the syndrome register
461 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
462 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
463 b.eq el0_svc
464 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
465 b.eq el0_da
466 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
467 b.eq el0_ia
468 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
469 b.eq el0_fpsimd_acc
470 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
471 b.eq el0_fpsimd_exc
472 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
473 b.eq el0_sys
474 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
475 b.eq el0_sp_pc
476 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
477 b.eq el0_sp_pc
478 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
479 b.eq el0_undef
480 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
481 b.ge el0_dbg
482 b el0_inv
484 #ifdef CONFIG_COMPAT
485 .align 6
486 el0_sync_compat:
487 kernel_entry 0, 32
488 mrs x25, esr_el1 // read the syndrome register
489 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
490 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
491 b.eq el0_svc_compat
492 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
493 b.eq el0_da
494 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
495 b.eq el0_ia
496 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
497 b.eq el0_fpsimd_acc
498 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
499 b.eq el0_fpsimd_exc
500 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
501 b.eq el0_sp_pc
502 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
503 b.eq el0_undef
504 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
505 b.eq el0_undef
506 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
507 b.eq el0_undef
508 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
509 b.eq el0_undef
510 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
511 b.eq el0_undef
512 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
513 b.eq el0_undef
514 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
515 b.ge el0_dbg
516 b el0_inv
517 el0_svc_compat:
518 /*
519 * AArch32 syscall handling
520 */
521 adrp stbl, compat_sys_call_table // load compat syscall table pointer
522 uxtw scno, w7 // syscall number in w7 (r7)
523 mov sc_nr, #__NR_compat_syscalls
524 b el0_svc_naked
526 .align 6
527 el0_irq_compat:
528 kernel_entry 0, 32
529 b el0_irq_naked
530 #endif
532 el0_da:
533 /*
534 * Data abort handling
535 */
536 mrs x26, far_el1
537 // enable interrupts before calling the main handler
538 enable_dbg_and_irq
539 ct_user_exit
540 clear_address_tag x0, x26
541 mov x1, x25
542 mov x2, sp
543 bl do_mem_abort
544 b ret_to_user
545 el0_ia:
546 /*
547 * Instruction abort handling
548 */
549 mrs x26, far_el1
550 // enable interrupts before calling the main handler
551 enable_dbg_and_irq
552 ct_user_exit
553 mov x0, x26
554 mov x1, x25
555 mov x2, sp
556 bl do_mem_abort
557 b ret_to_user
558 el0_fpsimd_acc:
559 /*
560 * Floating Point or Advanced SIMD access
561 */
562 enable_dbg
563 ct_user_exit
564 mov x0, x25
565 mov x1, sp
566 bl do_fpsimd_acc
567 b ret_to_user
568 el0_fpsimd_exc:
569 /*
570 * Floating Point or Advanced SIMD exception
571 */
572 enable_dbg
573 ct_user_exit
574 mov x0, x25
575 mov x1, sp
576 bl do_fpsimd_exc
577 b ret_to_user
578 el0_sp_pc:
579 /*
580 * Stack or PC alignment exception handling
581 */
582 mrs x26, far_el1
583 // enable interrupts before calling the main handler
584 enable_dbg_and_irq
585 ct_user_exit
586 mov x0, x26
587 mov x1, x25
588 mov x2, sp
589 bl do_sp_pc_abort
590 b ret_to_user
591 el0_undef:
592 /*
593 * Undefined instruction
594 */
595 // enable interrupts before calling the main handler
596 enable_dbg_and_irq
597 ct_user_exit
598 mov x0, sp
599 bl do_undefinstr
600 b ret_to_user
601 el0_sys:
602 /*
603 * System instructions, for trapped cache maintenance instructions
604 */
605 enable_dbg_and_irq
606 ct_user_exit
607 mov x0, x25
608 mov x1, sp
609 bl do_sysinstr
610 b ret_to_user
611 el0_dbg:
612 /*
613 * Debug exception handling
614 */
615 tbnz x24, #0, el0_inv // EL0 only
616 mrs x0, far_el1
617 mov x1, x25
618 mov x2, sp
619 bl do_debug_exception
620 enable_dbg
621 ct_user_exit
622 b ret_to_user
623 el0_inv:
624 enable_dbg
625 ct_user_exit
626 mov x0, sp
627 mov x1, #BAD_SYNC
628 mov x2, x25
629 bl bad_el0_sync
630 b ret_to_user
631 ENDPROC(el0_sync)
633 .align 6
634 el0_irq:
635 kernel_entry 0
636 el0_irq_naked:
637 enable_dbg
638 #ifdef CONFIG_TRACE_IRQFLAGS
639 bl trace_hardirqs_off
640 #endif
642 ct_user_exit
643 irq_handler
645 #ifdef CONFIG_TRACE_IRQFLAGS
646 bl trace_hardirqs_on
647 #endif
648 b ret_to_user
649 ENDPROC(el0_irq)
651 /*
652 * Register switch for AArch64. The callee-saved registers need to be saved
653 * and restored. On entry:
654 * x0 = previous task_struct (must be preserved across the switch)
655 * x1 = next task_struct
656 * Previous and next are guaranteed not to be the same.
657 *
658 */
659 ENTRY(cpu_switch_to)
660 mov x10, #THREAD_CPU_CONTEXT
661 add x8, x0, x10
662 mov x9, sp
663 stp x19, x20, [x8], #16 // store callee-saved registers
664 stp x21, x22, [x8], #16
665 stp x23, x24, [x8], #16
666 stp x25, x26, [x8], #16
667 stp x27, x28, [x8], #16
668 stp x29, x9, [x8], #16
669 str lr, [x8]
670 add x8, x1, x10
671 ldp x19, x20, [x8], #16 // restore callee-saved registers
672 ldp x21, x22, [x8], #16
673 ldp x23, x24, [x8], #16
674 ldp x25, x26, [x8], #16
675 ldp x27, x28, [x8], #16
676 ldp x29, x9, [x8], #16
677 ldr lr, [x8]
678 mov sp, x9
679 and x9, x9, #~(THREAD_SIZE - 1)
680 msr sp_el0, x9
681 ret
682 ENDPROC(cpu_switch_to)
684 /*
685 * This is the fast syscall return path. We do as little as possible here,
686 * and this includes saving x0 back into the kernel stack.
687 */
688 ret_fast_syscall:
689 disable_irq // disable interrupts
690 str x0, [sp, #S_X0] // returned x0
691 ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing
692 and x2, x1, #_TIF_SYSCALL_WORK
693 cbnz x2, ret_fast_syscall_trace
694 and x2, x1, #_TIF_WORK_MASK
695 cbnz x2, work_pending
696 enable_step_tsk x1, x2
697 kernel_exit 0
698 ret_fast_syscall_trace:
699 enable_irq // enable interrupts
700 b __sys_trace_return_skipped // we already saved x0
702 /*
703 * Ok, we need to do extra processing, enter the slow path.
704 */
705 work_pending:
706 mov x0, sp // 'regs'
707 bl do_notify_resume
708 #ifdef CONFIG_TRACE_IRQFLAGS
709 bl trace_hardirqs_on // enabled while in userspace
710 #endif
711 ldr x1, [tsk, #TI_FLAGS] // re-check for single-step
712 b finish_ret_to_user
713 /*
714 * "slow" syscall return path.
715 */
716 ret_to_user:
717 disable_irq // disable interrupts
718 ldr x1, [tsk, #TI_FLAGS]
719 and x2, x1, #_TIF_WORK_MASK
720 cbnz x2, work_pending
721 finish_ret_to_user:
722 enable_step_tsk x1, x2
723 kernel_exit 0
724 ENDPROC(ret_to_user)
726 /*
727 * This is how we return from a fork.
728 */
729 ENTRY(ret_from_fork)
730 bl schedule_tail
731 cbz x19, 1f // not a kernel thread
732 mov x0, x20
733 blr x19
734 1: get_thread_info tsk
735 b ret_to_user
736 ENDPROC(ret_from_fork)
738 /*
739 * SVC handler.
740 */
741 .align 6
742 el0_svc:
743 adrp stbl, sys_call_table // load syscall table pointer
744 uxtw scno, w8 // syscall number in w8
745 mov sc_nr, #__NR_syscalls
746 el0_svc_naked: // compat entry point
747 stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
748 enable_dbg_and_irq
749 ct_user_exit 1
751 ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks
752 tst x16, #_TIF_SYSCALL_WORK
753 b.ne __sys_trace
754 cmp scno, sc_nr // check upper syscall limit
755 b.hs ni_sys
756 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
757 blr x16 // call sys_* routine
758 b ret_fast_syscall
759 ni_sys:
760 mov x0, sp
761 bl do_ni_syscall
762 b ret_fast_syscall
763 ENDPROC(el0_svc)
765 /*
766 * This is the really slow path. We're going to be doing context
767 * switches, and waiting for our parent to respond.
768 */
769 __sys_trace:
770 mov w0, #-1 // set default errno for
771 cmp scno, x0 // user-issued syscall(-1)
772 b.ne 1f
773 mov x0, #-ENOSYS
774 str x0, [sp, #S_X0]
775 1: mov x0, sp
776 bl syscall_trace_enter
777 cmp w0, #-1 // skip the syscall?
778 b.eq __sys_trace_return_skipped
779 uxtw scno, w0 // syscall number (possibly new)
780 mov x1, sp // pointer to regs
781 cmp scno, sc_nr // check upper syscall limit
782 b.hs __ni_sys_trace
783 ldp x0, x1, [sp] // restore the syscall args
784 ldp x2, x3, [sp, #S_X2]
785 ldp x4, x5, [sp, #S_X4]
786 ldp x6, x7, [sp, #S_X6]
787 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
788 blr x16 // call sys_* routine
790 __sys_trace_return:
791 str x0, [sp, #S_X0] // save returned x0
792 __sys_trace_return_skipped:
793 mov x0, sp
794 bl syscall_trace_exit
795 b ret_to_user
797 __ni_sys_trace:
798 mov x0, sp
799 bl do_ni_syscall
800 b __sys_trace_return
802 .popsection // .entry.text
804 /*
805 * Special system call wrappers.
806 */
807 ENTRY(sys_rt_sigreturn_wrapper)
808 mov x0, sp
809 b sys_rt_sigreturn
810 ENDPROC(sys_rt_sigreturn_wrapper)