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pvrusb2: reduce stack usage pvr2_eeprom_analyze()
[linux/fpc-iii.git] / arch / arm64 / net / bpf_jit_comp.c
blobd8199e12fb6ef906087a0c071c8669553b3ee6fa
1 /*
2 * BPF JIT compiler for ARM64
3 *
4 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #define pr_fmt(fmt) "bpf_jit: " fmt
20
21 #include <linux/bpf.h>
22 #include <linux/filter.h>
23 #include <linux/printk.h>
24 #include <linux/skbuff.h>
25 #include <linux/slab.h>
26
27 #include <asm/byteorder.h>
28 #include <asm/cacheflush.h>
29 #include <asm/debug-monitors.h>
30
31 #include "bpf_jit.h"
32
33 int bpf_jit_enable __read_mostly;
34
35 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0)
36 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1)
37 #define TCALL_CNT (MAX_BPF_JIT_REG + 2)
38
39 /* Map BPF registers to A64 registers */
40 static const int bpf2a64[] = {
41 /* return value from in-kernel function, and exit value from eBPF */
42 [BPF_REG_0] = A64_R(7),
43 /* arguments from eBPF program to in-kernel function */
44 [BPF_REG_1] = A64_R(0),
45 [BPF_REG_2] = A64_R(1),
46 [BPF_REG_3] = A64_R(2),
47 [BPF_REG_4] = A64_R(3),
48 [BPF_REG_5] = A64_R(4),
49 /* callee saved registers that in-kernel function will preserve */
50 [BPF_REG_6] = A64_R(19),
51 [BPF_REG_7] = A64_R(20),
52 [BPF_REG_8] = A64_R(21),
53 [BPF_REG_9] = A64_R(22),
54 /* read-only frame pointer to access stack */
55 [BPF_REG_FP] = A64_R(25),
56 /* temporary registers for internal BPF JIT */
57 [TMP_REG_1] = A64_R(10),
58 [TMP_REG_2] = A64_R(11),
59 /* tail_call_cnt */
60 [TCALL_CNT] = A64_R(26),
61 /* temporary register for blinding constants */
62 [BPF_REG_AX] = A64_R(9),
63 };
64
65 struct jit_ctx {
66 const struct bpf_prog *prog;
67 int idx;
68 int epilogue_offset;
69 int *offset;
70 u32 *image;
71 };
72
73 static inline void emit(const u32 insn, struct jit_ctx *ctx)
74 {
75 if (ctx->image != NULL)
76 ctx->image[ctx->idx] = cpu_to_le32(insn);
77
78 ctx->idx++;
79 }
80
81 static inline void emit_a64_mov_i64(const int reg, const u64 val,
82 struct jit_ctx *ctx)
83 {
84 u64 tmp = val;
85 int shift = 0;
86
87 emit(A64_MOVZ(1, reg, tmp & 0xffff, shift), ctx);
88 tmp >>= 16;
89 shift += 16;
90 while (tmp) {
91 if (tmp & 0xffff)
92 emit(A64_MOVK(1, reg, tmp & 0xffff, shift), ctx);
93 tmp >>= 16;
94 shift += 16;
95 }
96 }
97
98 static inline void emit_a64_mov_i(const int is64, const int reg,
99 const s32 val, struct jit_ctx *ctx)
100 {
101 u16 hi = val >> 16;
102 u16 lo = val & 0xffff;
103
104 if (hi & 0x8000) {
105 if (hi == 0xffff) {
106 emit(A64_MOVN(is64, reg, (u16)~lo, 0), ctx);
107 } else {
108 emit(A64_MOVN(is64, reg, (u16)~hi, 16), ctx);
109 emit(A64_MOVK(is64, reg, lo, 0), ctx);
110 }
111 } else {
112 emit(A64_MOVZ(is64, reg, lo, 0), ctx);
113 if (hi)
114 emit(A64_MOVK(is64, reg, hi, 16), ctx);
115 }
116 }
117
118 static inline int bpf2a64_offset(int bpf_to, int bpf_from,
119 const struct jit_ctx *ctx)
120 {
121 int to = ctx->offset[bpf_to];
122 /* -1 to account for the Branch instruction */
123 int from = ctx->offset[bpf_from] - 1;
124
125 return to - from;
126 }
127
128 static void jit_fill_hole(void *area, unsigned int size)
129 {
130 u32 *ptr;
131 /* We are guaranteed to have aligned memory. */
132 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32))
133 *ptr++ = cpu_to_le32(AARCH64_BREAK_FAULT);
134 }
135
136 static inline int epilogue_offset(const struct jit_ctx *ctx)
137 {
138 int to = ctx->epilogue_offset;
139 int from = ctx->idx;
140
141 return to - from;
142 }
143
144 /* Stack must be multiples of 16B */
145 #define STACK_ALIGN(sz) (((sz) + 15) & ~15)
146
147 #define _STACK_SIZE \
148 (MAX_BPF_STACK \
149 + 4 /* extra for skb_copy_bits buffer */)
150
151 #define STACK_SIZE STACK_ALIGN(_STACK_SIZE)
152
153 #define PROLOGUE_OFFSET 8
154
155 static int build_prologue(struct jit_ctx *ctx)
156 {
157 const u8 r6 = bpf2a64[BPF_REG_6];
158 const u8 r7 = bpf2a64[BPF_REG_7];
159 const u8 r8 = bpf2a64[BPF_REG_8];
160 const u8 r9 = bpf2a64[BPF_REG_9];
161 const u8 fp = bpf2a64[BPF_REG_FP];
162 const u8 tcc = bpf2a64[TCALL_CNT];
163 const int idx0 = ctx->idx;
164 int cur_offset;
165
166 /*
167 * BPF prog stack layout
168 *
169 * high
170 * original A64_SP => 0:+-----+ BPF prologue
171 * |FP/LR|
172 * current A64_FP => -16:+-----+
173 * | ... | callee saved registers
174 * BPF fp register => -64:+-----+ <= (BPF_FP)
175 * | |
176 * | ... | BPF prog stack
177 * | |
178 * +-----+ <= (BPF_FP - MAX_BPF_STACK)
179 * |RSVD | JIT scratchpad
180 * current A64_SP => +-----+ <= (BPF_FP - STACK_SIZE)
181 * | |
182 * | ... | Function call stack
183 * | |
184 * +-----+
185 * low
186 *
187 */
188
189 /* Save FP and LR registers to stay align with ARM64 AAPCS */
190 emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx);
191 emit(A64_MOV(1, A64_FP, A64_SP), ctx);
192
193 /* Save callee-saved registers */
194 emit(A64_PUSH(r6, r7, A64_SP), ctx);
195 emit(A64_PUSH(r8, r9, A64_SP), ctx);
196 emit(A64_PUSH(fp, tcc, A64_SP), ctx);
197
198 /* Set up BPF prog stack base register */
199 emit(A64_MOV(1, fp, A64_SP), ctx);
200
201 /* Initialize tail_call_cnt */
202 emit(A64_MOVZ(1, tcc, 0, 0), ctx);
203
204 /* Set up function call stack */
205 emit(A64_SUB_I(1, A64_SP, A64_SP, STACK_SIZE), ctx);
206
207 cur_offset = ctx->idx - idx0;
208 if (cur_offset != PROLOGUE_OFFSET) {
209 pr_err_once("PROLOGUE_OFFSET = %d, expected %d!\n",
210 cur_offset, PROLOGUE_OFFSET);
211 return -1;
212 }
213 return 0;
214 }
215
216 static int out_offset = -1; /* initialized on the first pass of build_body() */
217 static int emit_bpf_tail_call(struct jit_ctx *ctx)
218 {
219 /* bpf_tail_call(void *prog_ctx, struct bpf_array *array, u64 index) */
220 const u8 r2 = bpf2a64[BPF_REG_2];
221 const u8 r3 = bpf2a64[BPF_REG_3];
222
223 const u8 tmp = bpf2a64[TMP_REG_1];
224 const u8 prg = bpf2a64[TMP_REG_2];
225 const u8 tcc = bpf2a64[TCALL_CNT];
226 const int idx0 = ctx->idx;
227 #define cur_offset (ctx->idx - idx0)
228 #define jmp_offset (out_offset - (cur_offset))
229 size_t off;
230
231 /* if (index >= array->map.max_entries)
232 * goto out;
233 */
234 off = offsetof(struct bpf_array, map.max_entries);
235 emit_a64_mov_i64(tmp, off, ctx);
236 emit(A64_LDR32(tmp, r2, tmp), ctx);
237 emit(A64_CMP(0, r3, tmp), ctx);
238 emit(A64_B_(A64_COND_GE, jmp_offset), ctx);
239
240 /* if (tail_call_cnt > MAX_TAIL_CALL_CNT)
241 * goto out;
242 * tail_call_cnt++;
243 */
244 emit_a64_mov_i64(tmp, MAX_TAIL_CALL_CNT, ctx);
245 emit(A64_CMP(1, tcc, tmp), ctx);
246 emit(A64_B_(A64_COND_GT, jmp_offset), ctx);
247 emit(A64_ADD_I(1, tcc, tcc, 1), ctx);
248
249 /* prog = array->ptrs[index];
250 * if (prog == NULL)
251 * goto out;
252 */
253 off = offsetof(struct bpf_array, ptrs);
254 emit_a64_mov_i64(tmp, off, ctx);
255 emit(A64_ADD(1, tmp, r2, tmp), ctx);
256 emit(A64_LSL(1, prg, r3, 3), ctx);
257 emit(A64_LDR64(prg, tmp, prg), ctx);
258 emit(A64_CBZ(1, prg, jmp_offset), ctx);
259
260 /* goto *(prog->bpf_func + prologue_size); */
261 off = offsetof(struct bpf_prog, bpf_func);
262 emit_a64_mov_i64(tmp, off, ctx);
263 emit(A64_LDR64(tmp, prg, tmp), ctx);
264 emit(A64_ADD_I(1, tmp, tmp, sizeof(u32) * PROLOGUE_OFFSET), ctx);
265 emit(A64_BR(tmp), ctx);
266
267 /* out: */
268 if (out_offset == -1)
269 out_offset = cur_offset;
270 if (cur_offset != out_offset) {
271 pr_err_once("tail_call out_offset = %d, expected %d!\n",
272 cur_offset, out_offset);
273 return -1;
274 }
275 return 0;
276 #undef cur_offset
277 #undef jmp_offset
278 }
279
280 static void build_epilogue(struct jit_ctx *ctx)
281 {
282 const u8 r0 = bpf2a64[BPF_REG_0];
283 const u8 r6 = bpf2a64[BPF_REG_6];
284 const u8 r7 = bpf2a64[BPF_REG_7];
285 const u8 r8 = bpf2a64[BPF_REG_8];
286 const u8 r9 = bpf2a64[BPF_REG_9];
287 const u8 fp = bpf2a64[BPF_REG_FP];
288
289 /* We're done with BPF stack */
290 emit(A64_ADD_I(1, A64_SP, A64_SP, STACK_SIZE), ctx);
291
292 /* Restore fs (x25) and x26 */
293 emit(A64_POP(fp, A64_R(26), A64_SP), ctx);
294
295 /* Restore callee-saved register */
296 emit(A64_POP(r8, r9, A64_SP), ctx);
297 emit(A64_POP(r6, r7, A64_SP), ctx);
298
299 /* Restore FP/LR registers */
300 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx);
301
302 /* Set return value */
303 emit(A64_MOV(1, A64_R(0), r0), ctx);
304
305 emit(A64_RET(A64_LR), ctx);
306 }
307
308 /* JITs an eBPF instruction.
309 * Returns:
310 * 0 - successfully JITed an 8-byte eBPF instruction.
311 * >0 - successfully JITed a 16-byte eBPF instruction.
312 * <0 - failed to JIT.
313 */
314 static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
315 {
316 const u8 code = insn->code;
317 const u8 dst = bpf2a64[insn->dst_reg];
318 const u8 src = bpf2a64[insn->src_reg];
319 const u8 tmp = bpf2a64[TMP_REG_1];
320 const u8 tmp2 = bpf2a64[TMP_REG_2];
321 const s16 off = insn->off;
322 const s32 imm = insn->imm;
323 const int i = insn - ctx->prog->insnsi;
324 const bool is64 = BPF_CLASS(code) == BPF_ALU64;
325 u8 jmp_cond;
326 s32 jmp_offset;
327
328 #define check_imm(bits, imm) do { \
329 if ((((imm) > 0) && ((imm) >> (bits))) || \
330 (((imm) < 0) && (~(imm) >> (bits)))) { \
331 pr_info("[%2d] imm=%d(0x%x) out of range\n", \
332 i, imm, imm); \
333 return -EINVAL; \
334 } \
335 } while (0)
336 #define check_imm19(imm) check_imm(19, imm)
337 #define check_imm26(imm) check_imm(26, imm)
338
339 switch (code) {
340 /* dst = src */
341 case BPF_ALU | BPF_MOV | BPF_X:
342 case BPF_ALU64 | BPF_MOV | BPF_X:
343 emit(A64_MOV(is64, dst, src), ctx);
344 break;
345 /* dst = dst OP src */
346 case BPF_ALU | BPF_ADD | BPF_X:
347 case BPF_ALU64 | BPF_ADD | BPF_X:
348 emit(A64_ADD(is64, dst, dst, src), ctx);
349 break;
350 case BPF_ALU | BPF_SUB | BPF_X:
351 case BPF_ALU64 | BPF_SUB | BPF_X:
352 emit(A64_SUB(is64, dst, dst, src), ctx);
353 break;
354 case BPF_ALU | BPF_AND | BPF_X:
355 case BPF_ALU64 | BPF_AND | BPF_X:
356 emit(A64_AND(is64, dst, dst, src), ctx);
357 break;
358 case BPF_ALU | BPF_OR | BPF_X:
359 case BPF_ALU64 | BPF_OR | BPF_X:
360 emit(A64_ORR(is64, dst, dst, src), ctx);
361 break;
362 case BPF_ALU | BPF_XOR | BPF_X:
363 case BPF_ALU64 | BPF_XOR | BPF_X:
364 emit(A64_EOR(is64, dst, dst, src), ctx);
365 break;
366 case BPF_ALU | BPF_MUL | BPF_X:
367 case BPF_ALU64 | BPF_MUL | BPF_X:
368 emit(A64_MUL(is64, dst, dst, src), ctx);
369 break;
370 case BPF_ALU | BPF_DIV | BPF_X:
371 case BPF_ALU64 | BPF_DIV | BPF_X:
372 case BPF_ALU | BPF_MOD | BPF_X:
373 case BPF_ALU64 | BPF_MOD | BPF_X:
374 {
375 const u8 r0 = bpf2a64[BPF_REG_0];
376
377 /* if (src == 0) return 0 */
378 jmp_offset = 3; /* skip ahead to else path */
379 check_imm19(jmp_offset);
380 emit(A64_CBNZ(is64, src, jmp_offset), ctx);
381 emit(A64_MOVZ(1, r0, 0, 0), ctx);
382 jmp_offset = epilogue_offset(ctx);
383 check_imm26(jmp_offset);
384 emit(A64_B(jmp_offset), ctx);
385 /* else */
386 switch (BPF_OP(code)) {
387 case BPF_DIV:
388 emit(A64_UDIV(is64, dst, dst, src), ctx);
389 break;
390 case BPF_MOD:
391 emit(A64_UDIV(is64, tmp, dst, src), ctx);
392 emit(A64_MUL(is64, tmp, tmp, src), ctx);
393 emit(A64_SUB(is64, dst, dst, tmp), ctx);
394 break;
395 }
396 break;
397 }
398 case BPF_ALU | BPF_LSH | BPF_X:
399 case BPF_ALU64 | BPF_LSH | BPF_X:
400 emit(A64_LSLV(is64, dst, dst, src), ctx);
401 break;
402 case BPF_ALU | BPF_RSH | BPF_X:
403 case BPF_ALU64 | BPF_RSH | BPF_X:
404 emit(A64_LSRV(is64, dst, dst, src), ctx);
405 break;
406 case BPF_ALU | BPF_ARSH | BPF_X:
407 case BPF_ALU64 | BPF_ARSH | BPF_X:
408 emit(A64_ASRV(is64, dst, dst, src), ctx);
409 break;
410 /* dst = -dst */
411 case BPF_ALU | BPF_NEG:
412 case BPF_ALU64 | BPF_NEG:
413 emit(A64_NEG(is64, dst, dst), ctx);
414 break;
415 /* dst = BSWAP##imm(dst) */
416 case BPF_ALU | BPF_END | BPF_FROM_LE:
417 case BPF_ALU | BPF_END | BPF_FROM_BE:
418 #ifdef CONFIG_CPU_BIG_ENDIAN
419 if (BPF_SRC(code) == BPF_FROM_BE)
420 goto emit_bswap_uxt;
421 #else /* !CONFIG_CPU_BIG_ENDIAN */
422 if (BPF_SRC(code) == BPF_FROM_LE)
423 goto emit_bswap_uxt;
424 #endif
425 switch (imm) {
426 case 16:
427 emit(A64_REV16(is64, dst, dst), ctx);
428 /* zero-extend 16 bits into 64 bits */
429 emit(A64_UXTH(is64, dst, dst), ctx);
430 break;
431 case 32:
432 emit(A64_REV32(is64, dst, dst), ctx);
433 /* upper 32 bits already cleared */
434 break;
435 case 64:
436 emit(A64_REV64(dst, dst), ctx);
437 break;
438 }
439 break;
440 emit_bswap_uxt:
441 switch (imm) {
442 case 16:
443 /* zero-extend 16 bits into 64 bits */
444 emit(A64_UXTH(is64, dst, dst), ctx);
445 break;
446 case 32:
447 /* zero-extend 32 bits into 64 bits */
448 emit(A64_UXTW(is64, dst, dst), ctx);
449 break;
450 case 64:
451 /* nop */
452 break;
453 }
454 break;
455 /* dst = imm */
456 case BPF_ALU | BPF_MOV | BPF_K:
457 case BPF_ALU64 | BPF_MOV | BPF_K:
458 emit_a64_mov_i(is64, dst, imm, ctx);
459 break;
460 /* dst = dst OP imm */
461 case BPF_ALU | BPF_ADD | BPF_K:
462 case BPF_ALU64 | BPF_ADD | BPF_K:
463 emit_a64_mov_i(is64, tmp, imm, ctx);
464 emit(A64_ADD(is64, dst, dst, tmp), ctx);
465 break;
466 case BPF_ALU | BPF_SUB | BPF_K:
467 case BPF_ALU64 | BPF_SUB | BPF_K:
468 emit_a64_mov_i(is64, tmp, imm, ctx);
469 emit(A64_SUB(is64, dst, dst, tmp), ctx);
470 break;
471 case BPF_ALU | BPF_AND | BPF_K:
472 case BPF_ALU64 | BPF_AND | BPF_K:
473 emit_a64_mov_i(is64, tmp, imm, ctx);
474 emit(A64_AND(is64, dst, dst, tmp), ctx);
475 break;
476 case BPF_ALU | BPF_OR | BPF_K:
477 case BPF_ALU64 | BPF_OR | BPF_K:
478 emit_a64_mov_i(is64, tmp, imm, ctx);
479 emit(A64_ORR(is64, dst, dst, tmp), ctx);
480 break;
481 case BPF_ALU | BPF_XOR | BPF_K:
482 case BPF_ALU64 | BPF_XOR | BPF_K:
483 emit_a64_mov_i(is64, tmp, imm, ctx);
484 emit(A64_EOR(is64, dst, dst, tmp), ctx);
485 break;
486 case BPF_ALU | BPF_MUL | BPF_K:
487 case BPF_ALU64 | BPF_MUL | BPF_K:
488 emit_a64_mov_i(is64, tmp, imm, ctx);
489 emit(A64_MUL(is64, dst, dst, tmp), ctx);
490 break;
491 case BPF_ALU | BPF_DIV | BPF_K:
492 case BPF_ALU64 | BPF_DIV | BPF_K:
493 emit_a64_mov_i(is64, tmp, imm, ctx);
494 emit(A64_UDIV(is64, dst, dst, tmp), ctx);
495 break;
496 case BPF_ALU | BPF_MOD | BPF_K:
497 case BPF_ALU64 | BPF_MOD | BPF_K:
498 emit_a64_mov_i(is64, tmp2, imm, ctx);
499 emit(A64_UDIV(is64, tmp, dst, tmp2), ctx);
500 emit(A64_MUL(is64, tmp, tmp, tmp2), ctx);
501 emit(A64_SUB(is64, dst, dst, tmp), ctx);
502 break;
503 case BPF_ALU | BPF_LSH | BPF_K:
504 case BPF_ALU64 | BPF_LSH | BPF_K:
505 emit(A64_LSL(is64, dst, dst, imm), ctx);
506 break;
507 case BPF_ALU | BPF_RSH | BPF_K:
508 case BPF_ALU64 | BPF_RSH | BPF_K:
509 emit(A64_LSR(is64, dst, dst, imm), ctx);
510 break;
511 case BPF_ALU | BPF_ARSH | BPF_K:
512 case BPF_ALU64 | BPF_ARSH | BPF_K:
513 emit(A64_ASR(is64, dst, dst, imm), ctx);
514 break;
515
516 /* JUMP off */
517 case BPF_JMP | BPF_JA:
518 jmp_offset = bpf2a64_offset(i + off, i, ctx);
519 check_imm26(jmp_offset);
520 emit(A64_B(jmp_offset), ctx);
521 break;
522 /* IF (dst COND src) JUMP off */
523 case BPF_JMP | BPF_JEQ | BPF_X:
524 case BPF_JMP | BPF_JGT | BPF_X:
525 case BPF_JMP | BPF_JGE | BPF_X:
526 case BPF_JMP | BPF_JNE | BPF_X:
527 case BPF_JMP | BPF_JSGT | BPF_X:
528 case BPF_JMP | BPF_JSGE | BPF_X:
529 emit(A64_CMP(1, dst, src), ctx);
530 emit_cond_jmp:
531 jmp_offset = bpf2a64_offset(i + off, i, ctx);
532 check_imm19(jmp_offset);
533 switch (BPF_OP(code)) {
534 case BPF_JEQ:
535 jmp_cond = A64_COND_EQ;
536 break;
537 case BPF_JGT:
538 jmp_cond = A64_COND_HI;
539 break;
540 case BPF_JGE:
541 jmp_cond = A64_COND_CS;
542 break;
543 case BPF_JSET:
544 case BPF_JNE:
545 jmp_cond = A64_COND_NE;
546 break;
547 case BPF_JSGT:
548 jmp_cond = A64_COND_GT;
549 break;
550 case BPF_JSGE:
551 jmp_cond = A64_COND_GE;
552 break;
553 default:
554 return -EFAULT;
555 }
556 emit(A64_B_(jmp_cond, jmp_offset), ctx);
557 break;
558 case BPF_JMP | BPF_JSET | BPF_X:
559 emit(A64_TST(1, dst, src), ctx);
560 goto emit_cond_jmp;
561 /* IF (dst COND imm) JUMP off */
562 case BPF_JMP | BPF_JEQ | BPF_K:
563 case BPF_JMP | BPF_JGT | BPF_K:
564 case BPF_JMP | BPF_JGE | BPF_K:
565 case BPF_JMP | BPF_JNE | BPF_K:
566 case BPF_JMP | BPF_JSGT | BPF_K:
567 case BPF_JMP | BPF_JSGE | BPF_K:
568 emit_a64_mov_i(1, tmp, imm, ctx);
569 emit(A64_CMP(1, dst, tmp), ctx);
570 goto emit_cond_jmp;
571 case BPF_JMP | BPF_JSET | BPF_K:
572 emit_a64_mov_i(1, tmp, imm, ctx);
573 emit(A64_TST(1, dst, tmp), ctx);
574 goto emit_cond_jmp;
575 /* function call */
576 case BPF_JMP | BPF_CALL:
577 {
578 const u8 r0 = bpf2a64[BPF_REG_0];
579 const u64 func = (u64)__bpf_call_base + imm;
580
581 emit_a64_mov_i64(tmp, func, ctx);
582 emit(A64_BLR(tmp), ctx);
583 emit(A64_MOV(1, r0, A64_R(0)), ctx);
584 break;
585 }
586 /* tail call */
587 case BPF_JMP | BPF_CALL | BPF_X:
588 if (emit_bpf_tail_call(ctx))
589 return -EFAULT;
590 break;
591 /* function return */
592 case BPF_JMP | BPF_EXIT:
593 /* Optimization: when last instruction is EXIT,
594 simply fallthrough to epilogue. */
595 if (i == ctx->prog->len - 1)
596 break;
597 jmp_offset = epilogue_offset(ctx);
598 check_imm26(jmp_offset);
599 emit(A64_B(jmp_offset), ctx);
600 break;
601
602 /* dst = imm64 */
603 case BPF_LD | BPF_IMM | BPF_DW:
604 {
605 const struct bpf_insn insn1 = insn[1];
606 u64 imm64;
607
608 if (insn1.code != 0 || insn1.src_reg != 0 ||
609 insn1.dst_reg != 0 || insn1.off != 0) {
610 /* Note: verifier in BPF core must catch invalid
611 * instructions.
612 */
613 pr_err_once("Invalid BPF_LD_IMM64 instruction\n");
614 return -EINVAL;
615 }
616
617 imm64 = (u64)insn1.imm << 32 | (u32)imm;
618 emit_a64_mov_i64(dst, imm64, ctx);
619
620 return 1;
621 }
622
623 /* LDX: dst = *(size *)(src + off) */
624 case BPF_LDX | BPF_MEM | BPF_W:
625 case BPF_LDX | BPF_MEM | BPF_H:
626 case BPF_LDX | BPF_MEM | BPF_B:
627 case BPF_LDX | BPF_MEM | BPF_DW:
628 emit_a64_mov_i(1, tmp, off, ctx);
629 switch (BPF_SIZE(code)) {
630 case BPF_W:
631 emit(A64_LDR32(dst, src, tmp), ctx);
632 break;
633 case BPF_H:
634 emit(A64_LDRH(dst, src, tmp), ctx);
635 break;
636 case BPF_B:
637 emit(A64_LDRB(dst, src, tmp), ctx);
638 break;
639 case BPF_DW:
640 emit(A64_LDR64(dst, src, tmp), ctx);
641 break;
642 }
643 break;
644
645 /* ST: *(size *)(dst + off) = imm */
646 case BPF_ST | BPF_MEM | BPF_W:
647 case BPF_ST | BPF_MEM | BPF_H:
648 case BPF_ST | BPF_MEM | BPF_B:
649 case BPF_ST | BPF_MEM | BPF_DW:
650 /* Load imm to a register then store it */
651 emit_a64_mov_i(1, tmp2, off, ctx);
652 emit_a64_mov_i(1, tmp, imm, ctx);
653 switch (BPF_SIZE(code)) {
654 case BPF_W:
655 emit(A64_STR32(tmp, dst, tmp2), ctx);
656 break;
657 case BPF_H:
658 emit(A64_STRH(tmp, dst, tmp2), ctx);
659 break;
660 case BPF_B:
661 emit(A64_STRB(tmp, dst, tmp2), ctx);
662 break;
663 case BPF_DW:
664 emit(A64_STR64(tmp, dst, tmp2), ctx);
665 break;
666 }
667 break;
668
669 /* STX: *(size *)(dst + off) = src */
670 case BPF_STX | BPF_MEM | BPF_W:
671 case BPF_STX | BPF_MEM | BPF_H:
672 case BPF_STX | BPF_MEM | BPF_B:
673 case BPF_STX | BPF_MEM | BPF_DW:
674 emit_a64_mov_i(1, tmp, off, ctx);
675 switch (BPF_SIZE(code)) {
676 case BPF_W:
677 emit(A64_STR32(src, dst, tmp), ctx);
678 break;
679 case BPF_H:
680 emit(A64_STRH(src, dst, tmp), ctx);
681 break;
682 case BPF_B:
683 emit(A64_STRB(src, dst, tmp), ctx);
684 break;
685 case BPF_DW:
686 emit(A64_STR64(src, dst, tmp), ctx);
687 break;
688 }
689 break;
690 /* STX XADD: lock *(u32 *)(dst + off) += src */
691 case BPF_STX | BPF_XADD | BPF_W:
692 /* STX XADD: lock *(u64 *)(dst + off) += src */
693 case BPF_STX | BPF_XADD | BPF_DW:
694 goto notyet;
695
696 /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + imm)) */
697 case BPF_LD | BPF_ABS | BPF_W:
698 case BPF_LD | BPF_ABS | BPF_H:
699 case BPF_LD | BPF_ABS | BPF_B:
700 /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + src + imm)) */
701 case BPF_LD | BPF_IND | BPF_W:
702 case BPF_LD | BPF_IND | BPF_H:
703 case BPF_LD | BPF_IND | BPF_B:
704 {
705 const u8 r0 = bpf2a64[BPF_REG_0]; /* r0 = return value */
706 const u8 r6 = bpf2a64[BPF_REG_6]; /* r6 = pointer to sk_buff */
707 const u8 fp = bpf2a64[BPF_REG_FP];
708 const u8 r1 = bpf2a64[BPF_REG_1]; /* r1: struct sk_buff *skb */
709 const u8 r2 = bpf2a64[BPF_REG_2]; /* r2: int k */
710 const u8 r3 = bpf2a64[BPF_REG_3]; /* r3: unsigned int size */
711 const u8 r4 = bpf2a64[BPF_REG_4]; /* r4: void *buffer */
712 const u8 r5 = bpf2a64[BPF_REG_5]; /* r5: void *(*func)(...) */
713 int size;
714
715 emit(A64_MOV(1, r1, r6), ctx);
716 emit_a64_mov_i(0, r2, imm, ctx);
717 if (BPF_MODE(code) == BPF_IND)
718 emit(A64_ADD(0, r2, r2, src), ctx);
719 switch (BPF_SIZE(code)) {
720 case BPF_W:
721 size = 4;
722 break;
723 case BPF_H:
724 size = 2;
725 break;
726 case BPF_B:
727 size = 1;
728 break;
729 default:
730 return -EINVAL;
731 }
732 emit_a64_mov_i64(r3, size, ctx);
733 emit(A64_SUB_I(1, r4, fp, STACK_SIZE), ctx);
734 emit_a64_mov_i64(r5, (unsigned long)bpf_load_pointer, ctx);
735 emit(A64_BLR(r5), ctx);
736 emit(A64_MOV(1, r0, A64_R(0)), ctx);
737
738 jmp_offset = epilogue_offset(ctx);
739 check_imm19(jmp_offset);
740 emit(A64_CBZ(1, r0, jmp_offset), ctx);
741 emit(A64_MOV(1, r5, r0), ctx);
742 switch (BPF_SIZE(code)) {
743 case BPF_W:
744 emit(A64_LDR32(r0, r5, A64_ZR), ctx);
745 #ifndef CONFIG_CPU_BIG_ENDIAN
746 emit(A64_REV32(0, r0, r0), ctx);
747 #endif
748 break;
749 case BPF_H:
750 emit(A64_LDRH(r0, r5, A64_ZR), ctx);
751 #ifndef CONFIG_CPU_BIG_ENDIAN
752 emit(A64_REV16(0, r0, r0), ctx);
753 #endif
754 break;
755 case BPF_B:
756 emit(A64_LDRB(r0, r5, A64_ZR), ctx);
757 break;
758 }
759 break;
760 }
761 notyet:
762 pr_info_once("*** NOT YET: opcode %02x ***\n", code);
763 return -EFAULT;
764
765 default:
766 pr_err_once("unknown opcode %02x\n", code);
767 return -EINVAL;
768 }
769
770 return 0;
771 }
772
773 static int build_body(struct jit_ctx *ctx)
774 {
775 const struct bpf_prog *prog = ctx->prog;
776 int i;
777
778 for (i = 0; i < prog->len; i++) {
779 const struct bpf_insn *insn = &prog->insnsi[i];
780 int ret;
781
782 ret = build_insn(insn, ctx);
783 if (ret > 0) {
784 i++;
785 if (ctx->image == NULL)
786 ctx->offset[i] = ctx->idx;
787 continue;
788 }
789 if (ctx->image == NULL)
790 ctx->offset[i] = ctx->idx;
791 if (ret)
792 return ret;
793 }
794
795 return 0;
796 }
797
798 static int validate_code(struct jit_ctx *ctx)
799 {
800 int i;
801
802 for (i = 0; i < ctx->idx; i++) {
803 u32 a64_insn = le32_to_cpu(ctx->image[i]);
804
805 if (a64_insn == AARCH64_BREAK_FAULT)
806 return -1;
807 }
808
809 return 0;
810 }
811
812 static inline void bpf_flush_icache(void *start, void *end)
813 {
814 flush_icache_range((unsigned long)start, (unsigned long)end);
815 }
816
817 void bpf_jit_compile(struct bpf_prog *prog)
818 {
819 /* Nothing to do here. We support Internal BPF. */
820 }
821
822 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
823 {
824 struct bpf_prog *tmp, *orig_prog = prog;
825 struct bpf_binary_header *header;
826 bool tmp_blinded = false;
827 struct jit_ctx ctx;
828 int image_size;
829 u8 *image_ptr;
830
831 if (!bpf_jit_enable)
832 return orig_prog;
833
834 tmp = bpf_jit_blind_constants(prog);
835 /* If blinding was requested and we failed during blinding,
836 * we must fall back to the interpreter.
837 */
838 if (IS_ERR(tmp))
839 return orig_prog;
840 if (tmp != prog) {
841 tmp_blinded = true;
842 prog = tmp;
843 }
844
845 memset(&ctx, 0, sizeof(ctx));
846 ctx.prog = prog;
847
848 ctx.offset = kcalloc(prog->len, sizeof(int), GFP_KERNEL);
849 if (ctx.offset == NULL) {
850 prog = orig_prog;
851 goto out;
852 }
853
854 /* 1. Initial fake pass to compute ctx->idx. */
855
856 /* Fake pass to fill in ctx->offset. */
857 if (build_body(&ctx)) {
858 prog = orig_prog;
859 goto out_off;
860 }
861
862 if (build_prologue(&ctx)) {
863 prog = orig_prog;
864 goto out_off;
865 }
866
867 ctx.epilogue_offset = ctx.idx;
868 build_epilogue(&ctx);
869
870 /* Now we know the actual image size. */
871 image_size = sizeof(u32) * ctx.idx;
872 header = bpf_jit_binary_alloc(image_size, &image_ptr,
873 sizeof(u32), jit_fill_hole);
874 if (header == NULL) {
875 prog = orig_prog;
876 goto out_off;
877 }
878
879 /* 2. Now, the actual pass. */
880
881 ctx.image = (u32 *)image_ptr;
882 ctx.idx = 0;
883
884 build_prologue(&ctx);
885
886 if (build_body(&ctx)) {
887 bpf_jit_binary_free(header);
888 prog = orig_prog;
889 goto out_off;
890 }
891
892 build_epilogue(&ctx);
893
894 /* 3. Extra pass to validate JITed code. */
895 if (validate_code(&ctx)) {
896 bpf_jit_binary_free(header);
897 prog = orig_prog;
898 goto out_off;
899 }
900
901 /* And we're done. */
902 if (bpf_jit_enable > 1)
903 bpf_jit_dump(prog->len, image_size, 2, ctx.image);
904
905 bpf_flush_icache(header, ctx.image + ctx.idx);
906
907 set_memory_ro((unsigned long)header, header->pages);
908 prog->bpf_func = (void *)ctx.image;
909 prog->jited = 1;
910
911 out_off:
912 kfree(ctx.offset);
913 out:
914 if (tmp_blinded)
915 bpf_jit_prog_release_other(prog, prog == orig_prog ?
916 tmp : orig_prog);
917 return prog;
918 }
919
920 void bpf_jit_free(struct bpf_prog *prog)
921 {
922 unsigned long addr = (unsigned long)prog->bpf_func & PAGE_MASK;
923 struct bpf_binary_header *header = (void *)addr;
924
925 if (!prog->jited)
926 goto free_filter;
927
928 set_memory_rw(addr, header->pages);
929 bpf_jit_binary_free(header);
930
931 free_filter:
932 bpf_prog_unlock_free(prog);
933 }
Linux with added FPC-III support