2 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
4 * Registers and bits definitions of ARC EMAC
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/phy.h>
14 #include <linux/clk.h>
16 /* STATUS and ENABLE Register bit masks */
17 #define TXINT_MASK (1 << 0) /* Transmit interrupt */
18 #define RXINT_MASK (1 << 1) /* Receive interrupt */
19 #define ERR_MASK (1 << 2) /* Error interrupt */
20 #define TXCH_MASK (1 << 3) /* Transmit chaining error interrupt */
21 #define MSER_MASK (1 << 4) /* Missed packet counter error */
22 #define RXCR_MASK (1 << 8) /* RXCRCERR counter rolled over */
23 #define RXFR_MASK (1 << 9) /* RXFRAMEERR counter rolled over */
24 #define RXFL_MASK (1 << 10) /* RXOFLOWERR counter rolled over */
25 #define MDIO_MASK (1 << 12) /* MDIO complete interrupt */
26 #define TXPL_MASK (1 << 31) /* Force polling of BD by EMAC */
28 /* CONTROL Register bit masks */
29 #define EN_MASK (1 << 0) /* VMAC enable */
30 #define TXRN_MASK (1 << 3) /* TX enable */
31 #define RXRN_MASK (1 << 4) /* RX enable */
32 #define DSBC_MASK (1 << 8) /* Disable receive broadcast */
33 #define ENFL_MASK (1 << 10) /* Enable Full-duplex */
34 #define PROM_MASK (1 << 11) /* Promiscuous mode */
36 /* Buffer descriptor INFO bit masks */
37 #define OWN_MASK (1 << 31) /* 0-CPU or 1-EMAC owns buffer */
38 #define FIRST_MASK (1 << 16) /* First buffer in chain */
39 #define LAST_MASK (1 << 17) /* Last buffer in chain */
40 #define LEN_MASK 0x000007FF /* last 11 bits */
41 #define CRLS (1 << 21)
42 #define DEFR (1 << 22)
43 #define DROP (1 << 23)
44 #define RTRY (1 << 24)
45 #define LTCL (1 << 28)
46 #define UFLO (1 << 29)
48 #define FOR_EMAC OWN_MASK
51 /* ARC EMAC register set combines entries for MAC and MDIO */
69 #define TX_TIMEOUT (400 * HZ / 1000) /* Transmission timeout */
71 #define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */
73 #define EMAC_BUFFER_SIZE 1536 /* EMAC buffer size */
76 * struct arc_emac_bd - EMAC buffer descriptor (BD).
78 * @info: Contains status information on the buffer itself.
79 * @data: 32-bit byte addressable pointer to the packet data.
86 /* Number of Rx/Tx BD's */
90 #define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
91 #define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
94 * struct buffer_state - Stores Rx/Tx buffer state.
95 * @sk_buff: Pointer to socket buffer.
96 * @addr: Start address of DMA-mapped memory region.
97 * @len: Length of DMA-mapped memory region.
101 DEFINE_DMA_UNMAP_ADDR(addr
);
102 DEFINE_DMA_UNMAP_LEN(len
);
105 struct arc_emac_mdio_bus_data
{
106 struct gpio_desc
*reset_gpio
;
111 * struct arc_emac_priv - Storage of EMAC's private information.
112 * @dev: Pointer to the current device.
113 * @phy_dev: Pointer to attached PHY device.
114 * @bus: Pointer to the current MII bus.
115 * @regs: Base address of EMAC memory-mapped control registers.
116 * @napi: Structure for NAPI.
117 * @rxbd: Pointer to Rx BD ring.
118 * @txbd: Pointer to Tx BD ring.
119 * @rxbd_dma: DMA handle for Rx BD ring.
120 * @txbd_dma: DMA handle for Tx BD ring.
121 * @rx_buff: Storage for Rx buffers states.
122 * @tx_buff: Storage for Tx buffers states.
123 * @txbd_curr: Index of Tx BD to use on the next "ndo_start_xmit".
124 * @txbd_dirty: Index of Tx BD to free on the next Tx interrupt.
125 * @last_rx_bd: Index of the last Rx BD we've got from EMAC.
126 * @link: PHY's last seen link state.
127 * @duplex: PHY's last set duplex mode.
128 * @speed: PHY's last set speed.
130 struct arc_emac_priv
{
131 const char *drv_name
;
132 const char *drv_version
;
133 void (*set_mac_speed
)(void *priv
, unsigned int speed
);
138 struct arc_emac_mdio_bus_data bus_data
;
143 struct napi_struct napi
;
145 struct arc_emac_bd
*rxbd
;
146 struct arc_emac_bd
*txbd
;
151 struct buffer_state rx_buff
[RX_BD_NUM
];
152 struct buffer_state tx_buff
[TX_BD_NUM
];
153 unsigned int txbd_curr
;
154 unsigned int txbd_dirty
;
156 unsigned int last_rx_bd
;
164 * arc_reg_set - Sets EMAC register with provided value.
165 * @priv: Pointer to ARC EMAC private data structure.
166 * @reg: Register offset from base address.
167 * @value: Value to set in register.
169 static inline void arc_reg_set(struct arc_emac_priv
*priv
, int reg
, int value
)
171 iowrite32(value
, priv
->regs
+ reg
* sizeof(int));
175 * arc_reg_get - Gets value of specified EMAC register.
176 * @priv: Pointer to ARC EMAC private data structure.
177 * @reg: Register offset from base address.
179 * returns: Value of requested register.
181 static inline unsigned int arc_reg_get(struct arc_emac_priv
*priv
, int reg
)
183 return ioread32(priv
->regs
+ reg
* sizeof(int));
187 * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
188 * @priv: Pointer to ARC EMAC private data structure.
189 * @reg: Register offset from base address.
190 * @mask: Mask to apply to specified register.
192 * This function reads initial register value, then applies provided mask
193 * to it and then writes register back.
195 static inline void arc_reg_or(struct arc_emac_priv
*priv
, int reg
, int mask
)
197 unsigned int value
= arc_reg_get(priv
, reg
);
199 arc_reg_set(priv
, reg
, value
| mask
);
203 * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
204 * @priv: Pointer to ARC EMAC private data structure.
205 * @reg: Register offset from base address.
206 * @mask: Mask to apply to specified register.
208 * This function reads initial register value, then applies provided mask
209 * to it and then writes register back.
211 static inline void arc_reg_clr(struct arc_emac_priv
*priv
, int reg
, int mask
)
213 unsigned int value
= arc_reg_get(priv
, reg
);
215 arc_reg_set(priv
, reg
, value
& ~mask
);
218 int arc_mdio_probe(struct arc_emac_priv
*priv
);
219 int arc_mdio_remove(struct arc_emac_priv
*priv
);
220 int arc_emac_probe(struct net_device
*ndev
, int interface
);
221 int arc_emac_remove(struct net_device
*ndev
);
223 #endif /* ARC_EMAC_H */