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pvrusb2: reduce stack usage pvr2_eeprom_analyze()
[linux/fpc-iii.git] / drivers / net / ethernet / broadcom / bcm63xx_enet.c
blob08d91efceed080fd9c85544fa8cfa5427075e4e8
1 /*
2 * Driver for BCM963xx builtin Ethernet mac
3 *
4 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/etherdevice.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/ethtool.h>
28 #include <linux/crc32.h>
29 #include <linux/err.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/if_vlan.h>
33
34 #include <bcm63xx_dev_enet.h>
35 #include "bcm63xx_enet.h"
36
37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
38 static char bcm_enet_driver_version[] = "1.0";
39
40 static int copybreak __read_mostly = 128;
41 module_param(copybreak, int, 0);
42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
43
44 /* io registers memory shared between all devices */
45 static void __iomem *bcm_enet_shared_base[3];
46
47 /*
48 * io helpers to access mac registers
49 */
50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
51 {
52 return bcm_readl(priv->base + off);
53 }
54
55 static inline void enet_writel(struct bcm_enet_priv *priv,
56 u32 val, u32 off)
57 {
58 bcm_writel(val, priv->base + off);
59 }
60
61 /*
62 * io helpers to access switch registers
63 */
64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
65 {
66 return bcm_readl(priv->base + off);
67 }
68
69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
70 u32 val, u32 off)
71 {
72 bcm_writel(val, priv->base + off);
73 }
74
75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
76 {
77 return bcm_readw(priv->base + off);
78 }
79
80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
81 u16 val, u32 off)
82 {
83 bcm_writew(val, priv->base + off);
84 }
85
86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
87 {
88 return bcm_readb(priv->base + off);
89 }
90
91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
92 u8 val, u32 off)
93 {
94 bcm_writeb(val, priv->base + off);
95 }
96
97
98 /* io helpers to access shared registers */
99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
100 {
101 return bcm_readl(bcm_enet_shared_base[0] + off);
102 }
103
104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
105 u32 val, u32 off)
106 {
107 bcm_writel(val, bcm_enet_shared_base[0] + off);
108 }
109
110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
111 {
112 return bcm_readl(bcm_enet_shared_base[1] +
113 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
114 }
115
116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
117 u32 val, u32 off, int chan)
118 {
119 bcm_writel(val, bcm_enet_shared_base[1] +
120 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
121 }
122
123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
124 {
125 return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
126 }
127
128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
129 u32 val, u32 off, int chan)
130 {
131 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
132 }
133
134 /*
135 * write given data into mii register and wait for transfer to end
136 * with timeout (average measured transfer time is 25us)
137 */
138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
139 {
140 int limit;
141
142 /* make sure mii interrupt status is cleared */
143 enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
144
145 enet_writel(priv, data, ENET_MIIDATA_REG);
146 wmb();
147
148 /* busy wait on mii interrupt bit, with timeout */
149 limit = 1000;
150 do {
151 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
152 break;
153 udelay(1);
154 } while (limit-- > 0);
155
156 return (limit < 0) ? 1 : 0;
157 }
158
159 /*
160 * MII internal read callback
161 */
162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
163 int regnum)
164 {
165 u32 tmp, val;
166
167 tmp = regnum << ENET_MIIDATA_REG_SHIFT;
168 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
169 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
170 tmp |= ENET_MIIDATA_OP_READ_MASK;
171
172 if (do_mdio_op(priv, tmp))
173 return -1;
174
175 val = enet_readl(priv, ENET_MIIDATA_REG);
176 val &= 0xffff;
177 return val;
178 }
179
180 /*
181 * MII internal write callback
182 */
183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
184 int regnum, u16 value)
185 {
186 u32 tmp;
187
188 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
189 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
190 tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
191 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
192 tmp |= ENET_MIIDATA_OP_WRITE_MASK;
193
194 (void)do_mdio_op(priv, tmp);
195 return 0;
196 }
197
198 /*
199 * MII read callback from phylib
200 */
201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
202 int regnum)
203 {
204 return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
205 }
206
207 /*
208 * MII write callback from phylib
209 */
210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
211 int regnum, u16 value)
212 {
213 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
214 }
215
216 /*
217 * MII read callback from mii core
218 */
219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
220 int regnum)
221 {
222 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
223 }
224
225 /*
226 * MII write callback from mii core
227 */
228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
229 int regnum, int value)
230 {
231 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
232 }
233
234 /*
235 * refill rx queue
236 */
237 static int bcm_enet_refill_rx(struct net_device *dev)
238 {
239 struct bcm_enet_priv *priv;
240
241 priv = netdev_priv(dev);
242
243 while (priv->rx_desc_count < priv->rx_ring_size) {
244 struct bcm_enet_desc *desc;
245 struct sk_buff *skb;
246 dma_addr_t p;
247 int desc_idx;
248 u32 len_stat;
249
250 desc_idx = priv->rx_dirty_desc;
251 desc = &priv->rx_desc_cpu[desc_idx];
252
253 if (!priv->rx_skb[desc_idx]) {
254 skb = netdev_alloc_skb(dev, priv->rx_skb_size);
255 if (!skb)
256 break;
257 priv->rx_skb[desc_idx] = skb;
258 p = dma_map_single(&priv->pdev->dev, skb->data,
259 priv->rx_skb_size,
260 DMA_FROM_DEVICE);
261 desc->address = p;
262 }
263
264 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
265 len_stat |= DMADESC_OWNER_MASK;
266 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
267 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
268 priv->rx_dirty_desc = 0;
269 } else {
270 priv->rx_dirty_desc++;
271 }
272 wmb();
273 desc->len_stat = len_stat;
274
275 priv->rx_desc_count++;
276
277 /* tell dma engine we allocated one buffer */
278 if (priv->dma_has_sram)
279 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
280 else
281 enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
282 }
283
284 /* If rx ring is still empty, set a timer to try allocating
285 * again at a later time. */
286 if (priv->rx_desc_count == 0 && netif_running(dev)) {
287 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
288 priv->rx_timeout.expires = jiffies + HZ;
289 add_timer(&priv->rx_timeout);
290 }
291
292 return 0;
293 }
294
295 /*
296 * timer callback to defer refill rx queue in case we're OOM
297 */
298 static void bcm_enet_refill_rx_timer(unsigned long data)
299 {
300 struct net_device *dev;
301 struct bcm_enet_priv *priv;
302
303 dev = (struct net_device *)data;
304 priv = netdev_priv(dev);
305
306 spin_lock(&priv->rx_lock);
307 bcm_enet_refill_rx((struct net_device *)data);
308 spin_unlock(&priv->rx_lock);
309 }
310
311 /*
312 * extract packet from rx queue
313 */
314 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
315 {
316 struct bcm_enet_priv *priv;
317 struct device *kdev;
318 int processed;
319
320 priv = netdev_priv(dev);
321 kdev = &priv->pdev->dev;
322 processed = 0;
323
324 /* don't scan ring further than number of refilled
325 * descriptor */
326 if (budget > priv->rx_desc_count)
327 budget = priv->rx_desc_count;
328
329 do {
330 struct bcm_enet_desc *desc;
331 struct sk_buff *skb;
332 int desc_idx;
333 u32 len_stat;
334 unsigned int len;
335
336 desc_idx = priv->rx_curr_desc;
337 desc = &priv->rx_desc_cpu[desc_idx];
338
339 /* make sure we actually read the descriptor status at
340 * each loop */
341 rmb();
342
343 len_stat = desc->len_stat;
344
345 /* break if dma ownership belongs to hw */
346 if (len_stat & DMADESC_OWNER_MASK)
347 break;
348
349 processed++;
350 priv->rx_curr_desc++;
351 if (priv->rx_curr_desc == priv->rx_ring_size)
352 priv->rx_curr_desc = 0;
353 priv->rx_desc_count--;
354
355 /* if the packet does not have start of packet _and_
356 * end of packet flag set, then just recycle it */
357 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
358 (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
359 dev->stats.rx_dropped++;
360 continue;
361 }
362
363 /* recycle packet if it's marked as bad */
364 if (!priv->enet_is_sw &&
365 unlikely(len_stat & DMADESC_ERR_MASK)) {
366 dev->stats.rx_errors++;
367
368 if (len_stat & DMADESC_OVSIZE_MASK)
369 dev->stats.rx_length_errors++;
370 if (len_stat & DMADESC_CRC_MASK)
371 dev->stats.rx_crc_errors++;
372 if (len_stat & DMADESC_UNDER_MASK)
373 dev->stats.rx_frame_errors++;
374 if (len_stat & DMADESC_OV_MASK)
375 dev->stats.rx_fifo_errors++;
376 continue;
377 }
378
379 /* valid packet */
380 skb = priv->rx_skb[desc_idx];
381 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
382 /* don't include FCS */
383 len -= 4;
384
385 if (len < copybreak) {
386 struct sk_buff *nskb;
387
388 nskb = napi_alloc_skb(&priv->napi, len);
389 if (!nskb) {
390 /* forget packet, just rearm desc */
391 dev->stats.rx_dropped++;
392 continue;
393 }
394
395 dma_sync_single_for_cpu(kdev, desc->address,
396 len, DMA_FROM_DEVICE);
397 memcpy(nskb->data, skb->data, len);
398 dma_sync_single_for_device(kdev, desc->address,
399 len, DMA_FROM_DEVICE);
400 skb = nskb;
401 } else {
402 dma_unmap_single(&priv->pdev->dev, desc->address,
403 priv->rx_skb_size, DMA_FROM_DEVICE);
404 priv->rx_skb[desc_idx] = NULL;
405 }
406
407 skb_put(skb, len);
408 skb->protocol = eth_type_trans(skb, dev);
409 dev->stats.rx_packets++;
410 dev->stats.rx_bytes += len;
411 netif_receive_skb(skb);
412
413 } while (--budget > 0);
414
415 if (processed || !priv->rx_desc_count) {
416 bcm_enet_refill_rx(dev);
417
418 /* kick rx dma */
419 enet_dmac_writel(priv, priv->dma_chan_en_mask,
420 ENETDMAC_CHANCFG, priv->rx_chan);
421 }
422
423 return processed;
424 }
425
426
427 /*
428 * try to or force reclaim of transmitted buffers
429 */
430 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
431 {
432 struct bcm_enet_priv *priv;
433 int released;
434
435 priv = netdev_priv(dev);
436 released = 0;
437
438 while (priv->tx_desc_count < priv->tx_ring_size) {
439 struct bcm_enet_desc *desc;
440 struct sk_buff *skb;
441
442 /* We run in a bh and fight against start_xmit, which
443 * is called with bh disabled */
444 spin_lock(&priv->tx_lock);
445
446 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
447
448 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
449 spin_unlock(&priv->tx_lock);
450 break;
451 }
452
453 /* ensure other field of the descriptor were not read
454 * before we checked ownership */
455 rmb();
456
457 skb = priv->tx_skb[priv->tx_dirty_desc];
458 priv->tx_skb[priv->tx_dirty_desc] = NULL;
459 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
460 DMA_TO_DEVICE);
461
462 priv->tx_dirty_desc++;
463 if (priv->tx_dirty_desc == priv->tx_ring_size)
464 priv->tx_dirty_desc = 0;
465 priv->tx_desc_count++;
466
467 spin_unlock(&priv->tx_lock);
468
469 if (desc->len_stat & DMADESC_UNDER_MASK)
470 dev->stats.tx_errors++;
471
472 dev_kfree_skb(skb);
473 released++;
474 }
475
476 if (netif_queue_stopped(dev) && released)
477 netif_wake_queue(dev);
478
479 return released;
480 }
481
482 /*
483 * poll func, called by network core
484 */
485 static int bcm_enet_poll(struct napi_struct *napi, int budget)
486 {
487 struct bcm_enet_priv *priv;
488 struct net_device *dev;
489 int rx_work_done;
490
491 priv = container_of(napi, struct bcm_enet_priv, napi);
492 dev = priv->net_dev;
493
494 /* ack interrupts */
495 enet_dmac_writel(priv, priv->dma_chan_int_mask,
496 ENETDMAC_IR, priv->rx_chan);
497 enet_dmac_writel(priv, priv->dma_chan_int_mask,
498 ENETDMAC_IR, priv->tx_chan);
499
500 /* reclaim sent skb */
501 bcm_enet_tx_reclaim(dev, 0);
502
503 spin_lock(&priv->rx_lock);
504 rx_work_done = bcm_enet_receive_queue(dev, budget);
505 spin_unlock(&priv->rx_lock);
506
507 if (rx_work_done >= budget) {
508 /* rx queue is not yet empty/clean */
509 return rx_work_done;
510 }
511
512 /* no more packet in rx/tx queue, remove device from poll
513 * queue */
514 napi_complete(napi);
515
516 /* restore rx/tx interrupt */
517 enet_dmac_writel(priv, priv->dma_chan_int_mask,
518 ENETDMAC_IRMASK, priv->rx_chan);
519 enet_dmac_writel(priv, priv->dma_chan_int_mask,
520 ENETDMAC_IRMASK, priv->tx_chan);
521
522 return rx_work_done;
523 }
524
525 /*
526 * mac interrupt handler
527 */
528 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
529 {
530 struct net_device *dev;
531 struct bcm_enet_priv *priv;
532 u32 stat;
533
534 dev = dev_id;
535 priv = netdev_priv(dev);
536
537 stat = enet_readl(priv, ENET_IR_REG);
538 if (!(stat & ENET_IR_MIB))
539 return IRQ_NONE;
540
541 /* clear & mask interrupt */
542 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
543 enet_writel(priv, 0, ENET_IRMASK_REG);
544
545 /* read mib registers in workqueue */
546 schedule_work(&priv->mib_update_task);
547
548 return IRQ_HANDLED;
549 }
550
551 /*
552 * rx/tx dma interrupt handler
553 */
554 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
555 {
556 struct net_device *dev;
557 struct bcm_enet_priv *priv;
558
559 dev = dev_id;
560 priv = netdev_priv(dev);
561
562 /* mask rx/tx interrupts */
563 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
564 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
565
566 napi_schedule(&priv->napi);
567
568 return IRQ_HANDLED;
569 }
570
571 /*
572 * tx request callback
573 */
574 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
575 {
576 struct bcm_enet_priv *priv;
577 struct bcm_enet_desc *desc;
578 u32 len_stat;
579 int ret;
580
581 priv = netdev_priv(dev);
582
583 /* lock against tx reclaim */
584 spin_lock(&priv->tx_lock);
585
586 /* make sure the tx hw queue is not full, should not happen
587 * since we stop queue before it's the case */
588 if (unlikely(!priv->tx_desc_count)) {
589 netif_stop_queue(dev);
590 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
591 "available?\n");
592 ret = NETDEV_TX_BUSY;
593 goto out_unlock;
594 }
595
596 /* pad small packets sent on a switch device */
597 if (priv->enet_is_sw && skb->len < 64) {
598 int needed = 64 - skb->len;
599 char *data;
600
601 if (unlikely(skb_tailroom(skb) < needed)) {
602 struct sk_buff *nskb;
603
604 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
605 if (!nskb) {
606 ret = NETDEV_TX_BUSY;
607 goto out_unlock;
608 }
609 dev_kfree_skb(skb);
610 skb = nskb;
611 }
612 data = skb_put(skb, needed);
613 memset(data, 0, needed);
614 }
615
616 /* point to the next available desc */
617 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
618 priv->tx_skb[priv->tx_curr_desc] = skb;
619
620 /* fill descriptor */
621 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
622 DMA_TO_DEVICE);
623
624 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
625 len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
626 DMADESC_APPEND_CRC |
627 DMADESC_OWNER_MASK;
628
629 priv->tx_curr_desc++;
630 if (priv->tx_curr_desc == priv->tx_ring_size) {
631 priv->tx_curr_desc = 0;
632 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
633 }
634 priv->tx_desc_count--;
635
636 /* dma might be already polling, make sure we update desc
637 * fields in correct order */
638 wmb();
639 desc->len_stat = len_stat;
640 wmb();
641
642 /* kick tx dma */
643 enet_dmac_writel(priv, priv->dma_chan_en_mask,
644 ENETDMAC_CHANCFG, priv->tx_chan);
645
646 /* stop queue if no more desc available */
647 if (!priv->tx_desc_count)
648 netif_stop_queue(dev);
649
650 dev->stats.tx_bytes += skb->len;
651 dev->stats.tx_packets++;
652 ret = NETDEV_TX_OK;
653
654 out_unlock:
655 spin_unlock(&priv->tx_lock);
656 return ret;
657 }
658
659 /*
660 * Change the interface's mac address.
661 */
662 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
663 {
664 struct bcm_enet_priv *priv;
665 struct sockaddr *addr = p;
666 u32 val;
667
668 priv = netdev_priv(dev);
669 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
670
671 /* use perfect match register 0 to store my mac address */
672 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
673 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
674 enet_writel(priv, val, ENET_PML_REG(0));
675
676 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
677 val |= ENET_PMH_DATAVALID_MASK;
678 enet_writel(priv, val, ENET_PMH_REG(0));
679
680 return 0;
681 }
682
683 /*
684 * Change rx mode (promiscuous/allmulti) and update multicast list
685 */
686 static void bcm_enet_set_multicast_list(struct net_device *dev)
687 {
688 struct bcm_enet_priv *priv;
689 struct netdev_hw_addr *ha;
690 u32 val;
691 int i;
692
693 priv = netdev_priv(dev);
694
695 val = enet_readl(priv, ENET_RXCFG_REG);
696
697 if (dev->flags & IFF_PROMISC)
698 val |= ENET_RXCFG_PROMISC_MASK;
699 else
700 val &= ~ENET_RXCFG_PROMISC_MASK;
701
702 /* only 3 perfect match registers left, first one is used for
703 * own mac address */
704 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
705 val |= ENET_RXCFG_ALLMCAST_MASK;
706 else
707 val &= ~ENET_RXCFG_ALLMCAST_MASK;
708
709 /* no need to set perfect match registers if we catch all
710 * multicast */
711 if (val & ENET_RXCFG_ALLMCAST_MASK) {
712 enet_writel(priv, val, ENET_RXCFG_REG);
713 return;
714 }
715
716 i = 0;
717 netdev_for_each_mc_addr(ha, dev) {
718 u8 *dmi_addr;
719 u32 tmp;
720
721 if (i == 3)
722 break;
723 /* update perfect match registers */
724 dmi_addr = ha->addr;
725 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
726 (dmi_addr[4] << 8) | dmi_addr[5];
727 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
728
729 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
730 tmp |= ENET_PMH_DATAVALID_MASK;
731 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
732 }
733
734 for (; i < 3; i++) {
735 enet_writel(priv, 0, ENET_PML_REG(i + 1));
736 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
737 }
738
739 enet_writel(priv, val, ENET_RXCFG_REG);
740 }
741
742 /*
743 * set mac duplex parameters
744 */
745 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
746 {
747 u32 val;
748
749 val = enet_readl(priv, ENET_TXCTL_REG);
750 if (fullduplex)
751 val |= ENET_TXCTL_FD_MASK;
752 else
753 val &= ~ENET_TXCTL_FD_MASK;
754 enet_writel(priv, val, ENET_TXCTL_REG);
755 }
756
757 /*
758 * set mac flow control parameters
759 */
760 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
761 {
762 u32 val;
763
764 /* rx flow control (pause frame handling) */
765 val = enet_readl(priv, ENET_RXCFG_REG);
766 if (rx_en)
767 val |= ENET_RXCFG_ENFLOW_MASK;
768 else
769 val &= ~ENET_RXCFG_ENFLOW_MASK;
770 enet_writel(priv, val, ENET_RXCFG_REG);
771
772 if (!priv->dma_has_sram)
773 return;
774
775 /* tx flow control (pause frame generation) */
776 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
777 if (tx_en)
778 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
779 else
780 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
781 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
782 }
783
784 /*
785 * link changed callback (from phylib)
786 */
787 static void bcm_enet_adjust_phy_link(struct net_device *dev)
788 {
789 struct bcm_enet_priv *priv;
790 struct phy_device *phydev;
791 int status_changed;
792
793 priv = netdev_priv(dev);
794 phydev = dev->phydev;
795 status_changed = 0;
796
797 if (priv->old_link != phydev->link) {
798 status_changed = 1;
799 priv->old_link = phydev->link;
800 }
801
802 /* reflect duplex change in mac configuration */
803 if (phydev->link && phydev->duplex != priv->old_duplex) {
804 bcm_enet_set_duplex(priv,
805 (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
806 status_changed = 1;
807 priv->old_duplex = phydev->duplex;
808 }
809
810 /* enable flow control if remote advertise it (trust phylib to
811 * check that duplex is full */
812 if (phydev->link && phydev->pause != priv->old_pause) {
813 int rx_pause_en, tx_pause_en;
814
815 if (phydev->pause) {
816 /* pause was advertised by lpa and us */
817 rx_pause_en = 1;
818 tx_pause_en = 1;
819 } else if (!priv->pause_auto) {
820 /* pause setting overrided by user */
821 rx_pause_en = priv->pause_rx;
822 tx_pause_en = priv->pause_tx;
823 } else {
824 rx_pause_en = 0;
825 tx_pause_en = 0;
826 }
827
828 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
829 status_changed = 1;
830 priv->old_pause = phydev->pause;
831 }
832
833 if (status_changed) {
834 pr_info("%s: link %s", dev->name, phydev->link ?
835 "UP" : "DOWN");
836 if (phydev->link)
837 pr_cont(" - %d/%s - flow control %s", phydev->speed,
838 DUPLEX_FULL == phydev->duplex ? "full" : "half",
839 phydev->pause == 1 ? "rx&tx" : "off");
840
841 pr_cont("\n");
842 }
843 }
844
845 /*
846 * link changed callback (if phylib is not used)
847 */
848 static void bcm_enet_adjust_link(struct net_device *dev)
849 {
850 struct bcm_enet_priv *priv;
851
852 priv = netdev_priv(dev);
853 bcm_enet_set_duplex(priv, priv->force_duplex_full);
854 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
855 netif_carrier_on(dev);
856
857 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
858 dev->name,
859 priv->force_speed_100 ? 100 : 10,
860 priv->force_duplex_full ? "full" : "half",
861 priv->pause_rx ? "rx" : "off",
862 priv->pause_tx ? "tx" : "off");
863 }
864
865 /*
866 * open callback, allocate dma rings & buffers and start rx operation
867 */
868 static int bcm_enet_open(struct net_device *dev)
869 {
870 struct bcm_enet_priv *priv;
871 struct sockaddr addr;
872 struct device *kdev;
873 struct phy_device *phydev;
874 int i, ret;
875 unsigned int size;
876 char phy_id[MII_BUS_ID_SIZE + 3];
877 void *p;
878 u32 val;
879
880 priv = netdev_priv(dev);
881 kdev = &priv->pdev->dev;
882
883 if (priv->has_phy) {
884 /* connect to PHY */
885 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
886 priv->mii_bus->id, priv->phy_id);
887
888 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
889 PHY_INTERFACE_MODE_MII);
890
891 if (IS_ERR(phydev)) {
892 dev_err(kdev, "could not attach to PHY\n");
893 return PTR_ERR(phydev);
894 }
895
896 /* mask with MAC supported features */
897 phydev->supported &= (SUPPORTED_10baseT_Half |
898 SUPPORTED_10baseT_Full |
899 SUPPORTED_100baseT_Half |
900 SUPPORTED_100baseT_Full |
901 SUPPORTED_Autoneg |
902 SUPPORTED_Pause |
903 SUPPORTED_MII);
904 phydev->advertising = phydev->supported;
905
906 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
907 phydev->advertising |= SUPPORTED_Pause;
908 else
909 phydev->advertising &= ~SUPPORTED_Pause;
910
911 phy_attached_info(phydev);
912
913 priv->old_link = 0;
914 priv->old_duplex = -1;
915 priv->old_pause = -1;
916 } else {
917 phydev = NULL;
918 }
919
920 /* mask all interrupts and request them */
921 enet_writel(priv, 0, ENET_IRMASK_REG);
922 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
923 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
924
925 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
926 if (ret)
927 goto out_phy_disconnect;
928
929 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
930 dev->name, dev);
931 if (ret)
932 goto out_freeirq;
933
934 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
935 0, dev->name, dev);
936 if (ret)
937 goto out_freeirq_rx;
938
939 /* initialize perfect match registers */
940 for (i = 0; i < 4; i++) {
941 enet_writel(priv, 0, ENET_PML_REG(i));
942 enet_writel(priv, 0, ENET_PMH_REG(i));
943 }
944
945 /* write device mac address */
946 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
947 bcm_enet_set_mac_address(dev, &addr);
948
949 /* allocate rx dma ring */
950 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
951 p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
952 if (!p) {
953 ret = -ENOMEM;
954 goto out_freeirq_tx;
955 }
956
957 priv->rx_desc_alloc_size = size;
958 priv->rx_desc_cpu = p;
959
960 /* allocate tx dma ring */
961 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
962 p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
963 if (!p) {
964 ret = -ENOMEM;
965 goto out_free_rx_ring;
966 }
967
968 priv->tx_desc_alloc_size = size;
969 priv->tx_desc_cpu = p;
970
971 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
972 GFP_KERNEL);
973 if (!priv->tx_skb) {
974 ret = -ENOMEM;
975 goto out_free_tx_ring;
976 }
977
978 priv->tx_desc_count = priv->tx_ring_size;
979 priv->tx_dirty_desc = 0;
980 priv->tx_curr_desc = 0;
981 spin_lock_init(&priv->tx_lock);
982
983 /* init & fill rx ring with skbs */
984 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
985 GFP_KERNEL);
986 if (!priv->rx_skb) {
987 ret = -ENOMEM;
988 goto out_free_tx_skb;
989 }
990
991 priv->rx_desc_count = 0;
992 priv->rx_dirty_desc = 0;
993 priv->rx_curr_desc = 0;
994
995 /* initialize flow control buffer allocation */
996 if (priv->dma_has_sram)
997 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
998 ENETDMA_BUFALLOC_REG(priv->rx_chan));
999 else
1000 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
1001 ENETDMAC_BUFALLOC, priv->rx_chan);
1002
1003 if (bcm_enet_refill_rx(dev)) {
1004 dev_err(kdev, "cannot allocate rx skb queue\n");
1005 ret = -ENOMEM;
1006 goto out;
1007 }
1008
1009 /* write rx & tx ring addresses */
1010 if (priv->dma_has_sram) {
1011 enet_dmas_writel(priv, priv->rx_desc_dma,
1012 ENETDMAS_RSTART_REG, priv->rx_chan);
1013 enet_dmas_writel(priv, priv->tx_desc_dma,
1014 ENETDMAS_RSTART_REG, priv->tx_chan);
1015 } else {
1016 enet_dmac_writel(priv, priv->rx_desc_dma,
1017 ENETDMAC_RSTART, priv->rx_chan);
1018 enet_dmac_writel(priv, priv->tx_desc_dma,
1019 ENETDMAC_RSTART, priv->tx_chan);
1020 }
1021
1022 /* clear remaining state ram for rx & tx channel */
1023 if (priv->dma_has_sram) {
1024 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1025 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1026 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1027 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1028 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1029 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1030 } else {
1031 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1032 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1033 }
1034
1035 /* set max rx/tx length */
1036 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1037 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1038
1039 /* set dma maximum burst len */
1040 enet_dmac_writel(priv, priv->dma_maxburst,
1041 ENETDMAC_MAXBURST, priv->rx_chan);
1042 enet_dmac_writel(priv, priv->dma_maxburst,
1043 ENETDMAC_MAXBURST, priv->tx_chan);
1044
1045 /* set correct transmit fifo watermark */
1046 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1047
1048 /* set flow control low/high threshold to 1/3 / 2/3 */
1049 if (priv->dma_has_sram) {
1050 val = priv->rx_ring_size / 3;
1051 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1052 val = (priv->rx_ring_size * 2) / 3;
1053 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1054 } else {
1055 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1056 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1057 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1058 }
1059
1060 /* all set, enable mac and interrupts, start dma engine and
1061 * kick rx dma channel */
1062 wmb();
1063 val = enet_readl(priv, ENET_CTL_REG);
1064 val |= ENET_CTL_ENABLE_MASK;
1065 enet_writel(priv, val, ENET_CTL_REG);
1066 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1067 enet_dmac_writel(priv, priv->dma_chan_en_mask,
1068 ENETDMAC_CHANCFG, priv->rx_chan);
1069
1070 /* watch "mib counters about to overflow" interrupt */
1071 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1072 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1073
1074 /* watch "packet transferred" interrupt in rx and tx */
1075 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1076 ENETDMAC_IR, priv->rx_chan);
1077 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1078 ENETDMAC_IR, priv->tx_chan);
1079
1080 /* make sure we enable napi before rx interrupt */
1081 napi_enable(&priv->napi);
1082
1083 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1084 ENETDMAC_IRMASK, priv->rx_chan);
1085 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1086 ENETDMAC_IRMASK, priv->tx_chan);
1087
1088 if (phydev)
1089 phy_start(phydev);
1090 else
1091 bcm_enet_adjust_link(dev);
1092
1093 netif_start_queue(dev);
1094 return 0;
1095
1096 out:
1097 for (i = 0; i < priv->rx_ring_size; i++) {
1098 struct bcm_enet_desc *desc;
1099
1100 if (!priv->rx_skb[i])
1101 continue;
1102
1103 desc = &priv->rx_desc_cpu[i];
1104 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1105 DMA_FROM_DEVICE);
1106 kfree_skb(priv->rx_skb[i]);
1107 }
1108 kfree(priv->rx_skb);
1109
1110 out_free_tx_skb:
1111 kfree(priv->tx_skb);
1112
1113 out_free_tx_ring:
1114 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1115 priv->tx_desc_cpu, priv->tx_desc_dma);
1116
1117 out_free_rx_ring:
1118 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1119 priv->rx_desc_cpu, priv->rx_desc_dma);
1120
1121 out_freeirq_tx:
1122 free_irq(priv->irq_tx, dev);
1123
1124 out_freeirq_rx:
1125 free_irq(priv->irq_rx, dev);
1126
1127 out_freeirq:
1128 free_irq(dev->irq, dev);
1129
1130 out_phy_disconnect:
1131 if (phydev)
1132 phy_disconnect(phydev);
1133
1134 return ret;
1135 }
1136
1137 /*
1138 * disable mac
1139 */
1140 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1141 {
1142 int limit;
1143 u32 val;
1144
1145 val = enet_readl(priv, ENET_CTL_REG);
1146 val |= ENET_CTL_DISABLE_MASK;
1147 enet_writel(priv, val, ENET_CTL_REG);
1148
1149 limit = 1000;
1150 do {
1151 u32 val;
1152
1153 val = enet_readl(priv, ENET_CTL_REG);
1154 if (!(val & ENET_CTL_DISABLE_MASK))
1155 break;
1156 udelay(1);
1157 } while (limit--);
1158 }
1159
1160 /*
1161 * disable dma in given channel
1162 */
1163 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1164 {
1165 int limit;
1166
1167 enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1168
1169 limit = 1000;
1170 do {
1171 u32 val;
1172
1173 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1174 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1175 break;
1176 udelay(1);
1177 } while (limit--);
1178 }
1179
1180 /*
1181 * stop callback
1182 */
1183 static int bcm_enet_stop(struct net_device *dev)
1184 {
1185 struct bcm_enet_priv *priv;
1186 struct device *kdev;
1187 int i;
1188
1189 priv = netdev_priv(dev);
1190 kdev = &priv->pdev->dev;
1191
1192 netif_stop_queue(dev);
1193 napi_disable(&priv->napi);
1194 if (priv->has_phy)
1195 phy_stop(dev->phydev);
1196 del_timer_sync(&priv->rx_timeout);
1197
1198 /* mask all interrupts */
1199 enet_writel(priv, 0, ENET_IRMASK_REG);
1200 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1201 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1202
1203 /* make sure no mib update is scheduled */
1204 cancel_work_sync(&priv->mib_update_task);
1205
1206 /* disable dma & mac */
1207 bcm_enet_disable_dma(priv, priv->tx_chan);
1208 bcm_enet_disable_dma(priv, priv->rx_chan);
1209 bcm_enet_disable_mac(priv);
1210
1211 /* force reclaim of all tx buffers */
1212 bcm_enet_tx_reclaim(dev, 1);
1213
1214 /* free the rx skb ring */
1215 for (i = 0; i < priv->rx_ring_size; i++) {
1216 struct bcm_enet_desc *desc;
1217
1218 if (!priv->rx_skb[i])
1219 continue;
1220
1221 desc = &priv->rx_desc_cpu[i];
1222 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1223 DMA_FROM_DEVICE);
1224 kfree_skb(priv->rx_skb[i]);
1225 }
1226
1227 /* free remaining allocated memory */
1228 kfree(priv->rx_skb);
1229 kfree(priv->tx_skb);
1230 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1231 priv->rx_desc_cpu, priv->rx_desc_dma);
1232 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1233 priv->tx_desc_cpu, priv->tx_desc_dma);
1234 free_irq(priv->irq_tx, dev);
1235 free_irq(priv->irq_rx, dev);
1236 free_irq(dev->irq, dev);
1237
1238 /* release phy */
1239 if (priv->has_phy)
1240 phy_disconnect(dev->phydev);
1241
1242 return 0;
1243 }
1244
1245 /*
1246 * ethtool callbacks
1247 */
1248 struct bcm_enet_stats {
1249 char stat_string[ETH_GSTRING_LEN];
1250 int sizeof_stat;
1251 int stat_offset;
1252 int mib_reg;
1253 };
1254
1255 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \
1256 offsetof(struct bcm_enet_priv, m)
1257 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \
1258 offsetof(struct net_device_stats, m)
1259
1260 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1261 { "rx_packets", DEV_STAT(rx_packets), -1 },
1262 { "tx_packets", DEV_STAT(tx_packets), -1 },
1263 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1264 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1265 { "rx_errors", DEV_STAT(rx_errors), -1 },
1266 { "tx_errors", DEV_STAT(tx_errors), -1 },
1267 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1268 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1269
1270 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1271 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1272 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1273 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1274 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1275 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1276 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1277 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1278 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1279 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1280 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1281 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1282 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1283 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1284 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1285 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1286 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1287 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1288 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1289 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1290 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1291
1292 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1293 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1294 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1295 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1296 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1297 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1298 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1299 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1300 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1301 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1302 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1303 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1304 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1305 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1306 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1307 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1308 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1309 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1310 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1311 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1312 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1313 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1314
1315 };
1316
1317 #define BCM_ENET_STATS_LEN ARRAY_SIZE(bcm_enet_gstrings_stats)
1318
1319 static const u32 unused_mib_regs[] = {
1320 ETH_MIB_TX_ALL_OCTETS,
1321 ETH_MIB_TX_ALL_PKTS,
1322 ETH_MIB_RX_ALL_OCTETS,
1323 ETH_MIB_RX_ALL_PKTS,
1324 };
1325
1326
1327 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1328 struct ethtool_drvinfo *drvinfo)
1329 {
1330 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1331 strlcpy(drvinfo->version, bcm_enet_driver_version,
1332 sizeof(drvinfo->version));
1333 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1334 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1335 }
1336
1337 static int bcm_enet_get_sset_count(struct net_device *netdev,
1338 int string_set)
1339 {
1340 switch (string_set) {
1341 case ETH_SS_STATS:
1342 return BCM_ENET_STATS_LEN;
1343 default:
1344 return -EINVAL;
1345 }
1346 }
1347
1348 static void bcm_enet_get_strings(struct net_device *netdev,
1349 u32 stringset, u8 *data)
1350 {
1351 int i;
1352
1353 switch (stringset) {
1354 case ETH_SS_STATS:
1355 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1356 memcpy(data + i * ETH_GSTRING_LEN,
1357 bcm_enet_gstrings_stats[i].stat_string,
1358 ETH_GSTRING_LEN);
1359 }
1360 break;
1361 }
1362 }
1363
1364 static void update_mib_counters(struct bcm_enet_priv *priv)
1365 {
1366 int i;
1367
1368 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1369 const struct bcm_enet_stats *s;
1370 u32 val;
1371 char *p;
1372
1373 s = &bcm_enet_gstrings_stats[i];
1374 if (s->mib_reg == -1)
1375 continue;
1376
1377 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1378 p = (char *)priv + s->stat_offset;
1379
1380 if (s->sizeof_stat == sizeof(u64))
1381 *(u64 *)p += val;
1382 else
1383 *(u32 *)p += val;
1384 }
1385
1386 /* also empty unused mib counters to make sure mib counter
1387 * overflow interrupt is cleared */
1388 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1389 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1390 }
1391
1392 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1393 {
1394 struct bcm_enet_priv *priv;
1395
1396 priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1397 mutex_lock(&priv->mib_update_lock);
1398 update_mib_counters(priv);
1399 mutex_unlock(&priv->mib_update_lock);
1400
1401 /* reenable mib interrupt */
1402 if (netif_running(priv->net_dev))
1403 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1404 }
1405
1406 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1407 struct ethtool_stats *stats,
1408 u64 *data)
1409 {
1410 struct bcm_enet_priv *priv;
1411 int i;
1412
1413 priv = netdev_priv(netdev);
1414
1415 mutex_lock(&priv->mib_update_lock);
1416 update_mib_counters(priv);
1417
1418 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1419 const struct bcm_enet_stats *s;
1420 char *p;
1421
1422 s = &bcm_enet_gstrings_stats[i];
1423 if (s->mib_reg == -1)
1424 p = (char *)&netdev->stats;
1425 else
1426 p = (char *)priv;
1427 p += s->stat_offset;
1428 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1429 *(u64 *)p : *(u32 *)p;
1430 }
1431 mutex_unlock(&priv->mib_update_lock);
1432 }
1433
1434 static int bcm_enet_nway_reset(struct net_device *dev)
1435 {
1436 struct bcm_enet_priv *priv;
1437
1438 priv = netdev_priv(dev);
1439 if (priv->has_phy) {
1440 if (!dev->phydev)
1441 return -ENODEV;
1442 return genphy_restart_aneg(dev->phydev);
1443 }
1444
1445 return -EOPNOTSUPP;
1446 }
1447
1448 static int bcm_enet_get_link_ksettings(struct net_device *dev,
1449 struct ethtool_link_ksettings *cmd)
1450 {
1451 struct bcm_enet_priv *priv;
1452 u32 supported, advertising;
1453
1454 priv = netdev_priv(dev);
1455
1456 if (priv->has_phy) {
1457 if (!dev->phydev)
1458 return -ENODEV;
1459 return phy_ethtool_ksettings_get(dev->phydev, cmd);
1460 } else {
1461 cmd->base.autoneg = 0;
1462 cmd->base.speed = (priv->force_speed_100) ?
1463 SPEED_100 : SPEED_10;
1464 cmd->base.duplex = (priv->force_duplex_full) ?
1465 DUPLEX_FULL : DUPLEX_HALF;
1466 supported = ADVERTISED_10baseT_Half |
1467 ADVERTISED_10baseT_Full |
1468 ADVERTISED_100baseT_Half |
1469 ADVERTISED_100baseT_Full;
1470 advertising = 0;
1471 ethtool_convert_legacy_u32_to_link_mode(
1472 cmd->link_modes.supported, supported);
1473 ethtool_convert_legacy_u32_to_link_mode(
1474 cmd->link_modes.advertising, advertising);
1475 cmd->base.port = PORT_MII;
1476 }
1477 return 0;
1478 }
1479
1480 static int bcm_enet_set_link_ksettings(struct net_device *dev,
1481 const struct ethtool_link_ksettings *cmd)
1482 {
1483 struct bcm_enet_priv *priv;
1484
1485 priv = netdev_priv(dev);
1486 if (priv->has_phy) {
1487 if (!dev->phydev)
1488 return -ENODEV;
1489 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1490 } else {
1491
1492 if (cmd->base.autoneg ||
1493 (cmd->base.speed != SPEED_100 &&
1494 cmd->base.speed != SPEED_10) ||
1495 cmd->base.port != PORT_MII)
1496 return -EINVAL;
1497
1498 priv->force_speed_100 =
1499 (cmd->base.speed == SPEED_100) ? 1 : 0;
1500 priv->force_duplex_full =
1501 (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1502
1503 if (netif_running(dev))
1504 bcm_enet_adjust_link(dev);
1505 return 0;
1506 }
1507 }
1508
1509 static void bcm_enet_get_ringparam(struct net_device *dev,
1510 struct ethtool_ringparam *ering)
1511 {
1512 struct bcm_enet_priv *priv;
1513
1514 priv = netdev_priv(dev);
1515
1516 /* rx/tx ring is actually only limited by memory */
1517 ering->rx_max_pending = 8192;
1518 ering->tx_max_pending = 8192;
1519 ering->rx_pending = priv->rx_ring_size;
1520 ering->tx_pending = priv->tx_ring_size;
1521 }
1522
1523 static int bcm_enet_set_ringparam(struct net_device *dev,
1524 struct ethtool_ringparam *ering)
1525 {
1526 struct bcm_enet_priv *priv;
1527 int was_running;
1528
1529 priv = netdev_priv(dev);
1530
1531 was_running = 0;
1532 if (netif_running(dev)) {
1533 bcm_enet_stop(dev);
1534 was_running = 1;
1535 }
1536
1537 priv->rx_ring_size = ering->rx_pending;
1538 priv->tx_ring_size = ering->tx_pending;
1539
1540 if (was_running) {
1541 int err;
1542
1543 err = bcm_enet_open(dev);
1544 if (err)
1545 dev_close(dev);
1546 else
1547 bcm_enet_set_multicast_list(dev);
1548 }
1549 return 0;
1550 }
1551
1552 static void bcm_enet_get_pauseparam(struct net_device *dev,
1553 struct ethtool_pauseparam *ecmd)
1554 {
1555 struct bcm_enet_priv *priv;
1556
1557 priv = netdev_priv(dev);
1558 ecmd->autoneg = priv->pause_auto;
1559 ecmd->rx_pause = priv->pause_rx;
1560 ecmd->tx_pause = priv->pause_tx;
1561 }
1562
1563 static int bcm_enet_set_pauseparam(struct net_device *dev,
1564 struct ethtool_pauseparam *ecmd)
1565 {
1566 struct bcm_enet_priv *priv;
1567
1568 priv = netdev_priv(dev);
1569
1570 if (priv->has_phy) {
1571 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1572 /* asymetric pause mode not supported,
1573 * actually possible but integrated PHY has RO
1574 * asym_pause bit */
1575 return -EINVAL;
1576 }
1577 } else {
1578 /* no pause autoneg on direct mii connection */
1579 if (ecmd->autoneg)
1580 return -EINVAL;
1581 }
1582
1583 priv->pause_auto = ecmd->autoneg;
1584 priv->pause_rx = ecmd->rx_pause;
1585 priv->pause_tx = ecmd->tx_pause;
1586
1587 return 0;
1588 }
1589
1590 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1591 .get_strings = bcm_enet_get_strings,
1592 .get_sset_count = bcm_enet_get_sset_count,
1593 .get_ethtool_stats = bcm_enet_get_ethtool_stats,
1594 .nway_reset = bcm_enet_nway_reset,
1595 .get_drvinfo = bcm_enet_get_drvinfo,
1596 .get_link = ethtool_op_get_link,
1597 .get_ringparam = bcm_enet_get_ringparam,
1598 .set_ringparam = bcm_enet_set_ringparam,
1599 .get_pauseparam = bcm_enet_get_pauseparam,
1600 .set_pauseparam = bcm_enet_set_pauseparam,
1601 .get_link_ksettings = bcm_enet_get_link_ksettings,
1602 .set_link_ksettings = bcm_enet_set_link_ksettings,
1603 };
1604
1605 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1606 {
1607 struct bcm_enet_priv *priv;
1608
1609 priv = netdev_priv(dev);
1610 if (priv->has_phy) {
1611 if (!dev->phydev)
1612 return -ENODEV;
1613 return phy_mii_ioctl(dev->phydev, rq, cmd);
1614 } else {
1615 struct mii_if_info mii;
1616
1617 mii.dev = dev;
1618 mii.mdio_read = bcm_enet_mdio_read_mii;
1619 mii.mdio_write = bcm_enet_mdio_write_mii;
1620 mii.phy_id = 0;
1621 mii.phy_id_mask = 0x3f;
1622 mii.reg_num_mask = 0x1f;
1623 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1624 }
1625 }
1626
1627 /*
1628 * calculate actual hardware mtu
1629 */
1630 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1631 {
1632 int actual_mtu;
1633
1634 actual_mtu = mtu;
1635
1636 /* add ethernet header + vlan tag size */
1637 actual_mtu += VLAN_ETH_HLEN;
1638
1639 if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1640 return -EINVAL;
1641
1642 /*
1643 * setup maximum size before we get overflow mark in
1644 * descriptor, note that this will not prevent reception of
1645 * big frames, they will be split into multiple buffers
1646 * anyway
1647 */
1648 priv->hw_mtu = actual_mtu;
1649
1650 /*
1651 * align rx buffer size to dma burst len, account FCS since
1652 * it's appended
1653 */
1654 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1655 priv->dma_maxburst * 4);
1656 return 0;
1657 }
1658
1659 /*
1660 * adjust mtu, can't be called while device is running
1661 */
1662 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1663 {
1664 int ret;
1665
1666 if (netif_running(dev))
1667 return -EBUSY;
1668
1669 ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1670 if (ret)
1671 return ret;
1672 dev->mtu = new_mtu;
1673 return 0;
1674 }
1675
1676 /*
1677 * preinit hardware to allow mii operation while device is down
1678 */
1679 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1680 {
1681 u32 val;
1682 int limit;
1683
1684 /* make sure mac is disabled */
1685 bcm_enet_disable_mac(priv);
1686
1687 /* soft reset mac */
1688 val = ENET_CTL_SRESET_MASK;
1689 enet_writel(priv, val, ENET_CTL_REG);
1690 wmb();
1691
1692 limit = 1000;
1693 do {
1694 val = enet_readl(priv, ENET_CTL_REG);
1695 if (!(val & ENET_CTL_SRESET_MASK))
1696 break;
1697 udelay(1);
1698 } while (limit--);
1699
1700 /* select correct mii interface */
1701 val = enet_readl(priv, ENET_CTL_REG);
1702 if (priv->use_external_mii)
1703 val |= ENET_CTL_EPHYSEL_MASK;
1704 else
1705 val &= ~ENET_CTL_EPHYSEL_MASK;
1706 enet_writel(priv, val, ENET_CTL_REG);
1707
1708 /* turn on mdc clock */
1709 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1710 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1711
1712 /* set mib counters to self-clear when read */
1713 val = enet_readl(priv, ENET_MIBCTL_REG);
1714 val |= ENET_MIBCTL_RDCLEAR_MASK;
1715 enet_writel(priv, val, ENET_MIBCTL_REG);
1716 }
1717
1718 static const struct net_device_ops bcm_enet_ops = {
1719 .ndo_open = bcm_enet_open,
1720 .ndo_stop = bcm_enet_stop,
1721 .ndo_start_xmit = bcm_enet_start_xmit,
1722 .ndo_set_mac_address = bcm_enet_set_mac_address,
1723 .ndo_set_rx_mode = bcm_enet_set_multicast_list,
1724 .ndo_do_ioctl = bcm_enet_ioctl,
1725 .ndo_change_mtu = bcm_enet_change_mtu,
1726 };
1727
1728 /*
1729 * allocate netdevice, request register memory and register device.
1730 */
1731 static int bcm_enet_probe(struct platform_device *pdev)
1732 {
1733 struct bcm_enet_priv *priv;
1734 struct net_device *dev;
1735 struct bcm63xx_enet_platform_data *pd;
1736 struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1737 struct mii_bus *bus;
1738 const char *clk_name;
1739 int i, ret;
1740
1741 /* stop if shared driver failed, assume driver->probe will be
1742 * called in the same order we register devices (correct ?) */
1743 if (!bcm_enet_shared_base[0])
1744 return -ENODEV;
1745
1746 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1747 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1748 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1749 if (!res_irq || !res_irq_rx || !res_irq_tx)
1750 return -ENODEV;
1751
1752 ret = 0;
1753 dev = alloc_etherdev(sizeof(*priv));
1754 if (!dev)
1755 return -ENOMEM;
1756 priv = netdev_priv(dev);
1757
1758 priv->enet_is_sw = false;
1759 priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1760
1761 ret = compute_hw_mtu(priv, dev->mtu);
1762 if (ret)
1763 goto out;
1764
1765 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1766 priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1767 if (IS_ERR(priv->base)) {
1768 ret = PTR_ERR(priv->base);
1769 goto out;
1770 }
1771
1772 dev->irq = priv->irq = res_irq->start;
1773 priv->irq_rx = res_irq_rx->start;
1774 priv->irq_tx = res_irq_tx->start;
1775 priv->mac_id = pdev->id;
1776
1777 /* get rx & tx dma channel id for this mac */
1778 if (priv->mac_id == 0) {
1779 priv->rx_chan = 0;
1780 priv->tx_chan = 1;
1781 clk_name = "enet0";
1782 } else {
1783 priv->rx_chan = 2;
1784 priv->tx_chan = 3;
1785 clk_name = "enet1";
1786 }
1787
1788 priv->mac_clk = clk_get(&pdev->dev, clk_name);
1789 if (IS_ERR(priv->mac_clk)) {
1790 ret = PTR_ERR(priv->mac_clk);
1791 goto out;
1792 }
1793 clk_prepare_enable(priv->mac_clk);
1794
1795 /* initialize default and fetch platform data */
1796 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1797 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1798
1799 pd = dev_get_platdata(&pdev->dev);
1800 if (pd) {
1801 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1802 priv->has_phy = pd->has_phy;
1803 priv->phy_id = pd->phy_id;
1804 priv->has_phy_interrupt = pd->has_phy_interrupt;
1805 priv->phy_interrupt = pd->phy_interrupt;
1806 priv->use_external_mii = !pd->use_internal_phy;
1807 priv->pause_auto = pd->pause_auto;
1808 priv->pause_rx = pd->pause_rx;
1809 priv->pause_tx = pd->pause_tx;
1810 priv->force_duplex_full = pd->force_duplex_full;
1811 priv->force_speed_100 = pd->force_speed_100;
1812 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1813 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1814 priv->dma_chan_width = pd->dma_chan_width;
1815 priv->dma_has_sram = pd->dma_has_sram;
1816 priv->dma_desc_shift = pd->dma_desc_shift;
1817 }
1818
1819 if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1820 /* using internal PHY, enable clock */
1821 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1822 if (IS_ERR(priv->phy_clk)) {
1823 ret = PTR_ERR(priv->phy_clk);
1824 priv->phy_clk = NULL;
1825 goto out_put_clk_mac;
1826 }
1827 clk_prepare_enable(priv->phy_clk);
1828 }
1829
1830 /* do minimal hardware init to be able to probe mii bus */
1831 bcm_enet_hw_preinit(priv);
1832
1833 /* MII bus registration */
1834 if (priv->has_phy) {
1835
1836 priv->mii_bus = mdiobus_alloc();
1837 if (!priv->mii_bus) {
1838 ret = -ENOMEM;
1839 goto out_uninit_hw;
1840 }
1841
1842 bus = priv->mii_bus;
1843 bus->name = "bcm63xx_enet MII bus";
1844 bus->parent = &pdev->dev;
1845 bus->priv = priv;
1846 bus->read = bcm_enet_mdio_read_phylib;
1847 bus->write = bcm_enet_mdio_write_phylib;
1848 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1849
1850 /* only probe bus where we think the PHY is, because
1851 * the mdio read operation return 0 instead of 0xffff
1852 * if a slave is not present on hw */
1853 bus->phy_mask = ~(1 << priv->phy_id);
1854
1855 if (priv->has_phy_interrupt)
1856 bus->irq[priv->phy_id] = priv->phy_interrupt;
1857
1858 ret = mdiobus_register(bus);
1859 if (ret) {
1860 dev_err(&pdev->dev, "unable to register mdio bus\n");
1861 goto out_free_mdio;
1862 }
1863 } else {
1864
1865 /* run platform code to initialize PHY device */
1866 if (pd && pd->mii_config &&
1867 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1868 bcm_enet_mdio_write_mii)) {
1869 dev_err(&pdev->dev, "unable to configure mdio bus\n");
1870 goto out_uninit_hw;
1871 }
1872 }
1873
1874 spin_lock_init(&priv->rx_lock);
1875
1876 /* init rx timeout (used for oom) */
1877 init_timer(&priv->rx_timeout);
1878 priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1879 priv->rx_timeout.data = (unsigned long)dev;
1880
1881 /* init the mib update lock&work */
1882 mutex_init(&priv->mib_update_lock);
1883 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1884
1885 /* zero mib counters */
1886 for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1887 enet_writel(priv, 0, ENET_MIB_REG(i));
1888
1889 /* register netdevice */
1890 dev->netdev_ops = &bcm_enet_ops;
1891 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1892
1893 dev->ethtool_ops = &bcm_enet_ethtool_ops;
1894 SET_NETDEV_DEV(dev, &pdev->dev);
1895
1896 ret = register_netdev(dev);
1897 if (ret)
1898 goto out_unregister_mdio;
1899
1900 netif_carrier_off(dev);
1901 platform_set_drvdata(pdev, dev);
1902 priv->pdev = pdev;
1903 priv->net_dev = dev;
1904
1905 return 0;
1906
1907 out_unregister_mdio:
1908 if (priv->mii_bus)
1909 mdiobus_unregister(priv->mii_bus);
1910
1911 out_free_mdio:
1912 if (priv->mii_bus)
1913 mdiobus_free(priv->mii_bus);
1914
1915 out_uninit_hw:
1916 /* turn off mdc clock */
1917 enet_writel(priv, 0, ENET_MIISC_REG);
1918 if (priv->phy_clk) {
1919 clk_disable_unprepare(priv->phy_clk);
1920 clk_put(priv->phy_clk);
1921 }
1922
1923 out_put_clk_mac:
1924 clk_disable_unprepare(priv->mac_clk);
1925 clk_put(priv->mac_clk);
1926 out:
1927 free_netdev(dev);
1928 return ret;
1929 }
1930
1931
1932 /*
1933 * exit func, stops hardware and unregisters netdevice
1934 */
1935 static int bcm_enet_remove(struct platform_device *pdev)
1936 {
1937 struct bcm_enet_priv *priv;
1938 struct net_device *dev;
1939
1940 /* stop netdevice */
1941 dev = platform_get_drvdata(pdev);
1942 priv = netdev_priv(dev);
1943 unregister_netdev(dev);
1944
1945 /* turn off mdc clock */
1946 enet_writel(priv, 0, ENET_MIISC_REG);
1947
1948 if (priv->has_phy) {
1949 mdiobus_unregister(priv->mii_bus);
1950 mdiobus_free(priv->mii_bus);
1951 } else {
1952 struct bcm63xx_enet_platform_data *pd;
1953
1954 pd = dev_get_platdata(&pdev->dev);
1955 if (pd && pd->mii_config)
1956 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1957 bcm_enet_mdio_write_mii);
1958 }
1959
1960 /* disable hw block clocks */
1961 if (priv->phy_clk) {
1962 clk_disable_unprepare(priv->phy_clk);
1963 clk_put(priv->phy_clk);
1964 }
1965 clk_disable_unprepare(priv->mac_clk);
1966 clk_put(priv->mac_clk);
1967
1968 free_netdev(dev);
1969 return 0;
1970 }
1971
1972 struct platform_driver bcm63xx_enet_driver = {
1973 .probe = bcm_enet_probe,
1974 .remove = bcm_enet_remove,
1975 .driver = {
1976 .name = "bcm63xx_enet",
1977 .owner = THIS_MODULE,
1978 },
1979 };
1980
1981 /*
1982 * switch mii access callbacks
1983 */
1984 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1985 int ext, int phy_id, int location)
1986 {
1987 u32 reg;
1988 int ret;
1989
1990 spin_lock_bh(&priv->enetsw_mdio_lock);
1991 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1992
1993 reg = ENETSW_MDIOC_RD_MASK |
1994 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1995 (location << ENETSW_MDIOC_REG_SHIFT);
1996
1997 if (ext)
1998 reg |= ENETSW_MDIOC_EXT_MASK;
1999
2000 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2001 udelay(50);
2002 ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
2003 spin_unlock_bh(&priv->enetsw_mdio_lock);
2004 return ret;
2005 }
2006
2007 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
2008 int ext, int phy_id, int location,
2009 uint16_t data)
2010 {
2011 u32 reg;
2012
2013 spin_lock_bh(&priv->enetsw_mdio_lock);
2014 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2015
2016 reg = ENETSW_MDIOC_WR_MASK |
2017 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2018 (location << ENETSW_MDIOC_REG_SHIFT);
2019
2020 if (ext)
2021 reg |= ENETSW_MDIOC_EXT_MASK;
2022
2023 reg |= data;
2024
2025 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2026 udelay(50);
2027 spin_unlock_bh(&priv->enetsw_mdio_lock);
2028 }
2029
2030 static inline int bcm_enet_port_is_rgmii(int portid)
2031 {
2032 return portid >= ENETSW_RGMII_PORT0;
2033 }
2034
2035 /*
2036 * enet sw PHY polling
2037 */
2038 static void swphy_poll_timer(unsigned long data)
2039 {
2040 struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2041 unsigned int i;
2042
2043 for (i = 0; i < priv->num_ports; i++) {
2044 struct bcm63xx_enetsw_port *port;
2045 int val, j, up, advertise, lpa, speed, duplex, media;
2046 int external_phy = bcm_enet_port_is_rgmii(i);
2047 u8 override;
2048
2049 port = &priv->used_ports[i];
2050 if (!port->used)
2051 continue;
2052
2053 if (port->bypass_link)
2054 continue;
2055
2056 /* dummy read to clear */
2057 for (j = 0; j < 2; j++)
2058 val = bcmenet_sw_mdio_read(priv, external_phy,
2059 port->phy_id, MII_BMSR);
2060
2061 if (val == 0xffff)
2062 continue;
2063
2064 up = (val & BMSR_LSTATUS) ? 1 : 0;
2065 if (!(up ^ priv->sw_port_link[i]))
2066 continue;
2067
2068 priv->sw_port_link[i] = up;
2069
2070 /* link changed */
2071 if (!up) {
2072 dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2073 port->name);
2074 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2075 ENETSW_PORTOV_REG(i));
2076 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2077 ENETSW_PTCTRL_TXDIS_MASK,
2078 ENETSW_PTCTRL_REG(i));
2079 continue;
2080 }
2081
2082 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2083 port->phy_id, MII_ADVERTISE);
2084
2085 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2086 MII_LPA);
2087
2088 /* figure out media and duplex from advertise and LPA values */
2089 media = mii_nway_result(lpa & advertise);
2090 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2091
2092 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2093 speed = 100;
2094 else
2095 speed = 10;
2096
2097 if (val & BMSR_ESTATEN) {
2098 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2099 port->phy_id, MII_CTRL1000);
2100
2101 lpa = bcmenet_sw_mdio_read(priv, external_phy,
2102 port->phy_id, MII_STAT1000);
2103
2104 if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2105 && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2106 speed = 1000;
2107 duplex = (lpa & LPA_1000FULL);
2108 }
2109 }
2110
2111 dev_info(&priv->pdev->dev,
2112 "link UP on %s, %dMbps, %s-duplex\n",
2113 port->name, speed, duplex ? "full" : "half");
2114
2115 override = ENETSW_PORTOV_ENABLE_MASK |
2116 ENETSW_PORTOV_LINKUP_MASK;
2117
2118 if (speed == 1000)
2119 override |= ENETSW_IMPOV_1000_MASK;
2120 else if (speed == 100)
2121 override |= ENETSW_IMPOV_100_MASK;
2122 if (duplex)
2123 override |= ENETSW_IMPOV_FDX_MASK;
2124
2125 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2126 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2127 }
2128
2129 priv->swphy_poll.expires = jiffies + HZ;
2130 add_timer(&priv->swphy_poll);
2131 }
2132
2133 /*
2134 * open callback, allocate dma rings & buffers and start rx operation
2135 */
2136 static int bcm_enetsw_open(struct net_device *dev)
2137 {
2138 struct bcm_enet_priv *priv;
2139 struct device *kdev;
2140 int i, ret;
2141 unsigned int size;
2142 void *p;
2143 u32 val;
2144
2145 priv = netdev_priv(dev);
2146 kdev = &priv->pdev->dev;
2147
2148 /* mask all interrupts and request them */
2149 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2150 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2151
2152 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2153 0, dev->name, dev);
2154 if (ret)
2155 goto out_freeirq;
2156
2157 if (priv->irq_tx != -1) {
2158 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2159 0, dev->name, dev);
2160 if (ret)
2161 goto out_freeirq_rx;
2162 }
2163
2164 /* allocate rx dma ring */
2165 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2166 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2167 if (!p) {
2168 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2169 ret = -ENOMEM;
2170 goto out_freeirq_tx;
2171 }
2172
2173 memset(p, 0, size);
2174 priv->rx_desc_alloc_size = size;
2175 priv->rx_desc_cpu = p;
2176
2177 /* allocate tx dma ring */
2178 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2179 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2180 if (!p) {
2181 dev_err(kdev, "cannot allocate tx ring\n");
2182 ret = -ENOMEM;
2183 goto out_free_rx_ring;
2184 }
2185
2186 memset(p, 0, size);
2187 priv->tx_desc_alloc_size = size;
2188 priv->tx_desc_cpu = p;
2189
2190 priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2191 GFP_KERNEL);
2192 if (!priv->tx_skb) {
2193 dev_err(kdev, "cannot allocate rx skb queue\n");
2194 ret = -ENOMEM;
2195 goto out_free_tx_ring;
2196 }
2197
2198 priv->tx_desc_count = priv->tx_ring_size;
2199 priv->tx_dirty_desc = 0;
2200 priv->tx_curr_desc = 0;
2201 spin_lock_init(&priv->tx_lock);
2202
2203 /* init & fill rx ring with skbs */
2204 priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2205 GFP_KERNEL);
2206 if (!priv->rx_skb) {
2207 dev_err(kdev, "cannot allocate rx skb queue\n");
2208 ret = -ENOMEM;
2209 goto out_free_tx_skb;
2210 }
2211
2212 priv->rx_desc_count = 0;
2213 priv->rx_dirty_desc = 0;
2214 priv->rx_curr_desc = 0;
2215
2216 /* disable all ports */
2217 for (i = 0; i < priv->num_ports; i++) {
2218 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2219 ENETSW_PORTOV_REG(i));
2220 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2221 ENETSW_PTCTRL_TXDIS_MASK,
2222 ENETSW_PTCTRL_REG(i));
2223
2224 priv->sw_port_link[i] = 0;
2225 }
2226
2227 /* reset mib */
2228 val = enetsw_readb(priv, ENETSW_GMCR_REG);
2229 val |= ENETSW_GMCR_RST_MIB_MASK;
2230 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2231 mdelay(1);
2232 val &= ~ENETSW_GMCR_RST_MIB_MASK;
2233 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2234 mdelay(1);
2235
2236 /* force CPU port state */
2237 val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2238 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2239 enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2240
2241 /* enable switch forward engine */
2242 val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2243 val |= ENETSW_SWMODE_FWD_EN_MASK;
2244 enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2245
2246 /* enable jumbo on all ports */
2247 enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2248 enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2249
2250 /* initialize flow control buffer allocation */
2251 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2252 ENETDMA_BUFALLOC_REG(priv->rx_chan));
2253
2254 if (bcm_enet_refill_rx(dev)) {
2255 dev_err(kdev, "cannot allocate rx skb queue\n");
2256 ret = -ENOMEM;
2257 goto out;
2258 }
2259
2260 /* write rx & tx ring addresses */
2261 enet_dmas_writel(priv, priv->rx_desc_dma,
2262 ENETDMAS_RSTART_REG, priv->rx_chan);
2263 enet_dmas_writel(priv, priv->tx_desc_dma,
2264 ENETDMAS_RSTART_REG, priv->tx_chan);
2265
2266 /* clear remaining state ram for rx & tx channel */
2267 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2268 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2269 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2270 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2271 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2272 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2273
2274 /* set dma maximum burst len */
2275 enet_dmac_writel(priv, priv->dma_maxburst,
2276 ENETDMAC_MAXBURST, priv->rx_chan);
2277 enet_dmac_writel(priv, priv->dma_maxburst,
2278 ENETDMAC_MAXBURST, priv->tx_chan);
2279
2280 /* set flow control low/high threshold to 1/3 / 2/3 */
2281 val = priv->rx_ring_size / 3;
2282 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2283 val = (priv->rx_ring_size * 2) / 3;
2284 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2285
2286 /* all set, enable mac and interrupts, start dma engine and
2287 * kick rx dma channel
2288 */
2289 wmb();
2290 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2291 enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2292 ENETDMAC_CHANCFG, priv->rx_chan);
2293
2294 /* watch "packet transferred" interrupt in rx and tx */
2295 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2296 ENETDMAC_IR, priv->rx_chan);
2297 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2298 ENETDMAC_IR, priv->tx_chan);
2299
2300 /* make sure we enable napi before rx interrupt */
2301 napi_enable(&priv->napi);
2302
2303 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2304 ENETDMAC_IRMASK, priv->rx_chan);
2305 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2306 ENETDMAC_IRMASK, priv->tx_chan);
2307
2308 netif_carrier_on(dev);
2309 netif_start_queue(dev);
2310
2311 /* apply override config for bypass_link ports here. */
2312 for (i = 0; i < priv->num_ports; i++) {
2313 struct bcm63xx_enetsw_port *port;
2314 u8 override;
2315 port = &priv->used_ports[i];
2316 if (!port->used)
2317 continue;
2318
2319 if (!port->bypass_link)
2320 continue;
2321
2322 override = ENETSW_PORTOV_ENABLE_MASK |
2323 ENETSW_PORTOV_LINKUP_MASK;
2324
2325 switch (port->force_speed) {
2326 case 1000:
2327 override |= ENETSW_IMPOV_1000_MASK;
2328 break;
2329 case 100:
2330 override |= ENETSW_IMPOV_100_MASK;
2331 break;
2332 case 10:
2333 break;
2334 default:
2335 pr_warn("invalid forced speed on port %s: assume 10\n",
2336 port->name);
2337 break;
2338 }
2339
2340 if (port->force_duplex_full)
2341 override |= ENETSW_IMPOV_FDX_MASK;
2342
2343
2344 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2345 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2346 }
2347
2348 /* start phy polling timer */
2349 init_timer(&priv->swphy_poll);
2350 priv->swphy_poll.function = swphy_poll_timer;
2351 priv->swphy_poll.data = (unsigned long)priv;
2352 priv->swphy_poll.expires = jiffies;
2353 add_timer(&priv->swphy_poll);
2354 return 0;
2355
2356 out:
2357 for (i = 0; i < priv->rx_ring_size; i++) {
2358 struct bcm_enet_desc *desc;
2359
2360 if (!priv->rx_skb[i])
2361 continue;
2362
2363 desc = &priv->rx_desc_cpu[i];
2364 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2365 DMA_FROM_DEVICE);
2366 kfree_skb(priv->rx_skb[i]);
2367 }
2368 kfree(priv->rx_skb);
2369
2370 out_free_tx_skb:
2371 kfree(priv->tx_skb);
2372
2373 out_free_tx_ring:
2374 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2375 priv->tx_desc_cpu, priv->tx_desc_dma);
2376
2377 out_free_rx_ring:
2378 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2379 priv->rx_desc_cpu, priv->rx_desc_dma);
2380
2381 out_freeirq_tx:
2382 if (priv->irq_tx != -1)
2383 free_irq(priv->irq_tx, dev);
2384
2385 out_freeirq_rx:
2386 free_irq(priv->irq_rx, dev);
2387
2388 out_freeirq:
2389 return ret;
2390 }
2391
2392 /* stop callback */
2393 static int bcm_enetsw_stop(struct net_device *dev)
2394 {
2395 struct bcm_enet_priv *priv;
2396 struct device *kdev;
2397 int i;
2398
2399 priv = netdev_priv(dev);
2400 kdev = &priv->pdev->dev;
2401
2402 del_timer_sync(&priv->swphy_poll);
2403 netif_stop_queue(dev);
2404 napi_disable(&priv->napi);
2405 del_timer_sync(&priv->rx_timeout);
2406
2407 /* mask all interrupts */
2408 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2409 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2410
2411 /* disable dma & mac */
2412 bcm_enet_disable_dma(priv, priv->tx_chan);
2413 bcm_enet_disable_dma(priv, priv->rx_chan);
2414
2415 /* force reclaim of all tx buffers */
2416 bcm_enet_tx_reclaim(dev, 1);
2417
2418 /* free the rx skb ring */
2419 for (i = 0; i < priv->rx_ring_size; i++) {
2420 struct bcm_enet_desc *desc;
2421
2422 if (!priv->rx_skb[i])
2423 continue;
2424
2425 desc = &priv->rx_desc_cpu[i];
2426 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2427 DMA_FROM_DEVICE);
2428 kfree_skb(priv->rx_skb[i]);
2429 }
2430
2431 /* free remaining allocated memory */
2432 kfree(priv->rx_skb);
2433 kfree(priv->tx_skb);
2434 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2435 priv->rx_desc_cpu, priv->rx_desc_dma);
2436 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2437 priv->tx_desc_cpu, priv->tx_desc_dma);
2438 if (priv->irq_tx != -1)
2439 free_irq(priv->irq_tx, dev);
2440 free_irq(priv->irq_rx, dev);
2441
2442 return 0;
2443 }
2444
2445 /* try to sort out phy external status by walking the used_port field
2446 * in the bcm_enet_priv structure. in case the phy address is not
2447 * assigned to any physical port on the switch, assume it is external
2448 * (and yell at the user).
2449 */
2450 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2451 {
2452 int i;
2453
2454 for (i = 0; i < priv->num_ports; ++i) {
2455 if (!priv->used_ports[i].used)
2456 continue;
2457 if (priv->used_ports[i].phy_id == phy_id)
2458 return bcm_enet_port_is_rgmii(i);
2459 }
2460
2461 printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2462 phy_id);
2463 return 1;
2464 }
2465
2466 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2467 * external/internal status of the given phy_id first.
2468 */
2469 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2470 int location)
2471 {
2472 struct bcm_enet_priv *priv;
2473
2474 priv = netdev_priv(dev);
2475 return bcmenet_sw_mdio_read(priv,
2476 bcm_enetsw_phy_is_external(priv, phy_id),
2477 phy_id, location);
2478 }
2479
2480 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2481 * external/internal status of the given phy_id first.
2482 */
2483 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2484 int location,
2485 int val)
2486 {
2487 struct bcm_enet_priv *priv;
2488
2489 priv = netdev_priv(dev);
2490 bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2491 phy_id, location, val);
2492 }
2493
2494 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2495 {
2496 struct mii_if_info mii;
2497
2498 mii.dev = dev;
2499 mii.mdio_read = bcm_enetsw_mii_mdio_read;
2500 mii.mdio_write = bcm_enetsw_mii_mdio_write;
2501 mii.phy_id = 0;
2502 mii.phy_id_mask = 0x3f;
2503 mii.reg_num_mask = 0x1f;
2504 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2505
2506 }
2507
2508 static const struct net_device_ops bcm_enetsw_ops = {
2509 .ndo_open = bcm_enetsw_open,
2510 .ndo_stop = bcm_enetsw_stop,
2511 .ndo_start_xmit = bcm_enet_start_xmit,
2512 .ndo_change_mtu = bcm_enet_change_mtu,
2513 .ndo_do_ioctl = bcm_enetsw_ioctl,
2514 };
2515
2516
2517 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2518 { "rx_packets", DEV_STAT(rx_packets), -1 },
2519 { "tx_packets", DEV_STAT(tx_packets), -1 },
2520 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2521 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2522 { "rx_errors", DEV_STAT(rx_errors), -1 },
2523 { "tx_errors", DEV_STAT(tx_errors), -1 },
2524 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2525 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2526
2527 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2528 { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2529 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2530 { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2531 { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2532 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2533 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2534 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2535 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2536 { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2537 ETHSW_MIB_RX_1024_1522 },
2538 { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2539 ETHSW_MIB_RX_1523_2047 },
2540 { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2541 ETHSW_MIB_RX_2048_4095 },
2542 { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2543 ETHSW_MIB_RX_4096_8191 },
2544 { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2545 ETHSW_MIB_RX_8192_9728 },
2546 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2547 { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2548 { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2549 { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2550 { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2551
2552 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2553 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2554 { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2555 { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2556 { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2557 { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2558
2559 };
2560
2561 #define BCM_ENETSW_STATS_LEN \
2562 (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2563
2564 static void bcm_enetsw_get_strings(struct net_device *netdev,
2565 u32 stringset, u8 *data)
2566 {
2567 int i;
2568
2569 switch (stringset) {
2570 case ETH_SS_STATS:
2571 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2572 memcpy(data + i * ETH_GSTRING_LEN,
2573 bcm_enetsw_gstrings_stats[i].stat_string,
2574 ETH_GSTRING_LEN);
2575 }
2576 break;
2577 }
2578 }
2579
2580 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2581 int string_set)
2582 {
2583 switch (string_set) {
2584 case ETH_SS_STATS:
2585 return BCM_ENETSW_STATS_LEN;
2586 default:
2587 return -EINVAL;
2588 }
2589 }
2590
2591 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2592 struct ethtool_drvinfo *drvinfo)
2593 {
2594 strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2595 strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2596 strncpy(drvinfo->fw_version, "N/A", 32);
2597 strncpy(drvinfo->bus_info, "bcm63xx", 32);
2598 }
2599
2600 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2601 struct ethtool_stats *stats,
2602 u64 *data)
2603 {
2604 struct bcm_enet_priv *priv;
2605 int i;
2606
2607 priv = netdev_priv(netdev);
2608
2609 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2610 const struct bcm_enet_stats *s;
2611 u32 lo, hi;
2612 char *p;
2613 int reg;
2614
2615 s = &bcm_enetsw_gstrings_stats[i];
2616
2617 reg = s->mib_reg;
2618 if (reg == -1)
2619 continue;
2620
2621 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2622 p = (char *)priv + s->stat_offset;
2623
2624 if (s->sizeof_stat == sizeof(u64)) {
2625 hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2626 *(u64 *)p = ((u64)hi << 32 | lo);
2627 } else {
2628 *(u32 *)p = lo;
2629 }
2630 }
2631
2632 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2633 const struct bcm_enet_stats *s;
2634 char *p;
2635
2636 s = &bcm_enetsw_gstrings_stats[i];
2637
2638 if (s->mib_reg == -1)
2639 p = (char *)&netdev->stats + s->stat_offset;
2640 else
2641 p = (char *)priv + s->stat_offset;
2642
2643 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2644 *(u64 *)p : *(u32 *)p;
2645 }
2646 }
2647
2648 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2649 struct ethtool_ringparam *ering)
2650 {
2651 struct bcm_enet_priv *priv;
2652
2653 priv = netdev_priv(dev);
2654
2655 /* rx/tx ring is actually only limited by memory */
2656 ering->rx_max_pending = 8192;
2657 ering->tx_max_pending = 8192;
2658 ering->rx_mini_max_pending = 0;
2659 ering->rx_jumbo_max_pending = 0;
2660 ering->rx_pending = priv->rx_ring_size;
2661 ering->tx_pending = priv->tx_ring_size;
2662 }
2663
2664 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2665 struct ethtool_ringparam *ering)
2666 {
2667 struct bcm_enet_priv *priv;
2668 int was_running;
2669
2670 priv = netdev_priv(dev);
2671
2672 was_running = 0;
2673 if (netif_running(dev)) {
2674 bcm_enetsw_stop(dev);
2675 was_running = 1;
2676 }
2677
2678 priv->rx_ring_size = ering->rx_pending;
2679 priv->tx_ring_size = ering->tx_pending;
2680
2681 if (was_running) {
2682 int err;
2683
2684 err = bcm_enetsw_open(dev);
2685 if (err)
2686 dev_close(dev);
2687 }
2688 return 0;
2689 }
2690
2691 static struct ethtool_ops bcm_enetsw_ethtool_ops = {
2692 .get_strings = bcm_enetsw_get_strings,
2693 .get_sset_count = bcm_enetsw_get_sset_count,
2694 .get_ethtool_stats = bcm_enetsw_get_ethtool_stats,
2695 .get_drvinfo = bcm_enetsw_get_drvinfo,
2696 .get_ringparam = bcm_enetsw_get_ringparam,
2697 .set_ringparam = bcm_enetsw_set_ringparam,
2698 };
2699
2700 /* allocate netdevice, request register memory and register device. */
2701 static int bcm_enetsw_probe(struct platform_device *pdev)
2702 {
2703 struct bcm_enet_priv *priv;
2704 struct net_device *dev;
2705 struct bcm63xx_enetsw_platform_data *pd;
2706 struct resource *res_mem;
2707 int ret, irq_rx, irq_tx;
2708
2709 /* stop if shared driver failed, assume driver->probe will be
2710 * called in the same order we register devices (correct ?)
2711 */
2712 if (!bcm_enet_shared_base[0])
2713 return -ENODEV;
2714
2715 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2716 irq_rx = platform_get_irq(pdev, 0);
2717 irq_tx = platform_get_irq(pdev, 1);
2718 if (!res_mem || irq_rx < 0)
2719 return -ENODEV;
2720
2721 ret = 0;
2722 dev = alloc_etherdev(sizeof(*priv));
2723 if (!dev)
2724 return -ENOMEM;
2725 priv = netdev_priv(dev);
2726 memset(priv, 0, sizeof(*priv));
2727
2728 /* initialize default and fetch platform data */
2729 priv->enet_is_sw = true;
2730 priv->irq_rx = irq_rx;
2731 priv->irq_tx = irq_tx;
2732 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2733 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2734 priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2735
2736 pd = dev_get_platdata(&pdev->dev);
2737 if (pd) {
2738 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2739 memcpy(priv->used_ports, pd->used_ports,
2740 sizeof(pd->used_ports));
2741 priv->num_ports = pd->num_ports;
2742 priv->dma_has_sram = pd->dma_has_sram;
2743 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2744 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2745 priv->dma_chan_width = pd->dma_chan_width;
2746 }
2747
2748 ret = compute_hw_mtu(priv, dev->mtu);
2749 if (ret)
2750 goto out;
2751
2752 if (!request_mem_region(res_mem->start, resource_size(res_mem),
2753 "bcm63xx_enetsw")) {
2754 ret = -EBUSY;
2755 goto out;
2756 }
2757
2758 priv->base = ioremap(res_mem->start, resource_size(res_mem));
2759 if (priv->base == NULL) {
2760 ret = -ENOMEM;
2761 goto out_release_mem;
2762 }
2763
2764 priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2765 if (IS_ERR(priv->mac_clk)) {
2766 ret = PTR_ERR(priv->mac_clk);
2767 goto out_unmap;
2768 }
2769 clk_enable(priv->mac_clk);
2770
2771 priv->rx_chan = 0;
2772 priv->tx_chan = 1;
2773 spin_lock_init(&priv->rx_lock);
2774
2775 /* init rx timeout (used for oom) */
2776 init_timer(&priv->rx_timeout);
2777 priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2778 priv->rx_timeout.data = (unsigned long)dev;
2779
2780 /* register netdevice */
2781 dev->netdev_ops = &bcm_enetsw_ops;
2782 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2783 dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2784 SET_NETDEV_DEV(dev, &pdev->dev);
2785
2786 spin_lock_init(&priv->enetsw_mdio_lock);
2787
2788 ret = register_netdev(dev);
2789 if (ret)
2790 goto out_put_clk;
2791
2792 netif_carrier_off(dev);
2793 platform_set_drvdata(pdev, dev);
2794 priv->pdev = pdev;
2795 priv->net_dev = dev;
2796
2797 return 0;
2798
2799 out_put_clk:
2800 clk_put(priv->mac_clk);
2801
2802 out_unmap:
2803 iounmap(priv->base);
2804
2805 out_release_mem:
2806 release_mem_region(res_mem->start, resource_size(res_mem));
2807 out:
2808 free_netdev(dev);
2809 return ret;
2810 }
2811
2812
2813 /* exit func, stops hardware and unregisters netdevice */
2814 static int bcm_enetsw_remove(struct platform_device *pdev)
2815 {
2816 struct bcm_enet_priv *priv;
2817 struct net_device *dev;
2818 struct resource *res;
2819
2820 /* stop netdevice */
2821 dev = platform_get_drvdata(pdev);
2822 priv = netdev_priv(dev);
2823 unregister_netdev(dev);
2824
2825 /* release device resources */
2826 iounmap(priv->base);
2827 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2828 release_mem_region(res->start, resource_size(res));
2829
2830 free_netdev(dev);
2831 return 0;
2832 }
2833
2834 struct platform_driver bcm63xx_enetsw_driver = {
2835 .probe = bcm_enetsw_probe,
2836 .remove = bcm_enetsw_remove,
2837 .driver = {
2838 .name = "bcm63xx_enetsw",
2839 .owner = THIS_MODULE,
2840 },
2841 };
2842
2843 /* reserve & remap memory space shared between all macs */
2844 static int bcm_enet_shared_probe(struct platform_device *pdev)
2845 {
2846 struct resource *res;
2847 void __iomem *p[3];
2848 unsigned int i;
2849
2850 memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2851
2852 for (i = 0; i < 3; i++) {
2853 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2854 p[i] = devm_ioremap_resource(&pdev->dev, res);
2855 if (IS_ERR(p[i]))
2856 return PTR_ERR(p[i]);
2857 }
2858
2859 memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2860
2861 return 0;
2862 }
2863
2864 static int bcm_enet_shared_remove(struct platform_device *pdev)
2865 {
2866 return 0;
2867 }
2868
2869 /* this "shared" driver is needed because both macs share a single
2870 * address space
2871 */
2872 struct platform_driver bcm63xx_enet_shared_driver = {
2873 .probe = bcm_enet_shared_probe,
2874 .remove = bcm_enet_shared_remove,
2875 .driver = {
2876 .name = "bcm63xx_enet_shared",
2877 .owner = THIS_MODULE,
2878 },
2879 };
2880
2881 static struct platform_driver * const drivers[] = {
2882 &bcm63xx_enet_shared_driver,
2883 &bcm63xx_enet_driver,
2884 &bcm63xx_enetsw_driver,
2885 };
2886
2887 /* entry point */
2888 static int __init bcm_enet_init(void)
2889 {
2890 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2891 }
2892
2893 static void __exit bcm_enet_exit(void)
2894 {
2895 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2896 }
2897
2898
2899 module_init(bcm_enet_init);
2900 module_exit(bcm_enet_exit);
2901
2902 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2903 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2904 MODULE_LICENSE("GPL");
Linux with added FPC-III support