2 * EP93xx ethernet network device driver
3 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
4 * Dedicated to Marija Kulikova.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
14 #include <linux/dma-mapping.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/mii.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/interrupt.h>
22 #include <linux/moduleparam.h>
23 #include <linux/platform_device.h>
24 #include <linux/delay.h>
26 #include <linux/slab.h>
28 #include <mach/hardware.h>
30 #define DRV_MODULE_NAME "ep93xx-eth"
31 #define DRV_MODULE_VERSION "0.1"
33 #define RX_QUEUE_ENTRIES 64
34 #define TX_QUEUE_ENTRIES 8
36 #define MAX_PKT_SIZE 2044
37 #define PKT_BUF_SIZE 2048
39 #define REG_RXCTL 0x0000
40 #define REG_RXCTL_DEFAULT 0x00073800
41 #define REG_TXCTL 0x0004
42 #define REG_TXCTL_ENABLE 0x00000001
43 #define REG_MIICMD 0x0010
44 #define REG_MIICMD_READ 0x00008000
45 #define REG_MIICMD_WRITE 0x00004000
46 #define REG_MIIDATA 0x0014
47 #define REG_MIISTS 0x0018
48 #define REG_MIISTS_BUSY 0x00000001
49 #define REG_SELFCTL 0x0020
50 #define REG_SELFCTL_RESET 0x00000001
51 #define REG_INTEN 0x0024
52 #define REG_INTEN_TX 0x00000008
53 #define REG_INTEN_RX 0x00000007
54 #define REG_INTSTSP 0x0028
55 #define REG_INTSTS_TX 0x00000008
56 #define REG_INTSTS_RX 0x00000004
57 #define REG_INTSTSC 0x002c
58 #define REG_AFP 0x004c
59 #define REG_INDAD0 0x0050
60 #define REG_INDAD1 0x0051
61 #define REG_INDAD2 0x0052
62 #define REG_INDAD3 0x0053
63 #define REG_INDAD4 0x0054
64 #define REG_INDAD5 0x0055
65 #define REG_GIINTMSK 0x0064
66 #define REG_GIINTMSK_ENABLE 0x00008000
67 #define REG_BMCTL 0x0080
68 #define REG_BMCTL_ENABLE_TX 0x00000100
69 #define REG_BMCTL_ENABLE_RX 0x00000001
70 #define REG_BMSTS 0x0084
71 #define REG_BMSTS_RX_ACTIVE 0x00000008
72 #define REG_RXDQBADD 0x0090
73 #define REG_RXDQBLEN 0x0094
74 #define REG_RXDCURADD 0x0098
75 #define REG_RXDENQ 0x009c
76 #define REG_RXSTSQBADD 0x00a0
77 #define REG_RXSTSQBLEN 0x00a4
78 #define REG_RXSTSQCURADD 0x00a8
79 #define REG_RXSTSENQ 0x00ac
80 #define REG_TXDQBADD 0x00b0
81 #define REG_TXDQBLEN 0x00b4
82 #define REG_TXDQCURADD 0x00b8
83 #define REG_TXDENQ 0x00bc
84 #define REG_TXSTSQBADD 0x00c0
85 #define REG_TXSTSQBLEN 0x00c4
86 #define REG_TXSTSQCURADD 0x00c8
87 #define REG_MAXFRMLEN 0x00e8
95 #define RDESC1_NSOF 0x80000000
96 #define RDESC1_BUFFER_INDEX 0x7fff0000
97 #define RDESC1_BUFFER_LENGTH 0x0000ffff
105 #define RSTAT0_RFP 0x80000000
106 #define RSTAT0_RWE 0x40000000
107 #define RSTAT0_EOF 0x20000000
108 #define RSTAT0_EOB 0x10000000
109 #define RSTAT0_AM 0x00c00000
110 #define RSTAT0_RX_ERR 0x00200000
111 #define RSTAT0_OE 0x00100000
112 #define RSTAT0_FE 0x00080000
113 #define RSTAT0_RUNT 0x00040000
114 #define RSTAT0_EDATA 0x00020000
115 #define RSTAT0_CRCE 0x00010000
116 #define RSTAT0_CRCI 0x00008000
117 #define RSTAT0_HTI 0x00003f00
118 #define RSTAT1_RFP 0x80000000
119 #define RSTAT1_BUFFER_INDEX 0x7fff0000
120 #define RSTAT1_FRAME_LENGTH 0x0000ffff
128 #define TDESC1_EOF 0x80000000
129 #define TDESC1_BUFFER_INDEX 0x7fff0000
130 #define TDESC1_BUFFER_ABORT 0x00008000
131 #define TDESC1_BUFFER_LENGTH 0x00000fff
138 #define TSTAT0_TXFP 0x80000000
139 #define TSTAT0_TXWE 0x40000000
140 #define TSTAT0_FA 0x20000000
141 #define TSTAT0_LCRS 0x10000000
142 #define TSTAT0_OW 0x04000000
143 #define TSTAT0_TXU 0x02000000
144 #define TSTAT0_ECOLL 0x01000000
145 #define TSTAT0_NCOLL 0x001f0000
146 #define TSTAT0_BUFFER_INDEX 0x00007fff
150 struct ep93xx_rdesc rdesc
[RX_QUEUE_ENTRIES
];
151 struct ep93xx_tdesc tdesc
[TX_QUEUE_ENTRIES
];
152 struct ep93xx_rstat rstat
[RX_QUEUE_ENTRIES
];
153 struct ep93xx_tstat tstat
[TX_QUEUE_ENTRIES
];
158 struct resource
*res
;
159 void __iomem
*base_addr
;
162 struct ep93xx_descs
*descs
;
163 dma_addr_t descs_dma_addr
;
165 void *rx_buf
[RX_QUEUE_ENTRIES
];
166 void *tx_buf
[TX_QUEUE_ENTRIES
];
169 unsigned int rx_pointer
;
170 unsigned int tx_clean_pointer
;
171 unsigned int tx_pointer
;
172 spinlock_t tx_pending_lock
;
173 unsigned int tx_pending
;
175 struct net_device
*dev
;
176 struct napi_struct napi
;
178 struct mii_if_info mii
;
182 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
183 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
184 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
185 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
186 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
187 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
189 static int ep93xx_mdio_read(struct net_device
*dev
, int phy_id
, int reg
)
191 struct ep93xx_priv
*ep
= netdev_priv(dev
);
195 wrl(ep
, REG_MIICMD
, REG_MIICMD_READ
| (phy_id
<< 5) | reg
);
197 for (i
= 0; i
< 10; i
++) {
198 if ((rdl(ep
, REG_MIISTS
) & REG_MIISTS_BUSY
) == 0)
204 pr_info("mdio read timed out\n");
207 data
= rdl(ep
, REG_MIIDATA
);
213 static void ep93xx_mdio_write(struct net_device
*dev
, int phy_id
, int reg
, int data
)
215 struct ep93xx_priv
*ep
= netdev_priv(dev
);
218 wrl(ep
, REG_MIIDATA
, data
);
219 wrl(ep
, REG_MIICMD
, REG_MIICMD_WRITE
| (phy_id
<< 5) | reg
);
221 for (i
= 0; i
< 10; i
++) {
222 if ((rdl(ep
, REG_MIISTS
) & REG_MIISTS_BUSY
) == 0)
228 pr_info("mdio write timed out\n");
231 static int ep93xx_rx(struct net_device
*dev
, int processed
, int budget
)
233 struct ep93xx_priv
*ep
= netdev_priv(dev
);
235 while (processed
< budget
) {
237 struct ep93xx_rstat
*rstat
;
243 entry
= ep
->rx_pointer
;
244 rstat
= ep
->descs
->rstat
+ entry
;
246 rstat0
= rstat
->rstat0
;
247 rstat1
= rstat
->rstat1
;
248 if (!(rstat0
& RSTAT0_RFP
) || !(rstat1
& RSTAT1_RFP
))
254 if (!(rstat0
& RSTAT0_EOF
))
255 pr_crit("not end-of-frame %.8x %.8x\n", rstat0
, rstat1
);
256 if (!(rstat0
& RSTAT0_EOB
))
257 pr_crit("not end-of-buffer %.8x %.8x\n", rstat0
, rstat1
);
258 if ((rstat1
& RSTAT1_BUFFER_INDEX
) >> 16 != entry
)
259 pr_crit("entry mismatch %.8x %.8x\n", rstat0
, rstat1
);
261 if (!(rstat0
& RSTAT0_RWE
)) {
262 dev
->stats
.rx_errors
++;
263 if (rstat0
& RSTAT0_OE
)
264 dev
->stats
.rx_fifo_errors
++;
265 if (rstat0
& RSTAT0_FE
)
266 dev
->stats
.rx_frame_errors
++;
267 if (rstat0
& (RSTAT0_RUNT
| RSTAT0_EDATA
))
268 dev
->stats
.rx_length_errors
++;
269 if (rstat0
& RSTAT0_CRCE
)
270 dev
->stats
.rx_crc_errors
++;
274 length
= rstat1
& RSTAT1_FRAME_LENGTH
;
275 if (length
> MAX_PKT_SIZE
) {
276 pr_notice("invalid length %.8x %.8x\n", rstat0
, rstat1
);
281 if (rstat0
& RSTAT0_CRCI
)
284 skb
= netdev_alloc_skb(dev
, length
+ 2);
285 if (likely(skb
!= NULL
)) {
286 struct ep93xx_rdesc
*rxd
= &ep
->descs
->rdesc
[entry
];
288 dma_sync_single_for_cpu(dev
->dev
.parent
, rxd
->buf_addr
,
289 length
, DMA_FROM_DEVICE
);
290 skb_copy_to_linear_data(skb
, ep
->rx_buf
[entry
], length
);
291 dma_sync_single_for_device(dev
->dev
.parent
,
292 rxd
->buf_addr
, length
,
294 skb_put(skb
, length
);
295 skb
->protocol
= eth_type_trans(skb
, dev
);
297 netif_receive_skb(skb
);
299 dev
->stats
.rx_packets
++;
300 dev
->stats
.rx_bytes
+= length
;
302 dev
->stats
.rx_dropped
++;
306 ep
->rx_pointer
= (entry
+ 1) & (RX_QUEUE_ENTRIES
- 1);
313 static int ep93xx_have_more_rx(struct ep93xx_priv
*ep
)
315 struct ep93xx_rstat
*rstat
= ep
->descs
->rstat
+ ep
->rx_pointer
;
316 return !!((rstat
->rstat0
& RSTAT0_RFP
) && (rstat
->rstat1
& RSTAT1_RFP
));
319 static int ep93xx_poll(struct napi_struct
*napi
, int budget
)
321 struct ep93xx_priv
*ep
= container_of(napi
, struct ep93xx_priv
, napi
);
322 struct net_device
*dev
= ep
->dev
;
326 rx
= ep93xx_rx(dev
, rx
, budget
);
330 spin_lock_irq(&ep
->rx_lock
);
331 __napi_complete(napi
);
332 wrl(ep
, REG_INTEN
, REG_INTEN_TX
| REG_INTEN_RX
);
333 if (ep93xx_have_more_rx(ep
)) {
334 wrl(ep
, REG_INTEN
, REG_INTEN_TX
);
335 wrl(ep
, REG_INTSTSP
, REG_INTSTS_RX
);
338 spin_unlock_irq(&ep
->rx_lock
);
340 if (more
&& napi_reschedule(napi
))
345 wrw(ep
, REG_RXDENQ
, rx
);
346 wrw(ep
, REG_RXSTSENQ
, rx
);
352 static int ep93xx_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
354 struct ep93xx_priv
*ep
= netdev_priv(dev
);
355 struct ep93xx_tdesc
*txd
;
358 if (unlikely(skb
->len
> MAX_PKT_SIZE
)) {
359 dev
->stats
.tx_dropped
++;
364 entry
= ep
->tx_pointer
;
365 ep
->tx_pointer
= (ep
->tx_pointer
+ 1) & (TX_QUEUE_ENTRIES
- 1);
367 txd
= &ep
->descs
->tdesc
[entry
];
369 txd
->tdesc1
= TDESC1_EOF
| (entry
<< 16) | (skb
->len
& 0xfff);
370 dma_sync_single_for_cpu(dev
->dev
.parent
, txd
->buf_addr
, skb
->len
,
372 skb_copy_and_csum_dev(skb
, ep
->tx_buf
[entry
]);
373 dma_sync_single_for_device(dev
->dev
.parent
, txd
->buf_addr
, skb
->len
,
377 spin_lock_irq(&ep
->tx_pending_lock
);
379 if (ep
->tx_pending
== TX_QUEUE_ENTRIES
)
380 netif_stop_queue(dev
);
381 spin_unlock_irq(&ep
->tx_pending_lock
);
383 wrl(ep
, REG_TXDENQ
, 1);
388 static void ep93xx_tx_complete(struct net_device
*dev
)
390 struct ep93xx_priv
*ep
= netdev_priv(dev
);
395 spin_lock(&ep
->tx_pending_lock
);
398 struct ep93xx_tstat
*tstat
;
401 entry
= ep
->tx_clean_pointer
;
402 tstat
= ep
->descs
->tstat
+ entry
;
404 tstat0
= tstat
->tstat0
;
405 if (!(tstat0
& TSTAT0_TXFP
))
410 if (tstat0
& TSTAT0_FA
)
411 pr_crit("frame aborted %.8x\n", tstat0
);
412 if ((tstat0
& TSTAT0_BUFFER_INDEX
) != entry
)
413 pr_crit("entry mismatch %.8x\n", tstat0
);
415 if (tstat0
& TSTAT0_TXWE
) {
416 int length
= ep
->descs
->tdesc
[entry
].tdesc1
& 0xfff;
418 dev
->stats
.tx_packets
++;
419 dev
->stats
.tx_bytes
+= length
;
421 dev
->stats
.tx_errors
++;
424 if (tstat0
& TSTAT0_OW
)
425 dev
->stats
.tx_window_errors
++;
426 if (tstat0
& TSTAT0_TXU
)
427 dev
->stats
.tx_fifo_errors
++;
428 dev
->stats
.collisions
+= (tstat0
>> 16) & 0x1f;
430 ep
->tx_clean_pointer
= (entry
+ 1) & (TX_QUEUE_ENTRIES
- 1);
431 if (ep
->tx_pending
== TX_QUEUE_ENTRIES
)
435 spin_unlock(&ep
->tx_pending_lock
);
438 netif_wake_queue(dev
);
441 static irqreturn_t
ep93xx_irq(int irq
, void *dev_id
)
443 struct net_device
*dev
= dev_id
;
444 struct ep93xx_priv
*ep
= netdev_priv(dev
);
447 status
= rdl(ep
, REG_INTSTSC
);
451 if (status
& REG_INTSTS_RX
) {
452 spin_lock(&ep
->rx_lock
);
453 if (likely(napi_schedule_prep(&ep
->napi
))) {
454 wrl(ep
, REG_INTEN
, REG_INTEN_TX
);
455 __napi_schedule(&ep
->napi
);
457 spin_unlock(&ep
->rx_lock
);
460 if (status
& REG_INTSTS_TX
)
461 ep93xx_tx_complete(dev
);
466 static void ep93xx_free_buffers(struct ep93xx_priv
*ep
)
468 struct device
*dev
= ep
->dev
->dev
.parent
;
474 for (i
= 0; i
< RX_QUEUE_ENTRIES
; i
++) {
477 d
= ep
->descs
->rdesc
[i
].buf_addr
;
479 dma_unmap_single(dev
, d
, PKT_BUF_SIZE
, DMA_FROM_DEVICE
);
481 kfree(ep
->rx_buf
[i
]);
484 for (i
= 0; i
< TX_QUEUE_ENTRIES
; i
++) {
487 d
= ep
->descs
->tdesc
[i
].buf_addr
;
489 dma_unmap_single(dev
, d
, PKT_BUF_SIZE
, DMA_TO_DEVICE
);
491 kfree(ep
->tx_buf
[i
]);
494 dma_free_coherent(dev
, sizeof(struct ep93xx_descs
), ep
->descs
,
499 static int ep93xx_alloc_buffers(struct ep93xx_priv
*ep
)
501 struct device
*dev
= ep
->dev
->dev
.parent
;
504 ep
->descs
= dma_alloc_coherent(dev
, sizeof(struct ep93xx_descs
),
505 &ep
->descs_dma_addr
, GFP_KERNEL
);
506 if (ep
->descs
== NULL
)
509 for (i
= 0; i
< RX_QUEUE_ENTRIES
; i
++) {
513 buf
= kmalloc(PKT_BUF_SIZE
, GFP_KERNEL
);
517 d
= dma_map_single(dev
, buf
, PKT_BUF_SIZE
, DMA_FROM_DEVICE
);
518 if (dma_mapping_error(dev
, d
)) {
524 ep
->descs
->rdesc
[i
].buf_addr
= d
;
525 ep
->descs
->rdesc
[i
].rdesc1
= (i
<< 16) | PKT_BUF_SIZE
;
528 for (i
= 0; i
< TX_QUEUE_ENTRIES
; i
++) {
532 buf
= kmalloc(PKT_BUF_SIZE
, GFP_KERNEL
);
536 d
= dma_map_single(dev
, buf
, PKT_BUF_SIZE
, DMA_TO_DEVICE
);
537 if (dma_mapping_error(dev
, d
)) {
543 ep
->descs
->tdesc
[i
].buf_addr
= d
;
549 ep93xx_free_buffers(ep
);
553 static int ep93xx_start_hw(struct net_device
*dev
)
555 struct ep93xx_priv
*ep
= netdev_priv(dev
);
559 wrl(ep
, REG_SELFCTL
, REG_SELFCTL_RESET
);
560 for (i
= 0; i
< 10; i
++) {
561 if ((rdl(ep
, REG_SELFCTL
) & REG_SELFCTL_RESET
) == 0)
567 pr_crit("hw failed to reset\n");
571 wrl(ep
, REG_SELFCTL
, ((ep
->mdc_divisor
- 1) << 9));
573 /* Does the PHY support preamble suppress? */
574 if ((ep93xx_mdio_read(dev
, ep
->mii
.phy_id
, MII_BMSR
) & 0x0040) != 0)
575 wrl(ep
, REG_SELFCTL
, ((ep
->mdc_divisor
- 1) << 9) | (1 << 8));
577 /* Receive descriptor ring. */
578 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, rdesc
);
579 wrl(ep
, REG_RXDQBADD
, addr
);
580 wrl(ep
, REG_RXDCURADD
, addr
);
581 wrw(ep
, REG_RXDQBLEN
, RX_QUEUE_ENTRIES
* sizeof(struct ep93xx_rdesc
));
583 /* Receive status ring. */
584 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, rstat
);
585 wrl(ep
, REG_RXSTSQBADD
, addr
);
586 wrl(ep
, REG_RXSTSQCURADD
, addr
);
587 wrw(ep
, REG_RXSTSQBLEN
, RX_QUEUE_ENTRIES
* sizeof(struct ep93xx_rstat
));
589 /* Transmit descriptor ring. */
590 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, tdesc
);
591 wrl(ep
, REG_TXDQBADD
, addr
);
592 wrl(ep
, REG_TXDQCURADD
, addr
);
593 wrw(ep
, REG_TXDQBLEN
, TX_QUEUE_ENTRIES
* sizeof(struct ep93xx_tdesc
));
595 /* Transmit status ring. */
596 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, tstat
);
597 wrl(ep
, REG_TXSTSQBADD
, addr
);
598 wrl(ep
, REG_TXSTSQCURADD
, addr
);
599 wrw(ep
, REG_TXSTSQBLEN
, TX_QUEUE_ENTRIES
* sizeof(struct ep93xx_tstat
));
601 wrl(ep
, REG_BMCTL
, REG_BMCTL_ENABLE_TX
| REG_BMCTL_ENABLE_RX
);
602 wrl(ep
, REG_INTEN
, REG_INTEN_TX
| REG_INTEN_RX
);
603 wrl(ep
, REG_GIINTMSK
, 0);
605 for (i
= 0; i
< 10; i
++) {
606 if ((rdl(ep
, REG_BMSTS
) & REG_BMSTS_RX_ACTIVE
) != 0)
612 pr_crit("hw failed to start\n");
616 wrl(ep
, REG_RXDENQ
, RX_QUEUE_ENTRIES
);
617 wrl(ep
, REG_RXSTSENQ
, RX_QUEUE_ENTRIES
);
619 wrb(ep
, REG_INDAD0
, dev
->dev_addr
[0]);
620 wrb(ep
, REG_INDAD1
, dev
->dev_addr
[1]);
621 wrb(ep
, REG_INDAD2
, dev
->dev_addr
[2]);
622 wrb(ep
, REG_INDAD3
, dev
->dev_addr
[3]);
623 wrb(ep
, REG_INDAD4
, dev
->dev_addr
[4]);
624 wrb(ep
, REG_INDAD5
, dev
->dev_addr
[5]);
627 wrl(ep
, REG_MAXFRMLEN
, (MAX_PKT_SIZE
<< 16) | MAX_PKT_SIZE
);
629 wrl(ep
, REG_RXCTL
, REG_RXCTL_DEFAULT
);
630 wrl(ep
, REG_TXCTL
, REG_TXCTL_ENABLE
);
635 static void ep93xx_stop_hw(struct net_device
*dev
)
637 struct ep93xx_priv
*ep
= netdev_priv(dev
);
640 wrl(ep
, REG_SELFCTL
, REG_SELFCTL_RESET
);
641 for (i
= 0; i
< 10; i
++) {
642 if ((rdl(ep
, REG_SELFCTL
) & REG_SELFCTL_RESET
) == 0)
648 pr_crit("hw failed to reset\n");
651 static int ep93xx_open(struct net_device
*dev
)
653 struct ep93xx_priv
*ep
= netdev_priv(dev
);
656 if (ep93xx_alloc_buffers(ep
))
659 napi_enable(&ep
->napi
);
661 if (ep93xx_start_hw(dev
)) {
662 napi_disable(&ep
->napi
);
663 ep93xx_free_buffers(ep
);
667 spin_lock_init(&ep
->rx_lock
);
669 ep
->tx_clean_pointer
= 0;
671 spin_lock_init(&ep
->tx_pending_lock
);
674 err
= request_irq(ep
->irq
, ep93xx_irq
, IRQF_SHARED
, dev
->name
, dev
);
676 napi_disable(&ep
->napi
);
678 ep93xx_free_buffers(ep
);
682 wrl(ep
, REG_GIINTMSK
, REG_GIINTMSK_ENABLE
);
684 netif_start_queue(dev
);
689 static int ep93xx_close(struct net_device
*dev
)
691 struct ep93xx_priv
*ep
= netdev_priv(dev
);
693 napi_disable(&ep
->napi
);
694 netif_stop_queue(dev
);
696 wrl(ep
, REG_GIINTMSK
, 0);
697 free_irq(ep
->irq
, dev
);
699 ep93xx_free_buffers(ep
);
704 static int ep93xx_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
706 struct ep93xx_priv
*ep
= netdev_priv(dev
);
707 struct mii_ioctl_data
*data
= if_mii(ifr
);
709 return generic_mii_ioctl(&ep
->mii
, data
, cmd
, NULL
);
712 static void ep93xx_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
714 strlcpy(info
->driver
, DRV_MODULE_NAME
, sizeof(info
->driver
));
715 strlcpy(info
->version
, DRV_MODULE_VERSION
, sizeof(info
->version
));
718 static int ep93xx_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
720 struct ep93xx_priv
*ep
= netdev_priv(dev
);
721 return mii_ethtool_gset(&ep
->mii
, cmd
);
724 static int ep93xx_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
726 struct ep93xx_priv
*ep
= netdev_priv(dev
);
727 return mii_ethtool_sset(&ep
->mii
, cmd
);
730 static int ep93xx_nway_reset(struct net_device
*dev
)
732 struct ep93xx_priv
*ep
= netdev_priv(dev
);
733 return mii_nway_restart(&ep
->mii
);
736 static u32
ep93xx_get_link(struct net_device
*dev
)
738 struct ep93xx_priv
*ep
= netdev_priv(dev
);
739 return mii_link_ok(&ep
->mii
);
742 static const struct ethtool_ops ep93xx_ethtool_ops
= {
743 .get_drvinfo
= ep93xx_get_drvinfo
,
744 .get_settings
= ep93xx_get_settings
,
745 .set_settings
= ep93xx_set_settings
,
746 .nway_reset
= ep93xx_nway_reset
,
747 .get_link
= ep93xx_get_link
,
750 static const struct net_device_ops ep93xx_netdev_ops
= {
751 .ndo_open
= ep93xx_open
,
752 .ndo_stop
= ep93xx_close
,
753 .ndo_start_xmit
= ep93xx_xmit
,
754 .ndo_do_ioctl
= ep93xx_ioctl
,
755 .ndo_validate_addr
= eth_validate_addr
,
756 .ndo_change_mtu
= eth_change_mtu
,
757 .ndo_set_mac_address
= eth_mac_addr
,
760 static struct net_device
*ep93xx_dev_alloc(struct ep93xx_eth_data
*data
)
762 struct net_device
*dev
;
764 dev
= alloc_etherdev(sizeof(struct ep93xx_priv
));
768 memcpy(dev
->dev_addr
, data
->dev_addr
, ETH_ALEN
);
770 dev
->ethtool_ops
= &ep93xx_ethtool_ops
;
771 dev
->netdev_ops
= &ep93xx_netdev_ops
;
773 dev
->features
|= NETIF_F_SG
| NETIF_F_HW_CSUM
;
779 static int ep93xx_eth_remove(struct platform_device
*pdev
)
781 struct net_device
*dev
;
782 struct ep93xx_priv
*ep
;
784 dev
= platform_get_drvdata(pdev
);
788 ep
= netdev_priv(dev
);
790 /* @@@ Force down. */
791 unregister_netdev(dev
);
792 ep93xx_free_buffers(ep
);
794 if (ep
->base_addr
!= NULL
)
795 iounmap(ep
->base_addr
);
797 if (ep
->res
!= NULL
) {
798 release_resource(ep
->res
);
807 static int ep93xx_eth_probe(struct platform_device
*pdev
)
809 struct ep93xx_eth_data
*data
;
810 struct net_device
*dev
;
811 struct ep93xx_priv
*ep
;
812 struct resource
*mem
;
818 data
= dev_get_platdata(&pdev
->dev
);
820 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
821 irq
= platform_get_irq(pdev
, 0);
825 dev
= ep93xx_dev_alloc(data
);
830 ep
= netdev_priv(dev
);
832 SET_NETDEV_DEV(dev
, &pdev
->dev
);
833 netif_napi_add(dev
, &ep
->napi
, ep93xx_poll
, 64);
835 platform_set_drvdata(pdev
, dev
);
837 ep
->res
= request_mem_region(mem
->start
, resource_size(mem
),
838 dev_name(&pdev
->dev
));
839 if (ep
->res
== NULL
) {
840 dev_err(&pdev
->dev
, "Could not reserve memory region\n");
845 ep
->base_addr
= ioremap(mem
->start
, resource_size(mem
));
846 if (ep
->base_addr
== NULL
) {
847 dev_err(&pdev
->dev
, "Failed to ioremap ethernet registers\n");
853 ep
->mii
.phy_id
= data
->phy_id
;
854 ep
->mii
.phy_id_mask
= 0x1f;
855 ep
->mii
.reg_num_mask
= 0x1f;
857 ep
->mii
.mdio_read
= ep93xx_mdio_read
;
858 ep
->mii
.mdio_write
= ep93xx_mdio_write
;
859 ep
->mdc_divisor
= 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
861 if (is_zero_ether_addr(dev
->dev_addr
))
862 eth_hw_addr_random(dev
);
864 err
= register_netdev(dev
);
866 dev_err(&pdev
->dev
, "Failed to register netdev\n");
870 printk(KERN_INFO
"%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
871 dev
->name
, ep
->irq
, dev
->dev_addr
);
876 ep93xx_eth_remove(pdev
);
881 static struct platform_driver ep93xx_eth_driver
= {
882 .probe
= ep93xx_eth_probe
,
883 .remove
= ep93xx_eth_remove
,
885 .name
= "ep93xx-eth",
889 module_platform_driver(ep93xx_eth_driver
);
891 MODULE_LICENSE("GPL");
892 MODULE_ALIAS("platform:ep93xx-eth");