pvrusb2: reduce stack usage pvr2_eeprom_analyze()
[linux/fpc-iii.git] / drivers / net / ethernet / intel / igb / e1000_82575.h
blobacf06051e111cb9dd1be2386bd84ce8ca6ad220d
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 #ifndef _E1000_82575_H_
25 #define _E1000_82575_H_
27 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw);
28 void igb_power_up_serdes_link_82575(struct e1000_hw *hw);
29 void igb_power_down_phy_copper_82575(struct e1000_hw *hw);
30 void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
31 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
32 u8 *data);
33 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
34 u8 data);
36 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
37 (ID_LED_DEF1_DEF2 << 8) | \
38 (ID_LED_DEF1_DEF2 << 4) | \
39 (ID_LED_OFF1_ON2))
41 #define E1000_RAR_ENTRIES_82575 16
42 #define E1000_RAR_ENTRIES_82576 24
43 #define E1000_RAR_ENTRIES_82580 24
44 #define E1000_RAR_ENTRIES_I350 32
46 #define E1000_SW_SYNCH_MB 0x00000100
47 #define E1000_STAT_DEV_RST_SET 0x00100000
48 #define E1000_CTRL_DEV_RST 0x20000000
50 /* SRRCTL bit definitions */
51 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
52 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
53 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
54 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
55 #define E1000_SRRCTL_DROP_EN 0x80000000
56 #define E1000_SRRCTL_TIMESTAMP 0x40000000
59 #define E1000_MRQC_ENABLE_RSS_MQ 0x00000002
60 #define E1000_MRQC_ENABLE_VMDQ 0x00000003
61 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
62 #define E1000_MRQC_ENABLE_VMDQ_RSS_MQ 0x00000005
63 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
64 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
66 #define E1000_EICR_TX_QUEUE ( \
67 E1000_EICR_TX_QUEUE0 | \
68 E1000_EICR_TX_QUEUE1 | \
69 E1000_EICR_TX_QUEUE2 | \
70 E1000_EICR_TX_QUEUE3)
72 #define E1000_EICR_RX_QUEUE ( \
73 E1000_EICR_RX_QUEUE0 | \
74 E1000_EICR_RX_QUEUE1 | \
75 E1000_EICR_RX_QUEUE2 | \
76 E1000_EICR_RX_QUEUE3)
78 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
79 #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
80 #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
82 /* Receive Descriptor - Advanced */
83 union e1000_adv_rx_desc {
84 struct {
85 __le64 pkt_addr; /* Packet buffer address */
86 __le64 hdr_addr; /* Header buffer address */
87 } read;
88 struct {
89 struct {
90 struct {
91 __le16 pkt_info; /* RSS type, Packet type */
92 __le16 hdr_info; /* Split Head, buf len */
93 } lo_dword;
94 union {
95 __le32 rss; /* RSS Hash */
96 struct {
97 __le16 ip_id; /* IP id */
98 __le16 csum; /* Packet Checksum */
99 } csum_ip;
100 } hi_dword;
101 } lower;
102 struct {
103 __le32 status_error; /* ext status/error */
104 __le16 length; /* Packet length */
105 __le16 vlan; /* VLAN tag */
106 } upper;
107 } wb; /* writeback */
110 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
111 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5
112 #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
113 #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
115 /* Transmit Descriptor - Advanced */
116 union e1000_adv_tx_desc {
117 struct {
118 __le64 buffer_addr; /* Address of descriptor's data buf */
119 __le32 cmd_type_len;
120 __le32 olinfo_status;
121 } read;
122 struct {
123 __le64 rsvd; /* Reserved */
124 __le32 nxtseq_seed;
125 __le32 status;
126 } wb;
129 /* Adv Transmit Descriptor Config Masks */
130 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
131 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
132 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
133 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
134 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
135 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
136 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
137 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
138 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
139 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
141 /* Context descriptors */
142 struct e1000_adv_tx_context_desc {
143 __le32 vlan_macip_lens;
144 __le32 seqnum_seed;
145 __le32 type_tucmd_mlhl;
146 __le32 mss_l4len_idx;
149 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
150 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
151 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
152 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
153 /* IPSec Encrypt Enable for ESP */
154 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
155 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
156 /* Adv ctxt IPSec SA IDX mask */
157 /* Adv ctxt IPSec ESP len mask */
159 /* Additional Transmit Descriptor Control definitions */
160 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
161 /* Tx Queue Arbitration Priority 0=low, 1=high */
163 /* Additional Receive Descriptor Control definitions */
164 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
166 /* Direct Cache Access (DCA) definitions */
167 #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
168 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
170 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
171 #define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
172 #define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
173 #define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
174 #define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
176 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
177 #define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
178 #define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
179 #define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
180 #define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
182 /* Additional DCA related definitions, note change in position of CPUID */
183 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
184 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
185 #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
186 #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
188 /* ETQF register bit definitions */
189 #define E1000_ETQF_FILTER_ENABLE BIT(26)
190 #define E1000_ETQF_1588 BIT(30)
191 #define E1000_ETQF_IMM_INT BIT(29)
192 #define E1000_ETQF_QUEUE_ENABLE BIT(31)
193 #define E1000_ETQF_QUEUE_SHIFT 16
194 #define E1000_ETQF_QUEUE_MASK 0x00070000
195 #define E1000_ETQF_ETYPE_MASK 0x0000FFFF
197 /* FTQF register bit definitions */
198 #define E1000_FTQF_VF_BP 0x00008000
199 #define E1000_FTQF_1588_TIME_STAMP 0x08000000
200 #define E1000_FTQF_MASK 0xF0000000
201 #define E1000_FTQF_MASK_PROTO_BP 0x10000000
202 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
204 #define E1000_NVM_APME_82575 0x0400
205 #define MAX_NUM_VFS 8
207 #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
208 #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
209 #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
210 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
211 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31) /* global VF LB enable */
213 /* Easy defines for setting default pool, would normally be left a zero */
214 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
215 #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
217 /* Other useful VMD_CTL register defines */
218 #define E1000_VT_CTL_IGNORE_MAC BIT(28)
219 #define E1000_VT_CTL_DISABLE_DEF_POOL BIT(29)
220 #define E1000_VT_CTL_VM_REPL_EN BIT(30)
222 /* Per VM Offload register setup */
223 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
224 #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
225 #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
226 #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
227 #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
228 #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
229 #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
230 #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
231 #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
232 #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
234 #define E1000_DVMOLR_HIDEVLAN 0x20000000 /* Hide vlan enable */
235 #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
236 #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */
238 #define E1000_VLVF_ARRAY_SIZE 32
239 #define E1000_VLVF_VLANID_MASK 0x00000FFF
240 #define E1000_VLVF_POOLSEL_SHIFT 12
241 #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
242 #define E1000_VLVF_LVLAN 0x00100000
243 #define E1000_VLVF_VLANID_ENABLE 0x80000000
245 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
246 #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
248 #define E1000_IOVCTL 0x05BBC
249 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
251 #define E1000_RPLOLR_STRVLAN 0x40000000
252 #define E1000_RPLOLR_STRCRC 0x80000000
254 #define E1000_DTXCTL_8023LL 0x0004
255 #define E1000_DTXCTL_VLAN_ADDED 0x0008
256 #define E1000_DTXCTL_OOS_ENABLE 0x0010
257 #define E1000_DTXCTL_MDP_EN 0x0020
258 #define E1000_DTXCTL_SPOOF_INT 0x0040
260 #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT BIT(14)
262 #define ALL_QUEUES 0xFFFF
264 /* RX packet buffer size defines */
265 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
266 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
267 void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
268 void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
269 u16 igb_rxpbs_adjust_82580(u32 data);
270 s32 igb_read_emi_reg(struct e1000_hw *, u16 addr, u16 *data);
271 s32 igb_set_eee_i350(struct e1000_hw *, bool adv1G, bool adv100M);
272 s32 igb_set_eee_i354(struct e1000_hw *, bool adv1G, bool adv100M);
273 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status);
275 #define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8
276 #define E1000_EMC_INTERNAL_DATA 0x00
277 #define E1000_EMC_INTERNAL_THERM_LIMIT 0x20
278 #define E1000_EMC_DIODE1_DATA 0x01
279 #define E1000_EMC_DIODE1_THERM_LIMIT 0x19
280 #define E1000_EMC_DIODE2_DATA 0x23
281 #define E1000_EMC_DIODE2_THERM_LIMIT 0x1A
282 #define E1000_EMC_DIODE3_DATA 0x2A
283 #define E1000_EMC_DIODE3_THERM_LIMIT 0x30
284 #endif