drivers/net/ethernet/intel/igb/e1000_i210.h

   1 /* Intel(R) Gigabit Ethernet Linux driver
   2  * Copyright(c) 2007-2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * The full GNU General Public License is included in this distribution in
  17  * the file called "COPYING".
  18  *
  19  * Contact Information:
  20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  */
  23
  24 #ifndef _E1000_I210_H_
  25 #define _E1000_I210_H_
  26
  27 s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
  28 void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
  29 s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data);
  30 s32 igb_read_invm_version(struct e1000_hw *hw,
  31                           struct e1000_fw_version *invm_ver);
  32 s32 igb_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data);
  33 s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data);
  34 s32 igb_init_nvm_params_i210(struct e1000_hw *hw);
  35 bool igb_get_flash_presence_i210(struct e1000_hw *hw);
  36 s32 igb_pll_workaround_i210(struct e1000_hw *hw);
  37 s32 igb_get_cfg_done_i210(struct e1000_hw *hw);
  38
  39 #define E1000_STM_OPCODE                0xDB00
  40 #define E1000_EEPROM_FLASH_SIZE_WORD    0x11
  41
  42 #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \
  43         (u8)((invm_dword) & 0x7)
  44 #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \
  45         (u8)(((invm_dword) & 0x0000FE00) >> 9)
  46 #define INVM_DWORD_TO_WORD_DATA(invm_dword) \
  47         (u16)(((invm_dword) & 0xFFFF0000) >> 16)
  48
  49 enum E1000_INVM_STRUCTURE_TYPE {
  50         E1000_INVM_UNINITIALIZED_STRUCTURE              = 0x00,
  51         E1000_INVM_WORD_AUTOLOAD_STRUCTURE              = 0x01,
  52         E1000_INVM_CSR_AUTOLOAD_STRUCTURE               = 0x02,
  53         E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE      = 0x03,
  54         E1000_INVM_RSA_KEY_SHA256_STRUCTURE             = 0x04,
  55         E1000_INVM_INVALIDATED_STRUCTURE                = 0x0F,
  56 };
  57
  58 #define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS   8
  59 #define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS     1
  60 #define E1000_INVM_ULT_BYTES_SIZE                       8
  61 #define E1000_INVM_RECORD_SIZE_IN_BYTES                 4
  62 #define E1000_INVM_VER_FIELD_ONE                        0x1FF8
  63 #define E1000_INVM_VER_FIELD_TWO                        0x7FE000
  64 #define E1000_INVM_IMGTYPE_FIELD                        0x1F800000
  65
  66 #define E1000_INVM_MAJOR_MASK           0x3F0
  67 #define E1000_INVM_MINOR_MASK           0xF
  68 #define E1000_INVM_MAJOR_SHIFT          4
  69
  70 #define ID_LED_DEFAULT_I210             ((ID_LED_OFF1_ON2  << 8) | \
  71                                          (ID_LED_DEF1_DEF2 <<  4) | \
  72                                          (ID_LED_OFF1_OFF2))
  73 #define ID_LED_DEFAULT_I210_SERDES      ((ID_LED_DEF1_DEF2 << 8) | \
  74                                          (ID_LED_DEF1_DEF2 <<  4) | \
  75                                          (ID_LED_OFF1_ON2))
  76
  77 /* NVM offset defaults for i211 device */
  78 #define NVM_INIT_CTRL_2_DEFAULT_I211    0X7243
  79 #define NVM_INIT_CTRL_4_DEFAULT_I211    0x00C1
  80 #define NVM_LED_1_CFG_DEFAULT_I211      0x0184
  81 #define NVM_LED_0_2_CFG_DEFAULT_I211    0x200C
  82
  83 /* PLL Defines */
  84 #define E1000_PCI_PMCSR                 0x44
  85 #define E1000_PCI_PMCSR_D3              0x03
  86 #define E1000_MAX_PLL_TRIES             5
  87 #define E1000_PHY_PLL_UNCONF            0xFF
  88 #define E1000_PHY_PLL_FREQ_PAGE         0xFC
  89 #define E1000_PHY_PLL_FREQ_REG          0x000E
  90 #define E1000_INVM_DEFAULT_AL           0x202F
  91 #define E1000_INVM_AUTOLOAD             0x0A
  92 #define E1000_INVM_PLL_WO_VAL           0x0010
  93
  94 #endif