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pvrusb2: reduce stack usage pvr2_eeprom_analyze()
[linux/fpc-iii.git] / drivers / net / ethernet / renesas / sh_eth.c
bloba2d218b28c0e22041fb38d197dc8fbc34e9252b4
1 /* SuperH Ethernet device driver
2 *
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
38 #include <linux/io.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
46
47 #include "sh_eth.h"
48
49 #define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
56
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
62
63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155 };
156
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
159
160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
204 [TSU_FWSLC] = 0x0038,
205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
207 [TSU_TEN] = 0x0064,
208 [TSU_POST1] = 0x0070,
209 [TSU_POST2] = 0x0074,
210 [TSU_POST3] = 0x0078,
211 [TSU_POST4] = 0x007c,
212 [TSU_ADRH0] = 0x0100,
213
214 [TXNLCR0] = 0x0080,
215 [TXALCR0] = 0x0084,
216 [RXNLCR0] = 0x0088,
217 [RXALCR0] = 0x008C,
218 };
219
220 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
221 SH_ETH_OFFSET_DEFAULTS,
222
223 [ECMR] = 0x0300,
224 [RFLR] = 0x0308,
225 [ECSR] = 0x0310,
226 [ECSIPR] = 0x0318,
227 [PIR] = 0x0320,
228 [PSR] = 0x0328,
229 [RDMLR] = 0x0340,
230 [IPGR] = 0x0350,
231 [APR] = 0x0354,
232 [MPR] = 0x0358,
233 [RFCF] = 0x0360,
234 [TPAUSER] = 0x0364,
235 [TPAUSECR] = 0x0368,
236 [MAHR] = 0x03c0,
237 [MALR] = 0x03c8,
238 [TROCR] = 0x03d0,
239 [CDCR] = 0x03d4,
240 [LCCR] = 0x03d8,
241 [CNDCR] = 0x03dc,
242 [CEFCR] = 0x03e4,
243 [FRECR] = 0x03e8,
244 [TSFRCR] = 0x03ec,
245 [TLFRCR] = 0x03f0,
246 [RFCR] = 0x03f4,
247 [MAFCR] = 0x03f8,
248
249 [EDMR] = 0x0200,
250 [EDTRR] = 0x0208,
251 [EDRRR] = 0x0210,
252 [TDLAR] = 0x0218,
253 [RDLAR] = 0x0220,
254 [EESR] = 0x0228,
255 [EESIPR] = 0x0230,
256 [TRSCER] = 0x0238,
257 [RMFCR] = 0x0240,
258 [TFTR] = 0x0248,
259 [FDR] = 0x0250,
260 [RMCR] = 0x0258,
261 [TFUCR] = 0x0264,
262 [RFOCR] = 0x0268,
263 [RMIIMODE] = 0x026c,
264 [FCFTR] = 0x0270,
265 [TRIMD] = 0x027c,
266 };
267
268 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
269 SH_ETH_OFFSET_DEFAULTS,
270
271 [ECMR] = 0x0100,
272 [RFLR] = 0x0108,
273 [ECSR] = 0x0110,
274 [ECSIPR] = 0x0118,
275 [PIR] = 0x0120,
276 [PSR] = 0x0128,
277 [RDMLR] = 0x0140,
278 [IPGR] = 0x0150,
279 [APR] = 0x0154,
280 [MPR] = 0x0158,
281 [TPAUSER] = 0x0164,
282 [RFCF] = 0x0160,
283 [TPAUSECR] = 0x0168,
284 [BCFRR] = 0x016c,
285 [MAHR] = 0x01c0,
286 [MALR] = 0x01c8,
287 [TROCR] = 0x01d0,
288 [CDCR] = 0x01d4,
289 [LCCR] = 0x01d8,
290 [CNDCR] = 0x01dc,
291 [CEFCR] = 0x01e4,
292 [FRECR] = 0x01e8,
293 [TSFRCR] = 0x01ec,
294 [TLFRCR] = 0x01f0,
295 [RFCR] = 0x01f4,
296 [MAFCR] = 0x01f8,
297 [RTRATE] = 0x01fc,
298
299 [EDMR] = 0x0000,
300 [EDTRR] = 0x0008,
301 [EDRRR] = 0x0010,
302 [TDLAR] = 0x0018,
303 [RDLAR] = 0x0020,
304 [EESR] = 0x0028,
305 [EESIPR] = 0x0030,
306 [TRSCER] = 0x0038,
307 [RMFCR] = 0x0040,
308 [TFTR] = 0x0048,
309 [FDR] = 0x0050,
310 [RMCR] = 0x0058,
311 [TFUCR] = 0x0064,
312 [RFOCR] = 0x0068,
313 [FCFTR] = 0x0070,
314 [RPADIR] = 0x0078,
315 [TRIMD] = 0x007c,
316 [RBWAR] = 0x00c8,
317 [RDFAR] = 0x00cc,
318 [TBRAR] = 0x00d4,
319 [TDFAR] = 0x00d8,
320 };
321
322 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
323 SH_ETH_OFFSET_DEFAULTS,
324
325 [EDMR] = 0x0000,
326 [EDTRR] = 0x0004,
327 [EDRRR] = 0x0008,
328 [TDLAR] = 0x000c,
329 [RDLAR] = 0x0010,
330 [EESR] = 0x0014,
331 [EESIPR] = 0x0018,
332 [TRSCER] = 0x001c,
333 [RMFCR] = 0x0020,
334 [TFTR] = 0x0024,
335 [FDR] = 0x0028,
336 [RMCR] = 0x002c,
337 [EDOCR] = 0x0030,
338 [FCFTR] = 0x0034,
339 [RPADIR] = 0x0038,
340 [TRIMD] = 0x003c,
341 [RBWAR] = 0x0040,
342 [RDFAR] = 0x0044,
343 [TBRAR] = 0x004c,
344 [TDFAR] = 0x0050,
345
346 [ECMR] = 0x0160,
347 [ECSR] = 0x0164,
348 [ECSIPR] = 0x0168,
349 [PIR] = 0x016c,
350 [MAHR] = 0x0170,
351 [MALR] = 0x0174,
352 [RFLR] = 0x0178,
353 [PSR] = 0x017c,
354 [TROCR] = 0x0180,
355 [CDCR] = 0x0184,
356 [LCCR] = 0x0188,
357 [CNDCR] = 0x018c,
358 [CEFCR] = 0x0194,
359 [FRECR] = 0x0198,
360 [TSFRCR] = 0x019c,
361 [TLFRCR] = 0x01a0,
362 [RFCR] = 0x01a4,
363 [MAFCR] = 0x01a8,
364 [IPGR] = 0x01b4,
365 [APR] = 0x01b8,
366 [MPR] = 0x01bc,
367 [TPAUSER] = 0x01c4,
368 [BCFR] = 0x01cc,
369
370 [ARSTR] = 0x0000,
371 [TSU_CTRST] = 0x0004,
372 [TSU_FWEN0] = 0x0010,
373 [TSU_FWEN1] = 0x0014,
374 [TSU_FCM] = 0x0018,
375 [TSU_BSYSL0] = 0x0020,
376 [TSU_BSYSL1] = 0x0024,
377 [TSU_PRISL0] = 0x0028,
378 [TSU_PRISL1] = 0x002c,
379 [TSU_FWSL0] = 0x0030,
380 [TSU_FWSL1] = 0x0034,
381 [TSU_FWSLC] = 0x0038,
382 [TSU_QTAGM0] = 0x0040,
383 [TSU_QTAGM1] = 0x0044,
384 [TSU_ADQT0] = 0x0048,
385 [TSU_ADQT1] = 0x004c,
386 [TSU_FWSR] = 0x0050,
387 [TSU_FWINMK] = 0x0054,
388 [TSU_ADSBSY] = 0x0060,
389 [TSU_TEN] = 0x0064,
390 [TSU_POST1] = 0x0070,
391 [TSU_POST2] = 0x0074,
392 [TSU_POST3] = 0x0078,
393 [TSU_POST4] = 0x007c,
394
395 [TXNLCR0] = 0x0080,
396 [TXALCR0] = 0x0084,
397 [RXNLCR0] = 0x0088,
398 [RXALCR0] = 0x008c,
399 [FWNLCR0] = 0x0090,
400 [FWALCR0] = 0x0094,
401 [TXNLCR1] = 0x00a0,
402 [TXALCR1] = 0x00a0,
403 [RXNLCR1] = 0x00a8,
404 [RXALCR1] = 0x00ac,
405 [FWNLCR1] = 0x00b0,
406 [FWALCR1] = 0x00b4,
407
408 [TSU_ADRH0] = 0x0100,
409 };
410
411 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
412 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
413
414 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
415 {
416 struct sh_eth_private *mdp = netdev_priv(ndev);
417 u16 offset = mdp->reg_offset[enum_index];
418
419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
420 return;
421
422 iowrite32(data, mdp->addr + offset);
423 }
424
425 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
426 {
427 struct sh_eth_private *mdp = netdev_priv(ndev);
428 u16 offset = mdp->reg_offset[enum_index];
429
430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
431 return ~0U;
432
433 return ioread32(mdp->addr + offset);
434 }
435
436 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
437 u32 set)
438 {
439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
440 enum_index);
441 }
442
443 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
444 {
445 return mdp->reg_offset == sh_eth_offset_gigabit;
446 }
447
448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
449 {
450 return mdp->reg_offset == sh_eth_offset_fast_rz;
451 }
452
453 static void sh_eth_select_mii(struct net_device *ndev)
454 {
455 struct sh_eth_private *mdp = netdev_priv(ndev);
456 u32 value;
457
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
460 value = 0x2;
461 break;
462 case PHY_INTERFACE_MODE_MII:
463 value = 0x1;
464 break;
465 case PHY_INTERFACE_MODE_RMII:
466 value = 0x0;
467 break;
468 default:
469 netdev_warn(ndev,
470 "PHY interface mode was not setup. Set to MII.\n");
471 value = 0x1;
472 break;
473 }
474
475 sh_eth_write(ndev, value, RMII_MII);
476 }
477
478 static void sh_eth_set_duplex(struct net_device *ndev)
479 {
480 struct sh_eth_private *mdp = netdev_priv(ndev);
481
482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
483 }
484
485 static void sh_eth_chip_reset(struct net_device *ndev)
486 {
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488
489 /* reset device */
490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
491 mdelay(1);
492 }
493
494 static void sh_eth_set_rate_gether(struct net_device *ndev)
495 {
496 struct sh_eth_private *mdp = netdev_priv(ndev);
497
498 switch (mdp->speed) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev, GECMR_10, GECMR);
501 break;
502 case 100:/* 100BASE */
503 sh_eth_write(ndev, GECMR_100, GECMR);
504 break;
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev, GECMR_1000, GECMR);
507 break;
508 }
509 }
510
511 #ifdef CONFIG_OF
512 /* R7S72100 */
513 static struct sh_eth_cpu_data r7s72100_data = {
514 .chip_reset = sh_eth_chip_reset,
515 .set_duplex = sh_eth_set_duplex,
516
517 .register_type = SH_ETH_REG_FAST_RZ,
518
519 .ecsr_value = ECSR_ICD,
520 .ecsipr_value = ECSIPR_ICDIP,
521 .eesipr_value = 0xe77f009f,
522
523 .tx_check = EESR_TC1 | EESR_FTC,
524 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
525 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
526 EESR_TDE | EESR_ECI,
527 .fdr_value = 0x0000070f,
528
529 .no_psr = 1,
530 .apr = 1,
531 .mpr = 1,
532 .tpauser = 1,
533 .hw_swap = 1,
534 .rpadir = 1,
535 .rpadir_value = 2 << 16,
536 .no_trimd = 1,
537 .no_ade = 1,
538 .hw_crc = 1,
539 .tsu = 1,
540 .shift_rd0 = 1,
541 };
542
543 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
544 {
545 sh_eth_chip_reset(ndev);
546
547 sh_eth_select_mii(ndev);
548 }
549
550 /* R8A7740 */
551 static struct sh_eth_cpu_data r8a7740_data = {
552 .chip_reset = sh_eth_chip_reset_r8a7740,
553 .set_duplex = sh_eth_set_duplex,
554 .set_rate = sh_eth_set_rate_gether,
555
556 .register_type = SH_ETH_REG_GIGABIT,
557
558 .ecsr_value = ECSR_ICD | ECSR_MPD,
559 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
560 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
561
562 .tx_check = EESR_TC1 | EESR_FTC,
563 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
564 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
565 EESR_TDE | EESR_ECI,
566 .fdr_value = 0x0000070f,
567
568 .apr = 1,
569 .mpr = 1,
570 .tpauser = 1,
571 .bculr = 1,
572 .hw_swap = 1,
573 .rpadir = 1,
574 .rpadir_value = 2 << 16,
575 .no_trimd = 1,
576 .no_ade = 1,
577 .tsu = 1,
578 .select_mii = 1,
579 .shift_rd0 = 1,
580 };
581
582 /* There is CPU dependent code */
583 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
584 {
585 struct sh_eth_private *mdp = netdev_priv(ndev);
586
587 switch (mdp->speed) {
588 case 10: /* 10BASE */
589 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
590 break;
591 case 100:/* 100BASE */
592 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
593 break;
594 }
595 }
596
597 /* R8A7778/9 */
598 static struct sh_eth_cpu_data r8a777x_data = {
599 .set_duplex = sh_eth_set_duplex,
600 .set_rate = sh_eth_set_rate_r8a777x,
601
602 .register_type = SH_ETH_REG_FAST_RCAR,
603
604 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
605 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
606 .eesipr_value = 0x01ff009f,
607
608 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
609 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
610 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
611 EESR_ECI,
612 .fdr_value = 0x00000f0f,
613
614 .apr = 1,
615 .mpr = 1,
616 .tpauser = 1,
617 .hw_swap = 1,
618 };
619
620 /* R8A7790/1 */
621 static struct sh_eth_cpu_data r8a779x_data = {
622 .set_duplex = sh_eth_set_duplex,
623 .set_rate = sh_eth_set_rate_r8a777x,
624
625 .register_type = SH_ETH_REG_FAST_RCAR,
626
627 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
628 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
629 .eesipr_value = 0x01ff009f,
630
631 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
632 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
633 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
634 EESR_ECI,
635 .fdr_value = 0x00000f0f,
636
637 .trscer_err_mask = DESC_I_RINT8,
638
639 .apr = 1,
640 .mpr = 1,
641 .tpauser = 1,
642 .hw_swap = 1,
643 .rmiimode = 1,
644 };
645 #endif /* CONFIG_OF */
646
647 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
648 {
649 struct sh_eth_private *mdp = netdev_priv(ndev);
650
651 switch (mdp->speed) {
652 case 10: /* 10BASE */
653 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
654 break;
655 case 100:/* 100BASE */
656 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
657 break;
658 }
659 }
660
661 /* SH7724 */
662 static struct sh_eth_cpu_data sh7724_data = {
663 .set_duplex = sh_eth_set_duplex,
664 .set_rate = sh_eth_set_rate_sh7724,
665
666 .register_type = SH_ETH_REG_FAST_SH4,
667
668 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
669 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
670 .eesipr_value = 0x01ff009f,
671
672 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
673 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
674 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
675 EESR_ECI,
676
677 .apr = 1,
678 .mpr = 1,
679 .tpauser = 1,
680 .hw_swap = 1,
681 .rpadir = 1,
682 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
683 };
684
685 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
686 {
687 struct sh_eth_private *mdp = netdev_priv(ndev);
688
689 switch (mdp->speed) {
690 case 10: /* 10BASE */
691 sh_eth_write(ndev, 0, RTRATE);
692 break;
693 case 100:/* 100BASE */
694 sh_eth_write(ndev, 1, RTRATE);
695 break;
696 }
697 }
698
699 /* SH7757 */
700 static struct sh_eth_cpu_data sh7757_data = {
701 .set_duplex = sh_eth_set_duplex,
702 .set_rate = sh_eth_set_rate_sh7757,
703
704 .register_type = SH_ETH_REG_FAST_SH4,
705
706 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
707
708 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
709 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
710 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
711 EESR_ECI,
712
713 .irq_flags = IRQF_SHARED,
714 .apr = 1,
715 .mpr = 1,
716 .tpauser = 1,
717 .hw_swap = 1,
718 .no_ade = 1,
719 .rpadir = 1,
720 .rpadir_value = 2 << 16,
721 .rtrate = 1,
722 };
723
724 #define SH_GIGA_ETH_BASE 0xfee00000UL
725 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
726 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
727 static void sh_eth_chip_reset_giga(struct net_device *ndev)
728 {
729 u32 mahr[2], malr[2];
730 int i;
731
732 /* save MAHR and MALR */
733 for (i = 0; i < 2; i++) {
734 malr[i] = ioread32((void *)GIGA_MALR(i));
735 mahr[i] = ioread32((void *)GIGA_MAHR(i));
736 }
737
738 sh_eth_chip_reset(ndev);
739
740 /* restore MAHR and MALR */
741 for (i = 0; i < 2; i++) {
742 iowrite32(malr[i], (void *)GIGA_MALR(i));
743 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
744 }
745 }
746
747 static void sh_eth_set_rate_giga(struct net_device *ndev)
748 {
749 struct sh_eth_private *mdp = netdev_priv(ndev);
750
751 switch (mdp->speed) {
752 case 10: /* 10BASE */
753 sh_eth_write(ndev, 0x00000000, GECMR);
754 break;
755 case 100:/* 100BASE */
756 sh_eth_write(ndev, 0x00000010, GECMR);
757 break;
758 case 1000: /* 1000BASE */
759 sh_eth_write(ndev, 0x00000020, GECMR);
760 break;
761 }
762 }
763
764 /* SH7757(GETHERC) */
765 static struct sh_eth_cpu_data sh7757_data_giga = {
766 .chip_reset = sh_eth_chip_reset_giga,
767 .set_duplex = sh_eth_set_duplex,
768 .set_rate = sh_eth_set_rate_giga,
769
770 .register_type = SH_ETH_REG_GIGABIT,
771
772 .ecsr_value = ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
774 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
775
776 .tx_check = EESR_TC1 | EESR_FTC,
777 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
778 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
779 EESR_TDE | EESR_ECI,
780 .fdr_value = 0x0000072f,
781
782 .irq_flags = IRQF_SHARED,
783 .apr = 1,
784 .mpr = 1,
785 .tpauser = 1,
786 .bculr = 1,
787 .hw_swap = 1,
788 .rpadir = 1,
789 .rpadir_value = 2 << 16,
790 .no_trimd = 1,
791 .no_ade = 1,
792 .tsu = 1,
793 };
794
795 /* SH7734 */
796 static struct sh_eth_cpu_data sh7734_data = {
797 .chip_reset = sh_eth_chip_reset,
798 .set_duplex = sh_eth_set_duplex,
799 .set_rate = sh_eth_set_rate_gether,
800
801 .register_type = SH_ETH_REG_GIGABIT,
802
803 .ecsr_value = ECSR_ICD | ECSR_MPD,
804 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
805 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
806
807 .tx_check = EESR_TC1 | EESR_FTC,
808 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
809 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
810 EESR_TDE | EESR_ECI,
811
812 .apr = 1,
813 .mpr = 1,
814 .tpauser = 1,
815 .bculr = 1,
816 .hw_swap = 1,
817 .no_trimd = 1,
818 .no_ade = 1,
819 .tsu = 1,
820 .hw_crc = 1,
821 .select_mii = 1,
822 };
823
824 /* SH7763 */
825 static struct sh_eth_cpu_data sh7763_data = {
826 .chip_reset = sh_eth_chip_reset,
827 .set_duplex = sh_eth_set_duplex,
828 .set_rate = sh_eth_set_rate_gether,
829
830 .register_type = SH_ETH_REG_GIGABIT,
831
832 .ecsr_value = ECSR_ICD | ECSR_MPD,
833 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
834 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
835
836 .tx_check = EESR_TC1 | EESR_FTC,
837 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
838 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
839 EESR_ECI,
840
841 .apr = 1,
842 .mpr = 1,
843 .tpauser = 1,
844 .bculr = 1,
845 .hw_swap = 1,
846 .no_trimd = 1,
847 .no_ade = 1,
848 .tsu = 1,
849 .irq_flags = IRQF_SHARED,
850 };
851
852 static struct sh_eth_cpu_data sh7619_data = {
853 .register_type = SH_ETH_REG_FAST_SH3_SH2,
854
855 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
856
857 .apr = 1,
858 .mpr = 1,
859 .tpauser = 1,
860 .hw_swap = 1,
861 };
862
863 static struct sh_eth_cpu_data sh771x_data = {
864 .register_type = SH_ETH_REG_FAST_SH3_SH2,
865
866 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
867 .tsu = 1,
868 };
869
870 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
871 {
872 if (!cd->ecsr_value)
873 cd->ecsr_value = DEFAULT_ECSR_INIT;
874
875 if (!cd->ecsipr_value)
876 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
877
878 if (!cd->fcftr_value)
879 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
880 DEFAULT_FIFO_F_D_RFD;
881
882 if (!cd->fdr_value)
883 cd->fdr_value = DEFAULT_FDR_INIT;
884
885 if (!cd->tx_check)
886 cd->tx_check = DEFAULT_TX_CHECK;
887
888 if (!cd->eesr_err_check)
889 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
890
891 if (!cd->trscer_err_mask)
892 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
893 }
894
895 static int sh_eth_check_reset(struct net_device *ndev)
896 {
897 int ret = 0;
898 int cnt = 100;
899
900 while (cnt > 0) {
901 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
902 break;
903 mdelay(1);
904 cnt--;
905 }
906 if (cnt <= 0) {
907 netdev_err(ndev, "Device reset failed\n");
908 ret = -ETIMEDOUT;
909 }
910 return ret;
911 }
912
913 static int sh_eth_reset(struct net_device *ndev)
914 {
915 struct sh_eth_private *mdp = netdev_priv(ndev);
916 int ret = 0;
917
918 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
919 sh_eth_write(ndev, EDSR_ENALL, EDSR);
920 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
921
922 ret = sh_eth_check_reset(ndev);
923 if (ret)
924 return ret;
925
926 /* Table Init */
927 sh_eth_write(ndev, 0x0, TDLAR);
928 sh_eth_write(ndev, 0x0, TDFAR);
929 sh_eth_write(ndev, 0x0, TDFXR);
930 sh_eth_write(ndev, 0x0, TDFFR);
931 sh_eth_write(ndev, 0x0, RDLAR);
932 sh_eth_write(ndev, 0x0, RDFAR);
933 sh_eth_write(ndev, 0x0, RDFXR);
934 sh_eth_write(ndev, 0x0, RDFFR);
935
936 /* Reset HW CRC register */
937 if (mdp->cd->hw_crc)
938 sh_eth_write(ndev, 0x0, CSMR);
939
940 /* Select MII mode */
941 if (mdp->cd->select_mii)
942 sh_eth_select_mii(ndev);
943 } else {
944 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
945 mdelay(3);
946 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
947 }
948
949 return ret;
950 }
951
952 static void sh_eth_set_receive_align(struct sk_buff *skb)
953 {
954 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
955
956 if (reserve)
957 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
958 }
959
960 /* Program the hardware MAC address from dev->dev_addr. */
961 static void update_mac_address(struct net_device *ndev)
962 {
963 sh_eth_write(ndev,
964 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
965 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
966 sh_eth_write(ndev,
967 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
968 }
969
970 /* Get MAC address from SuperH MAC address register
971 *
972 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
973 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
974 * When you want use this device, you must set MAC address in bootloader.
975 *
976 */
977 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
978 {
979 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
980 memcpy(ndev->dev_addr, mac, ETH_ALEN);
981 } else {
982 u32 mahr = sh_eth_read(ndev, MAHR);
983 u32 malr = sh_eth_read(ndev, MALR);
984
985 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
986 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
987 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
988 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
989 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
990 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
991 }
992 }
993
994 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
995 {
996 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
997 return EDTRR_TRNS_GETHER;
998 else
999 return EDTRR_TRNS_ETHER;
1000 }
1001
1002 struct bb_info {
1003 void (*set_gate)(void *addr);
1004 struct mdiobb_ctrl ctrl;
1005 void *addr;
1006 };
1007
1008 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1009 {
1010 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1011 u32 pir;
1012
1013 if (bitbang->set_gate)
1014 bitbang->set_gate(bitbang->addr);
1015
1016 pir = ioread32(bitbang->addr);
1017 if (set)
1018 pir |= mask;
1019 else
1020 pir &= ~mask;
1021 iowrite32(pir, bitbang->addr);
1022 }
1023
1024 /* Data I/O pin control */
1025 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1026 {
1027 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1028 }
1029
1030 /* Set bit data*/
1031 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1032 {
1033 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1034 }
1035
1036 /* Get bit data*/
1037 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1038 {
1039 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1040
1041 if (bitbang->set_gate)
1042 bitbang->set_gate(bitbang->addr);
1043
1044 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1045 }
1046
1047 /* MDC pin control */
1048 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1049 {
1050 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1051 }
1052
1053 /* mdio bus control struct */
1054 static struct mdiobb_ops bb_ops = {
1055 .owner = THIS_MODULE,
1056 .set_mdc = sh_mdc_ctrl,
1057 .set_mdio_dir = sh_mmd_ctrl,
1058 .set_mdio_data = sh_set_mdio,
1059 .get_mdio_data = sh_get_mdio,
1060 };
1061
1062 /* free Tx skb function */
1063 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1064 {
1065 struct sh_eth_private *mdp = netdev_priv(ndev);
1066 struct sh_eth_txdesc *txdesc;
1067 int free_num = 0;
1068 int entry;
1069 bool sent;
1070
1071 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1072 entry = mdp->dirty_tx % mdp->num_tx_ring;
1073 txdesc = &mdp->tx_ring[entry];
1074 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1075 if (sent_only && !sent)
1076 break;
1077 /* TACT bit must be checked before all the following reads */
1078 dma_rmb();
1079 netif_info(mdp, tx_done, ndev,
1080 "tx entry %d status 0x%08x\n",
1081 entry, le32_to_cpu(txdesc->status));
1082 /* Free the original skb. */
1083 if (mdp->tx_skbuff[entry]) {
1084 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1085 le32_to_cpu(txdesc->len) >> 16,
1086 DMA_TO_DEVICE);
1087 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1088 mdp->tx_skbuff[entry] = NULL;
1089 free_num++;
1090 }
1091 txdesc->status = cpu_to_le32(TD_TFP);
1092 if (entry >= mdp->num_tx_ring - 1)
1093 txdesc->status |= cpu_to_le32(TD_TDLE);
1094
1095 if (sent) {
1096 ndev->stats.tx_packets++;
1097 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1098 }
1099 }
1100 return free_num;
1101 }
1102
1103 /* free skb and descriptor buffer */
1104 static void sh_eth_ring_free(struct net_device *ndev)
1105 {
1106 struct sh_eth_private *mdp = netdev_priv(ndev);
1107 int ringsize, i;
1108
1109 if (mdp->rx_ring) {
1110 for (i = 0; i < mdp->num_rx_ring; i++) {
1111 if (mdp->rx_skbuff[i]) {
1112 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1113
1114 dma_unmap_single(&ndev->dev,
1115 le32_to_cpu(rxdesc->addr),
1116 ALIGN(mdp->rx_buf_sz, 32),
1117 DMA_FROM_DEVICE);
1118 }
1119 }
1120 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1121 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1122 mdp->rx_desc_dma);
1123 mdp->rx_ring = NULL;
1124 }
1125
1126 /* Free Rx skb ringbuffer */
1127 if (mdp->rx_skbuff) {
1128 for (i = 0; i < mdp->num_rx_ring; i++)
1129 dev_kfree_skb(mdp->rx_skbuff[i]);
1130 }
1131 kfree(mdp->rx_skbuff);
1132 mdp->rx_skbuff = NULL;
1133
1134 if (mdp->tx_ring) {
1135 sh_eth_tx_free(ndev, false);
1136
1137 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1138 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1139 mdp->tx_desc_dma);
1140 mdp->tx_ring = NULL;
1141 }
1142
1143 /* Free Tx skb ringbuffer */
1144 kfree(mdp->tx_skbuff);
1145 mdp->tx_skbuff = NULL;
1146 }
1147
1148 /* format skb and descriptor buffer */
1149 static void sh_eth_ring_format(struct net_device *ndev)
1150 {
1151 struct sh_eth_private *mdp = netdev_priv(ndev);
1152 int i;
1153 struct sk_buff *skb;
1154 struct sh_eth_rxdesc *rxdesc = NULL;
1155 struct sh_eth_txdesc *txdesc = NULL;
1156 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1157 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1158 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1159 dma_addr_t dma_addr;
1160 u32 buf_len;
1161
1162 mdp->cur_rx = 0;
1163 mdp->cur_tx = 0;
1164 mdp->dirty_rx = 0;
1165 mdp->dirty_tx = 0;
1166
1167 memset(mdp->rx_ring, 0, rx_ringsize);
1168
1169 /* build Rx ring buffer */
1170 for (i = 0; i < mdp->num_rx_ring; i++) {
1171 /* skb */
1172 mdp->rx_skbuff[i] = NULL;
1173 skb = netdev_alloc_skb(ndev, skbuff_size);
1174 if (skb == NULL)
1175 break;
1176 sh_eth_set_receive_align(skb);
1177
1178 /* The size of the buffer is a multiple of 32 bytes. */
1179 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1180 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1181 DMA_FROM_DEVICE);
1182 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1183 kfree_skb(skb);
1184 break;
1185 }
1186 mdp->rx_skbuff[i] = skb;
1187
1188 /* RX descriptor */
1189 rxdesc = &mdp->rx_ring[i];
1190 rxdesc->len = cpu_to_le32(buf_len << 16);
1191 rxdesc->addr = cpu_to_le32(dma_addr);
1192 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1193
1194 /* Rx descriptor address set */
1195 if (i == 0) {
1196 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1197 if (sh_eth_is_gether(mdp) ||
1198 sh_eth_is_rz_fast_ether(mdp))
1199 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1200 }
1201 }
1202
1203 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1204
1205 /* Mark the last entry as wrapping the ring. */
1206 if (rxdesc)
1207 rxdesc->status |= cpu_to_le32(RD_RDLE);
1208
1209 memset(mdp->tx_ring, 0, tx_ringsize);
1210
1211 /* build Tx ring buffer */
1212 for (i = 0; i < mdp->num_tx_ring; i++) {
1213 mdp->tx_skbuff[i] = NULL;
1214 txdesc = &mdp->tx_ring[i];
1215 txdesc->status = cpu_to_le32(TD_TFP);
1216 txdesc->len = cpu_to_le32(0);
1217 if (i == 0) {
1218 /* Tx descriptor address set */
1219 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1220 if (sh_eth_is_gether(mdp) ||
1221 sh_eth_is_rz_fast_ether(mdp))
1222 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1223 }
1224 }
1225
1226 txdesc->status |= cpu_to_le32(TD_TDLE);
1227 }
1228
1229 /* Get skb and descriptor buffer */
1230 static int sh_eth_ring_init(struct net_device *ndev)
1231 {
1232 struct sh_eth_private *mdp = netdev_priv(ndev);
1233 int rx_ringsize, tx_ringsize;
1234
1235 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1236 * card needs room to do 8 byte alignment, +2 so we can reserve
1237 * the first 2 bytes, and +16 gets room for the status word from the
1238 * card.
1239 */
1240 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1241 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1242 if (mdp->cd->rpadir)
1243 mdp->rx_buf_sz += NET_IP_ALIGN;
1244
1245 /* Allocate RX and TX skb rings */
1246 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1247 GFP_KERNEL);
1248 if (!mdp->rx_skbuff)
1249 return -ENOMEM;
1250
1251 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1252 GFP_KERNEL);
1253 if (!mdp->tx_skbuff)
1254 goto ring_free;
1255
1256 /* Allocate all Rx descriptors. */
1257 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1258 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1259 GFP_KERNEL);
1260 if (!mdp->rx_ring)
1261 goto ring_free;
1262
1263 mdp->dirty_rx = 0;
1264
1265 /* Allocate all Tx descriptors. */
1266 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1267 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1268 GFP_KERNEL);
1269 if (!mdp->tx_ring)
1270 goto ring_free;
1271 return 0;
1272
1273 ring_free:
1274 /* Free Rx and Tx skb ring buffer and DMA buffer */
1275 sh_eth_ring_free(ndev);
1276
1277 return -ENOMEM;
1278 }
1279
1280 static int sh_eth_dev_init(struct net_device *ndev)
1281 {
1282 struct sh_eth_private *mdp = netdev_priv(ndev);
1283 int ret;
1284
1285 /* Soft Reset */
1286 ret = sh_eth_reset(ndev);
1287 if (ret)
1288 return ret;
1289
1290 if (mdp->cd->rmiimode)
1291 sh_eth_write(ndev, 0x1, RMIIMODE);
1292
1293 /* Descriptor format */
1294 sh_eth_ring_format(ndev);
1295 if (mdp->cd->rpadir)
1296 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1297
1298 /* all sh_eth int mask */
1299 sh_eth_write(ndev, 0, EESIPR);
1300
1301 #if defined(__LITTLE_ENDIAN)
1302 if (mdp->cd->hw_swap)
1303 sh_eth_write(ndev, EDMR_EL, EDMR);
1304 else
1305 #endif
1306 sh_eth_write(ndev, 0, EDMR);
1307
1308 /* FIFO size set */
1309 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1310 sh_eth_write(ndev, 0, TFTR);
1311
1312 /* Frame recv control (enable multiple-packets per rx irq) */
1313 sh_eth_write(ndev, RMCR_RNC, RMCR);
1314
1315 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1316
1317 if (mdp->cd->bculr)
1318 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1319
1320 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1321
1322 if (!mdp->cd->no_trimd)
1323 sh_eth_write(ndev, 0, TRIMD);
1324
1325 /* Recv frame limit set register */
1326 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1327 RFLR);
1328
1329 sh_eth_modify(ndev, EESR, 0, 0);
1330 mdp->irq_enabled = true;
1331 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1332
1333 /* PAUSE Prohibition */
1334 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1335 ECMR_TE | ECMR_RE, ECMR);
1336
1337 if (mdp->cd->set_rate)
1338 mdp->cd->set_rate(ndev);
1339
1340 /* E-MAC Status Register clear */
1341 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1342
1343 /* E-MAC Interrupt Enable register */
1344 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1345
1346 /* Set MAC address */
1347 update_mac_address(ndev);
1348
1349 /* mask reset */
1350 if (mdp->cd->apr)
1351 sh_eth_write(ndev, APR_AP, APR);
1352 if (mdp->cd->mpr)
1353 sh_eth_write(ndev, MPR_MP, MPR);
1354 if (mdp->cd->tpauser)
1355 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1356
1357 /* Setting the Rx mode will start the Rx process. */
1358 sh_eth_write(ndev, EDRRR_R, EDRRR);
1359
1360 return ret;
1361 }
1362
1363 static void sh_eth_dev_exit(struct net_device *ndev)
1364 {
1365 struct sh_eth_private *mdp = netdev_priv(ndev);
1366 int i;
1367
1368 /* Deactivate all TX descriptors, so DMA should stop at next
1369 * packet boundary if it's currently running
1370 */
1371 for (i = 0; i < mdp->num_tx_ring; i++)
1372 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1373
1374 /* Disable TX FIFO egress to MAC */
1375 sh_eth_rcv_snd_disable(ndev);
1376
1377 /* Stop RX DMA at next packet boundary */
1378 sh_eth_write(ndev, 0, EDRRR);
1379
1380 /* Aside from TX DMA, we can't tell when the hardware is
1381 * really stopped, so we need to reset to make sure.
1382 * Before doing that, wait for long enough to *probably*
1383 * finish transmitting the last packet and poll stats.
1384 */
1385 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1386 sh_eth_get_stats(ndev);
1387 sh_eth_reset(ndev);
1388
1389 /* Set MAC address again */
1390 update_mac_address(ndev);
1391 }
1392
1393 /* Packet receive function */
1394 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1395 {
1396 struct sh_eth_private *mdp = netdev_priv(ndev);
1397 struct sh_eth_rxdesc *rxdesc;
1398
1399 int entry = mdp->cur_rx % mdp->num_rx_ring;
1400 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1401 int limit;
1402 struct sk_buff *skb;
1403 u32 desc_status;
1404 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1405 dma_addr_t dma_addr;
1406 u16 pkt_len;
1407 u32 buf_len;
1408
1409 boguscnt = min(boguscnt, *quota);
1410 limit = boguscnt;
1411 rxdesc = &mdp->rx_ring[entry];
1412 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1413 /* RACT bit must be checked before all the following reads */
1414 dma_rmb();
1415 desc_status = le32_to_cpu(rxdesc->status);
1416 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1417
1418 if (--boguscnt < 0)
1419 break;
1420
1421 netif_info(mdp, rx_status, ndev,
1422 "rx entry %d status 0x%08x len %d\n",
1423 entry, desc_status, pkt_len);
1424
1425 if (!(desc_status & RDFEND))
1426 ndev->stats.rx_length_errors++;
1427
1428 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1429 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1430 * bit 0. However, in case of the R8A7740 and R7S72100
1431 * the RFS bits are from bit 25 to bit 16. So, the
1432 * driver needs right shifting by 16.
1433 */
1434 if (mdp->cd->shift_rd0)
1435 desc_status >>= 16;
1436
1437 skb = mdp->rx_skbuff[entry];
1438 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1439 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1440 ndev->stats.rx_errors++;
1441 if (desc_status & RD_RFS1)
1442 ndev->stats.rx_crc_errors++;
1443 if (desc_status & RD_RFS2)
1444 ndev->stats.rx_frame_errors++;
1445 if (desc_status & RD_RFS3)
1446 ndev->stats.rx_length_errors++;
1447 if (desc_status & RD_RFS4)
1448 ndev->stats.rx_length_errors++;
1449 if (desc_status & RD_RFS6)
1450 ndev->stats.rx_missed_errors++;
1451 if (desc_status & RD_RFS10)
1452 ndev->stats.rx_over_errors++;
1453 } else if (skb) {
1454 dma_addr = le32_to_cpu(rxdesc->addr);
1455 if (!mdp->cd->hw_swap)
1456 sh_eth_soft_swap(
1457 phys_to_virt(ALIGN(dma_addr, 4)),
1458 pkt_len + 2);
1459 mdp->rx_skbuff[entry] = NULL;
1460 if (mdp->cd->rpadir)
1461 skb_reserve(skb, NET_IP_ALIGN);
1462 dma_unmap_single(&ndev->dev, dma_addr,
1463 ALIGN(mdp->rx_buf_sz, 32),
1464 DMA_FROM_DEVICE);
1465 skb_put(skb, pkt_len);
1466 skb->protocol = eth_type_trans(skb, ndev);
1467 netif_receive_skb(skb);
1468 ndev->stats.rx_packets++;
1469 ndev->stats.rx_bytes += pkt_len;
1470 if (desc_status & RD_RFS8)
1471 ndev->stats.multicast++;
1472 }
1473 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1474 rxdesc = &mdp->rx_ring[entry];
1475 }
1476
1477 /* Refill the Rx ring buffers. */
1478 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1479 entry = mdp->dirty_rx % mdp->num_rx_ring;
1480 rxdesc = &mdp->rx_ring[entry];
1481 /* The size of the buffer is 32 byte boundary. */
1482 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1483 rxdesc->len = cpu_to_le32(buf_len << 16);
1484
1485 if (mdp->rx_skbuff[entry] == NULL) {
1486 skb = netdev_alloc_skb(ndev, skbuff_size);
1487 if (skb == NULL)
1488 break; /* Better luck next round. */
1489 sh_eth_set_receive_align(skb);
1490 dma_addr = dma_map_single(&ndev->dev, skb->data,
1491 buf_len, DMA_FROM_DEVICE);
1492 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1493 kfree_skb(skb);
1494 break;
1495 }
1496 mdp->rx_skbuff[entry] = skb;
1497
1498 skb_checksum_none_assert(skb);
1499 rxdesc->addr = cpu_to_le32(dma_addr);
1500 }
1501 dma_wmb(); /* RACT bit must be set after all the above writes */
1502 if (entry >= mdp->num_rx_ring - 1)
1503 rxdesc->status |=
1504 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1505 else
1506 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1507 }
1508
1509 /* Restart Rx engine if stopped. */
1510 /* If we don't need to check status, don't. -KDU */
1511 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1512 /* fix the values for the next receiving if RDE is set */
1513 if (intr_status & EESR_RDE &&
1514 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1515 u32 count = (sh_eth_read(ndev, RDFAR) -
1516 sh_eth_read(ndev, RDLAR)) >> 4;
1517
1518 mdp->cur_rx = count;
1519 mdp->dirty_rx = count;
1520 }
1521 sh_eth_write(ndev, EDRRR_R, EDRRR);
1522 }
1523
1524 *quota -= limit - boguscnt - 1;
1525
1526 return *quota <= 0;
1527 }
1528
1529 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1530 {
1531 /* disable tx and rx */
1532 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1533 }
1534
1535 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1536 {
1537 /* enable tx and rx */
1538 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1539 }
1540
1541 /* error control function */
1542 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1543 {
1544 struct sh_eth_private *mdp = netdev_priv(ndev);
1545 u32 felic_stat;
1546 u32 link_stat;
1547 u32 mask;
1548
1549 if (intr_status & EESR_ECI) {
1550 felic_stat = sh_eth_read(ndev, ECSR);
1551 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1552 if (felic_stat & ECSR_ICD)
1553 ndev->stats.tx_carrier_errors++;
1554 if (felic_stat & ECSR_LCHNG) {
1555 /* Link Changed */
1556 if (mdp->cd->no_psr || mdp->no_ether_link) {
1557 goto ignore_link;
1558 } else {
1559 link_stat = (sh_eth_read(ndev, PSR));
1560 if (mdp->ether_link_active_low)
1561 link_stat = ~link_stat;
1562 }
1563 if (!(link_stat & PHY_ST_LINK)) {
1564 sh_eth_rcv_snd_disable(ndev);
1565 } else {
1566 /* Link Up */
1567 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
1568 /* clear int */
1569 sh_eth_modify(ndev, ECSR, 0, 0);
1570 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1571 DMAC_M_ECI);
1572 /* enable tx and rx */
1573 sh_eth_rcv_snd_enable(ndev);
1574 }
1575 }
1576 }
1577
1578 ignore_link:
1579 if (intr_status & EESR_TWB) {
1580 /* Unused write back interrupt */
1581 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1582 ndev->stats.tx_aborted_errors++;
1583 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1584 }
1585 }
1586
1587 if (intr_status & EESR_RABT) {
1588 /* Receive Abort int */
1589 if (intr_status & EESR_RFRMER) {
1590 /* Receive Frame Overflow int */
1591 ndev->stats.rx_frame_errors++;
1592 }
1593 }
1594
1595 if (intr_status & EESR_TDE) {
1596 /* Transmit Descriptor Empty int */
1597 ndev->stats.tx_fifo_errors++;
1598 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1599 }
1600
1601 if (intr_status & EESR_TFE) {
1602 /* FIFO under flow */
1603 ndev->stats.tx_fifo_errors++;
1604 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1605 }
1606
1607 if (intr_status & EESR_RDE) {
1608 /* Receive Descriptor Empty int */
1609 ndev->stats.rx_over_errors++;
1610 }
1611
1612 if (intr_status & EESR_RFE) {
1613 /* Receive FIFO Overflow int */
1614 ndev->stats.rx_fifo_errors++;
1615 }
1616
1617 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1618 /* Address Error */
1619 ndev->stats.tx_fifo_errors++;
1620 netif_err(mdp, tx_err, ndev, "Address Error\n");
1621 }
1622
1623 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1624 if (mdp->cd->no_ade)
1625 mask &= ~EESR_ADE;
1626 if (intr_status & mask) {
1627 /* Tx error */
1628 u32 edtrr = sh_eth_read(ndev, EDTRR);
1629
1630 /* dmesg */
1631 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1632 intr_status, mdp->cur_tx, mdp->dirty_tx,
1633 (u32)ndev->state, edtrr);
1634 /* dirty buffer free */
1635 sh_eth_tx_free(ndev, true);
1636
1637 /* SH7712 BUG */
1638 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1639 /* tx dma start */
1640 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1641 }
1642 /* wakeup */
1643 netif_wake_queue(ndev);
1644 }
1645 }
1646
1647 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1648 {
1649 struct net_device *ndev = netdev;
1650 struct sh_eth_private *mdp = netdev_priv(ndev);
1651 struct sh_eth_cpu_data *cd = mdp->cd;
1652 irqreturn_t ret = IRQ_NONE;
1653 u32 intr_status, intr_enable;
1654
1655 spin_lock(&mdp->lock);
1656
1657 /* Get interrupt status */
1658 intr_status = sh_eth_read(ndev, EESR);
1659 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1660 * enabled since it's the one that comes thru regardless of the mask,
1661 * and we need to fully handle it in sh_eth_error() in order to quench
1662 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1663 */
1664 intr_enable = sh_eth_read(ndev, EESIPR);
1665 intr_status &= intr_enable | DMAC_M_ECI;
1666 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1667 ret = IRQ_HANDLED;
1668 else
1669 goto out;
1670
1671 if (!likely(mdp->irq_enabled)) {
1672 sh_eth_write(ndev, 0, EESIPR);
1673 goto out;
1674 }
1675
1676 if (intr_status & EESR_RX_CHECK) {
1677 if (napi_schedule_prep(&mdp->napi)) {
1678 /* Mask Rx interrupts */
1679 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1680 EESIPR);
1681 __napi_schedule(&mdp->napi);
1682 } else {
1683 netdev_warn(ndev,
1684 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1685 intr_status, intr_enable);
1686 }
1687 }
1688
1689 /* Tx Check */
1690 if (intr_status & cd->tx_check) {
1691 /* Clear Tx interrupts */
1692 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1693
1694 sh_eth_tx_free(ndev, true);
1695 netif_wake_queue(ndev);
1696 }
1697
1698 if (intr_status & cd->eesr_err_check) {
1699 /* Clear error interrupts */
1700 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1701
1702 sh_eth_error(ndev, intr_status);
1703 }
1704
1705 out:
1706 spin_unlock(&mdp->lock);
1707
1708 return ret;
1709 }
1710
1711 static int sh_eth_poll(struct napi_struct *napi, int budget)
1712 {
1713 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1714 napi);
1715 struct net_device *ndev = napi->dev;
1716 int quota = budget;
1717 u32 intr_status;
1718
1719 for (;;) {
1720 intr_status = sh_eth_read(ndev, EESR);
1721 if (!(intr_status & EESR_RX_CHECK))
1722 break;
1723 /* Clear Rx interrupts */
1724 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1725
1726 if (sh_eth_rx(ndev, intr_status, &quota))
1727 goto out;
1728 }
1729
1730 napi_complete(napi);
1731
1732 /* Reenable Rx interrupts */
1733 if (mdp->irq_enabled)
1734 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1735 out:
1736 return budget - quota;
1737 }
1738
1739 /* PHY state control function */
1740 static void sh_eth_adjust_link(struct net_device *ndev)
1741 {
1742 struct sh_eth_private *mdp = netdev_priv(ndev);
1743 struct phy_device *phydev = ndev->phydev;
1744 int new_state = 0;
1745
1746 if (phydev->link) {
1747 if (phydev->duplex != mdp->duplex) {
1748 new_state = 1;
1749 mdp->duplex = phydev->duplex;
1750 if (mdp->cd->set_duplex)
1751 mdp->cd->set_duplex(ndev);
1752 }
1753
1754 if (phydev->speed != mdp->speed) {
1755 new_state = 1;
1756 mdp->speed = phydev->speed;
1757 if (mdp->cd->set_rate)
1758 mdp->cd->set_rate(ndev);
1759 }
1760 if (!mdp->link) {
1761 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1762 new_state = 1;
1763 mdp->link = phydev->link;
1764 if (mdp->cd->no_psr || mdp->no_ether_link)
1765 sh_eth_rcv_snd_enable(ndev);
1766 }
1767 } else if (mdp->link) {
1768 new_state = 1;
1769 mdp->link = 0;
1770 mdp->speed = 0;
1771 mdp->duplex = -1;
1772 if (mdp->cd->no_psr || mdp->no_ether_link)
1773 sh_eth_rcv_snd_disable(ndev);
1774 }
1775
1776 if (new_state && netif_msg_link(mdp))
1777 phy_print_status(phydev);
1778 }
1779
1780 /* PHY init function */
1781 static int sh_eth_phy_init(struct net_device *ndev)
1782 {
1783 struct device_node *np = ndev->dev.parent->of_node;
1784 struct sh_eth_private *mdp = netdev_priv(ndev);
1785 struct phy_device *phydev;
1786
1787 mdp->link = 0;
1788 mdp->speed = 0;
1789 mdp->duplex = -1;
1790
1791 /* Try connect to PHY */
1792 if (np) {
1793 struct device_node *pn;
1794
1795 pn = of_parse_phandle(np, "phy-handle", 0);
1796 phydev = of_phy_connect(ndev, pn,
1797 sh_eth_adjust_link, 0,
1798 mdp->phy_interface);
1799
1800 of_node_put(pn);
1801 if (!phydev)
1802 phydev = ERR_PTR(-ENOENT);
1803 } else {
1804 char phy_id[MII_BUS_ID_SIZE + 3];
1805
1806 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1807 mdp->mii_bus->id, mdp->phy_id);
1808
1809 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1810 mdp->phy_interface);
1811 }
1812
1813 if (IS_ERR(phydev)) {
1814 netdev_err(ndev, "failed to connect PHY\n");
1815 return PTR_ERR(phydev);
1816 }
1817
1818 phy_attached_info(phydev);
1819
1820 return 0;
1821 }
1822
1823 /* PHY control start function */
1824 static int sh_eth_phy_start(struct net_device *ndev)
1825 {
1826 int ret;
1827
1828 ret = sh_eth_phy_init(ndev);
1829 if (ret)
1830 return ret;
1831
1832 phy_start(ndev->phydev);
1833
1834 return 0;
1835 }
1836
1837 static int sh_eth_get_link_ksettings(struct net_device *ndev,
1838 struct ethtool_link_ksettings *cmd)
1839 {
1840 struct sh_eth_private *mdp = netdev_priv(ndev);
1841 unsigned long flags;
1842 int ret;
1843
1844 if (!ndev->phydev)
1845 return -ENODEV;
1846
1847 spin_lock_irqsave(&mdp->lock, flags);
1848 ret = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1849 spin_unlock_irqrestore(&mdp->lock, flags);
1850
1851 return ret;
1852 }
1853
1854 static int sh_eth_set_link_ksettings(struct net_device *ndev,
1855 const struct ethtool_link_ksettings *cmd)
1856 {
1857 struct sh_eth_private *mdp = netdev_priv(ndev);
1858 unsigned long flags;
1859 int ret;
1860
1861 if (!ndev->phydev)
1862 return -ENODEV;
1863
1864 spin_lock_irqsave(&mdp->lock, flags);
1865
1866 /* disable tx and rx */
1867 sh_eth_rcv_snd_disable(ndev);
1868
1869 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1870 if (ret)
1871 goto error_exit;
1872
1873 if (cmd->base.duplex == DUPLEX_FULL)
1874 mdp->duplex = 1;
1875 else
1876 mdp->duplex = 0;
1877
1878 if (mdp->cd->set_duplex)
1879 mdp->cd->set_duplex(ndev);
1880
1881 error_exit:
1882 mdelay(1);
1883
1884 /* enable tx and rx */
1885 sh_eth_rcv_snd_enable(ndev);
1886
1887 spin_unlock_irqrestore(&mdp->lock, flags);
1888
1889 return ret;
1890 }
1891
1892 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1893 * version must be bumped as well. Just adding registers up to that
1894 * limit is fine, as long as the existing register indices don't
1895 * change.
1896 */
1897 #define SH_ETH_REG_DUMP_VERSION 1
1898 #define SH_ETH_REG_DUMP_MAX_REGS 256
1899
1900 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1901 {
1902 struct sh_eth_private *mdp = netdev_priv(ndev);
1903 struct sh_eth_cpu_data *cd = mdp->cd;
1904 u32 *valid_map;
1905 size_t len;
1906
1907 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1908
1909 /* Dump starts with a bitmap that tells ethtool which
1910 * registers are defined for this chip.
1911 */
1912 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1913 if (buf) {
1914 valid_map = buf;
1915 buf += len;
1916 } else {
1917 valid_map = NULL;
1918 }
1919
1920 /* Add a register to the dump, if it has a defined offset.
1921 * This automatically skips most undefined registers, but for
1922 * some it is also necessary to check a capability flag in
1923 * struct sh_eth_cpu_data.
1924 */
1925 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1926 #define add_reg_from(reg, read_expr) do { \
1927 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1928 if (buf) { \
1929 mark_reg_valid(reg); \
1930 *buf++ = read_expr; \
1931 } \
1932 ++len; \
1933 } \
1934 } while (0)
1935 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1936 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1937
1938 add_reg(EDSR);
1939 add_reg(EDMR);
1940 add_reg(EDTRR);
1941 add_reg(EDRRR);
1942 add_reg(EESR);
1943 add_reg(EESIPR);
1944 add_reg(TDLAR);
1945 add_reg(TDFAR);
1946 add_reg(TDFXR);
1947 add_reg(TDFFR);
1948 add_reg(RDLAR);
1949 add_reg(RDFAR);
1950 add_reg(RDFXR);
1951 add_reg(RDFFR);
1952 add_reg(TRSCER);
1953 add_reg(RMFCR);
1954 add_reg(TFTR);
1955 add_reg(FDR);
1956 add_reg(RMCR);
1957 add_reg(TFUCR);
1958 add_reg(RFOCR);
1959 if (cd->rmiimode)
1960 add_reg(RMIIMODE);
1961 add_reg(FCFTR);
1962 if (cd->rpadir)
1963 add_reg(RPADIR);
1964 if (!cd->no_trimd)
1965 add_reg(TRIMD);
1966 add_reg(ECMR);
1967 add_reg(ECSR);
1968 add_reg(ECSIPR);
1969 add_reg(PIR);
1970 if (!cd->no_psr)
1971 add_reg(PSR);
1972 add_reg(RDMLR);
1973 add_reg(RFLR);
1974 add_reg(IPGR);
1975 if (cd->apr)
1976 add_reg(APR);
1977 if (cd->mpr)
1978 add_reg(MPR);
1979 add_reg(RFCR);
1980 add_reg(RFCF);
1981 if (cd->tpauser)
1982 add_reg(TPAUSER);
1983 add_reg(TPAUSECR);
1984 add_reg(GECMR);
1985 if (cd->bculr)
1986 add_reg(BCULR);
1987 add_reg(MAHR);
1988 add_reg(MALR);
1989 add_reg(TROCR);
1990 add_reg(CDCR);
1991 add_reg(LCCR);
1992 add_reg(CNDCR);
1993 add_reg(CEFCR);
1994 add_reg(FRECR);
1995 add_reg(TSFRCR);
1996 add_reg(TLFRCR);
1997 add_reg(CERCR);
1998 add_reg(CEECR);
1999 add_reg(MAFCR);
2000 if (cd->rtrate)
2001 add_reg(RTRATE);
2002 if (cd->hw_crc)
2003 add_reg(CSMR);
2004 if (cd->select_mii)
2005 add_reg(RMII_MII);
2006 add_reg(ARSTR);
2007 if (cd->tsu) {
2008 add_tsu_reg(TSU_CTRST);
2009 add_tsu_reg(TSU_FWEN0);
2010 add_tsu_reg(TSU_FWEN1);
2011 add_tsu_reg(TSU_FCM);
2012 add_tsu_reg(TSU_BSYSL0);
2013 add_tsu_reg(TSU_BSYSL1);
2014 add_tsu_reg(TSU_PRISL0);
2015 add_tsu_reg(TSU_PRISL1);
2016 add_tsu_reg(TSU_FWSL0);
2017 add_tsu_reg(TSU_FWSL1);
2018 add_tsu_reg(TSU_FWSLC);
2019 add_tsu_reg(TSU_QTAG0);
2020 add_tsu_reg(TSU_QTAG1);
2021 add_tsu_reg(TSU_QTAGM0);
2022 add_tsu_reg(TSU_QTAGM1);
2023 add_tsu_reg(TSU_FWSR);
2024 add_tsu_reg(TSU_FWINMK);
2025 add_tsu_reg(TSU_ADQT0);
2026 add_tsu_reg(TSU_ADQT1);
2027 add_tsu_reg(TSU_VTAG0);
2028 add_tsu_reg(TSU_VTAG1);
2029 add_tsu_reg(TSU_ADSBSY);
2030 add_tsu_reg(TSU_TEN);
2031 add_tsu_reg(TSU_POST1);
2032 add_tsu_reg(TSU_POST2);
2033 add_tsu_reg(TSU_POST3);
2034 add_tsu_reg(TSU_POST4);
2035 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2036 /* This is the start of a table, not just a single
2037 * register.
2038 */
2039 if (buf) {
2040 unsigned int i;
2041
2042 mark_reg_valid(TSU_ADRH0);
2043 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2044 *buf++ = ioread32(
2045 mdp->tsu_addr +
2046 mdp->reg_offset[TSU_ADRH0] +
2047 i * 4);
2048 }
2049 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2050 }
2051 }
2052
2053 #undef mark_reg_valid
2054 #undef add_reg_from
2055 #undef add_reg
2056 #undef add_tsu_reg
2057
2058 return len * 4;
2059 }
2060
2061 static int sh_eth_get_regs_len(struct net_device *ndev)
2062 {
2063 return __sh_eth_get_regs(ndev, NULL);
2064 }
2065
2066 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2067 void *buf)
2068 {
2069 struct sh_eth_private *mdp = netdev_priv(ndev);
2070
2071 regs->version = SH_ETH_REG_DUMP_VERSION;
2072
2073 pm_runtime_get_sync(&mdp->pdev->dev);
2074 __sh_eth_get_regs(ndev, buf);
2075 pm_runtime_put_sync(&mdp->pdev->dev);
2076 }
2077
2078 static int sh_eth_nway_reset(struct net_device *ndev)
2079 {
2080 struct sh_eth_private *mdp = netdev_priv(ndev);
2081 unsigned long flags;
2082 int ret;
2083
2084 if (!ndev->phydev)
2085 return -ENODEV;
2086
2087 spin_lock_irqsave(&mdp->lock, flags);
2088 ret = phy_start_aneg(ndev->phydev);
2089 spin_unlock_irqrestore(&mdp->lock, flags);
2090
2091 return ret;
2092 }
2093
2094 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2095 {
2096 struct sh_eth_private *mdp = netdev_priv(ndev);
2097 return mdp->msg_enable;
2098 }
2099
2100 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2101 {
2102 struct sh_eth_private *mdp = netdev_priv(ndev);
2103 mdp->msg_enable = value;
2104 }
2105
2106 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2107 "rx_current", "tx_current",
2108 "rx_dirty", "tx_dirty",
2109 };
2110 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2111
2112 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2113 {
2114 switch (sset) {
2115 case ETH_SS_STATS:
2116 return SH_ETH_STATS_LEN;
2117 default:
2118 return -EOPNOTSUPP;
2119 }
2120 }
2121
2122 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2123 struct ethtool_stats *stats, u64 *data)
2124 {
2125 struct sh_eth_private *mdp = netdev_priv(ndev);
2126 int i = 0;
2127
2128 /* device-specific stats */
2129 data[i++] = mdp->cur_rx;
2130 data[i++] = mdp->cur_tx;
2131 data[i++] = mdp->dirty_rx;
2132 data[i++] = mdp->dirty_tx;
2133 }
2134
2135 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2136 {
2137 switch (stringset) {
2138 case ETH_SS_STATS:
2139 memcpy(data, *sh_eth_gstrings_stats,
2140 sizeof(sh_eth_gstrings_stats));
2141 break;
2142 }
2143 }
2144
2145 static void sh_eth_get_ringparam(struct net_device *ndev,
2146 struct ethtool_ringparam *ring)
2147 {
2148 struct sh_eth_private *mdp = netdev_priv(ndev);
2149
2150 ring->rx_max_pending = RX_RING_MAX;
2151 ring->tx_max_pending = TX_RING_MAX;
2152 ring->rx_pending = mdp->num_rx_ring;
2153 ring->tx_pending = mdp->num_tx_ring;
2154 }
2155
2156 static int sh_eth_set_ringparam(struct net_device *ndev,
2157 struct ethtool_ringparam *ring)
2158 {
2159 struct sh_eth_private *mdp = netdev_priv(ndev);
2160 int ret;
2161
2162 if (ring->tx_pending > TX_RING_MAX ||
2163 ring->rx_pending > RX_RING_MAX ||
2164 ring->tx_pending < TX_RING_MIN ||
2165 ring->rx_pending < RX_RING_MIN)
2166 return -EINVAL;
2167 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2168 return -EINVAL;
2169
2170 if (netif_running(ndev)) {
2171 netif_device_detach(ndev);
2172 netif_tx_disable(ndev);
2173
2174 /* Serialise with the interrupt handler and NAPI, then
2175 * disable interrupts. We have to clear the
2176 * irq_enabled flag first to ensure that interrupts
2177 * won't be re-enabled.
2178 */
2179 mdp->irq_enabled = false;
2180 synchronize_irq(ndev->irq);
2181 napi_synchronize(&mdp->napi);
2182 sh_eth_write(ndev, 0x0000, EESIPR);
2183
2184 sh_eth_dev_exit(ndev);
2185
2186 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2187 sh_eth_ring_free(ndev);
2188 }
2189
2190 /* Set new parameters */
2191 mdp->num_rx_ring = ring->rx_pending;
2192 mdp->num_tx_ring = ring->tx_pending;
2193
2194 if (netif_running(ndev)) {
2195 ret = sh_eth_ring_init(ndev);
2196 if (ret < 0) {
2197 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2198 __func__);
2199 return ret;
2200 }
2201 ret = sh_eth_dev_init(ndev);
2202 if (ret < 0) {
2203 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2204 __func__);
2205 return ret;
2206 }
2207
2208 netif_device_attach(ndev);
2209 }
2210
2211 return 0;
2212 }
2213
2214 static const struct ethtool_ops sh_eth_ethtool_ops = {
2215 .get_regs_len = sh_eth_get_regs_len,
2216 .get_regs = sh_eth_get_regs,
2217 .nway_reset = sh_eth_nway_reset,
2218 .get_msglevel = sh_eth_get_msglevel,
2219 .set_msglevel = sh_eth_set_msglevel,
2220 .get_link = ethtool_op_get_link,
2221 .get_strings = sh_eth_get_strings,
2222 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2223 .get_sset_count = sh_eth_get_sset_count,
2224 .get_ringparam = sh_eth_get_ringparam,
2225 .set_ringparam = sh_eth_set_ringparam,
2226 .get_link_ksettings = sh_eth_get_link_ksettings,
2227 .set_link_ksettings = sh_eth_set_link_ksettings,
2228 };
2229
2230 /* network device open function */
2231 static int sh_eth_open(struct net_device *ndev)
2232 {
2233 struct sh_eth_private *mdp = netdev_priv(ndev);
2234 int ret;
2235
2236 pm_runtime_get_sync(&mdp->pdev->dev);
2237
2238 napi_enable(&mdp->napi);
2239
2240 ret = request_irq(ndev->irq, sh_eth_interrupt,
2241 mdp->cd->irq_flags, ndev->name, ndev);
2242 if (ret) {
2243 netdev_err(ndev, "Can not assign IRQ number\n");
2244 goto out_napi_off;
2245 }
2246
2247 /* Descriptor set */
2248 ret = sh_eth_ring_init(ndev);
2249 if (ret)
2250 goto out_free_irq;
2251
2252 /* device init */
2253 ret = sh_eth_dev_init(ndev);
2254 if (ret)
2255 goto out_free_irq;
2256
2257 /* PHY control start*/
2258 ret = sh_eth_phy_start(ndev);
2259 if (ret)
2260 goto out_free_irq;
2261
2262 netif_start_queue(ndev);
2263
2264 mdp->is_opened = 1;
2265
2266 return ret;
2267
2268 out_free_irq:
2269 free_irq(ndev->irq, ndev);
2270 out_napi_off:
2271 napi_disable(&mdp->napi);
2272 pm_runtime_put_sync(&mdp->pdev->dev);
2273 return ret;
2274 }
2275
2276 /* Timeout function */
2277 static void sh_eth_tx_timeout(struct net_device *ndev)
2278 {
2279 struct sh_eth_private *mdp = netdev_priv(ndev);
2280 struct sh_eth_rxdesc *rxdesc;
2281 int i;
2282
2283 netif_stop_queue(ndev);
2284
2285 netif_err(mdp, timer, ndev,
2286 "transmit timed out, status %8.8x, resetting...\n",
2287 sh_eth_read(ndev, EESR));
2288
2289 /* tx_errors count up */
2290 ndev->stats.tx_errors++;
2291
2292 /* Free all the skbuffs in the Rx queue. */
2293 for (i = 0; i < mdp->num_rx_ring; i++) {
2294 rxdesc = &mdp->rx_ring[i];
2295 rxdesc->status = cpu_to_le32(0);
2296 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2297 dev_kfree_skb(mdp->rx_skbuff[i]);
2298 mdp->rx_skbuff[i] = NULL;
2299 }
2300 for (i = 0; i < mdp->num_tx_ring; i++) {
2301 dev_kfree_skb(mdp->tx_skbuff[i]);
2302 mdp->tx_skbuff[i] = NULL;
2303 }
2304
2305 /* device init */
2306 sh_eth_dev_init(ndev);
2307
2308 netif_start_queue(ndev);
2309 }
2310
2311 /* Packet transmit function */
2312 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2313 {
2314 struct sh_eth_private *mdp = netdev_priv(ndev);
2315 struct sh_eth_txdesc *txdesc;
2316 dma_addr_t dma_addr;
2317 u32 entry;
2318 unsigned long flags;
2319
2320 spin_lock_irqsave(&mdp->lock, flags);
2321 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2322 if (!sh_eth_tx_free(ndev, true)) {
2323 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2324 netif_stop_queue(ndev);
2325 spin_unlock_irqrestore(&mdp->lock, flags);
2326 return NETDEV_TX_BUSY;
2327 }
2328 }
2329 spin_unlock_irqrestore(&mdp->lock, flags);
2330
2331 if (skb_put_padto(skb, ETH_ZLEN))
2332 return NETDEV_TX_OK;
2333
2334 entry = mdp->cur_tx % mdp->num_tx_ring;
2335 mdp->tx_skbuff[entry] = skb;
2336 txdesc = &mdp->tx_ring[entry];
2337 /* soft swap. */
2338 if (!mdp->cd->hw_swap)
2339 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2340 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2341 DMA_TO_DEVICE);
2342 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2343 kfree_skb(skb);
2344 return NETDEV_TX_OK;
2345 }
2346 txdesc->addr = cpu_to_le32(dma_addr);
2347 txdesc->len = cpu_to_le32(skb->len << 16);
2348
2349 dma_wmb(); /* TACT bit must be set after all the above writes */
2350 if (entry >= mdp->num_tx_ring - 1)
2351 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2352 else
2353 txdesc->status |= cpu_to_le32(TD_TACT);
2354
2355 mdp->cur_tx++;
2356
2357 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2358 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2359
2360 return NETDEV_TX_OK;
2361 }
2362
2363 /* The statistics registers have write-clear behaviour, which means we
2364 * will lose any increment between the read and write. We mitigate
2365 * this by only clearing when we read a non-zero value, so we will
2366 * never falsely report a total of zero.
2367 */
2368 static void
2369 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2370 {
2371 u32 delta = sh_eth_read(ndev, reg);
2372
2373 if (delta) {
2374 *stat += delta;
2375 sh_eth_write(ndev, 0, reg);
2376 }
2377 }
2378
2379 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2380 {
2381 struct sh_eth_private *mdp = netdev_priv(ndev);
2382
2383 if (sh_eth_is_rz_fast_ether(mdp))
2384 return &ndev->stats;
2385
2386 if (!mdp->is_opened)
2387 return &ndev->stats;
2388
2389 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2390 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2391 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2392
2393 if (sh_eth_is_gether(mdp)) {
2394 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2395 CERCR);
2396 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2397 CEECR);
2398 } else {
2399 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2400 CNDCR);
2401 }
2402
2403 return &ndev->stats;
2404 }
2405
2406 /* device close function */
2407 static int sh_eth_close(struct net_device *ndev)
2408 {
2409 struct sh_eth_private *mdp = netdev_priv(ndev);
2410
2411 netif_stop_queue(ndev);
2412
2413 /* Serialise with the interrupt handler and NAPI, then disable
2414 * interrupts. We have to clear the irq_enabled flag first to
2415 * ensure that interrupts won't be re-enabled.
2416 */
2417 mdp->irq_enabled = false;
2418 synchronize_irq(ndev->irq);
2419 napi_disable(&mdp->napi);
2420 sh_eth_write(ndev, 0x0000, EESIPR);
2421
2422 sh_eth_dev_exit(ndev);
2423
2424 /* PHY Disconnect */
2425 if (ndev->phydev) {
2426 phy_stop(ndev->phydev);
2427 phy_disconnect(ndev->phydev);
2428 }
2429
2430 free_irq(ndev->irq, ndev);
2431
2432 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2433 sh_eth_ring_free(ndev);
2434
2435 pm_runtime_put_sync(&mdp->pdev->dev);
2436
2437 mdp->is_opened = 0;
2438
2439 return 0;
2440 }
2441
2442 /* ioctl to device function */
2443 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2444 {
2445 struct phy_device *phydev = ndev->phydev;
2446
2447 if (!netif_running(ndev))
2448 return -EINVAL;
2449
2450 if (!phydev)
2451 return -ENODEV;
2452
2453 return phy_mii_ioctl(phydev, rq, cmd);
2454 }
2455
2456 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2457 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2458 int entry)
2459 {
2460 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2461 }
2462
2463 static u32 sh_eth_tsu_get_post_mask(int entry)
2464 {
2465 return 0x0f << (28 - ((entry % 8) * 4));
2466 }
2467
2468 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2469 {
2470 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2471 }
2472
2473 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2474 int entry)
2475 {
2476 struct sh_eth_private *mdp = netdev_priv(ndev);
2477 u32 tmp;
2478 void *reg_offset;
2479
2480 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2481 tmp = ioread32(reg_offset);
2482 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2483 }
2484
2485 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2486 int entry)
2487 {
2488 struct sh_eth_private *mdp = netdev_priv(ndev);
2489 u32 post_mask, ref_mask, tmp;
2490 void *reg_offset;
2491
2492 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2493 post_mask = sh_eth_tsu_get_post_mask(entry);
2494 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2495
2496 tmp = ioread32(reg_offset);
2497 iowrite32(tmp & ~post_mask, reg_offset);
2498
2499 /* If other port enables, the function returns "true" */
2500 return tmp & ref_mask;
2501 }
2502
2503 static int sh_eth_tsu_busy(struct net_device *ndev)
2504 {
2505 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2506 struct sh_eth_private *mdp = netdev_priv(ndev);
2507
2508 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2509 udelay(10);
2510 timeout--;
2511 if (timeout <= 0) {
2512 netdev_err(ndev, "%s: timeout\n", __func__);
2513 return -ETIMEDOUT;
2514 }
2515 }
2516
2517 return 0;
2518 }
2519
2520 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2521 const u8 *addr)
2522 {
2523 u32 val;
2524
2525 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2526 iowrite32(val, reg);
2527 if (sh_eth_tsu_busy(ndev) < 0)
2528 return -EBUSY;
2529
2530 val = addr[4] << 8 | addr[5];
2531 iowrite32(val, reg + 4);
2532 if (sh_eth_tsu_busy(ndev) < 0)
2533 return -EBUSY;
2534
2535 return 0;
2536 }
2537
2538 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2539 {
2540 u32 val;
2541
2542 val = ioread32(reg);
2543 addr[0] = (val >> 24) & 0xff;
2544 addr[1] = (val >> 16) & 0xff;
2545 addr[2] = (val >> 8) & 0xff;
2546 addr[3] = val & 0xff;
2547 val = ioread32(reg + 4);
2548 addr[4] = (val >> 8) & 0xff;
2549 addr[5] = val & 0xff;
2550 }
2551
2552
2553 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2554 {
2555 struct sh_eth_private *mdp = netdev_priv(ndev);
2556 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2557 int i;
2558 u8 c_addr[ETH_ALEN];
2559
2560 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2561 sh_eth_tsu_read_entry(reg_offset, c_addr);
2562 if (ether_addr_equal(addr, c_addr))
2563 return i;
2564 }
2565
2566 return -ENOENT;
2567 }
2568
2569 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2570 {
2571 u8 blank[ETH_ALEN];
2572 int entry;
2573
2574 memset(blank, 0, sizeof(blank));
2575 entry = sh_eth_tsu_find_entry(ndev, blank);
2576 return (entry < 0) ? -ENOMEM : entry;
2577 }
2578
2579 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2580 int entry)
2581 {
2582 struct sh_eth_private *mdp = netdev_priv(ndev);
2583 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2584 int ret;
2585 u8 blank[ETH_ALEN];
2586
2587 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2588 ~(1 << (31 - entry)), TSU_TEN);
2589
2590 memset(blank, 0, sizeof(blank));
2591 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2592 if (ret < 0)
2593 return ret;
2594 return 0;
2595 }
2596
2597 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2598 {
2599 struct sh_eth_private *mdp = netdev_priv(ndev);
2600 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2601 int i, ret;
2602
2603 if (!mdp->cd->tsu)
2604 return 0;
2605
2606 i = sh_eth_tsu_find_entry(ndev, addr);
2607 if (i < 0) {
2608 /* No entry found, create one */
2609 i = sh_eth_tsu_find_empty(ndev);
2610 if (i < 0)
2611 return -ENOMEM;
2612 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2613 if (ret < 0)
2614 return ret;
2615
2616 /* Enable the entry */
2617 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2618 (1 << (31 - i)), TSU_TEN);
2619 }
2620
2621 /* Entry found or created, enable POST */
2622 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2623
2624 return 0;
2625 }
2626
2627 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2628 {
2629 struct sh_eth_private *mdp = netdev_priv(ndev);
2630 int i, ret;
2631
2632 if (!mdp->cd->tsu)
2633 return 0;
2634
2635 i = sh_eth_tsu_find_entry(ndev, addr);
2636 if (i) {
2637 /* Entry found */
2638 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2639 goto done;
2640
2641 /* Disable the entry if both ports was disabled */
2642 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2643 if (ret < 0)
2644 return ret;
2645 }
2646 done:
2647 return 0;
2648 }
2649
2650 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2651 {
2652 struct sh_eth_private *mdp = netdev_priv(ndev);
2653 int i, ret;
2654
2655 if (!mdp->cd->tsu)
2656 return 0;
2657
2658 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2659 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2660 continue;
2661
2662 /* Disable the entry if both ports was disabled */
2663 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2664 if (ret < 0)
2665 return ret;
2666 }
2667
2668 return 0;
2669 }
2670
2671 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2672 {
2673 struct sh_eth_private *mdp = netdev_priv(ndev);
2674 u8 addr[ETH_ALEN];
2675 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2676 int i;
2677
2678 if (!mdp->cd->tsu)
2679 return;
2680
2681 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2682 sh_eth_tsu_read_entry(reg_offset, addr);
2683 if (is_multicast_ether_addr(addr))
2684 sh_eth_tsu_del_entry(ndev, addr);
2685 }
2686 }
2687
2688 /* Update promiscuous flag and multicast filter */
2689 static void sh_eth_set_rx_mode(struct net_device *ndev)
2690 {
2691 struct sh_eth_private *mdp = netdev_priv(ndev);
2692 u32 ecmr_bits;
2693 int mcast_all = 0;
2694 unsigned long flags;
2695
2696 spin_lock_irqsave(&mdp->lock, flags);
2697 /* Initial condition is MCT = 1, PRM = 0.
2698 * Depending on ndev->flags, set PRM or clear MCT
2699 */
2700 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2701 if (mdp->cd->tsu)
2702 ecmr_bits |= ECMR_MCT;
2703
2704 if (!(ndev->flags & IFF_MULTICAST)) {
2705 sh_eth_tsu_purge_mcast(ndev);
2706 mcast_all = 1;
2707 }
2708 if (ndev->flags & IFF_ALLMULTI) {
2709 sh_eth_tsu_purge_mcast(ndev);
2710 ecmr_bits &= ~ECMR_MCT;
2711 mcast_all = 1;
2712 }
2713
2714 if (ndev->flags & IFF_PROMISC) {
2715 sh_eth_tsu_purge_all(ndev);
2716 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2717 } else if (mdp->cd->tsu) {
2718 struct netdev_hw_addr *ha;
2719 netdev_for_each_mc_addr(ha, ndev) {
2720 if (mcast_all && is_multicast_ether_addr(ha->addr))
2721 continue;
2722
2723 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2724 if (!mcast_all) {
2725 sh_eth_tsu_purge_mcast(ndev);
2726 ecmr_bits &= ~ECMR_MCT;
2727 mcast_all = 1;
2728 }
2729 }
2730 }
2731 }
2732
2733 /* update the ethernet mode */
2734 sh_eth_write(ndev, ecmr_bits, ECMR);
2735
2736 spin_unlock_irqrestore(&mdp->lock, flags);
2737 }
2738
2739 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2740 {
2741 if (!mdp->port)
2742 return TSU_VTAG0;
2743 else
2744 return TSU_VTAG1;
2745 }
2746
2747 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2748 __be16 proto, u16 vid)
2749 {
2750 struct sh_eth_private *mdp = netdev_priv(ndev);
2751 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2752
2753 if (unlikely(!mdp->cd->tsu))
2754 return -EPERM;
2755
2756 /* No filtering if vid = 0 */
2757 if (!vid)
2758 return 0;
2759
2760 mdp->vlan_num_ids++;
2761
2762 /* The controller has one VLAN tag HW filter. So, if the filter is
2763 * already enabled, the driver disables it and the filte
2764 */
2765 if (mdp->vlan_num_ids > 1) {
2766 /* disable VLAN filter */
2767 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2768 return 0;
2769 }
2770
2771 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2772 vtag_reg_index);
2773
2774 return 0;
2775 }
2776
2777 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2778 __be16 proto, u16 vid)
2779 {
2780 struct sh_eth_private *mdp = netdev_priv(ndev);
2781 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2782
2783 if (unlikely(!mdp->cd->tsu))
2784 return -EPERM;
2785
2786 /* No filtering if vid = 0 */
2787 if (!vid)
2788 return 0;
2789
2790 mdp->vlan_num_ids--;
2791 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2792
2793 return 0;
2794 }
2795
2796 /* SuperH's TSU register init function */
2797 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2798 {
2799 if (sh_eth_is_rz_fast_ether(mdp)) {
2800 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2801 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2802 TSU_FWSLC); /* Enable POST registers */
2803 return;
2804 }
2805
2806 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2807 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2808 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2809 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2810 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2811 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2812 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2813 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2814 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2815 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2816 if (sh_eth_is_gether(mdp)) {
2817 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2818 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2819 } else {
2820 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2821 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2822 }
2823 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2824 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2825 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2826 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2827 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2828 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2829 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2830 }
2831
2832 /* MDIO bus release function */
2833 static int sh_mdio_release(struct sh_eth_private *mdp)
2834 {
2835 /* unregister mdio bus */
2836 mdiobus_unregister(mdp->mii_bus);
2837
2838 /* free bitbang info */
2839 free_mdio_bitbang(mdp->mii_bus);
2840
2841 return 0;
2842 }
2843
2844 /* MDIO bus init function */
2845 static int sh_mdio_init(struct sh_eth_private *mdp,
2846 struct sh_eth_plat_data *pd)
2847 {
2848 int ret;
2849 struct bb_info *bitbang;
2850 struct platform_device *pdev = mdp->pdev;
2851 struct device *dev = &mdp->pdev->dev;
2852
2853 /* create bit control struct for PHY */
2854 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2855 if (!bitbang)
2856 return -ENOMEM;
2857
2858 /* bitbang init */
2859 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2860 bitbang->set_gate = pd->set_mdio_gate;
2861 bitbang->ctrl.ops = &bb_ops;
2862
2863 /* MII controller setting */
2864 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2865 if (!mdp->mii_bus)
2866 return -ENOMEM;
2867
2868 /* Hook up MII support for ethtool */
2869 mdp->mii_bus->name = "sh_mii";
2870 mdp->mii_bus->parent = dev;
2871 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2872 pdev->name, pdev->id);
2873
2874 /* register MDIO bus */
2875 if (dev->of_node) {
2876 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2877 } else {
2878 if (pd->phy_irq > 0)
2879 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2880
2881 ret = mdiobus_register(mdp->mii_bus);
2882 }
2883
2884 if (ret)
2885 goto out_free_bus;
2886
2887 return 0;
2888
2889 out_free_bus:
2890 free_mdio_bitbang(mdp->mii_bus);
2891 return ret;
2892 }
2893
2894 static const u16 *sh_eth_get_register_offset(int register_type)
2895 {
2896 const u16 *reg_offset = NULL;
2897
2898 switch (register_type) {
2899 case SH_ETH_REG_GIGABIT:
2900 reg_offset = sh_eth_offset_gigabit;
2901 break;
2902 case SH_ETH_REG_FAST_RZ:
2903 reg_offset = sh_eth_offset_fast_rz;
2904 break;
2905 case SH_ETH_REG_FAST_RCAR:
2906 reg_offset = sh_eth_offset_fast_rcar;
2907 break;
2908 case SH_ETH_REG_FAST_SH4:
2909 reg_offset = sh_eth_offset_fast_sh4;
2910 break;
2911 case SH_ETH_REG_FAST_SH3_SH2:
2912 reg_offset = sh_eth_offset_fast_sh3_sh2;
2913 break;
2914 }
2915
2916 return reg_offset;
2917 }
2918
2919 static const struct net_device_ops sh_eth_netdev_ops = {
2920 .ndo_open = sh_eth_open,
2921 .ndo_stop = sh_eth_close,
2922 .ndo_start_xmit = sh_eth_start_xmit,
2923 .ndo_get_stats = sh_eth_get_stats,
2924 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2925 .ndo_tx_timeout = sh_eth_tx_timeout,
2926 .ndo_do_ioctl = sh_eth_do_ioctl,
2927 .ndo_validate_addr = eth_validate_addr,
2928 .ndo_set_mac_address = eth_mac_addr,
2929 .ndo_change_mtu = eth_change_mtu,
2930 };
2931
2932 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2933 .ndo_open = sh_eth_open,
2934 .ndo_stop = sh_eth_close,
2935 .ndo_start_xmit = sh_eth_start_xmit,
2936 .ndo_get_stats = sh_eth_get_stats,
2937 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2938 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2939 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2940 .ndo_tx_timeout = sh_eth_tx_timeout,
2941 .ndo_do_ioctl = sh_eth_do_ioctl,
2942 .ndo_validate_addr = eth_validate_addr,
2943 .ndo_set_mac_address = eth_mac_addr,
2944 .ndo_change_mtu = eth_change_mtu,
2945 };
2946
2947 #ifdef CONFIG_OF
2948 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2949 {
2950 struct device_node *np = dev->of_node;
2951 struct sh_eth_plat_data *pdata;
2952 const char *mac_addr;
2953
2954 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2955 if (!pdata)
2956 return NULL;
2957
2958 pdata->phy_interface = of_get_phy_mode(np);
2959
2960 mac_addr = of_get_mac_address(np);
2961 if (mac_addr)
2962 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2963
2964 pdata->no_ether_link =
2965 of_property_read_bool(np, "renesas,no-ether-link");
2966 pdata->ether_link_active_low =
2967 of_property_read_bool(np, "renesas,ether-link-active-low");
2968
2969 return pdata;
2970 }
2971
2972 static const struct of_device_id sh_eth_match_table[] = {
2973 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2974 { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
2975 { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
2976 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2977 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2978 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2979 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2980 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2981 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2982 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2983 { }
2984 };
2985 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2986 #else
2987 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2988 {
2989 return NULL;
2990 }
2991 #endif
2992
2993 static int sh_eth_drv_probe(struct platform_device *pdev)
2994 {
2995 struct resource *res;
2996 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2997 const struct platform_device_id *id = platform_get_device_id(pdev);
2998 struct sh_eth_private *mdp;
2999 struct net_device *ndev;
3000 int ret, devno;
3001
3002 /* get base addr */
3003 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3004
3005 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3006 if (!ndev)
3007 return -ENOMEM;
3008
3009 pm_runtime_enable(&pdev->dev);
3010 pm_runtime_get_sync(&pdev->dev);
3011
3012 devno = pdev->id;
3013 if (devno < 0)
3014 devno = 0;
3015
3016 ret = platform_get_irq(pdev, 0);
3017 if (ret < 0)
3018 goto out_release;
3019 ndev->irq = ret;
3020
3021 SET_NETDEV_DEV(ndev, &pdev->dev);
3022
3023 mdp = netdev_priv(ndev);
3024 mdp->num_tx_ring = TX_RING_SIZE;
3025 mdp->num_rx_ring = RX_RING_SIZE;
3026 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3027 if (IS_ERR(mdp->addr)) {
3028 ret = PTR_ERR(mdp->addr);
3029 goto out_release;
3030 }
3031
3032 ndev->base_addr = res->start;
3033
3034 spin_lock_init(&mdp->lock);
3035 mdp->pdev = pdev;
3036
3037 if (pdev->dev.of_node)
3038 pd = sh_eth_parse_dt(&pdev->dev);
3039 if (!pd) {
3040 dev_err(&pdev->dev, "no platform data\n");
3041 ret = -EINVAL;
3042 goto out_release;
3043 }
3044
3045 /* get PHY ID */
3046 mdp->phy_id = pd->phy;
3047 mdp->phy_interface = pd->phy_interface;
3048 mdp->no_ether_link = pd->no_ether_link;
3049 mdp->ether_link_active_low = pd->ether_link_active_low;
3050
3051 /* set cpu data */
3052 if (id)
3053 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3054 else
3055 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3056
3057 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3058 if (!mdp->reg_offset) {
3059 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3060 mdp->cd->register_type);
3061 ret = -EINVAL;
3062 goto out_release;
3063 }
3064 sh_eth_set_default_cpu_data(mdp->cd);
3065
3066 /* set function */
3067 if (mdp->cd->tsu)
3068 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3069 else
3070 ndev->netdev_ops = &sh_eth_netdev_ops;
3071 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3072 ndev->watchdog_timeo = TX_TIMEOUT;
3073
3074 /* debug message level */
3075 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3076
3077 /* read and set MAC address */
3078 read_mac_address(ndev, pd->mac_addr);
3079 if (!is_valid_ether_addr(ndev->dev_addr)) {
3080 dev_warn(&pdev->dev,
3081 "no valid MAC address supplied, using a random one.\n");
3082 eth_hw_addr_random(ndev);
3083 }
3084
3085 /* ioremap the TSU registers */
3086 if (mdp->cd->tsu) {
3087 struct resource *rtsu;
3088 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3089 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3090 if (IS_ERR(mdp->tsu_addr)) {
3091 ret = PTR_ERR(mdp->tsu_addr);
3092 goto out_release;
3093 }
3094 mdp->port = devno % 2;
3095 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3096 }
3097
3098 /* initialize first or needed device */
3099 if (!devno || pd->needs_init) {
3100 if (mdp->cd->chip_reset)
3101 mdp->cd->chip_reset(ndev);
3102
3103 if (mdp->cd->tsu) {
3104 /* TSU init (Init only)*/
3105 sh_eth_tsu_init(mdp);
3106 }
3107 }
3108
3109 if (mdp->cd->rmiimode)
3110 sh_eth_write(ndev, 0x1, RMIIMODE);
3111
3112 /* MDIO bus init */
3113 ret = sh_mdio_init(mdp, pd);
3114 if (ret) {
3115 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3116 goto out_release;
3117 }
3118
3119 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3120
3121 /* network device register */
3122 ret = register_netdev(ndev);
3123 if (ret)
3124 goto out_napi_del;
3125
3126 /* print device information */
3127 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3128 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3129
3130 pm_runtime_put(&pdev->dev);
3131 platform_set_drvdata(pdev, ndev);
3132
3133 return ret;
3134
3135 out_napi_del:
3136 netif_napi_del(&mdp->napi);
3137 sh_mdio_release(mdp);
3138
3139 out_release:
3140 /* net_dev free */
3141 if (ndev)
3142 free_netdev(ndev);
3143
3144 pm_runtime_put(&pdev->dev);
3145 pm_runtime_disable(&pdev->dev);
3146 return ret;
3147 }
3148
3149 static int sh_eth_drv_remove(struct platform_device *pdev)
3150 {
3151 struct net_device *ndev = platform_get_drvdata(pdev);
3152 struct sh_eth_private *mdp = netdev_priv(ndev);
3153
3154 unregister_netdev(ndev);
3155 netif_napi_del(&mdp->napi);
3156 sh_mdio_release(mdp);
3157 pm_runtime_disable(&pdev->dev);
3158 free_netdev(ndev);
3159
3160 return 0;
3161 }
3162
3163 #ifdef CONFIG_PM
3164 #ifdef CONFIG_PM_SLEEP
3165 static int sh_eth_suspend(struct device *dev)
3166 {
3167 struct net_device *ndev = dev_get_drvdata(dev);
3168 int ret = 0;
3169
3170 if (netif_running(ndev)) {
3171 netif_device_detach(ndev);
3172 ret = sh_eth_close(ndev);
3173 }
3174
3175 return ret;
3176 }
3177
3178 static int sh_eth_resume(struct device *dev)
3179 {
3180 struct net_device *ndev = dev_get_drvdata(dev);
3181 int ret = 0;
3182
3183 if (netif_running(ndev)) {
3184 ret = sh_eth_open(ndev);
3185 if (ret < 0)
3186 return ret;
3187 netif_device_attach(ndev);
3188 }
3189
3190 return ret;
3191 }
3192 #endif
3193
3194 static int sh_eth_runtime_nop(struct device *dev)
3195 {
3196 /* Runtime PM callback shared between ->runtime_suspend()
3197 * and ->runtime_resume(). Simply returns success.
3198 *
3199 * This driver re-initializes all registers after
3200 * pm_runtime_get_sync() anyway so there is no need
3201 * to save and restore registers here.
3202 */
3203 return 0;
3204 }
3205
3206 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3207 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3208 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3209 };
3210 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3211 #else
3212 #define SH_ETH_PM_OPS NULL
3213 #endif
3214
3215 static struct platform_device_id sh_eth_id_table[] = {
3216 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3217 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3218 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3219 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3220 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3221 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3222 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3223 { }
3224 };
3225 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3226
3227 static struct platform_driver sh_eth_driver = {
3228 .probe = sh_eth_drv_probe,
3229 .remove = sh_eth_drv_remove,
3230 .id_table = sh_eth_id_table,
3231 .driver = {
3232 .name = CARDNAME,
3233 .pm = SH_ETH_PM_OPS,
3234 .of_match_table = of_match_ptr(sh_eth_match_table),
3235 },
3236 };
3237
3238 module_platform_driver(sh_eth_driver);
3239
3240 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3241 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3242 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support