?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
pvrusb2: reduce stack usage pvr2_eeprom_analyze()
[linux/fpc-iii.git] / drivers / net / ethernet / smsc / smsc9420.c
blobb7bfed4bc96bb4670f997f8ab7b93067892d7ad5
1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 ***************************************************************************
19 */
20
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/netdevice.h>
26 #include <linux/phy.h>
27 #include <linux/pci.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/crc32.h>
31 #include <linux/slab.h>
32 #include <linux/module.h>
33 #include <asm/unaligned.h>
34 #include "smsc9420.h"
35
36 #define DRV_NAME "smsc9420"
37 #define DRV_MDIONAME "smsc9420-mdio"
38 #define DRV_DESCRIPTION "SMSC LAN9420 driver"
39 #define DRV_VERSION "1.01"
40
41 MODULE_LICENSE("GPL");
42 MODULE_VERSION(DRV_VERSION);
43
44 struct smsc9420_dma_desc {
45 u32 status;
46 u32 length;
47 u32 buffer1;
48 u32 buffer2;
49 };
50
51 struct smsc9420_ring_info {
52 struct sk_buff *skb;
53 dma_addr_t mapping;
54 };
55
56 struct smsc9420_pdata {
57 void __iomem *ioaddr;
58 struct pci_dev *pdev;
59 struct net_device *dev;
60
61 struct smsc9420_dma_desc *rx_ring;
62 struct smsc9420_dma_desc *tx_ring;
63 struct smsc9420_ring_info *tx_buffers;
64 struct smsc9420_ring_info *rx_buffers;
65 dma_addr_t rx_dma_addr;
66 dma_addr_t tx_dma_addr;
67 int tx_ring_head, tx_ring_tail;
68 int rx_ring_head, rx_ring_tail;
69
70 spinlock_t int_lock;
71 spinlock_t phy_lock;
72
73 struct napi_struct napi;
74
75 bool software_irq_signal;
76 bool rx_csum;
77 u32 msg_enable;
78
79 struct mii_bus *mii_bus;
80 int last_duplex;
81 int last_carrier;
82 };
83
84 static const struct pci_device_id smsc9420_id_table[] = {
85 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
86 { 0, }
87 };
88
89 MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
90
91 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
92
93 static uint smsc_debug;
94 static uint debug = -1;
95 module_param(debug, uint, 0);
96 MODULE_PARM_DESC(debug, "debug level");
97
98 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
99 {
100 return ioread32(pd->ioaddr + offset);
101 }
102
103 static inline void
104 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
105 {
106 iowrite32(value, pd->ioaddr + offset);
107 }
108
109 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
110 {
111 /* to ensure PCI write completion, we must perform a PCI read */
112 smsc9420_reg_read(pd, ID_REV);
113 }
114
115 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
116 {
117 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
118 unsigned long flags;
119 u32 addr;
120 int i, reg = -EIO;
121
122 spin_lock_irqsave(&pd->phy_lock, flags);
123
124 /* confirm MII not busy */
125 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
126 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
127 goto out;
128 }
129
130 /* set the address, index & direction (read from PHY) */
131 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
132 MII_ACCESS_MII_READ_;
133 smsc9420_reg_write(pd, MII_ACCESS, addr);
134
135 /* wait for read to complete with 50us timeout */
136 for (i = 0; i < 5; i++) {
137 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
138 MII_ACCESS_MII_BUSY_)) {
139 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
140 goto out;
141 }
142 udelay(10);
143 }
144
145 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
146
147 out:
148 spin_unlock_irqrestore(&pd->phy_lock, flags);
149 return reg;
150 }
151
152 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
153 u16 val)
154 {
155 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
156 unsigned long flags;
157 u32 addr;
158 int i, reg = -EIO;
159
160 spin_lock_irqsave(&pd->phy_lock, flags);
161
162 /* confirm MII not busy */
163 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
164 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
165 goto out;
166 }
167
168 /* put the data to write in the MAC */
169 smsc9420_reg_write(pd, MII_DATA, (u32)val);
170
171 /* set the address, index & direction (write to PHY) */
172 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
173 MII_ACCESS_MII_WRITE_;
174 smsc9420_reg_write(pd, MII_ACCESS, addr);
175
176 /* wait for write to complete with 50us timeout */
177 for (i = 0; i < 5; i++) {
178 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
179 MII_ACCESS_MII_BUSY_)) {
180 reg = 0;
181 goto out;
182 }
183 udelay(10);
184 }
185
186 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
187
188 out:
189 spin_unlock_irqrestore(&pd->phy_lock, flags);
190 return reg;
191 }
192
193 /* Returns hash bit number for given MAC address
194 * Example:
195 * 01 00 5E 00 00 01 -> returns bit number 31 */
196 static u32 smsc9420_hash(u8 addr[ETH_ALEN])
197 {
198 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
199 }
200
201 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
202 {
203 int timeout = 100000;
204
205 BUG_ON(!pd);
206
207 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
208 netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__);
209 return -EIO;
210 }
211
212 smsc9420_reg_write(pd, E2P_CMD,
213 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
214
215 do {
216 udelay(10);
217 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
218 return 0;
219 } while (timeout--);
220
221 netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__);
222 return -EIO;
223 }
224
225 /* Standard ioctls for mii-tool */
226 static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
227 {
228 if (!netif_running(dev) || !dev->phydev)
229 return -EINVAL;
230
231 return phy_mii_ioctl(dev->phydev, ifr, cmd);
232 }
233
234 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
235 struct ethtool_drvinfo *drvinfo)
236 {
237 struct smsc9420_pdata *pd = netdev_priv(netdev);
238
239 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
240 strlcpy(drvinfo->bus_info, pci_name(pd->pdev),
241 sizeof(drvinfo->bus_info));
242 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
243 }
244
245 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
246 {
247 struct smsc9420_pdata *pd = netdev_priv(netdev);
248 return pd->msg_enable;
249 }
250
251 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
252 {
253 struct smsc9420_pdata *pd = netdev_priv(netdev);
254 pd->msg_enable = data;
255 }
256
257 static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
258 {
259 if (!netdev->phydev)
260 return -ENODEV;
261
262 return phy_start_aneg(netdev->phydev);
263 }
264
265 static int smsc9420_ethtool_getregslen(struct net_device *dev)
266 {
267 /* all smsc9420 registers plus all phy registers */
268 return 0x100 + (32 * sizeof(u32));
269 }
270
271 static void
272 smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
273 void *buf)
274 {
275 struct smsc9420_pdata *pd = netdev_priv(dev);
276 struct phy_device *phy_dev = dev->phydev;
277 unsigned int i, j = 0;
278 u32 *data = buf;
279
280 regs->version = smsc9420_reg_read(pd, ID_REV);
281 for (i = 0; i < 0x100; i += (sizeof(u32)))
282 data[j++] = smsc9420_reg_read(pd, i);
283
284 // cannot read phy registers if the net device is down
285 if (!phy_dev)
286 return;
287
288 for (i = 0; i <= 31; i++)
289 data[j++] = smsc9420_mii_read(phy_dev->mdio.bus,
290 phy_dev->mdio.addr, i);
291 }
292
293 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
294 {
295 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
296 temp &= ~GPIO_CFG_EEPR_EN_;
297 smsc9420_reg_write(pd, GPIO_CFG, temp);
298 msleep(1);
299 }
300
301 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
302 {
303 int timeout = 100;
304 u32 e2cmd;
305
306 netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op);
307 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
308 netif_warn(pd, hw, pd->dev, "Busy at start\n");
309 return -EBUSY;
310 }
311
312 e2cmd = op | E2P_CMD_EPC_BUSY_;
313 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
314
315 do {
316 msleep(1);
317 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
318 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
319
320 if (!timeout) {
321 netif_info(pd, hw, pd->dev, "TIMED OUT\n");
322 return -EAGAIN;
323 }
324
325 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
326 netif_info(pd, hw, pd->dev,
327 "Error occurred during eeprom operation\n");
328 return -EINVAL;
329 }
330
331 return 0;
332 }
333
334 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
335 u8 address, u8 *data)
336 {
337 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
338 int ret;
339
340 netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address);
341 ret = smsc9420_eeprom_send_cmd(pd, op);
342
343 if (!ret)
344 data[address] = smsc9420_reg_read(pd, E2P_DATA);
345
346 return ret;
347 }
348
349 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
350 u8 address, u8 data)
351 {
352 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
353 int ret;
354
355 netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data);
356 ret = smsc9420_eeprom_send_cmd(pd, op);
357
358 if (!ret) {
359 op = E2P_CMD_EPC_CMD_WRITE_ | address;
360 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
361 ret = smsc9420_eeprom_send_cmd(pd, op);
362 }
363
364 return ret;
365 }
366
367 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
368 {
369 return SMSC9420_EEPROM_SIZE;
370 }
371
372 static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
373 struct ethtool_eeprom *eeprom, u8 *data)
374 {
375 struct smsc9420_pdata *pd = netdev_priv(dev);
376 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
377 int len, i;
378
379 smsc9420_eeprom_enable_access(pd);
380
381 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
382 for (i = 0; i < len; i++) {
383 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
384 if (ret < 0) {
385 eeprom->len = 0;
386 return ret;
387 }
388 }
389
390 memcpy(data, &eeprom_data[eeprom->offset], len);
391 eeprom->magic = SMSC9420_EEPROM_MAGIC;
392 eeprom->len = len;
393 return 0;
394 }
395
396 static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
397 struct ethtool_eeprom *eeprom, u8 *data)
398 {
399 struct smsc9420_pdata *pd = netdev_priv(dev);
400 int ret;
401
402 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
403 return -EINVAL;
404
405 smsc9420_eeprom_enable_access(pd);
406 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
407 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
408 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
409
410 /* Single byte write, according to man page */
411 eeprom->len = 1;
412
413 return ret;
414 }
415
416 static const struct ethtool_ops smsc9420_ethtool_ops = {
417 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
418 .get_msglevel = smsc9420_ethtool_get_msglevel,
419 .set_msglevel = smsc9420_ethtool_set_msglevel,
420 .nway_reset = smsc9420_ethtool_nway_reset,
421 .get_link = ethtool_op_get_link,
422 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
423 .get_eeprom = smsc9420_ethtool_get_eeprom,
424 .set_eeprom = smsc9420_ethtool_set_eeprom,
425 .get_regs_len = smsc9420_ethtool_getregslen,
426 .get_regs = smsc9420_ethtool_getregs,
427 .get_ts_info = ethtool_op_get_ts_info,
428 .get_link_ksettings = phy_ethtool_get_link_ksettings,
429 .set_link_ksettings = phy_ethtool_set_link_ksettings,
430 };
431
432 /* Sets the device MAC address to dev_addr */
433 static void smsc9420_set_mac_address(struct net_device *dev)
434 {
435 struct smsc9420_pdata *pd = netdev_priv(dev);
436 u8 *dev_addr = dev->dev_addr;
437 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
438 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
439 (dev_addr[1] << 8) | dev_addr[0];
440
441 smsc9420_reg_write(pd, ADDRH, mac_high16);
442 smsc9420_reg_write(pd, ADDRL, mac_low32);
443 }
444
445 static void smsc9420_check_mac_address(struct net_device *dev)
446 {
447 struct smsc9420_pdata *pd = netdev_priv(dev);
448
449 /* Check if mac address has been specified when bringing interface up */
450 if (is_valid_ether_addr(dev->dev_addr)) {
451 smsc9420_set_mac_address(dev);
452 netif_dbg(pd, probe, pd->dev,
453 "MAC Address is specified by configuration\n");
454 } else {
455 /* Try reading mac address from device. if EEPROM is present
456 * it will already have been set */
457 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
458 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
459 dev->dev_addr[0] = (u8)(mac_low32);
460 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
461 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
462 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
463 dev->dev_addr[4] = (u8)(mac_high16);
464 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
465
466 if (is_valid_ether_addr(dev->dev_addr)) {
467 /* eeprom values are valid so use them */
468 netif_dbg(pd, probe, pd->dev,
469 "Mac Address is read from EEPROM\n");
470 } else {
471 /* eeprom values are invalid, generate random MAC */
472 eth_hw_addr_random(dev);
473 smsc9420_set_mac_address(dev);
474 netif_dbg(pd, probe, pd->dev,
475 "MAC Address is set to random\n");
476 }
477 }
478 }
479
480 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
481 {
482 u32 dmac_control, mac_cr, dma_intr_ena;
483 int timeout = 1000;
484
485 /* disable TX DMAC */
486 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
487 dmac_control &= (~DMAC_CONTROL_ST_);
488 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
489
490 /* Wait max 10ms for transmit process to stop */
491 while (--timeout) {
492 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
493 break;
494 udelay(10);
495 }
496
497 if (!timeout)
498 netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n");
499
500 /* ACK Tx DMAC stop bit */
501 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
502
503 /* mask TX DMAC interrupts */
504 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
505 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
506 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
507 smsc9420_pci_flush_write(pd);
508
509 /* stop MAC TX */
510 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
511 smsc9420_reg_write(pd, MAC_CR, mac_cr);
512 smsc9420_pci_flush_write(pd);
513 }
514
515 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
516 {
517 int i;
518
519 BUG_ON(!pd->tx_ring);
520
521 if (!pd->tx_buffers)
522 return;
523
524 for (i = 0; i < TX_RING_SIZE; i++) {
525 struct sk_buff *skb = pd->tx_buffers[i].skb;
526
527 if (skb) {
528 BUG_ON(!pd->tx_buffers[i].mapping);
529 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
530 skb->len, PCI_DMA_TODEVICE);
531 dev_kfree_skb_any(skb);
532 }
533
534 pd->tx_ring[i].status = 0;
535 pd->tx_ring[i].length = 0;
536 pd->tx_ring[i].buffer1 = 0;
537 pd->tx_ring[i].buffer2 = 0;
538 }
539 wmb();
540
541 kfree(pd->tx_buffers);
542 pd->tx_buffers = NULL;
543
544 pd->tx_ring_head = 0;
545 pd->tx_ring_tail = 0;
546 }
547
548 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
549 {
550 int i;
551
552 BUG_ON(!pd->rx_ring);
553
554 if (!pd->rx_buffers)
555 return;
556
557 for (i = 0; i < RX_RING_SIZE; i++) {
558 if (pd->rx_buffers[i].skb)
559 dev_kfree_skb_any(pd->rx_buffers[i].skb);
560
561 if (pd->rx_buffers[i].mapping)
562 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
563 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
564
565 pd->rx_ring[i].status = 0;
566 pd->rx_ring[i].length = 0;
567 pd->rx_ring[i].buffer1 = 0;
568 pd->rx_ring[i].buffer2 = 0;
569 }
570 wmb();
571
572 kfree(pd->rx_buffers);
573 pd->rx_buffers = NULL;
574
575 pd->rx_ring_head = 0;
576 pd->rx_ring_tail = 0;
577 }
578
579 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
580 {
581 int timeout = 1000;
582 u32 mac_cr, dmac_control, dma_intr_ena;
583
584 /* mask RX DMAC interrupts */
585 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
586 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
587 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
588 smsc9420_pci_flush_write(pd);
589
590 /* stop RX MAC prior to stoping DMA */
591 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
592 smsc9420_reg_write(pd, MAC_CR, mac_cr);
593 smsc9420_pci_flush_write(pd);
594
595 /* stop RX DMAC */
596 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
597 dmac_control &= (~DMAC_CONTROL_SR_);
598 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
599 smsc9420_pci_flush_write(pd);
600
601 /* wait up to 10ms for receive to stop */
602 while (--timeout) {
603 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
604 break;
605 udelay(10);
606 }
607
608 if (!timeout)
609 netif_warn(pd, ifdown, pd->dev,
610 "RX DMAC did not stop! timeout\n");
611
612 /* ACK the Rx DMAC stop bit */
613 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
614 }
615
616 static irqreturn_t smsc9420_isr(int irq, void *dev_id)
617 {
618 struct smsc9420_pdata *pd = dev_id;
619 u32 int_cfg, int_sts, int_ctl;
620 irqreturn_t ret = IRQ_NONE;
621 ulong flags;
622
623 BUG_ON(!pd);
624 BUG_ON(!pd->ioaddr);
625
626 int_cfg = smsc9420_reg_read(pd, INT_CFG);
627
628 /* check if it's our interrupt */
629 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
630 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
631 return IRQ_NONE;
632
633 int_sts = smsc9420_reg_read(pd, INT_STAT);
634
635 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
636 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
637 u32 ints_to_clear = 0;
638
639 if (status & DMAC_STS_TX_) {
640 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
641 netif_wake_queue(pd->dev);
642 }
643
644 if (status & DMAC_STS_RX_) {
645 /* mask RX DMAC interrupts */
646 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
647 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
648 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
649 smsc9420_pci_flush_write(pd);
650
651 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
652 napi_schedule(&pd->napi);
653 }
654
655 if (ints_to_clear)
656 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
657
658 ret = IRQ_HANDLED;
659 }
660
661 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
662 /* mask software interrupt */
663 spin_lock_irqsave(&pd->int_lock, flags);
664 int_ctl = smsc9420_reg_read(pd, INT_CTL);
665 int_ctl &= (~INT_CTL_SW_INT_EN_);
666 smsc9420_reg_write(pd, INT_CTL, int_ctl);
667 spin_unlock_irqrestore(&pd->int_lock, flags);
668
669 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
670 pd->software_irq_signal = true;
671 smp_wmb();
672
673 ret = IRQ_HANDLED;
674 }
675
676 /* to ensure PCI write completion, we must perform a PCI read */
677 smsc9420_pci_flush_write(pd);
678
679 return ret;
680 }
681
682 #ifdef CONFIG_NET_POLL_CONTROLLER
683 static void smsc9420_poll_controller(struct net_device *dev)
684 {
685 struct smsc9420_pdata *pd = netdev_priv(dev);
686 const int irq = pd->pdev->irq;
687
688 disable_irq(irq);
689 smsc9420_isr(0, dev);
690 enable_irq(irq);
691 }
692 #endif /* CONFIG_NET_POLL_CONTROLLER */
693
694 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
695 {
696 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
697 smsc9420_reg_read(pd, BUS_MODE);
698 udelay(2);
699 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
700 netif_warn(pd, drv, pd->dev, "Software reset not cleared\n");
701 }
702
703 static int smsc9420_stop(struct net_device *dev)
704 {
705 struct smsc9420_pdata *pd = netdev_priv(dev);
706 u32 int_cfg;
707 ulong flags;
708
709 BUG_ON(!pd);
710 BUG_ON(!dev->phydev);
711
712 /* disable master interrupt */
713 spin_lock_irqsave(&pd->int_lock, flags);
714 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
715 smsc9420_reg_write(pd, INT_CFG, int_cfg);
716 spin_unlock_irqrestore(&pd->int_lock, flags);
717
718 netif_tx_disable(dev);
719 napi_disable(&pd->napi);
720
721 smsc9420_stop_tx(pd);
722 smsc9420_free_tx_ring(pd);
723
724 smsc9420_stop_rx(pd);
725 smsc9420_free_rx_ring(pd);
726
727 free_irq(pd->pdev->irq, pd);
728
729 smsc9420_dmac_soft_reset(pd);
730
731 phy_stop(dev->phydev);
732
733 phy_disconnect(dev->phydev);
734 mdiobus_unregister(pd->mii_bus);
735 mdiobus_free(pd->mii_bus);
736
737 return 0;
738 }
739
740 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
741 {
742 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
743 dev->stats.rx_errors++;
744 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
745 dev->stats.rx_over_errors++;
746 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
747 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
748 dev->stats.rx_frame_errors++;
749 else if (desc_status & RDES0_CRC_ERROR_)
750 dev->stats.rx_crc_errors++;
751 }
752
753 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
754 dev->stats.rx_length_errors++;
755
756 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
757 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
758 dev->stats.rx_length_errors++;
759
760 if (desc_status & RDES0_MULTICAST_FRAME_)
761 dev->stats.multicast++;
762 }
763
764 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
765 const u32 status)
766 {
767 struct net_device *dev = pd->dev;
768 struct sk_buff *skb;
769 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
770 >> RDES0_FRAME_LENGTH_SHFT_;
771
772 /* remove crc from packet lendth */
773 packet_length -= 4;
774
775 if (pd->rx_csum)
776 packet_length -= 2;
777
778 dev->stats.rx_packets++;
779 dev->stats.rx_bytes += packet_length;
780
781 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
782 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
783 pd->rx_buffers[index].mapping = 0;
784
785 skb = pd->rx_buffers[index].skb;
786 pd->rx_buffers[index].skb = NULL;
787
788 if (pd->rx_csum) {
789 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
790 NET_IP_ALIGN + packet_length + 4);
791 put_unaligned_le16(hw_csum, &skb->csum);
792 skb->ip_summed = CHECKSUM_COMPLETE;
793 }
794
795 skb_reserve(skb, NET_IP_ALIGN);
796 skb_put(skb, packet_length);
797
798 skb->protocol = eth_type_trans(skb, dev);
799
800 netif_receive_skb(skb);
801 }
802
803 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
804 {
805 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
806 dma_addr_t mapping;
807
808 BUG_ON(pd->rx_buffers[index].skb);
809 BUG_ON(pd->rx_buffers[index].mapping);
810
811 if (unlikely(!skb))
812 return -ENOMEM;
813
814 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
815 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
816 if (pci_dma_mapping_error(pd->pdev, mapping)) {
817 dev_kfree_skb_any(skb);
818 netif_warn(pd, rx_err, pd->dev, "pci_map_single failed!\n");
819 return -ENOMEM;
820 }
821
822 pd->rx_buffers[index].skb = skb;
823 pd->rx_buffers[index].mapping = mapping;
824 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
825 pd->rx_ring[index].status = RDES0_OWN_;
826 wmb();
827
828 return 0;
829 }
830
831 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
832 {
833 while (pd->rx_ring_tail != pd->rx_ring_head) {
834 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
835 break;
836
837 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
838 }
839 }
840
841 static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
842 {
843 struct smsc9420_pdata *pd =
844 container_of(napi, struct smsc9420_pdata, napi);
845 struct net_device *dev = pd->dev;
846 u32 drop_frame_cnt, dma_intr_ena, status;
847 int work_done;
848
849 for (work_done = 0; work_done < budget; work_done++) {
850 rmb();
851 status = pd->rx_ring[pd->rx_ring_head].status;
852
853 /* stop if DMAC owns this dma descriptor */
854 if (status & RDES0_OWN_)
855 break;
856
857 smsc9420_rx_count_stats(dev, status);
858 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
859 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
860 smsc9420_alloc_new_rx_buffers(pd);
861 }
862
863 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
864 dev->stats.rx_dropped +=
865 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
866
867 /* Kick RXDMA */
868 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
869 smsc9420_pci_flush_write(pd);
870
871 if (work_done < budget) {
872 napi_complete(&pd->napi);
873
874 /* re-enable RX DMA interrupts */
875 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
876 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
877 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
878 smsc9420_pci_flush_write(pd);
879 }
880 return work_done;
881 }
882
883 static void
884 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
885 {
886 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
887 dev->stats.tx_errors++;
888 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
889 TDES0_EXCESSIVE_COLLISIONS_))
890 dev->stats.tx_aborted_errors++;
891
892 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
893 dev->stats.tx_carrier_errors++;
894 } else {
895 dev->stats.tx_packets++;
896 dev->stats.tx_bytes += (length & 0x7FF);
897 }
898
899 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
900 dev->stats.collisions += 16;
901 } else {
902 dev->stats.collisions +=
903 (status & TDES0_COLLISION_COUNT_MASK_) >>
904 TDES0_COLLISION_COUNT_SHFT_;
905 }
906
907 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
908 dev->stats.tx_heartbeat_errors++;
909 }
910
911 /* Check for completed dma transfers, update stats and free skbs */
912 static void smsc9420_complete_tx(struct net_device *dev)
913 {
914 struct smsc9420_pdata *pd = netdev_priv(dev);
915
916 while (pd->tx_ring_tail != pd->tx_ring_head) {
917 int index = pd->tx_ring_tail;
918 u32 status, length;
919
920 rmb();
921 status = pd->tx_ring[index].status;
922 length = pd->tx_ring[index].length;
923
924 /* Check if DMA still owns this descriptor */
925 if (unlikely(TDES0_OWN_ & status))
926 break;
927
928 smsc9420_tx_update_stats(dev, status, length);
929
930 BUG_ON(!pd->tx_buffers[index].skb);
931 BUG_ON(!pd->tx_buffers[index].mapping);
932
933 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
934 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
935 pd->tx_buffers[index].mapping = 0;
936
937 dev_kfree_skb_any(pd->tx_buffers[index].skb);
938 pd->tx_buffers[index].skb = NULL;
939
940 pd->tx_ring[index].buffer1 = 0;
941 wmb();
942
943 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
944 }
945 }
946
947 static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
948 struct net_device *dev)
949 {
950 struct smsc9420_pdata *pd = netdev_priv(dev);
951 dma_addr_t mapping;
952 int index = pd->tx_ring_head;
953 u32 tmp_desc1;
954 bool about_to_take_last_desc =
955 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
956
957 smsc9420_complete_tx(dev);
958
959 rmb();
960 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
961 BUG_ON(pd->tx_buffers[index].skb);
962 BUG_ON(pd->tx_buffers[index].mapping);
963
964 mapping = pci_map_single(pd->pdev, skb->data,
965 skb->len, PCI_DMA_TODEVICE);
966 if (pci_dma_mapping_error(pd->pdev, mapping)) {
967 netif_warn(pd, tx_err, pd->dev,
968 "pci_map_single failed, dropping packet\n");
969 return NETDEV_TX_BUSY;
970 }
971
972 pd->tx_buffers[index].skb = skb;
973 pd->tx_buffers[index].mapping = mapping;
974
975 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
976 if (unlikely(about_to_take_last_desc)) {
977 tmp_desc1 |= TDES1_IC_;
978 netif_stop_queue(pd->dev);
979 }
980
981 /* check if we are at the last descriptor and need to set EOR */
982 if (unlikely(index == (TX_RING_SIZE - 1)))
983 tmp_desc1 |= TDES1_TER_;
984
985 pd->tx_ring[index].buffer1 = mapping;
986 pd->tx_ring[index].length = tmp_desc1;
987 wmb();
988
989 /* increment head */
990 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
991
992 /* assign ownership to DMAC */
993 pd->tx_ring[index].status = TDES0_OWN_;
994 wmb();
995
996 skb_tx_timestamp(skb);
997
998 /* kick the DMA */
999 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
1000 smsc9420_pci_flush_write(pd);
1001
1002 return NETDEV_TX_OK;
1003 }
1004
1005 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
1006 {
1007 struct smsc9420_pdata *pd = netdev_priv(dev);
1008 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
1009 dev->stats.rx_dropped +=
1010 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
1011 return &dev->stats;
1012 }
1013
1014 static void smsc9420_set_multicast_list(struct net_device *dev)
1015 {
1016 struct smsc9420_pdata *pd = netdev_priv(dev);
1017 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1018
1019 if (dev->flags & IFF_PROMISC) {
1020 netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n");
1021 mac_cr |= MAC_CR_PRMS_;
1022 mac_cr &= (~MAC_CR_MCPAS_);
1023 mac_cr &= (~MAC_CR_HPFILT_);
1024 } else if (dev->flags & IFF_ALLMULTI) {
1025 netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n");
1026 mac_cr &= (~MAC_CR_PRMS_);
1027 mac_cr |= MAC_CR_MCPAS_;
1028 mac_cr &= (~MAC_CR_HPFILT_);
1029 } else if (!netdev_mc_empty(dev)) {
1030 struct netdev_hw_addr *ha;
1031 u32 hash_lo = 0, hash_hi = 0;
1032
1033 netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n");
1034 netdev_for_each_mc_addr(ha, dev) {
1035 u32 bit_num = smsc9420_hash(ha->addr);
1036 u32 mask = 1 << (bit_num & 0x1F);
1037
1038 if (bit_num & 0x20)
1039 hash_hi |= mask;
1040 else
1041 hash_lo |= mask;
1042
1043 }
1044 smsc9420_reg_write(pd, HASHH, hash_hi);
1045 smsc9420_reg_write(pd, HASHL, hash_lo);
1046
1047 mac_cr &= (~MAC_CR_PRMS_);
1048 mac_cr &= (~MAC_CR_MCPAS_);
1049 mac_cr |= MAC_CR_HPFILT_;
1050 } else {
1051 netif_dbg(pd, hw, pd->dev, "Receive own packets only\n");
1052 smsc9420_reg_write(pd, HASHH, 0);
1053 smsc9420_reg_write(pd, HASHL, 0);
1054
1055 mac_cr &= (~MAC_CR_PRMS_);
1056 mac_cr &= (~MAC_CR_MCPAS_);
1057 mac_cr &= (~MAC_CR_HPFILT_);
1058 }
1059
1060 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1061 smsc9420_pci_flush_write(pd);
1062 }
1063
1064 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1065 {
1066 struct net_device *dev = pd->dev;
1067 struct phy_device *phy_dev = dev->phydev;
1068 u32 flow;
1069
1070 if (phy_dev->duplex == DUPLEX_FULL) {
1071 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1072 u16 rmtadv = phy_read(phy_dev, MII_LPA);
1073 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1074
1075 if (cap & FLOW_CTRL_RX)
1076 flow = 0xFFFF0002;
1077 else
1078 flow = 0;
1079
1080 netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n",
1081 cap & FLOW_CTRL_RX ? "enabled" : "disabled",
1082 cap & FLOW_CTRL_TX ? "enabled" : "disabled");
1083 } else {
1084 netif_info(pd, link, pd->dev, "half duplex\n");
1085 flow = 0;
1086 }
1087
1088 smsc9420_reg_write(pd, FLOW, flow);
1089 }
1090
1091 /* Update link mode if anything has changed. Called periodically when the
1092 * PHY is in polling mode, even if nothing has changed. */
1093 static void smsc9420_phy_adjust_link(struct net_device *dev)
1094 {
1095 struct smsc9420_pdata *pd = netdev_priv(dev);
1096 struct phy_device *phy_dev = dev->phydev;
1097 int carrier;
1098
1099 if (phy_dev->duplex != pd->last_duplex) {
1100 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1101 if (phy_dev->duplex) {
1102 netif_dbg(pd, link, pd->dev, "full duplex mode\n");
1103 mac_cr |= MAC_CR_FDPX_;
1104 } else {
1105 netif_dbg(pd, link, pd->dev, "half duplex mode\n");
1106 mac_cr &= ~MAC_CR_FDPX_;
1107 }
1108 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1109
1110 smsc9420_phy_update_flowcontrol(pd);
1111 pd->last_duplex = phy_dev->duplex;
1112 }
1113
1114 carrier = netif_carrier_ok(dev);
1115 if (carrier != pd->last_carrier) {
1116 if (carrier)
1117 netif_dbg(pd, link, pd->dev, "carrier OK\n");
1118 else
1119 netif_dbg(pd, link, pd->dev, "no carrier\n");
1120 pd->last_carrier = carrier;
1121 }
1122 }
1123
1124 static int smsc9420_mii_probe(struct net_device *dev)
1125 {
1126 struct smsc9420_pdata *pd = netdev_priv(dev);
1127 struct phy_device *phydev = NULL;
1128
1129 BUG_ON(dev->phydev);
1130
1131 /* Device only supports internal PHY at address 1 */
1132 phydev = mdiobus_get_phy(pd->mii_bus, 1);
1133 if (!phydev) {
1134 netdev_err(dev, "no PHY found at address 1\n");
1135 return -ENODEV;
1136 }
1137
1138 phydev = phy_connect(dev, phydev_name(phydev),
1139 smsc9420_phy_adjust_link, PHY_INTERFACE_MODE_MII);
1140
1141 if (IS_ERR(phydev)) {
1142 netdev_err(dev, "Could not attach to PHY\n");
1143 return PTR_ERR(phydev);
1144 }
1145
1146 /* mask with MAC supported features */
1147 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1148 SUPPORTED_Asym_Pause);
1149 phydev->advertising = phydev->supported;
1150
1151 phy_attached_info(phydev);
1152
1153 pd->last_duplex = -1;
1154 pd->last_carrier = -1;
1155
1156 return 0;
1157 }
1158
1159 static int smsc9420_mii_init(struct net_device *dev)
1160 {
1161 struct smsc9420_pdata *pd = netdev_priv(dev);
1162 int err = -ENXIO;
1163
1164 pd->mii_bus = mdiobus_alloc();
1165 if (!pd->mii_bus) {
1166 err = -ENOMEM;
1167 goto err_out_1;
1168 }
1169 pd->mii_bus->name = DRV_MDIONAME;
1170 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1171 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1172 pd->mii_bus->priv = pd;
1173 pd->mii_bus->read = smsc9420_mii_read;
1174 pd->mii_bus->write = smsc9420_mii_write;
1175
1176 /* Mask all PHYs except ID 1 (internal) */
1177 pd->mii_bus->phy_mask = ~(1 << 1);
1178
1179 if (mdiobus_register(pd->mii_bus)) {
1180 netif_warn(pd, probe, pd->dev, "Error registering mii bus\n");
1181 goto err_out_free_bus_2;
1182 }
1183
1184 if (smsc9420_mii_probe(dev) < 0) {
1185 netif_warn(pd, probe, pd->dev, "Error probing mii bus\n");
1186 goto err_out_unregister_bus_3;
1187 }
1188
1189 return 0;
1190
1191 err_out_unregister_bus_3:
1192 mdiobus_unregister(pd->mii_bus);
1193 err_out_free_bus_2:
1194 mdiobus_free(pd->mii_bus);
1195 err_out_1:
1196 return err;
1197 }
1198
1199 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1200 {
1201 int i;
1202
1203 BUG_ON(!pd->tx_ring);
1204
1205 pd->tx_buffers = kmalloc_array(TX_RING_SIZE,
1206 sizeof(struct smsc9420_ring_info),
1207 GFP_KERNEL);
1208 if (!pd->tx_buffers)
1209 return -ENOMEM;
1210
1211 /* Initialize the TX Ring */
1212 for (i = 0; i < TX_RING_SIZE; i++) {
1213 pd->tx_buffers[i].skb = NULL;
1214 pd->tx_buffers[i].mapping = 0;
1215 pd->tx_ring[i].status = 0;
1216 pd->tx_ring[i].length = 0;
1217 pd->tx_ring[i].buffer1 = 0;
1218 pd->tx_ring[i].buffer2 = 0;
1219 }
1220 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1221 wmb();
1222
1223 pd->tx_ring_head = 0;
1224 pd->tx_ring_tail = 0;
1225
1226 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1227 smsc9420_pci_flush_write(pd);
1228
1229 return 0;
1230 }
1231
1232 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1233 {
1234 int i;
1235
1236 BUG_ON(!pd->rx_ring);
1237
1238 pd->rx_buffers = kmalloc_array(RX_RING_SIZE,
1239 sizeof(struct smsc9420_ring_info),
1240 GFP_KERNEL);
1241 if (pd->rx_buffers == NULL)
1242 goto out;
1243
1244 /* initialize the rx ring */
1245 for (i = 0; i < RX_RING_SIZE; i++) {
1246 pd->rx_ring[i].status = 0;
1247 pd->rx_ring[i].length = PKT_BUF_SZ;
1248 pd->rx_ring[i].buffer2 = 0;
1249 pd->rx_buffers[i].skb = NULL;
1250 pd->rx_buffers[i].mapping = 0;
1251 }
1252 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1253
1254 /* now allocate the entire ring of skbs */
1255 for (i = 0; i < RX_RING_SIZE; i++) {
1256 if (smsc9420_alloc_rx_buffer(pd, i)) {
1257 netif_warn(pd, ifup, pd->dev,
1258 "failed to allocate rx skb %d\n", i);
1259 goto out_free_rx_skbs;
1260 }
1261 }
1262
1263 pd->rx_ring_head = 0;
1264 pd->rx_ring_tail = 0;
1265
1266 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1267 netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n",
1268 smsc9420_reg_read(pd, VLAN1));
1269
1270 if (pd->rx_csum) {
1271 /* Enable RX COE */
1272 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1273 smsc9420_reg_write(pd, COE_CR, coe);
1274 netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe);
1275 }
1276
1277 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1278 smsc9420_pci_flush_write(pd);
1279
1280 return 0;
1281
1282 out_free_rx_skbs:
1283 smsc9420_free_rx_ring(pd);
1284 out:
1285 return -ENOMEM;
1286 }
1287
1288 static int smsc9420_open(struct net_device *dev)
1289 {
1290 struct smsc9420_pdata *pd = netdev_priv(dev);
1291 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1292 const int irq = pd->pdev->irq;
1293 unsigned long flags;
1294 int result = 0, timeout;
1295
1296 if (!is_valid_ether_addr(dev->dev_addr)) {
1297 netif_warn(pd, ifup, pd->dev,
1298 "dev_addr is not a valid MAC address\n");
1299 result = -EADDRNOTAVAIL;
1300 goto out_0;
1301 }
1302
1303 netif_carrier_off(dev);
1304
1305 /* disable, mask and acknowledge all interrupts */
1306 spin_lock_irqsave(&pd->int_lock, flags);
1307 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1308 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1309 smsc9420_reg_write(pd, INT_CTL, 0);
1310 spin_unlock_irqrestore(&pd->int_lock, flags);
1311 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1312 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1313 smsc9420_pci_flush_write(pd);
1314
1315 result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);
1316 if (result) {
1317 netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq);
1318 result = -ENODEV;
1319 goto out_0;
1320 }
1321
1322 smsc9420_dmac_soft_reset(pd);
1323
1324 /* make sure MAC_CR is sane */
1325 smsc9420_reg_write(pd, MAC_CR, 0);
1326
1327 smsc9420_set_mac_address(dev);
1328
1329 /* Configure GPIO pins to drive LEDs */
1330 smsc9420_reg_write(pd, GPIO_CFG,
1331 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1332
1333 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1334
1335 #ifdef __BIG_ENDIAN
1336 bus_mode |= BUS_MODE_DBO_;
1337 #endif
1338
1339 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1340
1341 smsc9420_pci_flush_write(pd);
1342
1343 /* set bus master bridge arbitration priority for Rx and TX DMA */
1344 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1345
1346 smsc9420_reg_write(pd, DMAC_CONTROL,
1347 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1348
1349 smsc9420_pci_flush_write(pd);
1350
1351 /* test the IRQ connection to the ISR */
1352 netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq);
1353 pd->software_irq_signal = false;
1354
1355 spin_lock_irqsave(&pd->int_lock, flags);
1356 /* configure interrupt deassertion timer and enable interrupts */
1357 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1358 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1359 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1360 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1361
1362 /* unmask software interrupt */
1363 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1364 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1365 spin_unlock_irqrestore(&pd->int_lock, flags);
1366 smsc9420_pci_flush_write(pd);
1367
1368 timeout = 1000;
1369 while (timeout--) {
1370 if (pd->software_irq_signal)
1371 break;
1372 msleep(1);
1373 }
1374
1375 /* disable interrupts */
1376 spin_lock_irqsave(&pd->int_lock, flags);
1377 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1378 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1379 spin_unlock_irqrestore(&pd->int_lock, flags);
1380
1381 if (!pd->software_irq_signal) {
1382 netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n");
1383 result = -ENODEV;
1384 goto out_free_irq_1;
1385 }
1386
1387 netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq);
1388
1389 result = smsc9420_alloc_tx_ring(pd);
1390 if (result) {
1391 netif_warn(pd, ifup, pd->dev,
1392 "Failed to Initialize tx dma ring\n");
1393 result = -ENOMEM;
1394 goto out_free_irq_1;
1395 }
1396
1397 result = smsc9420_alloc_rx_ring(pd);
1398 if (result) {
1399 netif_warn(pd, ifup, pd->dev,
1400 "Failed to Initialize rx dma ring\n");
1401 result = -ENOMEM;
1402 goto out_free_tx_ring_2;
1403 }
1404
1405 result = smsc9420_mii_init(dev);
1406 if (result) {
1407 netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n");
1408 result = -ENODEV;
1409 goto out_free_rx_ring_3;
1410 }
1411
1412 /* Bring the PHY up */
1413 phy_start(dev->phydev);
1414
1415 napi_enable(&pd->napi);
1416
1417 /* start tx and rx */
1418 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1419 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1420
1421 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1422 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1423 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1424 smsc9420_pci_flush_write(pd);
1425
1426 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1427 dma_intr_ena |=
1428 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1429 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1430 smsc9420_pci_flush_write(pd);
1431
1432 netif_wake_queue(dev);
1433
1434 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1435
1436 /* enable interrupts */
1437 spin_lock_irqsave(&pd->int_lock, flags);
1438 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1439 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1440 spin_unlock_irqrestore(&pd->int_lock, flags);
1441
1442 return 0;
1443
1444 out_free_rx_ring_3:
1445 smsc9420_free_rx_ring(pd);
1446 out_free_tx_ring_2:
1447 smsc9420_free_tx_ring(pd);
1448 out_free_irq_1:
1449 free_irq(irq, pd);
1450 out_0:
1451 return result;
1452 }
1453
1454 #ifdef CONFIG_PM
1455
1456 static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1457 {
1458 struct net_device *dev = pci_get_drvdata(pdev);
1459 struct smsc9420_pdata *pd = netdev_priv(dev);
1460 u32 int_cfg;
1461 ulong flags;
1462
1463 /* disable interrupts */
1464 spin_lock_irqsave(&pd->int_lock, flags);
1465 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1466 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1467 spin_unlock_irqrestore(&pd->int_lock, flags);
1468
1469 if (netif_running(dev)) {
1470 netif_tx_disable(dev);
1471 smsc9420_stop_tx(pd);
1472 smsc9420_free_tx_ring(pd);
1473
1474 napi_disable(&pd->napi);
1475 smsc9420_stop_rx(pd);
1476 smsc9420_free_rx_ring(pd);
1477
1478 free_irq(pd->pdev->irq, pd);
1479
1480 netif_device_detach(dev);
1481 }
1482
1483 pci_save_state(pdev);
1484 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1485 pci_disable_device(pdev);
1486 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1487
1488 return 0;
1489 }
1490
1491 static int smsc9420_resume(struct pci_dev *pdev)
1492 {
1493 struct net_device *dev = pci_get_drvdata(pdev);
1494 struct smsc9420_pdata *pd = netdev_priv(dev);
1495 int err;
1496
1497 pci_set_power_state(pdev, PCI_D0);
1498 pci_restore_state(pdev);
1499
1500 err = pci_enable_device(pdev);
1501 if (err)
1502 return err;
1503
1504 pci_set_master(pdev);
1505
1506 err = pci_enable_wake(pdev, PCI_D0, 0);
1507 if (err)
1508 netif_warn(pd, ifup, pd->dev, "pci_enable_wake failed: %d\n",
1509 err);
1510
1511 if (netif_running(dev)) {
1512 /* FIXME: gross. It looks like ancient PM relic.*/
1513 err = smsc9420_open(dev);
1514 netif_device_attach(dev);
1515 }
1516 return err;
1517 }
1518
1519 #endif /* CONFIG_PM */
1520
1521 static const struct net_device_ops smsc9420_netdev_ops = {
1522 .ndo_open = smsc9420_open,
1523 .ndo_stop = smsc9420_stop,
1524 .ndo_start_xmit = smsc9420_hard_start_xmit,
1525 .ndo_get_stats = smsc9420_get_stats,
1526 .ndo_set_rx_mode = smsc9420_set_multicast_list,
1527 .ndo_do_ioctl = smsc9420_do_ioctl,
1528 .ndo_validate_addr = eth_validate_addr,
1529 .ndo_set_mac_address = eth_mac_addr,
1530 #ifdef CONFIG_NET_POLL_CONTROLLER
1531 .ndo_poll_controller = smsc9420_poll_controller,
1532 #endif /* CONFIG_NET_POLL_CONTROLLER */
1533 };
1534
1535 static int
1536 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1537 {
1538 struct net_device *dev;
1539 struct smsc9420_pdata *pd;
1540 void __iomem *virt_addr;
1541 int result = 0;
1542 u32 id_rev;
1543
1544 pr_info("%s version %s\n", DRV_DESCRIPTION, DRV_VERSION);
1545
1546 /* First do the PCI initialisation */
1547 result = pci_enable_device(pdev);
1548 if (unlikely(result)) {
1549 pr_err("Cannot enable smsc9420\n");
1550 goto out_0;
1551 }
1552
1553 pci_set_master(pdev);
1554
1555 dev = alloc_etherdev(sizeof(*pd));
1556 if (!dev)
1557 goto out_disable_pci_device_1;
1558
1559 SET_NETDEV_DEV(dev, &pdev->dev);
1560
1561 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1562 netdev_err(dev, "Cannot find PCI device base address\n");
1563 goto out_free_netdev_2;
1564 }
1565
1566 if ((pci_request_regions(pdev, DRV_NAME))) {
1567 netdev_err(dev, "Cannot obtain PCI resources, aborting\n");
1568 goto out_free_netdev_2;
1569 }
1570
1571 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1572 netdev_err(dev, "No usable DMA configuration, aborting\n");
1573 goto out_free_regions_3;
1574 }
1575
1576 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1577 pci_resource_len(pdev, SMSC_BAR));
1578 if (!virt_addr) {
1579 netdev_err(dev, "Cannot map device registers, aborting\n");
1580 goto out_free_regions_3;
1581 }
1582
1583 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1584 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1585
1586 pd = netdev_priv(dev);
1587
1588 /* pci descriptors are created in the PCI consistent area */
1589 pd->rx_ring = pci_alloc_consistent(pdev,
1590 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1591 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1592 &pd->rx_dma_addr);
1593
1594 if (!pd->rx_ring)
1595 goto out_free_io_4;
1596
1597 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1598 pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);
1599 pd->tx_dma_addr = pd->rx_dma_addr +
1600 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1601
1602 pd->pdev = pdev;
1603 pd->dev = dev;
1604 pd->ioaddr = virt_addr;
1605 pd->msg_enable = smsc_debug;
1606 pd->rx_csum = true;
1607
1608 netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr);
1609
1610 id_rev = smsc9420_reg_read(pd, ID_REV);
1611 switch (id_rev & 0xFFFF0000) {
1612 case 0x94200000:
1613 netif_info(pd, probe, pd->dev,
1614 "LAN9420 identified, ID_REV=0x%08X\n", id_rev);
1615 break;
1616 default:
1617 netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n");
1618 netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev);
1619 goto out_free_dmadesc_5;
1620 }
1621
1622 smsc9420_dmac_soft_reset(pd);
1623 smsc9420_eeprom_reload(pd);
1624 smsc9420_check_mac_address(dev);
1625
1626 dev->netdev_ops = &smsc9420_netdev_ops;
1627 dev->ethtool_ops = &smsc9420_ethtool_ops;
1628
1629 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1630
1631 result = register_netdev(dev);
1632 if (result) {
1633 netif_warn(pd, probe, pd->dev, "error %i registering device\n",
1634 result);
1635 goto out_free_dmadesc_5;
1636 }
1637
1638 pci_set_drvdata(pdev, dev);
1639
1640 spin_lock_init(&pd->int_lock);
1641 spin_lock_init(&pd->phy_lock);
1642
1643 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1644
1645 return 0;
1646
1647 out_free_dmadesc_5:
1648 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1649 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1650 out_free_io_4:
1651 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1652 out_free_regions_3:
1653 pci_release_regions(pdev);
1654 out_free_netdev_2:
1655 free_netdev(dev);
1656 out_disable_pci_device_1:
1657 pci_disable_device(pdev);
1658 out_0:
1659 return -ENODEV;
1660 }
1661
1662 static void smsc9420_remove(struct pci_dev *pdev)
1663 {
1664 struct net_device *dev;
1665 struct smsc9420_pdata *pd;
1666
1667 dev = pci_get_drvdata(pdev);
1668 if (!dev)
1669 return;
1670
1671 pd = netdev_priv(dev);
1672 unregister_netdev(dev);
1673
1674 /* tx_buffers and rx_buffers are freed in stop */
1675 BUG_ON(pd->tx_buffers);
1676 BUG_ON(pd->rx_buffers);
1677
1678 BUG_ON(!pd->tx_ring);
1679 BUG_ON(!pd->rx_ring);
1680
1681 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1682 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1683
1684 iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);
1685 pci_release_regions(pdev);
1686 free_netdev(dev);
1687 pci_disable_device(pdev);
1688 }
1689
1690 static struct pci_driver smsc9420_driver = {
1691 .name = DRV_NAME,
1692 .id_table = smsc9420_id_table,
1693 .probe = smsc9420_probe,
1694 .remove = smsc9420_remove,
1695 #ifdef CONFIG_PM
1696 .suspend = smsc9420_suspend,
1697 .resume = smsc9420_resume,
1698 #endif /* CONFIG_PM */
1699 };
1700
1701 static int __init smsc9420_init_module(void)
1702 {
1703 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1704
1705 return pci_register_driver(&smsc9420_driver);
1706 }
1707
1708 static void __exit smsc9420_exit_module(void)
1709 {
1710 pci_unregister_driver(&smsc9420_driver);
1711 }
1712
1713 module_init(smsc9420_init_module);
1714 module_exit(smsc9420_exit_module);
Linux with added FPC-III support