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1 /* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 zaumen Exp $
2 * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver.
3 *
4 * Copyright (C) 2004 Sun Microsystems Inc.
5 * Copyright (c) 2003 Adrian Sun (asun@darksunrising.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * vendor id: 0x108E (Sun Microsystems, Inc.)
21 * device id: 0xabba (Cassini)
22 * revision ids: 0x01 = Cassini
23 * 0x02 = Cassini rev 2
24 * 0x10 = Cassini+
25 * 0x11 = Cassini+ 0.2u
26 *
27 * vendor id: 0x100b (National Semiconductor)
28 * device id: 0x0035 (DP83065/Saturn)
29 * revision ids: 0x30 = Saturn B2
30 *
31 * rings are all offset from 0.
32 *
33 * there are two clock domains:
34 * PCI: 33/66MHz clock
35 * chip: 125MHz clock
36 */
38 #ifndef _CASSINI_H
39 #define _CASSINI_H
41 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
42 * 32-bit words. there is no i/o port access. REG_ addresses are
43 * shared between cassini and cassini+. REG_PLUS_ addresses only
44 * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
45 */
46 #define CAS_ID_REV2 0x02
47 #define CAS_ID_REVPLUS 0x10
48 #define CAS_ID_REVPLUS02u 0x11
49 #define CAS_ID_REVSATURNB2 0x30
51 /** global resources **/
53 /* this register sets the weights for the weighted round robin arbiter. e.g.,
54 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
55 * for its next turn to access the pci bus.
56 * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8
57 * DEFAULT: 0x0, SIZE: 5 bits
58 */
60 #define CAWR_RX_DMA_WEIGHT_SHIFT 0
62 #define CAWR_TX_DMA_WEIGHT_SHIFT 2
66 /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
67 * sizes determined by length of packet or descriptor transfer and the
68 * max length allowed by the target.
69 * DEFAULT: 0x0, SIZE: 1 bit
70 */
74 /* top level interrupts [0-9] are auto-cleared to 0 when the status
75 * register is read. second level interrupts [13 - 18] are cleared at
76 * the source. tx completion register 3 is replicated in [19 - 31]
77 * DEFAULT: 0x00000000, SIZE: 29 bits
78 */
81 xferred from host queue to
82 TX FIFO */
84 TX FIFO. i.e.,
85 TX Kick == TX complete. if
86 PACED_MODE set, then TX FIFO
87 also empty */
89 FIFO */
91 corrupted. FATAL ERROR */
93 from RX FIFO to host mem.
94 RX completion reg updated.
95 may be delayed by recv
96 intr blanking. */
98 RX Kick == RX complete */
100 corrupted. FATAL ERROR */
102 ring to post descriptors.
103 RX complete head incr to
104 almost reach RX complete
105 tail */
107 programmable threshold #
108 of free descr avail for
109 hw use */
111 programmable threshold #
112 of descr spaces for hw
113 use in completion descr
114 ring */
116 len of non-reassembly pkt
117 from fifo during DMA or
118 header parser provides TCP
119 header and payload size >
120 MAC packet size.
121 FATAL ERROR */
123 bit will be set if an interrupt
124 generated on the pci bus. useful
125 when driver is polling for
126 interrupts */
129 least 1 unmasked interrupt set */
131 least 1 unmasked interrupt set */
133 at least 1 unmasked interrupt
134 set */
136 1 unmasked interrupt set */
138 BIF has at least 1 unmasked
139 interrupt set */
141 3 reg data */
142 #define INTR_TX_COMP_3_SHIFT 19
143 #define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
144 INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
145 INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
146 INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
147 INTR_MAC_CTRL_STATUS)
149 /* determines which status events will cause an interrupt. layout same
150 * as REG_INTR_STATUS.
151 * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits
152 */
155 /* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS.
156 * useful when driver is polling for interrupts. layout same as REG_INTR_MASK.
157 * DEFAULT: 0x00000000, SIZE: 12 bits
158 */
160 (used w/ status alias) */
161 /* same as REG_INTR_STATUS except that only bits cleared are those selected by
162 * REG_ALIAS_CLEAR
163 * DEFAULT: 0x00000000, SIZE: 29 bits
164 */
166 (selective clear) */
168 /* DEFAULT: 0x0, SIZE: 3 bits */
171 set if no ACK64# during ABS64 cycle
172 in Cassini. */
174 no read retry after 2^15 clocks */
177 unused in Cassini. */
179 unused in Cassini. */
181 DMA. unused in cassini. */
183 /* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event
184 * causes an interrupt to be generated.
185 * DEFAULT: 0x7, SIZE: 3 bits
186 */
189 /* used to configure PCI related parameters that are not in PCI config space.
190 * DEFAULT: 0bxx000, SIZE: 5 bits
191 */
203 reset. reserved in Cassini. */
205 reserved in Cassini. */
207 reserved in Cassini. */
209 /* DEFAULT: 0x00000000, SIZE: 32 bits */
212 machine bits [21:0] */
214 machine bits [6:0] */
216 /* writing to SW_RESET_TX and SW_RESET_RX will issue a global
217 * reset. poll until TX and RX read back as 0's for completion.
218 */
221 cleared to 0. */
223 cleared to 0. */
225 resets PHY and anything else
226 connected to RSTOUT#. RSTOUT#
227 is also activated by local PCI
228 reset when hot-swap is being
229 done. */
231 this bit set, PCS and SLINK
232 modules won't be reset.
233 i.e., link won't drop. */
236 0b000: ARB_IDLE1
237 0b001: ARB_IDLE2
238 0b010: ARB_WB_ACK
239 0b011: ARB_WB_WAT
240 0b100: ARB_RB_ACK
241 0b101: ARB_RB_WAT
242 0b110: ARB_RB_END
243 0b111: ARB_WB_END */
245 0b00: RD_PCI_WAT
246 0b01: RD_PCI_RDY
247 0b11: RD_PCI_ACK */
249 0b00: AD_IDL_RX
250 0b01: AD_ACK_RX
251 0b10: AD_ACK_TX
252 0b11: AD_IDL_TX */
254 0b00: WR_PCI_WAT
255 0b01: WR_PCI_RDY
256 0b11: WR_PCI_ACK */
258 0b000: ARB_IDLE1
259 0b001: ARB_IDLE2
260 0b010: ARB_TX_ACK
261 0b011: ARB_TX_WAT
262 0b100: ARB_RX_ACK
263 0b110: ARB_RX_WAT */
265 /* Cassini only. 64-bit register used to check PCI datapath. when read,
266 * value written has both lower and upper 32-bit halves rotated to the right
267 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
268 */
270 Cassini+: reserved */
272 /* output enables are provided for each device's chip select and for the rest
273 * of the outputs from cassini to its local bus devices. two sw programmable
274 * bits are connected to general purpus control/status bits.
275 * DEFAULT: 0x7
276 */
278 output EN. default: 0x7 */
280 OE signal output enable on the
281 local bus interface. these
282 are shared between both local
283 bus devices. tristate when 0. */
286 select output enable */
291 /* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR
292 * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI.
293 * _DATA_HI should be the last access of the sequence.
294 * DEFAULT: undefined
295 */
297 purposes. */
300 read buffer access = 0 */
301 /* DEFAULT: undefined */
305 /* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
306 * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
307 */
309 control/status */
312 Cassini only. reserved in
313 Cassini+. */
315 buffer. */
317 buffer. Cassini only. reserved
318 in Cassini+. */
322 Cassini only. reserved in
323 Cassini+. */
325 Cassini only. reserved in
326 Cassini+. */
328 /* ASUN: i'm not sure what this does as it's not in the spec.
329 * DEFAULT: 0xFC
330 */
332 select register */
334 /* enable probe monitoring mode and select data appearing on the P_A* bus. bit
335 * values for _SEL_HI_MASK and _SEL_LOW_MASK:
336 * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w,
337 * wtc empty r, post pci)
338 * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp,
339 * pci rpkt comp, txdma wr req, txdma wr ack,
340 * txdma wr rdy, txdma wr xfr done)
341 * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd,
342 * rd arb state, rd pci state)
343 * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state,
344 * wrpci state)
345 * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8]
346 * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24]
347 * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40]
348 * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56]
349 * the following are not available in Cassini:
350 * 0xc: rx probe[7:0] 0xd: tx probe[7:0]
351 * 0xe: hp probe[7:0] 0xf: mac probe[7:0]
352 */
355 driven on local bus P_A[15:0]
356 for debugging */
358 0x03 = mac[1:0]
359 0x0C = rx[1:0]
360 0x30 = tx[1:0]
361 0xC0 = hp[1:0] */
363 on P_A[15:8]. see above for
364 values. */
366 on P_A[7:0]. see above for
367 values. */
369 /* values mean the same thing as REG_INTR_MASK excep that it's for INTB.
370 DEFAULT: 0x1F */
372 register 2 for INTB */
373 #define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
374 /* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to
375 * all of the alternate (2-4) INTR registers while _1 corresponds to only
376 * _MASK_1 and _STATUS_1 registers.
377 * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers
378 */
379 #define INTR_RX_DONE_ALT 0x01
380 #define INTR_RX_COMP_FULL_ALT 0x02
381 #define INTR_RX_COMP_AF_ALT 0x04
382 #define INTR_RX_BUF_UNAVAIL_1 0x08
384 #define INTRN_MASK_RX_EN 0x80
385 #define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \
386 INTR_RX_COMP_FULL_ALT | \
387 INTR_RX_COMP_AF_ALT | \
388 INTR_RX_BUF_UNAVAIL_1 | \
389 INTR_RX_BUF_AE_1)
391 register 2 for INTB. default: 0x1F */
392 #define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
394 flags are set. enables desc ring. */
397 register 2 for INTB */
398 #define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
401 register alias 2 for INTB */
402 #define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
405 integrated macphy */
413 0 = normal */
416 GMII on SERDES pins for
417 monitoring. */
419 pins configed as outputs.
420 for power saving when using
421 internal phy. */
423 polarity from strapping
424 value.
425 1 = mac core led ctrl
426 polarity active low. */
429 /** transmit dma registers **/
430 #define MAX_TX_RINGS_SHIFT 2
431 #define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT)
432 #define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
434 /* TX configuration.
435 * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8
436 * DEFAULT: 0x3F000001
437 */
440 will stop after xfer of current
441 buffer has been completed. */
443 accessed w/ FIFO addr
444 and data registers.
445 TX DMA should be
446 disabled. */
448 ring 1. */
449 #define TX_CFG_DESC_RING0_SHIFT 2
450 #define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4)
451 #define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4)
453 TX FIFO becomes empty.
454 if 0, TX_ALL set
455 if descr queue empty. */
458 the end of every packet kicked
459 through Q1. */
461 the end of every packet kicked
462 through Q2. */
464 the end of every packet kicked
465 through Q3 */
467 the end of every packet kicked
468 through Q4 */
470 writeback */
472 connection
473 0b00: tx mac req,
474 tx mac retry req,
475 tx ack and tx tag.
476 0b01: txdma rd req,
477 txdma rd ack,
478 txdma rd rdy,
479 txdma rd type0
480 0b11: txdma wr req,
481 txdma wr ack,
482 txdma wr rdy,
483 txdma wr xfr done. */
484 #define TX_CFG_CTX_SEL_SHIFT 30
486 /* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
487 * used for diagnostics only.
488 */
491 pointer. temp hold reg.
492 diagnostics only. */
495 pointer */
497 /* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */
500 /* current state of all state machines in TX */
505 = 0x01 when TX disabled. */
508 state machine */
516 /* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented
517 * while the upper 23 bits are taken from the TX descriptor
518 */
522 /* 13 bit registers written by driver w/ descriptor value that follows
523 * last valid xmit descriptor. kick # and complete # values are used by
524 * the xmit dma engine to control tx descr fetching. if > 1 valid
525 * tx descr is available within the cache line being read, cassini will
526 * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro.
527 */
529 #define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4)
531 #define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4)
533 /* values of TX_COMPLETE_1-4 are written. each completion register
534 * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment.
535 * NOTE: completion reg values are only written back prior to TX_INTME and
536 * TX_ALL interrupts. at all other times, the most up-to-date index values
537 * should be obtained from the REG_TX_COMPLETE_# registers.
538 * here's the layout:
539 * offset from base addr completion # byte
540 * 0 TX_COMPLETE_1_MSB
541 * 1 TX_COMPLETE_1_LSB
542 * 2 TX_COMPLETE_2_MSB
543 * 3 TX_COMPLETE_2_LSB
544 * 4 TX_COMPLETE_3_MSB
545 * 5 TX_COMPLETE_3_LSB
546 * 6 TX_COMPLETE_4_MSB
547 * 7 TX_COMPLETE_4_LSB
548 */
549 #define TX_COMPWB_SIZE 8
551 base low */
553 base high */
554 #define TX_COMPWB_MSB_MASK 0x00000000000000FFULL
555 #define TX_COMPWB_MSB_SHIFT 0
556 #define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
557 #define TX_COMPWB_LSB_SHIFT 8
558 #define TX_COMPWB_NEXT(x) ((x) >> 16)
560 /* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
561 * be 2KB-aligned. */
564 #define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8)
565 #define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8)
567 /* 16-bit registers hold weights for the weighted round-robin of the
568 * four CBQ TX descr rings. weights correspond to # bytes xferred from
569 * host to TXFIFO in a round of WRR arbitration. can be set
570 * dynamically with new weights set upon completion of the current
571 * packet transfer from host memory to TXFIFO. a dummy write to any of
572 * these registers causes a queue1 pre-emption with all historical bw
573 * deficit data reset to 0 (useful when congestion requires a
574 * pre-emption/re-allocation of network bandwidth
575 */
581 /* diagnostics access to any TX FIFO location. every access is 65
582 * bits. _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit.
583 * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag
584 * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if
585 * TX FIFO data integrity is desired, TX DMA should be
586 * disabled. _DATA_HI_Tx should be the last access of the sequence.
587 */
595 /* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
596 * passed for the specified memory
597 */
600 controller state machine */
607 clears on completion. */
609 /** receive dma registers **/
610 #define MAX_RX_DESC_RINGS 2
611 #define MAX_RX_COMP_RINGS 4
613 /* receive DMA channel configuration. default: 0x80910
614 * free ring size = (1 << n)*32 -> [32 - 8k]
615 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
616 * DEFAULT: 0x80910
617 */
620 channel as soon as current
621 frame xfer has completed.
622 driver should disable MAC
623 for 200ms before disabling
624 RX */
626 free desc ring.
627 def: 0x8 = 8k */
628 #define RX_CFG_DESC_RING_SHIFT 1
630 ring. def: 0x8 = 32k */
631 #define RX_CFG_COMP_RING_SHIFT 5
633 batching. def: 0x0 =
634 enabled */
636 data byte of the packet
637 w/in 8 byte boundares.
638 this swivels the data
639 DMA'ed to header
640 buffers, jumbo buffers
641 when header split is not
642 requested and MTU sized
643 buffers. def: 0x2 */
644 #define RX_CFG_SWIVEL_SHIFT 10
646 /* cassini+ only */
648 RX free desc ring 2.
649 def: 0x8 = 8k */
650 #define RX_CFG_DESC_RING1_SHIFT 16
653 /* the page size register allows cassini chips to do the following with
654 * received data:
655 * [--------------------------------------------------------------] page
656 * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad]
657 * |--------------| = PAGE_SIZE_BUFFER_STRIDE
658 * page = PAGE_SIZE
659 * offset = PAGE_SIZE_MTU_OFF
660 * for the above example, MTU_BUFFER_COUNT = 4.
661 * NOTE: as is apparent, you need to ensure that the following holds:
662 * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE
663 * DEFAULT: 0x48002002 (8k pages)
664 */
667 by receive descriptors.
668 if jumbo buffers are
669 supported the page size
670 should not be < 8k.
671 0b00 = 2k, 0b01 = 4k
672 0b10 = 8k, 0b11 = 16k
673 DEFAULT: 8k */
674 #define RX_PAGE_SIZE_SHIFT 0
676 packs into a page.
677 DEFAULT: 4 */
678 #define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
680 each MTU buffer +
681 offset from each
682 other.
683 0b00 = 1k, 0b01 = 2k
684 0b10 = 4k, 0b11 = 8k
685 DEFAULT: 0x1 */
686 #define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
688 hw writes the MTU buffer
689 into.
690 0b00 = 0,
691 0b01 = 64 bytes
692 0b10 = 96, 0b11 = 128
693 DEFAULT: 0x1 */
694 #define RX_PAGE_SIZE_MTU_OFF_SHIFT 30
696 /* 11-bit counter points to next location in RX FIFO to be loaded/read.
697 * shadow write pointers enable retries in case of early receive aborts.
698 * DEFAULT: 0x0. generated on 64-bit boundaries.
699 */
703 pointer */
705 pointer */
707 pointer. (8-bit counter) */
709 /* current state of RX DMA state engines + other info
710 * DEFAULT: 0x0
711 */
714 0x0 = idle, 0x1 = load_bop
715 0x2 = load 1, 0x3 = load 2
716 0x4 = load 3, 0x5 = load 4
717 0x6 = last detect
718 0x7 = wait req
719 0x8 = wait req statuss 1st
720 0x9 = load st
721 0xa = bubble mac
722 0xb = error */
724 RX FIFO:
725 0x0 = idle, 0x1 = hp xfr
726 0x2 = wait hp ready
727 0x3 = wait flow code
728 0x4 = fifo xfer
729 0x5 = make status
730 0x6 = csum ready
731 0x7 = error */
733 w/ MAC:
734 0x0 = idle
735 0x1 = wait xoff ack
736 0x2 = wait xon
737 0x3 = wait xon ack */
739 states:
740 0x0 = idle data
741 0x1 = header begin
742 0x2 = xfer header
743 0x3 = xfer header ld
744 0x4 = mtu begin
745 0x5 = xfer mtu
746 0x6 = xfer mtu ld
747 0x7 = jumbo begin
748 0x8 = xfer jumbo
749 0x9 = xfer jumbo ld
750 0xa = reas begin
751 0xb = xfer reas
752 0xc = flush tag
753 0xd = xfer reas ld
754 0xe = error
755 0xf = bubble idle */
757 states:
758 0x0 = idle desc
759 0x1 = wait ack
760 0x9 = wait ack 2
761 0x2 = fetch desc 1
762 0xa = fetch desc 2
763 0x3 = load ptrs
764 0x4 = wait dma
765 0x5 = wait ack batch
766 0x6 = post batch
767 0x7 = xfr done */
769 interrupt queue */
771 of the interrupt queue */
773 /* flow control frames are emitted using two PAUSE thresholds:
774 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
775 * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes.
776 * PAUSE thresholds defined in terms of FIFO occupancy and may be translated
777 * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames
778 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
779 * value is is 0x6F.
780 * DEFAULT: 0x00078
781 */
783 #define RX_PAUSE_THRESH_QUANTUM 64
785 RX FIFO occupancy >
786 value*64B */
787 #define RX_PAUSE_THRESH_OFF_SHIFT 0
789 emitting XOFF PAUSE when RX
790 FIFO occupancy falls below
791 this value*64B. must be
792 < XOFF threshold. if =
793 RX_FIFO_SIZE< XON frames are
794 never emitted. */
795 #define RX_PAUSE_THRESH_ON_SHIFT 12
797 /* 13-bit register used to control RX desc fetching and intr generation. if 4+
798 * valid RX descriptors are available, Cassini will read 4 at a time.
799 * writing N means that all desc up to *but* excluding N are available. N must
800 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
801 * DEFAULT: 0 on reset
802 */
805 /* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
806 * lower 13 bits of the low register are hard-wired to 0.
807 */
809 base low */
811 base hi */
813 base low */
815 base hi */
816 /* 13-bit register indicate desc used by cassini for receive frames. used
817 * for diagnostic purposes.
818 * DEFAULT: 0 on reset
819 */
822 /* HEAD and TAIL are used to control RX desc posting and interrupt
823 * generation. hw moves the head register to pass ownership to sw. sw
824 * moves the tail register to pass ownership back to hw. to give all
825 * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no
826 * more entries are available, DMA will pause and an interrupt will be
827 * generated to indicate no more entries are available. sw can use
828 * this interrupt to reduce the # of times it must update the
829 * completion tail register.
830 * DEFAULT: 0 on reset
831 */
835 /* values used for receive interrupt blanking. loaded each time the ISR is read
836 * DEFAULT: 0x00000000
837 */
839 for ISR read */
841 this many sets of completion
842 writebacks (up to 2 packets)
843 occur since the last time
844 the ISR was read. 0 = no
845 packet blanking */
846 #define RX_BLANK_INTR_PKT_SHIFT 0
848 if that many clocks were
849 counted since last time the
850 ISR was read.
851 each count is 512 core
852 clocks (125MHz). 0 = no
853 time blanking */
854 #define RX_BLANK_INTR_TIME_SHIFT 12
856 /* values used for interrupt generation based on threshold values of how
857 * many free desc and completion entries are available for hw use.
858 * DEFAULT: 0x00000000
859 */
861 thresholds */
863 generated if # desc
864 avail for hw use <=
865 # */
866 #define RX_AE_THRESH_FREE_SHIFT 0
868 generated if # of
869 completion entries
870 avail for hw use <=
871 # */
872 #define RX_AE_THRESH_COMP_SHIFT 13
874 /* probabilities for random early drop (RED) thresholds on a FIFO threshold
875 * basis. probability should increase when the FIFO level increases. control
876 * packets are never dropped and not counted in stats. probability programmed
877 * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped.
878 * DEFAULT: 0x00000000
879 */
886 /* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO.
887 * RX control FIFO = # of packets in RX FIFO.
888 * DEFAULT: 0x0
889 */
897 high */
899 /* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST
900 * START/COMPLETE is writeable. START will clear when the BIST has completed
901 * checking all 17 RAMS.
902 * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0
903 */
924 summary pass bit
925 contains AND of BIST
926 results of all 16
927 RAMS */
929 BIST. self clears
930 on completion. */
932 /* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read
933 * from to retrieve packet control info.
934 * DEFAULT: 0
935 */
937 write ptr */
939 ptr */
941 /* receive interrupt blanking. loaded each time interrupt alias register is
942 * read.
943 * DEFAULT: 0x0
944 */
946 alias read */
948 completion writebacks
949 > # since last ISR
950 read. 0 = no
951 blanking. up to 2
952 packets per
953 completion wb. */
955 clocks > # since last
956 ISR read. each count
957 is 512 core clocks
958 (125MHz). 0 = no
959 blanking. */
961 /* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed
962 * via DATA_HI_T0 or DATA_HI_T1. TAG reads the tag bit. writing HI_T0
963 * will unset the tag bit while writing HI_T1 will set the tag bit. to reset
964 * to normal operation after diagnostics, write to address location 0x0.
965 * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should
966 * be the last write access of a write sequence.
967 * DEFAULT: undefined
968 */
975 /* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of
976 * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit
977 * accesses. HI is 7-bits with 6-bit flow id and 1 bit control
978 * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI
979 * should be last write access of the write sequence.
980 * DEFAULT: undefined
981 */
983 Batching FIFO addr */
985 low */
987 mid */
989 hi and flow id */
993 /* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO.
994 * DEFAULT: undefined
995 */
1000 T0 */
1002 T1 */
1004 /* 64-bit pointer to receive data buffer in host memory used for headers and
1005 * small packets. MSB in high register. loaded by DMA state machine and
1006 * increments as DMA writes receive data. only 50 LSB are incremented. top
1007 * 13 bits taken from RX descriptor.
1008 * DEFAULT: undefined
1009 */
1011 low */
1013 high */
1015 low */
1017 high */
1019 /* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds
1020 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of
1021 * one of the 64 byte locations in the Batching table. LOW holds 32 LSB.
1022 * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set
1023 * to 0 for PIO access. DATA_HIGH should be last write of write sequence.
1024 * layout:
1025 * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0]
1026 * DEFAULT: undefined
1027 */
1029 address */
1033 data low */
1035 data mid */
1037 data high */
1039 /* cassini+ only */
1040 /* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to
1041 * 0. same semantics as primary desc/complete rings.
1042 */
1044 2 base low */
1046 2 base high */
1048 2 base low. 4 total */
1050 2 base high. 4 total */
1051 #define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1052 #define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1055 reg */
1057 head reg. 4 total. */
1059 tail reg. 4 total. */
1060 #define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1061 #define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
1063 thresholds */
1064 #define RX_AE1_THRESH_FREE_MASK RX_AE_THRESH_FREE_MASK
1065 #define RX_AE1_THRESH_FREE_SHIFT RX_AE_THRESH_FREE_SHIFT
1067 /** header parser registers **/
1069 /* RX parser configuration register.
1070 * DEFAULT: 0x1651004
1071 */
1073 configuration reg */
1076 0 = 64. 0x3f = 63 */
1077 #define HP_CFG_NUM_CPU_SHIFT 2
1079 TCP seq # by one when
1080 stored in FDBM */
1082 needed to be considered
1083 for reassembly */
1084 #define HP_CFG_TCP_THRESH_SHIFT 9
1086 /* access to RX Instruction RAM. 5-bit register/counter holds addr
1087 * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI.
1088 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
1089 * of sequence.
1090 * DEFAULT: undefined
1091 */
1093 address */
1096 data low */
1097 #define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF
1098 #define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0
1099 #define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000
1100 #define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16
1101 #define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000
1102 #define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20
1103 #define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000
1104 #define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22
1106 data mid */
1107 #define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003
1108 #define HP_INSTR_RAM_MID_OUTARG_SHIFT 0
1109 #define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C
1110 #define HP_INSTR_RAM_MID_OUTOP_SHIFT 2
1111 #define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0
1112 #define HP_INSTR_RAM_MID_FNEXT_SHIFT 6
1113 #define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800
1114 #define HP_INSTR_RAM_MID_FOFF_SHIFT 11
1115 #define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000
1116 #define HP_INSTR_RAM_MID_SNEXT_SHIFT 18
1117 #define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000
1118 #define HP_INSTR_RAM_MID_SOFF_SHIFT 23
1119 #define HP_INSTR_RAM_MID_OP_MASK 0xC0000000
1120 #define HP_INSTR_RAM_MID_OP_SHIFT 30
1122 data high */
1123 #define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF
1124 #define HP_INSTR_RAM_HI_VAL_SHIFT 0
1125 #define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000
1126 #define HP_INSTR_RAM_HI_MASK_SHIFT 16
1128 /* PIO access into RX Header parser data RAM and flow database.
1129 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits.
1130 * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM.
1131 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
1132 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access
1133 * flow database.
1134 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
1135 * should be the last write access of the write sequence.
1136 * DEFAULT: undefined
1137 */
1139 RAM address */
1141 locations in header
1142 parser data ram to
1143 read/write */
1145 in the flow database */
1148 /* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
1149 * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64]
1150 * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0]
1151 * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64]
1152 * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0]
1153 * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]}
1154 * FLOW_DB(10) = bit 0 has value for flow valid
1155 * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0]
1156 */
1158 #define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4)
1160 /* diagnostics for RX Header Parser block.
1161 * ASUN: the header parser state machine register is used for diagnostics
1162 * purposes. however, the spec doesn't have any details on it.
1163 */
1169 number */
1181 start offset */
1185 reassembly */
1187 enable */
1189 check */
1191 equal to zero */
1193 chk */
1195 threshold */
1203 /* BIST for header parser(HP) and flow database memories (FDBM). set _START
1204 * to start BIST. controller clears _START on completion. _START can also
1205 * be cleared to force termination of BIST. a bit set indicates that that
1206 * memory passed its BIST.
1207 */
1216 bank 0 */
1218 bank 0 */
1220 bank 0 */
1222 bank 0 */
1224 bank 1 */
1226 bank 2 */
1228 bank 1 */
1230 bank 1 */
1232 RAM */
1237 /** MAC registers. **/
1238 /* reset bits are set using a PIO write and self-cleared after the command
1239 * execution has completed.
1240 */
1242 command (default: 0x0) */
1244 command (default: 0x0) */
1245 /* execute a pause flow control frame transmission
1246 DEFAULT: 0x0XXXX */
1249 to be sent on network
1250 in units of slot
1251 times */
1253 frame on network */
1255 /* bit set indicates that event occurred. auto-cleared when status register
1256 * is read and have corresponding mask bits in mask register. events will
1257 * trigger an interrupt if the corresponding mask bit is 0.
1258 * status register default: 0x00000000
1259 * mask register default = 0xFFFFFFFF on reset
1260 */
1263 transmision */
1265 transmission due to
1266 data starvation in the
1267 xmit data path */
1269 length passed to TX MAC
1270 by the DMA engine */
1272 collision counter */
1274 collision counter */
1276 collision counter */
1278 collision counter */
1280 timer */
1282 attempts counter */
1286 a frame */
1288 RX FIFO overflow */
1290 counter */
1292 error counter */
1294 counter */
1296 error counter */
1298 violation error */
1300 /* DEFAULT: 0xXXXX0000 on reset */
1303 reception of a
1304 pause control
1305 frame */
1307 transition from
1308 "not paused" to
1309 "paused" */
1311 transition from
1312 "paused" to "not
1313 paused" */
1315 operand that was
1316 received in the last
1317 pause flow control
1318 frame */
1320 /* layout identical to TX MAC[8:0] */
1322 /* layout identical to RX MAC[6:0] */
1324 /* layout identical to CTRL MAC[2:0] */
1327 /* to ensure proper operation, CFG_EN must be cleared to 0 and a delay
1328 * imposed before writes to other bits in the TX_MAC_CFG register or any of
1329 * the MAC parameters is performed. delay dependent upon time required to
1330 * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g.,
1331 * the delay for a 1518-byte frame on a 100Mbps network is 125us.
1332 * alternatively, just poll TX_CFG_EN until it reads back as 0.
1333 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and
1334 * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should
1335 * be 0x200 (slot time of 512 bytes)
1336 */
1339 force TXMAC state
1340 machine to remain in
1341 idle state or to
1342 transition to idle state
1343 on completion of an
1344 ongoing packet. */
1346 process. set to 1 when
1347 full duplex and 0 when
1348 half duplex */
1350 algorithm. set to 1 when
1351 full duplex and 0 when
1352 half duplex */
1354 Rx-to-TX IPG. after
1355 receiving a frame, TX
1356 MAC will reset its
1357 deferral process to
1358 carrier sense for the
1359 amount of time = IPG0 +
1360 IPG1 and commit to
1361 transmission for time
1362 specified in IPG2. when
1363 0 or when xmitting frames
1364 back-to-pack (Tx-to-Tx
1365 IPG), TX MAC ignores
1366 IPG0 and will only use
1367 IPG1 for deferral time.
1368 IPG2 still used. */
1370 give up on frame
1371 xmission. if backoff
1372 algorithm reaches the
1373 ATTEMPT_LIMIT, it will
1374 clear attempts counter
1375 and continue trying to
1376 send the frame as
1377 specified by
1378 GIVE_UP_LIM. when 0,
1379 TX MAC will execute
1380 standard CSMA/CD prot. */
1382 continue to try to xmit
1383 until successful. when
1384 0, TX MAC will continue
1385 to try xmitting until
1386 successful or backoff
1387 algorithm reaches
1388 ATTEMPT_LIMIT*16 */
1390 backoff algorithm. TX
1391 MAC will not back off
1392 after a xmission attempt
1393 that resulted in a
1394 collision. */
1396 deferral process is reset
1397 in response to carrier
1398 sense during the entire
1399 duration of IPG. TX MAC
1400 will only commit to frame
1401 xmission after frame
1402 xmission has actually
1403 begun. */
1405 CRC for all xmitted
1406 packets. when clear, CRC
1407 generation is dependent
1408 upon NO_CRC bit in the
1409 xmit control word from
1410 TX DMA */
1412 carrier extension
1413 feature. this allows for
1414 longer collision domains
1415 by extending the carrier
1416 and collision window
1417 from the end of FCS until
1418 the end of the slot time
1419 if necessary. Required
1420 for half-duplex at 1Gbps,
1421 clear otherwise. */
1423 /* when CRC is not stripped, reassembly packets will not contain the CRC.
1424 * these will be stripped by HRP because it reassembles layer 4 data, and the
1425 * CRC is layer 2. however, non-reassembly packets will still contain the CRC
1426 * when passed to the host. to ensure proper operation, need to wait 3.2ms
1427 * after clearing RX_CFG_EN before writing to any other RX MAC registers
1428 * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears
1429 * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same
1430 * restrictions as CFG_EN.
1431 */
1435 feature not supported */
1437 last 4 bytes of a
1438 received frame. */
1441 multicast frames (group
1442 bit in DA field set) */
1444 multicast addresses */
1446 address filtering regs
1447 to filter both unicast
1448 and multicast
1449 addresses */
1451 RX DMA by setting BAD
1452 bit but not Abort bit
1453 in the status. CRC,
1454 framing, and length errs
1455 will not increment
1456 error counters. frames
1457 which don't match dest
1458 addr will be passed up
1459 w/ BAD bit set. */
1461 packet bursts generated
1462 by carrier extension
1463 with packet bursting
1464 senders. only applies
1465 to half-duplex 1Gbps */
1467 /* DEFAULT: 0x0 */
1470 sending pause flow ctrl
1471 frames */
1473 pause flow ctrl frames */
1475 packets to RX DMA */
1477 /* to ensure proper operation, a global initialization sequence should be
1478 * performed when a loopback config is entered or exited. if programmed after
1479 * a hw or global sw reset, RX/TX MAC software reset and initialization
1480 * should be done to ensure stable clocking.
1481 * DEFAULT: 0x0
1482 */
1485 on MII xmit bus */
1487 path to GMII recv data
1488 path. phy mode register
1489 clock selection must be
1490 set to GMII mode and
1491 GMII_MODE should be set
1492 to 1. in loopback mode,
1493 REFCLK will drive the
1494 entire mac core. 0 for
1495 normal operation. */
1497 path during packet
1498 xmission. clear to 0
1499 in any full duplex mode,
1500 in any loopback mode,
1501 or in half-duplex SERDES
1502 or SLINK modes. set when
1503 in half-duplex when
1504 using external phy. */
1506 clocks and datapath */
1508 external tristate buffer
1509 on the MII receive
1510 bus. */
1515 recommended: 0x00 */
1517 recommended: 0x08 */
1519 recommended: 0x04 */
1521 recommended: 0x40 */
1523 recommended: 0x40 */
1525 /* FRAMESIZE_MAX holds both the max frame size as well as the max burst size.
1526 * recommended value: 0x2000.05EE
1527 */
1530 #define MAC_FRAMESIZE_MAX_BURST_SHIFT 16
1532 #define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0
1534 preamble bytes that the
1535 TX MAC will xmit at the
1536 beginning of each frame
1537 value should be 2 or
1538 greater. recommended
1539 value: 0x07 */
1541 of jam in units of media
1542 byte time. recommended
1543 value: 0x04 */
1545 of attempts TX MAC will
1546 make to xmit a frame
1547 before it resets its
1548 attempts counter. after
1549 the limit has been
1550 reached, TX MAC may or
1551 may not drop the frame
1552 dependent upon value
1553 in TX_MAC_CFG.
1554 recommended
1555 value: 0x10 */
1557 type field of a MAC
1558 ctrl frame. recommended
1559 value: 0x8808 */
1561 /* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
1562 * register contains comparison
1563 * 0 16 MSB of primary MAC addr [47:32] of DA field
1564 * 1 16 middle bits "" [31:16] of DA field
1565 * 2 16 LSB "" [15:0] of DA field
1566 * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field
1567 * 4*x 16 middle bits "" [31:16]
1568 * 5*x 16 LSB "" [15:0]
1569 * 42 16 MSB of MAC CTRL addr [47:32] of DA.
1570 * 43 16 middle bits "" [31:16]
1571 * 44 16 LSB "" [15:0]
1572 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
1573 * if there is a match, MAC will set the bit for alternative address
1574 * filter pass [15]
1576 * here is the map of registers given MAC address notation: a:b:c:d:e:f
1577 * ab cd ef
1578 * primary addr reg 2 reg 1 reg 0
1579 * alt addr 1 reg 5 reg 4 reg 3
1580 * alt addr x reg 5*x reg 4*x reg 3*x
1581 * ctrl addr reg 44 reg 43 reg 42
1582 */
1584 #define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4)
1586 [47:32] */
1588 [31:16] */
1590 [15:0] */
1592 mask reg. 8-bit reg
1593 contains nibble mask for
1594 reg 2 and 1. */
1596 reg */
1598 /* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
1599 * 16-bit registers contain bits of the hash table.
1600 * reg x -> [16*(15 - x) + 15 : 16*(15 - x)].
1601 * e.g., 15 -> [15:0], 0 -> [255:240]
1602 */
1604 #define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4)
1606 /* statistics registers. these registers generate an interrupt on
1607 * overflow. recommended initialization: 0x0000. most are 16-bits except
1608 * for PEAK_ATTEMPTS register which is 8 bits.
1609 */
1611 counter. */
1613 successful collision
1614 counter */
1616 counter */
1619 is the media byte
1620 clock/256 */
1627 error counter */
1629 /* misc registers */
1631 10-bit register used as a
1632 seed for the random number
1633 generator for the CSMA/CD
1634 backoff algorithm. only
1635 programmed after power-on
1636 reset and should be a
1637 random value which has a
1638 high likelihood of being
1639 unique for each MAC
1640 attached to a network
1641 segment (e.g., 10 LSB of
1642 MAC address) */
1644 /* ASUN: there's a PAUSE_TIMER (ro) described, but it's not in the address
1645 * map
1646 */
1648 /* 27-bit register has the current state for key state machines in the MAC */
1650 #define MAC_SM_RLM_MASK 0x07800000
1651 #define MAC_SM_RLM_SHIFT 23
1652 #define MAC_SM_RX_FC_MASK 0x00700000
1653 #define MAC_SM_RX_FC_SHIFT 20
1654 #define MAC_SM_TLM_MASK 0x000F0000
1655 #define MAC_SM_TLM_SHIFT 16
1656 #define MAC_SM_ENCAP_SM_MASK 0x0000F000
1657 #define MAC_SM_ENCAP_SM_SHIFT 12
1658 #define MAC_SM_TX_REQ_MASK 0x00000C00
1659 #define MAC_SM_TX_REQ_SHIFT 10
1660 #define MAC_SM_TX_FC_MASK 0x000003C0
1661 #define MAC_SM_TX_FC_SHIFT 6
1662 #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038
1663 #define MAC_SM_FIFO_WRITE_SEL_SHIFT 3
1664 #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
1665 #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
1667 /** MIF registers. the MIF can be programmed in either bit-bang or
1668 * frame mode.
1669 **/
1671 1 -> 0 will generate a
1672 rising edge. 0 -> 1 will
1673 generate a falling edge. */
1675 register generates data */
1677 enable. enable when
1678 xmitting data from MIF to
1679 transceiver. */
1681 /* 32-bit register serves as an instruction register when the MIF is
1682 * programmed in frame mode. load this register w/ a valid instruction
1683 * (as per IEEE 802.3u MII spec). poll this register to check for instruction
1684 * execution completion. during a read operation, this register will also
1685 * contain the 16-bit data returned by the tranceiver. unless specified
1686 * otherwise, fields are considered "don't care" when polling for
1687 * completion.
1688 */
1691 load w/ 01 when
1692 issuing an instr */
1695 write. 10 for a
1696 read */
1700 issuing an instr,
1701 this field should be
1702 loaded w/ the XCVR
1703 addr */
1704 #define MIF_FRAME_PHY_ADDR_SHIFT 23
1706 when issuing an instr,
1707 addr of register
1708 to be read/written */
1709 #define MIF_FRAME_REG_ADDR_SHIFT 18
1711 when issuing an instr,
1712 set this bit to 1 */
1714 when issuing an instr,
1715 set this bit to 0.
1716 when polling for
1717 completion, 1 means
1718 that instr execution
1719 has been completed */
1721 load with 16-bit data
1722 to be written in
1723 transceiver reg for a
1724 write. doesn't matter
1725 in a read. when
1726 polling for
1727 completion, field is
1728 "don't care" for write
1729 and 16-bit data
1730 returned by the
1731 transceiver for a
1732 read (if valid bit
1733 is set) */
1736 0 -> select MDIO_0 */
1738 mechanism. if set,
1739 BB_MODE should be 0 */
1741 0 -> frame mode */
1743 used by polling mode.
1744 only meaningful if POLL_EN
1745 is set to 1 */
1746 #define MIF_CFG_POLL_REG_SHIFT 3
1748 when MDIO_0 is idle,
1749 1 -> tranceiver is
1750 connected to MDIO_0.
1751 when MIF is communicating
1752 w/ MDIO_0 in bit-bang
1753 mode, this bit indicates
1754 the incoming bit stream
1755 during a read op */
1757 when MDIO_1 is idle,
1758 1 -> transceiver is
1759 connected to MDIO_1.
1760 when MIF is communicating
1761 w/ MDIO_1 in bit-bang
1762 mode, this bit indicates
1763 the incoming bit stream
1764 during a read op */
1766 be polled */
1767 #define MIF_CFG_POLL_PHY_SHIFT 10
1769 /* 16-bit register used to determine which bits in the POLL_STATUS portion of
1770 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0,
1771 * corresponding bit of the POLL_STATUS will generate a MIF interrupt when
1772 * set. DEFAULT: 0xFFFF
1773 */
1776 /* 32-bit register used when in poll mode. auto-cleared after being read */
1779 the "latest image"
1780 update of the XCVR
1781 reg being read */
1782 #define MIF_STATUS_POLL_DATA_SHIFT 16
1784 which bits in the
1785 POLL_DATA field have
1786 changed since the
1787 MIF_STATUS reg was
1788 last read */
1789 #define MIF_STATUS_POLL_STATUS_SHIFT 0
1791 /* 7-bit register has current state for all state machines in the MIF */
1794 state */
1796 state */
1798 /** PCS/Serialink. the following registers are equivalent to the standard
1799 * MII management registers except that they're directly mapped in
1800 * Cassini's register space.
1801 **/
1803 /* the auto-negotiation enable bit should be programmed the same at
1804 * the link partner as in the local device to enable auto-negotiation to
1805 * complete. when that bit is reprogrammed, auto-neg/manual config is
1806 * restarted automatically.
1807 * DEFAULT: 0x1040
1808 */
1811 writes */
1813 to MAC interface is
1814 activated regardless
1815 of activity */
1817 behaviour same for
1818 half and full dplx */
1820 restart auto-
1821 negotiation */
1823 on writes */
1825 on writes */
1827 through automatic
1828 link config before it
1829 can be used. when 0,
1830 link can be used
1831 w/out any link config
1832 phase */
1834 writes */
1836 when done */
1838 /* DEFAULT: 0x0108 */
1843 0 -> link down. 0 is
1844 latched so that 0 is
1845 kept until read. read
1846 2x to determine if the
1847 link has gone up again */
1849 auto-neg) */
1851 from received link code
1852 word. only valid after
1853 auto-neg completed */
1855 completed
1856 0 -> auto-negotiation not
1857 completed */
1859 indication that this is
1860 a 1000 Base-X PHY. writes
1861 to it are ignored */
1863 /* used during auto-negotiation.
1864 * DEFAULT: 0x00E0
1865 */
1867 reg */
1869 1000 Base-X */
1871 1000 Base-X */
1873 symmetric capability */
1875 asymmetric capability */
1877 to optionally indicate to
1878 link partner that chip is
1879 going off-line. bit12 will
1880 get set when signal
1881 detect == FAIL and will
1882 remain set until
1883 successful negotiation */
1887 /* contents updated as a result of autonegotiation. layout and definitions
1888 * identical to PCS_MII_ADVERT
1889 */
1891 ability reg */
1892 #define PCS_MII_LPA_FD PCS_MII_ADVERT_FD
1893 #define PCS_MII_LPA_HD PCS_MII_ADVERT_HD
1894 #define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE
1895 #define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE
1896 #define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK
1897 #define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK
1898 #define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE
1900 /* DEFAULT: 0x0 */
1903 0 when modifying
1904 PCS_MII_ADVERT */
1906 OK. bit is
1907 non-resettable */
1909 of optical signal to make
1910 signal detect okay when
1911 signal is low */
1913 measurements. a single
1914 code group is xmitted
1915 regularly.
1916 0x0 = normal operation
1917 0x1 = high freq test
1918 pattern, D21.5
1919 0x2 = low freq test
1920 pattern, K28.7
1921 0x3 = reserved */
1923 negotiation timer to
1924 a few cycles for test
1925 purposes */
1927 /* used for diagnostic purposes. bits 20-22 autoclear on read */
1929 and diagnostic reg */
1931 xmission of idle.
1932 otherwise, xmission of
1933 a packet */
1935 of idle. otherwise,
1936 reception of packet */
1938 sync */
1940 indicates reception of
1941 Config codes. cycling
1942 through 0-1 indicates
1943 reception of idles */
1944 #define PCS_SM_LINK_STATE_MASK 0x0001E000
1948 recept of Config
1949 codes */
1951 loss of sync */
1953 from OK to FAIL. bit29
1954 will also be set if
1955 this is set */
1957 receipt of breaklink
1958 C codes from partner.
1959 C codes w/ 0 content
1960 received triggering
1961 start/restart of
1962 autonegotiation.
1963 should be sent for
1964 no longer than 20ms */
1966 initialized. see serdes
1967 state reg */
1969 not received */
1971 achieved */
1973 w/ ack bit set */
1975 to send C codes
1976 instead of idle
1977 symbols or pkt data */
1979 /* this register indicates interrupt changes in specific PCS MII status bits.
1980 * PCS_INT may be masked at the ISR level. only a single bit is implemented
1981 * for link status change.
1982 */
1985 since last read */
1987 /* control which network interface is used. no more than one bit should
1988 * be set.
1989 * DEFAULT: none
1990 */
1993 MII/GMII is selected.
1994 selection between MII and
1995 GMII is controlled by
1996 XIF_CFG */
1998 10-bit interface */
2000 /* input to serdes chip or serialink block */
2003 serdes interface */
2005 detection. should be
2006 0x0 for normal
2007 operation */
2009 to REFCLK when set.
2010 when clear, receiver
2011 clock locks to incoming
2012 serial data */
2014 /* multiplex test outputs into the PROM address (PA_3 through PA_0) pins.
2015 * should be 0x0 for normal operations.
2016 * 0b000 normal operation, PROM address[3:0] selected
2017 * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read
2018 * 0b010 rxmac req, rx ack, rx tag, rx clk shared
2019 * 0b011 txmac req, tx ack, tx tag, tx retry req
2020 * 0b100 tx tp3, tx tp2, tx tp1, tx tp0
2021 * 0b101 R period RX, R period TX, R period HP, R period BIM
2022 * DEFAULT: 0x0
2023 */
2025 #define PCS_SOS_PROM_ADDR_MASK 0x0007
2027 /* used for diagnostics. this register indicates progress of the SERDES
2028 * boot up.
2029 * 0b00 undergoing reset
2030 * 0b01 waiting 500us while lockrefn is asserted
2031 * 0b10 waiting for comma detect
2032 * 0b11 receive data is synchronized
2033 * DEFAULT: 0x0
2034 */
2036 #define PCS_SERDES_STATE_MASK 0x03
2038 /* used for diagnostics. indicates number of packets transmitted or received.
2039 * counters rollover w/out generating an interrupt.
2040 * DEFAULT: 0x0
2041 */
2045 whether they
2046 encountered an error
2047 or not */
2049 /** LocalBus Devices. the following provides run-time access to the
2050 * Cassini's PROM
2051 ***/
2053 access */
2054 #define REG_EXPANSION_ROM_RUN_END 0x17FFFF
2057 device */
2058 #define REG_SECOND_LOCALBUS_END 0x1FFFFF
2060 /* entropy device */
2061 #define REG_ENTROPY_START REG_SECOND_LOCALBUS_START
2062 #define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00)
2063 #define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04)
2064 #define ENTROPY_STATUS_DRDY 0x01
2065 #define ENTROPY_STATUS_BUSY 0x02
2066 #define ENTROPY_STATUS_CIPHER 0x04
2067 #define ENTROPY_STATUS_BYPASS_MASK 0x18
2068 #define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05)
2069 #define ENTROPY_MODE_KEY_MASK 0x07
2070 #define ENTROPY_MODE_ENCRYPT 0x40
2071 #define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06)
2072 #define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07)
2073 #define ENTROPY_RESET_DES_IO 0x01
2074 #define ENTROPY_RESET_STC_MODE 0x02
2075 #define ENTROPY_RESET_KEY_CACHE 0x04
2076 #define ENTROPY_RESET_IV 0x08
2077 #define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08)
2078 #define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10)
2079 #define REG_ENTROPY_KEYN(x) (REG_ENTROPY_KEY0 + 4*(x))
2081 /* phys of interest w/ their special mii registers */
2082 #define PHY_LUCENT_B0 0x00437421
2083 #define LUCENT_MII_REG 0x1F
2085 #define PHY_NS_DP83065 0x20005c78
2086 #define DP83065_MII_MEM 0x16
2087 #define DP83065_MII_REGD 0x1D
2088 #define DP83065_MII_REGE 0x1E
2090 #define PHY_BROADCOM_5411 0x00206071
2091 #define PHY_BROADCOM_B0 0x00206050
2092 #define BROADCOM_MII_REG4 0x14
2093 #define BROADCOM_MII_REG5 0x15
2094 #define BROADCOM_MII_REG7 0x17
2095 #define BROADCOM_MII_REG8 0x18
2097 #define CAS_MII_ANNPTR 0x07
2098 #define CAS_MII_ANNPRR 0x08
2099 #define CAS_MII_1000_CTRL 0x09
2100 #define CAS_MII_1000_STATUS 0x0A
2101 #define CAS_MII_1000_EXTEND 0x0F
2104 /*
2105 * if autoneg is disabled, here's the table:
2106 * BMCR_SPEED100 = 100Mbps
2107 * BMCR_SPEED1000 = 1000Mbps
2108 * ~(BMCR_SPEED100 | BMCR_SPEED1000) = 10Mbps
2109 */
2112 #define CAS_ADVERTISE_1000HALF 0x0100
2113 #define CAS_ADVERTISE_1000FULL 0x0200
2114 #define CAS_ADVERTISE_PAUSE 0x0400
2115 #define CAS_ADVERTISE_ASYM_PAUSE 0x0800
2117 /* regular lpa register */
2118 #define CAS_LPA_PAUSE CAS_ADVERTISE_PAUSE
2119 #define CAS_LPA_ASYM_PAUSE CAS_ADVERTISE_ASYM_PAUSE
2121 /* 1000_STATUS register */
2122 #define CAS_LPA_1000HALF 0x0400
2123 #define CAS_LPA_1000FULL 0x0800
2125 #define CAS_EXTEND_1000XFULL 0x8000
2126 #define CAS_EXTEND_1000XHALF 0x4000
2127 #define CAS_EXTEND_1000TFULL 0x2000
2128 #define CAS_EXTEND_1000THALF 0x1000
2130 /* cassini header parser firmware */
2136 u8 op;
2139 /* output info */
2144 2 = if !match, 3 = always */
2146 u16 outmask;
2149 /* comparison */
2155 /* output opcodes */
2156 #define CL_REG 0
2157 #define LD_FID 1
2158 #define LD_SEQ 2
2159 #define LD_CTL 3
2160 #define LD_SAP 4
2161 #define LD_R1 5
2162 #define LD_L3 6
2163 #define LD_SUM 7
2164 #define LD_HDR 8
2165 #define IM_FID 9
2166 #define IM_SEQ 10
2167 #define IM_SAP 11
2168 #define IM_R1 12
2169 #define IM_CTL 13
2170 #define LD_LEN 14
2171 #define ST_FLG 15
2173 /* match setp #s for IP4TCP4 */
2174 #define S1_PCKT 0
2175 #define S1_VLAN 1
2176 #define S1_CFI 2
2177 #define S1_8023 3
2178 #define S1_LLC 4
2179 #define S1_LLCc 5
2180 #define S1_IPV4 6
2181 #define S1_IPV4c 7
2182 #define S1_IPV4F 8
2183 #define S1_TCP44 9
2184 #define S1_IPV6 10
2185 #define S1_IPV6L 11
2186 #define S1_IPV6c 12
2187 #define S1_TCP64 13
2188 #define S1_TCPSQ 14
2189 #define S1_TCPFG 15
2190 #define S1_TCPHL 16
2191 #define S1_TCPHc 17
2192 #define S1_CLNP 18
2193 #define S1_CLNP2 19
2194 #define S1_DROP 20
2195 #define S2_HTTP 21
2196 #define S1_ESP4 22
2197 #define S1_AH4 23
2198 #define S1_ESP6 24
2199 #define S1_AH6 25
2201 #define CAS_PROG_IP46TCP4_PREAMBLE \
2203 CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
2205 IM_CTL, 0x00a, 3, 0x0, 0xffff}, \
2207 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2209 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2211 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2213 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2215 LD_SAP, 0x100, 3, 0x0, 0xffff}, \
2217 LD_SUM, 0x00a, 1, 0x0, 0x0000}, \
2219 LD_LEN, 0x03e, 1, 0x0, 0xffff}, \
2223 LD_SUM, 0x015, 1, 0x0, 0x0000}, \
2225 IM_R1, 0x128, 1, 0x0, 0xffff}, \
2229 LD_LEN, 0x03f, 1, 0x0, 0xffff}
2231 #ifdef USE_HP_IP46TCP4
2233 CAS_PROG_IP46TCP4_PREAMBLE,
2250 };
2251 #ifdef HP_IP46TCP4_DEFAULT
2252 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4tab
2253 #endif
2254 #endif
2256 /*
2257 * Alternate table load which excludes HTTP server traffic from reassembly.
2258 * It is substantially similar to the basic table, with one extra state
2259 * and a few extra compares. */
2260 #ifdef USE_HP_IP46TCP4NOHTTP
2262 CAS_PROG_IP46TCP4_PREAMBLE,
2281 };
2282 #ifdef HP_IP46TCP4NOHTTP_DEFAULT
2283 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4nohttptab
2284 #endif
2285 #endif
2287 /* match step #s for IP4FRAG */
2288 #define S3_IPV6c 11
2289 #define S3_TCP64 12
2290 #define S3_TCPSQ 13
2291 #define S3_TCPFG 14
2292 #define S3_TCPHL 15
2293 #define S3_TCPHc 16
2294 #define S3_FRAG 17
2295 #define S3_FOFF 18
2296 #define S3_CLNP 19
2298 #ifdef USE_HP_IP4FRAG
2342 };
2343 #ifdef HP_IP4FRAG_DEFAULT
2344 #define CAS_HP_FIRMWARE cas_prog_ip4fragtab
2345 #endif
2346 #endif
2348 /*
2349 * Alternate table which does batching without reassembly
2350 */
2351 #ifdef USE_HP_IP46TCP4BATCH
2353 CAS_PROG_IP46TCP4_PREAMBLE,
2368 };
2369 #ifdef HP_IP46TCP4BATCH_DEFAULT
2370 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4batchtab
2371 #endif
2372 #endif
2374 /* Workaround for Cassini rev2 descriptor corruption problem.
2375 * Does batching without reassembly, and sets the SAP to a known
2376 * data pattern for all packets.
2377 */
2378 #ifdef USE_HP_WORKAROUND
2422 };
2423 #ifdef HP_WORKAROUND_DEFAULT
2424 #define CAS_HP_FIRMWARE cas_prog_workaroundtab
2425 #endif
2426 #endif
2428 #ifdef USE_HP_ENCRYPT
2434 #if 0
2435 //"CFI?", /* 02 FIND CFI and If FIND go to S1_DROP */
2436 //0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, CL_REG, 0x000, 0, 0x0, 0x00
2438 #endif
2463 #if 0
2464 //@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff,
2465 #endif
2492 #if 0
2493 //@@@0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 0x021, 1, 0x0, 0xffff,
2494 #endif
2498 #if 0
2499 //@@@0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1, 0x0, 0xffff,
2500 #endif
2504 };
2505 #ifdef HP_ENCRYPT_DEFAULT
2506 #define CAS_HP_FIRMWARE cas_prog_encryptiontab
2507 #endif
2508 #endif
2511 #ifdef HP_NULL_DEFAULT
2512 #define CAS_HP_FIRMWARE cas_prog_null
2513 #endif
2515 /* phy types */
2516 #define CAS_PHY_UNKNOWN 0x00
2517 #define CAS_PHY_SERDES 0x01
2518 #define CAS_PHY_MII_MDIO0 0x02
2519 #define CAS_PHY_MII_MDIO1 0x04
2520 #define CAS_PHY_MII(x) ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))
2522 /* _RING_INDEX is the index for the ring sizes to be used. _RING_SIZE
2523 * is the actual size. the default index for the various rings is
2524 * 8. NOTE: there a bunch of alignment constraints for the rings. to
2525 * deal with that, i just allocate rings to create the desired
2526 * alignment. here are the constraints:
2527 * RX DESC and COMP rings must be 8KB aligned
2528 * TX DESC must be 2KB aligned.
2529 * if you change the numbers, be cognizant of how the alignment will change
2530 * in INIT_BLOCK as well.
2531 */
2533 #define DESC_RING_I_TO_S(x) (32*(1 << (x)))
2534 #define COMP_RING_I_TO_S(x) (128*(1 << (x)))
2539 #if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0)
2540 #error TX_DESC_RING_INDEX must be between 0 and 8
2541 #endif
2543 #if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0)
2544 #error RX_DESC_RING_INDEX must be between 0 and 8
2545 #endif
2547 #if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0)
2548 #error RX_COMP_RING_INDEX must be between 0 and 8
2549 #endif
2552 #define N_TX_RINGS_MASK MAX_TX_RINGS_MASK
2556 /* number of flows that can go through re-assembly */
2557 #define N_RX_FLOWS 64
2559 #define TX_DESC_RING_SIZE DESC_RING_I_TO_S(TX_DESC_RING_INDEX)
2560 #define RX_DESC_RING_SIZE DESC_RING_I_TO_S(RX_DESC_RING_INDEX)
2561 #define RX_COMP_RING_SIZE COMP_RING_I_TO_S(RX_COMP_RING_INDEX)
2562 #define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX
2563 #define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX
2564 #define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX
2565 #define TX_DESC_RINGN_SIZE(x) TX_DESC_RING_SIZE
2566 #define RX_DESC_RINGN_SIZE(x) RX_DESC_RING_SIZE
2567 #define RX_COMP_RINGN_SIZE(x) RX_COMP_RING_SIZE
2569 /* convert values */
2570 #define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK))
2571 #define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT))
2572 #define CAS_TX_RINGN_BASE(y) ((TX_DESC_RINGN_INDEX(y) << \
2573 TX_CFG_DESC_RINGN_SHIFT(y)) & \
2574 TX_CFG_DESC_RINGN_MASK(y))
2576 /* min is 2k, but we can't do jumbo frames unless it's at least 8k */
2582 bytes. 0 - 9256 */
2583 #define TX_DESC_BUFLEN_SHIFT 0
2585 of bytes to be
2586 skipped before
2587 csum calc begins.
2588 value must be
2589 even */
2590 #define TX_DESC_CSUM_START_SHIFT 15
2592 byte offset w/in
2593 the pkt for the
2594 1st csum byte.
2595 must be > 8 */
2596 #define TX_DESC_CSUM_STUFF_SHIFT 21
2602 CRC will not be
2603 inserted into
2604 outgoing frame. */
2606 __le64 control;
2607 __le64 buffer;
2608 };
2610 /* descriptor ring for free buffers contains page-sized buffers. the index
2611 * value is not used by the hw in any way. it's just stored and returned in
2612 * the completion ring.
2613 */
2615 __le64 index;
2616 __le64 buffer;
2617 };
2619 /* received packets are put on the completion ring. */
2620 /* word 1 */
2621 #define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL
2622 #define RX_COMP1_DATA_SIZE_SHIFT 13
2623 #define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL
2624 #define RX_COMP1_DATA_OFF_SHIFT 27
2625 #define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL
2626 #define RX_COMP1_DATA_INDEX_SHIFT 41
2627 #define RX_COMP1_SKIP_MASK 0x0180000000000000ULL
2628 #define RX_COMP1_SKIP_SHIFT 55
2629 #define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL
2630 #define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL
2631 #define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL
2632 #define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL
2633 #define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL
2634 #define RX_COMP1_TYPE_MASK 0xC000000000000000ULL
2635 #define RX_COMP1_TYPE_SHIFT 62
2637 /* word 2 */
2638 #define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL
2639 #define RX_COMP2_NEXT_INDEX_SHIFT 21
2640 #define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL
2641 #define RX_COMP2_HDR_SIZE_SHIFT 35
2642 #define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL
2643 #define RX_COMP2_HDR_OFF_SHIFT 44
2644 #define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL
2645 #define RX_COMP2_HDR_INDEX_SHIFT 50
2647 /* word 3 */
2648 #define RX_COMP3_SMALL_PKT 0x0000000000000001ULL
2649 #define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL
2650 #define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL
2651 #define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL
2652 #define RX_COMP3_CSUM_START_SHIFT 12
2653 #define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL
2654 #define RX_COMP3_FLOWID_SHIFT 19
2655 #define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL
2656 #define RX_COMP3_OPCODE_SHIFT 25
2657 #define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL
2658 #define RX_COMP3_NO_ASSIST 0x0000000020000000ULL
2659 #define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL
2660 #define RX_COMP3_LOAD_BAL_SHIFT 35
2663 #define RX_COMP3_L3_HEAD_OFF_SHIFT 41
2665 #define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT 42
2666 #define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL
2667 #define RX_COMP3_SAP_SHIFT 48
2669 /* word 4 */
2670 #define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL
2671 #define RX_COMP4_TCP_CSUM_SHIFT 0
2672 #define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL
2673 #define RX_COMP4_PKT_LEN_SHIFT 16
2674 #define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL
2675 #define RX_COMP4_PERFECT_MATCH_SHIFT 30
2676 #define RX_COMP4_ZERO 0x0000080000000000ULL
2677 #define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL
2678 #define RX_COMP4_HASH_VAL_SHIFT 44
2679 #define RX_COMP4_HASH_PASS 0x1000000000000000ULL
2680 #define RX_COMP4_BAD 0x4000000000000000ULL
2681 #define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL
2683 /* we encode the following: ring/index/release. only 14 bits
2684 * are usable.
2685 * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and
2686 * MAX_RX_DESC_RINGS. */
2687 #define RX_INDEX_NUM_MASK 0x0000000000000FFFULL
2688 #define RX_INDEX_NUM_SHIFT 0
2689 #define RX_INDEX_RING_MASK 0x0000000000001000ULL
2690 #define RX_INDEX_RING_SHIFT 12
2691 #define RX_INDEX_RELEASE 0x0000000000002000ULL
2694 __le64 word1;
2695 __le64 word2;
2696 __le64 word3;
2697 __le64 word4;
2698 };
2706 link_up /* Link is up */
2707 };
2712 dma_addr_t dma_addr;
2717 /* some alignment constraints:
2718 * TX DESC, RX DESC, and RX COMP must each be 8K aligned.
2719 * TX COMPWB must be 8-byte aligned.
2720 * to accomplish this, here's what we do:
2721 *
2722 * INIT_BLOCK_RX_COMP = 64k (already aligned)
2723 * INIT_BLOCK_RX_DESC = 8k
2724 * INIT_BLOCK_TX = 8k
2725 * INIT_BLOCK_RX1_DESC = 8k
2726 * TX COMPWB
2727 */
2728 #define INIT_BLOCK_TX (TX_DESC_RING_SIZE)
2729 #define INIT_BLOCK_RX_DESC (RX_DESC_RING_SIZE)
2730 #define INIT_BLOCK_RX_COMP (RX_COMP_RING_SIZE)
2736 __le64 tx_compwb;
2737 };
2739 /* tiny buffers to deal with target abort issue. we allocate a bit
2740 * over so that we don't have target abort issues with these buffers
2741 * as well.
2742 */
2743 #define TX_TINY_BUF_LEN 0x100
2744 #define TX_TINY_BUF_BLOCK ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)
2749 };
2766 /* Set when chip is actually in operational state
2767 * (ie. not power managed) */
2777 /* we use sk_buffs for tx and pages for rx. the rx skbuffs
2778 * are there for flow re-assembly. */
2785 /* for small packets when copying would be quicker than
2786 mapping */
2790 u32 msg_enable;
2792 /* N_TX_RINGS must be >= N_RX_DESC_RINGS */
2796 u8 pci_revision;
2800 u32 phy_id;
2801 #define CAS_FLAG_1000MB_CAP 0x00000001
2802 #define CAS_FLAG_REG_PLUS 0x00000002
2803 #define CAS_FLAG_TARGET_ABORT 0x00000004
2804 #define CAS_FLAG_SATURN 0x00000008
2805 #define CAS_FLAG_RXD_POST_MASK 0x000000F0
2806 #define CAS_FLAG_RXD_POST_SHIFT 4
2807 #define CAS_FLAG_RXD_POST(x) ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \
2808 CAS_FLAG_RXD_POST_MASK)
2809 #define CAS_FLAG_ENTROPY_DEV 0x00000100
2810 #define CAS_FLAG_NO_HW_CSUM 0x00000200
2811 u32 cas_flags;
2822 /* page size allocation */
2827 u32 mac_rx_cfg;
2829 /* Autoneg & PHY control */
2836 #if 0
2837 atomic_t reset_task_pending;
2838 #else
2839 atomic_t reset_task_pending;
2840 atomic_t reset_task_pending_mtu;
2841 atomic_t reset_task_pending_spare;
2842 atomic_t reset_task_pending_all;
2843 #endif
2845 /* Link-down problem workaround */
2846 #define LINK_TRANSITION_UNKNOWN 0
2847 #define LINK_TRANSITION_ON_FAILURE 1
2848 #define LINK_TRANSITION_STILL_FAILED 2
2849 #define LINK_TRANSITION_LINK_UP 3
2850 #define LINK_TRANSITION_LINK_CONFIG 4
2851 #define LINK_TRANSITION_LINK_DOWN 5
2852 #define LINK_TRANSITION_REQUESTED_RESET 6
2857 /* Tuning */
2861 /* Diagnostic counters and state. */
2863 u64 pause_entered;
2864 u16 pause_last_time_recvd;
2869 #if defined(CONFIG_OF)
2871 #endif
2873 /* Firmware Info */
2874 u16 fw_load_addr;
2875 u32 fw_size;
2877 };
2879 #define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
2880 #define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
2881 #define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
2883 #define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
2884 (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
2886 #define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
2887 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
2888 (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
2890 #define CAS_ALIGN(addr, align) \
2891 (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))
2893 #define RX_FIFO_SIZE 16384
2894 #define EXPANSION_ROM_SIZE 65536
2896 #define CAS_MC_EXACT_MATCH_SIZE 15
2897 #define CAS_MC_HASH_SIZE 256
2898 #define CAS_MC_HASH_MAX (CAS_MC_EXACT_MATCH_SIZE + \
2899 CAS_MC_HASH_SIZE)
2901 #define TX_TARGET_ABORT_LEN 0x20
2902 #define RX_SWIVEL_OFF_VAL 0x2
2903 #define RX_AE_FREEN_VAL(x) (RX_DESC_RINGN_SIZE(x) >> 1)
2904 #define RX_AE_COMP_VAL (RX_COMP_RING_SIZE >> 1)
2905 #define RX_BLANK_INTR_PKT_VAL 0x05
2906 #define RX_BLANK_INTR_TIME_VAL 0x0F
2909 #define RX_SPARE_COUNT (RX_DESC_RING_SIZE >> 1)
2910 #define RX_SPARE_RECOVER_VAL (RX_SPARE_COUNT >> 2)