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pvrusb2: reduce stack usage pvr2_eeprom_analyze()
[linux/fpc-iii.git] / drivers / net / ethernet / sun / sungem.c
blobd6ad0fbd054e10bf34d48d2f522b0660781de02d
1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 *
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
12 *
13 */
14
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/fcntl.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/in.h>
24 #include <linux/sched.h>
25 #include <linux/string.h>
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/pci.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/mii.h>
34 #include <linux/ethtool.h>
35 #include <linux/crc32.h>
36 #include <linux/random.h>
37 #include <linux/workqueue.h>
38 #include <linux/if_vlan.h>
39 #include <linux/bitops.h>
40 #include <linux/mm.h>
41 #include <linux/gfp.h>
42
43 #include <asm/io.h>
44 #include <asm/byteorder.h>
45 #include <asm/uaccess.h>
46 #include <asm/irq.h>
47
48 #ifdef CONFIG_SPARC
49 #include <asm/idprom.h>
50 #include <asm/prom.h>
51 #endif
52
53 #ifdef CONFIG_PPC_PMAC
54 #include <asm/prom.h>
55 #include <asm/machdep.h>
56 #include <asm/pmac_feature.h>
57 #endif
58
59 #include <linux/sungem_phy.h>
60 #include "sungem.h"
61
62 /* Stripping FCS is causing problems, disabled for now */
63 #undef STRIP_FCS
64
65 #define DEFAULT_MSG (NETIF_MSG_DRV | \
66 NETIF_MSG_PROBE | \
67 NETIF_MSG_LINK)
68
69 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
70 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
71 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
72 SUPPORTED_Pause | SUPPORTED_Autoneg)
73
74 #define DRV_NAME "sungem"
75 #define DRV_VERSION "1.0"
76 #define DRV_AUTHOR "David S. Miller <davem@redhat.com>"
77
78 static char version[] =
79 DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";
80
81 MODULE_AUTHOR(DRV_AUTHOR);
82 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
83 MODULE_LICENSE("GPL");
84
85 #define GEM_MODULE_NAME "gem"
86
87 static const struct pci_device_id gem_pci_tbl[] = {
88 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
89 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
90
91 /* These models only differ from the original GEM in
92 * that their tx/rx fifos are of a different size and
93 * they only support 10/100 speeds. -DaveM
94 *
95 * Apple's GMAC does support gigabit on machines with
96 * the BCM54xx PHYs. -BenH
97 */
98 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
99 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
100 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
102 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
104 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
106 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
108 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
110 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112 {0, }
113 };
114
115 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
116
117 static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg)
118 {
119 u32 cmd;
120 int limit = 10000;
121
122 cmd = (1 << 30);
123 cmd |= (2 << 28);
124 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
125 cmd |= (reg << 18) & MIF_FRAME_REGAD;
126 cmd |= (MIF_FRAME_TAMSB);
127 writel(cmd, gp->regs + MIF_FRAME);
128
129 while (--limit) {
130 cmd = readl(gp->regs + MIF_FRAME);
131 if (cmd & MIF_FRAME_TALSB)
132 break;
133
134 udelay(10);
135 }
136
137 if (!limit)
138 cmd = 0xffff;
139
140 return cmd & MIF_FRAME_DATA;
141 }
142
143 static inline int _sungem_phy_read(struct net_device *dev, int mii_id, int reg)
144 {
145 struct gem *gp = netdev_priv(dev);
146 return __sungem_phy_read(gp, mii_id, reg);
147 }
148
149 static inline u16 sungem_phy_read(struct gem *gp, int reg)
150 {
151 return __sungem_phy_read(gp, gp->mii_phy_addr, reg);
152 }
153
154 static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
155 {
156 u32 cmd;
157 int limit = 10000;
158
159 cmd = (1 << 30);
160 cmd |= (1 << 28);
161 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
162 cmd |= (reg << 18) & MIF_FRAME_REGAD;
163 cmd |= (MIF_FRAME_TAMSB);
164 cmd |= (val & MIF_FRAME_DATA);
165 writel(cmd, gp->regs + MIF_FRAME);
166
167 while (limit--) {
168 cmd = readl(gp->regs + MIF_FRAME);
169 if (cmd & MIF_FRAME_TALSB)
170 break;
171
172 udelay(10);
173 }
174 }
175
176 static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val)
177 {
178 struct gem *gp = netdev_priv(dev);
179 __sungem_phy_write(gp, mii_id, reg, val & 0xffff);
180 }
181
182 static inline void sungem_phy_write(struct gem *gp, int reg, u16 val)
183 {
184 __sungem_phy_write(gp, gp->mii_phy_addr, reg, val);
185 }
186
187 static inline void gem_enable_ints(struct gem *gp)
188 {
189 /* Enable all interrupts but TXDONE */
190 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
191 }
192
193 static inline void gem_disable_ints(struct gem *gp)
194 {
195 /* Disable all interrupts, including TXDONE */
196 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
197 (void)readl(gp->regs + GREG_IMASK); /* write posting */
198 }
199
200 static void gem_get_cell(struct gem *gp)
201 {
202 BUG_ON(gp->cell_enabled < 0);
203 gp->cell_enabled++;
204 #ifdef CONFIG_PPC_PMAC
205 if (gp->cell_enabled == 1) {
206 mb();
207 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
208 udelay(10);
209 }
210 #endif /* CONFIG_PPC_PMAC */
211 }
212
213 /* Turn off the chip's clock */
214 static void gem_put_cell(struct gem *gp)
215 {
216 BUG_ON(gp->cell_enabled <= 0);
217 gp->cell_enabled--;
218 #ifdef CONFIG_PPC_PMAC
219 if (gp->cell_enabled == 0) {
220 mb();
221 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
222 udelay(10);
223 }
224 #endif /* CONFIG_PPC_PMAC */
225 }
226
227 static inline void gem_netif_stop(struct gem *gp)
228 {
229 netif_trans_update(gp->dev); /* prevent tx timeout */
230 napi_disable(&gp->napi);
231 netif_tx_disable(gp->dev);
232 }
233
234 static inline void gem_netif_start(struct gem *gp)
235 {
236 /* NOTE: unconditional netif_wake_queue is only
237 * appropriate so long as all callers are assured to
238 * have free tx slots.
239 */
240 netif_wake_queue(gp->dev);
241 napi_enable(&gp->napi);
242 }
243
244 static void gem_schedule_reset(struct gem *gp)
245 {
246 gp->reset_task_pending = 1;
247 schedule_work(&gp->reset_task);
248 }
249
250 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
251 {
252 if (netif_msg_intr(gp))
253 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
254 }
255
256 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
257 {
258 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
259 u32 pcs_miistat;
260
261 if (netif_msg_intr(gp))
262 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
263 gp->dev->name, pcs_istat);
264
265 if (!(pcs_istat & PCS_ISTAT_LSC)) {
266 netdev_err(dev, "PCS irq but no link status change???\n");
267 return 0;
268 }
269
270 /* The link status bit latches on zero, so you must
271 * read it twice in such a case to see a transition
272 * to the link being up.
273 */
274 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
275 if (!(pcs_miistat & PCS_MIISTAT_LS))
276 pcs_miistat |=
277 (readl(gp->regs + PCS_MIISTAT) &
278 PCS_MIISTAT_LS);
279
280 if (pcs_miistat & PCS_MIISTAT_ANC) {
281 /* The remote-fault indication is only valid
282 * when autoneg has completed.
283 */
284 if (pcs_miistat & PCS_MIISTAT_RF)
285 netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
286 else
287 netdev_info(dev, "PCS AutoNEG complete\n");
288 }
289
290 if (pcs_miistat & PCS_MIISTAT_LS) {
291 netdev_info(dev, "PCS link is now up\n");
292 netif_carrier_on(gp->dev);
293 } else {
294 netdev_info(dev, "PCS link is now down\n");
295 netif_carrier_off(gp->dev);
296 /* If this happens and the link timer is not running,
297 * reset so we re-negotiate.
298 */
299 if (!timer_pending(&gp->link_timer))
300 return 1;
301 }
302
303 return 0;
304 }
305
306 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
307 {
308 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
309
310 if (netif_msg_intr(gp))
311 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
312 gp->dev->name, txmac_stat);
313
314 /* Defer timer expiration is quite normal,
315 * don't even log the event.
316 */
317 if ((txmac_stat & MAC_TXSTAT_DTE) &&
318 !(txmac_stat & ~MAC_TXSTAT_DTE))
319 return 0;
320
321 if (txmac_stat & MAC_TXSTAT_URUN) {
322 netdev_err(dev, "TX MAC xmit underrun\n");
323 dev->stats.tx_fifo_errors++;
324 }
325
326 if (txmac_stat & MAC_TXSTAT_MPE) {
327 netdev_err(dev, "TX MAC max packet size error\n");
328 dev->stats.tx_errors++;
329 }
330
331 /* The rest are all cases of one of the 16-bit TX
332 * counters expiring.
333 */
334 if (txmac_stat & MAC_TXSTAT_NCE)
335 dev->stats.collisions += 0x10000;
336
337 if (txmac_stat & MAC_TXSTAT_ECE) {
338 dev->stats.tx_aborted_errors += 0x10000;
339 dev->stats.collisions += 0x10000;
340 }
341
342 if (txmac_stat & MAC_TXSTAT_LCE) {
343 dev->stats.tx_aborted_errors += 0x10000;
344 dev->stats.collisions += 0x10000;
345 }
346
347 /* We do not keep track of MAC_TXSTAT_FCE and
348 * MAC_TXSTAT_PCE events.
349 */
350 return 0;
351 }
352
353 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
354 * so we do the following.
355 *
356 * If any part of the reset goes wrong, we return 1 and that causes the
357 * whole chip to be reset.
358 */
359 static int gem_rxmac_reset(struct gem *gp)
360 {
361 struct net_device *dev = gp->dev;
362 int limit, i;
363 u64 desc_dma;
364 u32 val;
365
366 /* First, reset & disable MAC RX. */
367 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
368 for (limit = 0; limit < 5000; limit++) {
369 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
370 break;
371 udelay(10);
372 }
373 if (limit == 5000) {
374 netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
375 return 1;
376 }
377
378 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
379 gp->regs + MAC_RXCFG);
380 for (limit = 0; limit < 5000; limit++) {
381 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
382 break;
383 udelay(10);
384 }
385 if (limit == 5000) {
386 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
387 return 1;
388 }
389
390 /* Second, disable RX DMA. */
391 writel(0, gp->regs + RXDMA_CFG);
392 for (limit = 0; limit < 5000; limit++) {
393 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
394 break;
395 udelay(10);
396 }
397 if (limit == 5000) {
398 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
399 return 1;
400 }
401
402 mdelay(5);
403
404 /* Execute RX reset command. */
405 writel(gp->swrst_base | GREG_SWRST_RXRST,
406 gp->regs + GREG_SWRST);
407 for (limit = 0; limit < 5000; limit++) {
408 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
409 break;
410 udelay(10);
411 }
412 if (limit == 5000) {
413 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
414 return 1;
415 }
416
417 /* Refresh the RX ring. */
418 for (i = 0; i < RX_RING_SIZE; i++) {
419 struct gem_rxd *rxd = &gp->init_block->rxd[i];
420
421 if (gp->rx_skbs[i] == NULL) {
422 netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
423 return 1;
424 }
425
426 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
427 }
428 gp->rx_new = gp->rx_old = 0;
429
430 /* Now we must reprogram the rest of RX unit. */
431 desc_dma = (u64) gp->gblock_dvma;
432 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
433 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
434 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
435 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
436 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
437 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
438 writel(val, gp->regs + RXDMA_CFG);
439 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
440 writel(((5 & RXDMA_BLANK_IPKTS) |
441 ((8 << 12) & RXDMA_BLANK_ITIME)),
442 gp->regs + RXDMA_BLANK);
443 else
444 writel(((5 & RXDMA_BLANK_IPKTS) |
445 ((4 << 12) & RXDMA_BLANK_ITIME)),
446 gp->regs + RXDMA_BLANK);
447 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
448 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
449 writel(val, gp->regs + RXDMA_PTHRESH);
450 val = readl(gp->regs + RXDMA_CFG);
451 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
452 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
453 val = readl(gp->regs + MAC_RXCFG);
454 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
455
456 return 0;
457 }
458
459 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
460 {
461 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
462 int ret = 0;
463
464 if (netif_msg_intr(gp))
465 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
466 gp->dev->name, rxmac_stat);
467
468 if (rxmac_stat & MAC_RXSTAT_OFLW) {
469 u32 smac = readl(gp->regs + MAC_SMACHINE);
470
471 netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
472 dev->stats.rx_over_errors++;
473 dev->stats.rx_fifo_errors++;
474
475 ret = gem_rxmac_reset(gp);
476 }
477
478 if (rxmac_stat & MAC_RXSTAT_ACE)
479 dev->stats.rx_frame_errors += 0x10000;
480
481 if (rxmac_stat & MAC_RXSTAT_CCE)
482 dev->stats.rx_crc_errors += 0x10000;
483
484 if (rxmac_stat & MAC_RXSTAT_LCE)
485 dev->stats.rx_length_errors += 0x10000;
486
487 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
488 * events.
489 */
490 return ret;
491 }
492
493 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
494 {
495 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
496
497 if (netif_msg_intr(gp))
498 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
499 gp->dev->name, mac_cstat);
500
501 /* This interrupt is just for pause frame and pause
502 * tracking. It is useful for diagnostics and debug
503 * but probably by default we will mask these events.
504 */
505 if (mac_cstat & MAC_CSTAT_PS)
506 gp->pause_entered++;
507
508 if (mac_cstat & MAC_CSTAT_PRCV)
509 gp->pause_last_time_recvd = (mac_cstat >> 16);
510
511 return 0;
512 }
513
514 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
515 {
516 u32 mif_status = readl(gp->regs + MIF_STATUS);
517 u32 reg_val, changed_bits;
518
519 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
520 changed_bits = (mif_status & MIF_STATUS_STAT);
521
522 gem_handle_mif_event(gp, reg_val, changed_bits);
523
524 return 0;
525 }
526
527 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
528 {
529 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
530
531 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
532 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
533 netdev_err(dev, "PCI error [%04x]", pci_estat);
534
535 if (pci_estat & GREG_PCIESTAT_BADACK)
536 pr_cont(" <No ACK64# during ABS64 cycle>");
537 if (pci_estat & GREG_PCIESTAT_DTRTO)
538 pr_cont(" <Delayed transaction timeout>");
539 if (pci_estat & GREG_PCIESTAT_OTHER)
540 pr_cont(" <other>");
541 pr_cont("\n");
542 } else {
543 pci_estat |= GREG_PCIESTAT_OTHER;
544 netdev_err(dev, "PCI error\n");
545 }
546
547 if (pci_estat & GREG_PCIESTAT_OTHER) {
548 u16 pci_cfg_stat;
549
550 /* Interrogate PCI config space for the
551 * true cause.
552 */
553 pci_read_config_word(gp->pdev, PCI_STATUS,
554 &pci_cfg_stat);
555 netdev_err(dev, "Read PCI cfg space status [%04x]\n",
556 pci_cfg_stat);
557 if (pci_cfg_stat & PCI_STATUS_PARITY)
558 netdev_err(dev, "PCI parity error detected\n");
559 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
560 netdev_err(dev, "PCI target abort\n");
561 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
562 netdev_err(dev, "PCI master acks target abort\n");
563 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
564 netdev_err(dev, "PCI master abort\n");
565 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
566 netdev_err(dev, "PCI system error SERR#\n");
567 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
568 netdev_err(dev, "PCI parity error\n");
569
570 /* Write the error bits back to clear them. */
571 pci_cfg_stat &= (PCI_STATUS_PARITY |
572 PCI_STATUS_SIG_TARGET_ABORT |
573 PCI_STATUS_REC_TARGET_ABORT |
574 PCI_STATUS_REC_MASTER_ABORT |
575 PCI_STATUS_SIG_SYSTEM_ERROR |
576 PCI_STATUS_DETECTED_PARITY);
577 pci_write_config_word(gp->pdev,
578 PCI_STATUS, pci_cfg_stat);
579 }
580
581 /* For all PCI errors, we should reset the chip. */
582 return 1;
583 }
584
585 /* All non-normal interrupt conditions get serviced here.
586 * Returns non-zero if we should just exit the interrupt
587 * handler right now (ie. if we reset the card which invalidates
588 * all of the other original irq status bits).
589 */
590 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
591 {
592 if (gem_status & GREG_STAT_RXNOBUF) {
593 /* Frame arrived, no free RX buffers available. */
594 if (netif_msg_rx_err(gp))
595 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
596 gp->dev->name);
597 dev->stats.rx_dropped++;
598 }
599
600 if (gem_status & GREG_STAT_RXTAGERR) {
601 /* corrupt RX tag framing */
602 if (netif_msg_rx_err(gp))
603 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
604 gp->dev->name);
605 dev->stats.rx_errors++;
606
607 return 1;
608 }
609
610 if (gem_status & GREG_STAT_PCS) {
611 if (gem_pcs_interrupt(dev, gp, gem_status))
612 return 1;
613 }
614
615 if (gem_status & GREG_STAT_TXMAC) {
616 if (gem_txmac_interrupt(dev, gp, gem_status))
617 return 1;
618 }
619
620 if (gem_status & GREG_STAT_RXMAC) {
621 if (gem_rxmac_interrupt(dev, gp, gem_status))
622 return 1;
623 }
624
625 if (gem_status & GREG_STAT_MAC) {
626 if (gem_mac_interrupt(dev, gp, gem_status))
627 return 1;
628 }
629
630 if (gem_status & GREG_STAT_MIF) {
631 if (gem_mif_interrupt(dev, gp, gem_status))
632 return 1;
633 }
634
635 if (gem_status & GREG_STAT_PCIERR) {
636 if (gem_pci_interrupt(dev, gp, gem_status))
637 return 1;
638 }
639
640 return 0;
641 }
642
643 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
644 {
645 int entry, limit;
646
647 entry = gp->tx_old;
648 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
649 while (entry != limit) {
650 struct sk_buff *skb;
651 struct gem_txd *txd;
652 dma_addr_t dma_addr;
653 u32 dma_len;
654 int frag;
655
656 if (netif_msg_tx_done(gp))
657 printk(KERN_DEBUG "%s: tx done, slot %d\n",
658 gp->dev->name, entry);
659 skb = gp->tx_skbs[entry];
660 if (skb_shinfo(skb)->nr_frags) {
661 int last = entry + skb_shinfo(skb)->nr_frags;
662 int walk = entry;
663 int incomplete = 0;
664
665 last &= (TX_RING_SIZE - 1);
666 for (;;) {
667 walk = NEXT_TX(walk);
668 if (walk == limit)
669 incomplete = 1;
670 if (walk == last)
671 break;
672 }
673 if (incomplete)
674 break;
675 }
676 gp->tx_skbs[entry] = NULL;
677 dev->stats.tx_bytes += skb->len;
678
679 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
680 txd = &gp->init_block->txd[entry];
681
682 dma_addr = le64_to_cpu(txd->buffer);
683 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
684
685 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
686 entry = NEXT_TX(entry);
687 }
688
689 dev->stats.tx_packets++;
690 dev_consume_skb_any(skb);
691 }
692 gp->tx_old = entry;
693
694 /* Need to make the tx_old update visible to gem_start_xmit()
695 * before checking for netif_queue_stopped(). Without the
696 * memory barrier, there is a small possibility that gem_start_xmit()
697 * will miss it and cause the queue to be stopped forever.
698 */
699 smp_mb();
700
701 if (unlikely(netif_queue_stopped(dev) &&
702 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {
703 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
704
705 __netif_tx_lock(txq, smp_processor_id());
706 if (netif_queue_stopped(dev) &&
707 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
708 netif_wake_queue(dev);
709 __netif_tx_unlock(txq);
710 }
711 }
712
713 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
714 {
715 int cluster_start, curr, count, kick;
716
717 cluster_start = curr = (gp->rx_new & ~(4 - 1));
718 count = 0;
719 kick = -1;
720 dma_wmb();
721 while (curr != limit) {
722 curr = NEXT_RX(curr);
723 if (++count == 4) {
724 struct gem_rxd *rxd =
725 &gp->init_block->rxd[cluster_start];
726 for (;;) {
727 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
728 rxd++;
729 cluster_start = NEXT_RX(cluster_start);
730 if (cluster_start == curr)
731 break;
732 }
733 kick = curr;
734 count = 0;
735 }
736 }
737 if (kick >= 0) {
738 mb();
739 writel(kick, gp->regs + RXDMA_KICK);
740 }
741 }
742
743 #define ALIGNED_RX_SKB_ADDR(addr) \
744 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
745 static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,
746 gfp_t gfp_flags)
747 {
748 struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
749
750 if (likely(skb)) {
751 unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);
752 skb_reserve(skb, offset);
753 }
754 return skb;
755 }
756
757 static int gem_rx(struct gem *gp, int work_to_do)
758 {
759 struct net_device *dev = gp->dev;
760 int entry, drops, work_done = 0;
761 u32 done;
762 __sum16 csum;
763
764 if (netif_msg_rx_status(gp))
765 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
766 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
767
768 entry = gp->rx_new;
769 drops = 0;
770 done = readl(gp->regs + RXDMA_DONE);
771 for (;;) {
772 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
773 struct sk_buff *skb;
774 u64 status = le64_to_cpu(rxd->status_word);
775 dma_addr_t dma_addr;
776 int len;
777
778 if ((status & RXDCTRL_OWN) != 0)
779 break;
780
781 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
782 break;
783
784 /* When writing back RX descriptor, GEM writes status
785 * then buffer address, possibly in separate transactions.
786 * If we don't wait for the chip to write both, we could
787 * post a new buffer to this descriptor then have GEM spam
788 * on the buffer address. We sync on the RX completion
789 * register to prevent this from happening.
790 */
791 if (entry == done) {
792 done = readl(gp->regs + RXDMA_DONE);
793 if (entry == done)
794 break;
795 }
796
797 /* We can now account for the work we're about to do */
798 work_done++;
799
800 skb = gp->rx_skbs[entry];
801
802 len = (status & RXDCTRL_BUFSZ) >> 16;
803 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
804 dev->stats.rx_errors++;
805 if (len < ETH_ZLEN)
806 dev->stats.rx_length_errors++;
807 if (len & RXDCTRL_BAD)
808 dev->stats.rx_crc_errors++;
809
810 /* We'll just return it to GEM. */
811 drop_it:
812 dev->stats.rx_dropped++;
813 goto next;
814 }
815
816 dma_addr = le64_to_cpu(rxd->buffer);
817 if (len > RX_COPY_THRESHOLD) {
818 struct sk_buff *new_skb;
819
820 new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
821 if (new_skb == NULL) {
822 drops++;
823 goto drop_it;
824 }
825 pci_unmap_page(gp->pdev, dma_addr,
826 RX_BUF_ALLOC_SIZE(gp),
827 PCI_DMA_FROMDEVICE);
828 gp->rx_skbs[entry] = new_skb;
829 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
830 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
831 virt_to_page(new_skb->data),
832 offset_in_page(new_skb->data),
833 RX_BUF_ALLOC_SIZE(gp),
834 PCI_DMA_FROMDEVICE));
835 skb_reserve(new_skb, RX_OFFSET);
836
837 /* Trim the original skb for the netif. */
838 skb_trim(skb, len);
839 } else {
840 struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
841
842 if (copy_skb == NULL) {
843 drops++;
844 goto drop_it;
845 }
846
847 skb_reserve(copy_skb, 2);
848 skb_put(copy_skb, len);
849 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
850 skb_copy_from_linear_data(skb, copy_skb->data, len);
851 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
852
853 /* We'll reuse the original ring buffer. */
854 skb = copy_skb;
855 }
856
857 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
858 skb->csum = csum_unfold(csum);
859 skb->ip_summed = CHECKSUM_COMPLETE;
860 skb->protocol = eth_type_trans(skb, gp->dev);
861
862 napi_gro_receive(&gp->napi, skb);
863
864 dev->stats.rx_packets++;
865 dev->stats.rx_bytes += len;
866
867 next:
868 entry = NEXT_RX(entry);
869 }
870
871 gem_post_rxds(gp, entry);
872
873 gp->rx_new = entry;
874
875 if (drops)
876 netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
877
878 return work_done;
879 }
880
881 static int gem_poll(struct napi_struct *napi, int budget)
882 {
883 struct gem *gp = container_of(napi, struct gem, napi);
884 struct net_device *dev = gp->dev;
885 int work_done;
886
887 work_done = 0;
888 do {
889 /* Handle anomalies */
890 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {
891 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
892 int reset;
893
894 /* We run the abnormal interrupt handling code with
895 * the Tx lock. It only resets the Rx portion of the
896 * chip, but we need to guard it against DMA being
897 * restarted by the link poll timer
898 */
899 __netif_tx_lock(txq, smp_processor_id());
900 reset = gem_abnormal_irq(dev, gp, gp->status);
901 __netif_tx_unlock(txq);
902 if (reset) {
903 gem_schedule_reset(gp);
904 napi_complete(napi);
905 return work_done;
906 }
907 }
908
909 /* Run TX completion thread */
910 gem_tx(dev, gp, gp->status);
911
912 /* Run RX thread. We don't use any locking here,
913 * code willing to do bad things - like cleaning the
914 * rx ring - must call napi_disable(), which
915 * schedule_timeout()'s if polling is already disabled.
916 */
917 work_done += gem_rx(gp, budget - work_done);
918
919 if (work_done >= budget)
920 return work_done;
921
922 gp->status = readl(gp->regs + GREG_STAT);
923 } while (gp->status & GREG_STAT_NAPI);
924
925 napi_complete(napi);
926 gem_enable_ints(gp);
927
928 return work_done;
929 }
930
931 static irqreturn_t gem_interrupt(int irq, void *dev_id)
932 {
933 struct net_device *dev = dev_id;
934 struct gem *gp = netdev_priv(dev);
935
936 if (napi_schedule_prep(&gp->napi)) {
937 u32 gem_status = readl(gp->regs + GREG_STAT);
938
939 if (unlikely(gem_status == 0)) {
940 napi_enable(&gp->napi);
941 return IRQ_NONE;
942 }
943 if (netif_msg_intr(gp))
944 printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",
945 gp->dev->name, gem_status);
946
947 gp->status = gem_status;
948 gem_disable_ints(gp);
949 __napi_schedule(&gp->napi);
950 }
951
952 /* If polling was disabled at the time we received that
953 * interrupt, we may return IRQ_HANDLED here while we
954 * should return IRQ_NONE. No big deal...
955 */
956 return IRQ_HANDLED;
957 }
958
959 #ifdef CONFIG_NET_POLL_CONTROLLER
960 static void gem_poll_controller(struct net_device *dev)
961 {
962 struct gem *gp = netdev_priv(dev);
963
964 disable_irq(gp->pdev->irq);
965 gem_interrupt(gp->pdev->irq, dev);
966 enable_irq(gp->pdev->irq);
967 }
968 #endif
969
970 static void gem_tx_timeout(struct net_device *dev)
971 {
972 struct gem *gp = netdev_priv(dev);
973
974 netdev_err(dev, "transmit timed out, resetting\n");
975
976 netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
977 readl(gp->regs + TXDMA_CFG),
978 readl(gp->regs + MAC_TXSTAT),
979 readl(gp->regs + MAC_TXCFG));
980 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
981 readl(gp->regs + RXDMA_CFG),
982 readl(gp->regs + MAC_RXSTAT),
983 readl(gp->regs + MAC_RXCFG));
984
985 gem_schedule_reset(gp);
986 }
987
988 static __inline__ int gem_intme(int entry)
989 {
990 /* Algorithm: IRQ every 1/2 of descriptors. */
991 if (!(entry & ((TX_RING_SIZE>>1)-1)))
992 return 1;
993
994 return 0;
995 }
996
997 static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
998 struct net_device *dev)
999 {
1000 struct gem *gp = netdev_priv(dev);
1001 int entry;
1002 u64 ctrl;
1003
1004 ctrl = 0;
1005 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1006 const u64 csum_start_off = skb_checksum_start_offset(skb);
1007 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1008
1009 ctrl = (TXDCTRL_CENAB |
1010 (csum_start_off << 15) |
1011 (csum_stuff_off << 21));
1012 }
1013
1014 if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1015 /* This is a hard error, log it. */
1016 if (!netif_queue_stopped(dev)) {
1017 netif_stop_queue(dev);
1018 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1019 }
1020 return NETDEV_TX_BUSY;
1021 }
1022
1023 entry = gp->tx_new;
1024 gp->tx_skbs[entry] = skb;
1025
1026 if (skb_shinfo(skb)->nr_frags == 0) {
1027 struct gem_txd *txd = &gp->init_block->txd[entry];
1028 dma_addr_t mapping;
1029 u32 len;
1030
1031 len = skb->len;
1032 mapping = pci_map_page(gp->pdev,
1033 virt_to_page(skb->data),
1034 offset_in_page(skb->data),
1035 len, PCI_DMA_TODEVICE);
1036 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1037 if (gem_intme(entry))
1038 ctrl |= TXDCTRL_INTME;
1039 txd->buffer = cpu_to_le64(mapping);
1040 dma_wmb();
1041 txd->control_word = cpu_to_le64(ctrl);
1042 entry = NEXT_TX(entry);
1043 } else {
1044 struct gem_txd *txd;
1045 u32 first_len;
1046 u64 intme;
1047 dma_addr_t first_mapping;
1048 int frag, first_entry = entry;
1049
1050 intme = 0;
1051 if (gem_intme(entry))
1052 intme |= TXDCTRL_INTME;
1053
1054 /* We must give this initial chunk to the device last.
1055 * Otherwise we could race with the device.
1056 */
1057 first_len = skb_headlen(skb);
1058 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1059 offset_in_page(skb->data),
1060 first_len, PCI_DMA_TODEVICE);
1061 entry = NEXT_TX(entry);
1062
1063 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1064 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1065 u32 len;
1066 dma_addr_t mapping;
1067 u64 this_ctrl;
1068
1069 len = skb_frag_size(this_frag);
1070 mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag,
1071 0, len, DMA_TO_DEVICE);
1072 this_ctrl = ctrl;
1073 if (frag == skb_shinfo(skb)->nr_frags - 1)
1074 this_ctrl |= TXDCTRL_EOF;
1075
1076 txd = &gp->init_block->txd[entry];
1077 txd->buffer = cpu_to_le64(mapping);
1078 dma_wmb();
1079 txd->control_word = cpu_to_le64(this_ctrl | len);
1080
1081 if (gem_intme(entry))
1082 intme |= TXDCTRL_INTME;
1083
1084 entry = NEXT_TX(entry);
1085 }
1086 txd = &gp->init_block->txd[first_entry];
1087 txd->buffer = cpu_to_le64(first_mapping);
1088 dma_wmb();
1089 txd->control_word =
1090 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1091 }
1092
1093 gp->tx_new = entry;
1094 if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {
1095 netif_stop_queue(dev);
1096
1097 /* netif_stop_queue() must be done before checking
1098 * checking tx index in TX_BUFFS_AVAIL() below, because
1099 * in gem_tx(), we update tx_old before checking for
1100 * netif_queue_stopped().
1101 */
1102 smp_mb();
1103 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
1104 netif_wake_queue(dev);
1105 }
1106 if (netif_msg_tx_queued(gp))
1107 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1108 dev->name, entry, skb->len);
1109 mb();
1110 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1111
1112 return NETDEV_TX_OK;
1113 }
1114
1115 static void gem_pcs_reset(struct gem *gp)
1116 {
1117 int limit;
1118 u32 val;
1119
1120 /* Reset PCS unit. */
1121 val = readl(gp->regs + PCS_MIICTRL);
1122 val |= PCS_MIICTRL_RST;
1123 writel(val, gp->regs + PCS_MIICTRL);
1124
1125 limit = 32;
1126 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1127 udelay(100);
1128 if (limit-- <= 0)
1129 break;
1130 }
1131 if (limit < 0)
1132 netdev_warn(gp->dev, "PCS reset bit would not clear\n");
1133 }
1134
1135 static void gem_pcs_reinit_adv(struct gem *gp)
1136 {
1137 u32 val;
1138
1139 /* Make sure PCS is disabled while changing advertisement
1140 * configuration.
1141 */
1142 val = readl(gp->regs + PCS_CFG);
1143 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1144 writel(val, gp->regs + PCS_CFG);
1145
1146 /* Advertise all capabilities except asymmetric
1147 * pause.
1148 */
1149 val = readl(gp->regs + PCS_MIIADV);
1150 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1151 PCS_MIIADV_SP | PCS_MIIADV_AP);
1152 writel(val, gp->regs + PCS_MIIADV);
1153
1154 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1155 * and re-enable PCS.
1156 */
1157 val = readl(gp->regs + PCS_MIICTRL);
1158 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1159 val &= ~PCS_MIICTRL_WB;
1160 writel(val, gp->regs + PCS_MIICTRL);
1161
1162 val = readl(gp->regs + PCS_CFG);
1163 val |= PCS_CFG_ENABLE;
1164 writel(val, gp->regs + PCS_CFG);
1165
1166 /* Make sure serialink loopback is off. The meaning
1167 * of this bit is logically inverted based upon whether
1168 * you are in Serialink or SERDES mode.
1169 */
1170 val = readl(gp->regs + PCS_SCTRL);
1171 if (gp->phy_type == phy_serialink)
1172 val &= ~PCS_SCTRL_LOOP;
1173 else
1174 val |= PCS_SCTRL_LOOP;
1175 writel(val, gp->regs + PCS_SCTRL);
1176 }
1177
1178 #define STOP_TRIES 32
1179
1180 static void gem_reset(struct gem *gp)
1181 {
1182 int limit;
1183 u32 val;
1184
1185 /* Make sure we won't get any more interrupts */
1186 writel(0xffffffff, gp->regs + GREG_IMASK);
1187
1188 /* Reset the chip */
1189 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1190 gp->regs + GREG_SWRST);
1191
1192 limit = STOP_TRIES;
1193
1194 do {
1195 udelay(20);
1196 val = readl(gp->regs + GREG_SWRST);
1197 if (limit-- <= 0)
1198 break;
1199 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1200
1201 if (limit < 0)
1202 netdev_err(gp->dev, "SW reset is ghetto\n");
1203
1204 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1205 gem_pcs_reinit_adv(gp);
1206 }
1207
1208 static void gem_start_dma(struct gem *gp)
1209 {
1210 u32 val;
1211
1212 /* We are ready to rock, turn everything on. */
1213 val = readl(gp->regs + TXDMA_CFG);
1214 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1215 val = readl(gp->regs + RXDMA_CFG);
1216 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1217 val = readl(gp->regs + MAC_TXCFG);
1218 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1219 val = readl(gp->regs + MAC_RXCFG);
1220 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1221
1222 (void) readl(gp->regs + MAC_RXCFG);
1223 udelay(100);
1224
1225 gem_enable_ints(gp);
1226
1227 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1228 }
1229
1230 /* DMA won't be actually stopped before about 4ms tho ...
1231 */
1232 static void gem_stop_dma(struct gem *gp)
1233 {
1234 u32 val;
1235
1236 /* We are done rocking, turn everything off. */
1237 val = readl(gp->regs + TXDMA_CFG);
1238 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1239 val = readl(gp->regs + RXDMA_CFG);
1240 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1241 val = readl(gp->regs + MAC_TXCFG);
1242 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1243 val = readl(gp->regs + MAC_RXCFG);
1244 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1245
1246 (void) readl(gp->regs + MAC_RXCFG);
1247
1248 /* Need to wait a bit ... done by the caller */
1249 }
1250
1251
1252 // XXX dbl check what that function should do when called on PCS PHY
1253 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1254 {
1255 u32 advertise, features;
1256 int autoneg;
1257 int speed;
1258 int duplex;
1259
1260 if (gp->phy_type != phy_mii_mdio0 &&
1261 gp->phy_type != phy_mii_mdio1)
1262 goto non_mii;
1263
1264 /* Setup advertise */
1265 if (found_mii_phy(gp))
1266 features = gp->phy_mii.def->features;
1267 else
1268 features = 0;
1269
1270 advertise = features & ADVERTISE_MASK;
1271 if (gp->phy_mii.advertising != 0)
1272 advertise &= gp->phy_mii.advertising;
1273
1274 autoneg = gp->want_autoneg;
1275 speed = gp->phy_mii.speed;
1276 duplex = gp->phy_mii.duplex;
1277
1278 /* Setup link parameters */
1279 if (!ep)
1280 goto start_aneg;
1281 if (ep->autoneg == AUTONEG_ENABLE) {
1282 advertise = ep->advertising;
1283 autoneg = 1;
1284 } else {
1285 autoneg = 0;
1286 speed = ethtool_cmd_speed(ep);
1287 duplex = ep->duplex;
1288 }
1289
1290 start_aneg:
1291 /* Sanitize settings based on PHY capabilities */
1292 if ((features & SUPPORTED_Autoneg) == 0)
1293 autoneg = 0;
1294 if (speed == SPEED_1000 &&
1295 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1296 speed = SPEED_100;
1297 if (speed == SPEED_100 &&
1298 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1299 speed = SPEED_10;
1300 if (duplex == DUPLEX_FULL &&
1301 !(features & (SUPPORTED_1000baseT_Full |
1302 SUPPORTED_100baseT_Full |
1303 SUPPORTED_10baseT_Full)))
1304 duplex = DUPLEX_HALF;
1305 if (speed == 0)
1306 speed = SPEED_10;
1307
1308 /* If we are asleep, we don't try to actually setup the PHY, we
1309 * just store the settings
1310 */
1311 if (!netif_device_present(gp->dev)) {
1312 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1313 gp->phy_mii.speed = speed;
1314 gp->phy_mii.duplex = duplex;
1315 return;
1316 }
1317
1318 /* Configure PHY & start aneg */
1319 gp->want_autoneg = autoneg;
1320 if (autoneg) {
1321 if (found_mii_phy(gp))
1322 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1323 gp->lstate = link_aneg;
1324 } else {
1325 if (found_mii_phy(gp))
1326 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1327 gp->lstate = link_force_ok;
1328 }
1329
1330 non_mii:
1331 gp->timer_ticks = 0;
1332 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1333 }
1334
1335 /* A link-up condition has occurred, initialize and enable the
1336 * rest of the chip.
1337 */
1338 static int gem_set_link_modes(struct gem *gp)
1339 {
1340 struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);
1341 int full_duplex, speed, pause;
1342 u32 val;
1343
1344 full_duplex = 0;
1345 speed = SPEED_10;
1346 pause = 0;
1347
1348 if (found_mii_phy(gp)) {
1349 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1350 return 1;
1351 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1352 speed = gp->phy_mii.speed;
1353 pause = gp->phy_mii.pause;
1354 } else if (gp->phy_type == phy_serialink ||
1355 gp->phy_type == phy_serdes) {
1356 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1357
1358 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1359 full_duplex = 1;
1360 speed = SPEED_1000;
1361 }
1362
1363 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1364 speed, (full_duplex ? "full" : "half"));
1365
1366
1367 /* We take the tx queue lock to avoid collisions between
1368 * this code, the tx path and the NAPI-driven error path
1369 */
1370 __netif_tx_lock(txq, smp_processor_id());
1371
1372 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1373 if (full_duplex) {
1374 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1375 } else {
1376 /* MAC_TXCFG_NBO must be zero. */
1377 }
1378 writel(val, gp->regs + MAC_TXCFG);
1379
1380 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1381 if (!full_duplex &&
1382 (gp->phy_type == phy_mii_mdio0 ||
1383 gp->phy_type == phy_mii_mdio1)) {
1384 val |= MAC_XIFCFG_DISE;
1385 } else if (full_duplex) {
1386 val |= MAC_XIFCFG_FLED;
1387 }
1388
1389 if (speed == SPEED_1000)
1390 val |= (MAC_XIFCFG_GMII);
1391
1392 writel(val, gp->regs + MAC_XIFCFG);
1393
1394 /* If gigabit and half-duplex, enable carrier extension
1395 * mode. Else, disable it.
1396 */
1397 if (speed == SPEED_1000 && !full_duplex) {
1398 val = readl(gp->regs + MAC_TXCFG);
1399 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1400
1401 val = readl(gp->regs + MAC_RXCFG);
1402 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1403 } else {
1404 val = readl(gp->regs + MAC_TXCFG);
1405 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1406
1407 val = readl(gp->regs + MAC_RXCFG);
1408 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1409 }
1410
1411 if (gp->phy_type == phy_serialink ||
1412 gp->phy_type == phy_serdes) {
1413 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1414
1415 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1416 pause = 1;
1417 }
1418
1419 if (!full_duplex)
1420 writel(512, gp->regs + MAC_STIME);
1421 else
1422 writel(64, gp->regs + MAC_STIME);
1423 val = readl(gp->regs + MAC_MCCFG);
1424 if (pause)
1425 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1426 else
1427 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1428 writel(val, gp->regs + MAC_MCCFG);
1429
1430 gem_start_dma(gp);
1431
1432 __netif_tx_unlock(txq);
1433
1434 if (netif_msg_link(gp)) {
1435 if (pause) {
1436 netdev_info(gp->dev,
1437 "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1438 gp->rx_fifo_sz,
1439 gp->rx_pause_off,
1440 gp->rx_pause_on);
1441 } else {
1442 netdev_info(gp->dev, "Pause is disabled\n");
1443 }
1444 }
1445
1446 return 0;
1447 }
1448
1449 static int gem_mdio_link_not_up(struct gem *gp)
1450 {
1451 switch (gp->lstate) {
1452 case link_force_ret:
1453 netif_info(gp, link, gp->dev,
1454 "Autoneg failed again, keeping forced mode\n");
1455 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1456 gp->last_forced_speed, DUPLEX_HALF);
1457 gp->timer_ticks = 5;
1458 gp->lstate = link_force_ok;
1459 return 0;
1460 case link_aneg:
1461 /* We try forced modes after a failed aneg only on PHYs that don't
1462 * have "magic_aneg" bit set, which means they internally do the
1463 * while forced-mode thingy. On these, we just restart aneg
1464 */
1465 if (gp->phy_mii.def->magic_aneg)
1466 return 1;
1467 netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1468 /* Try forced modes. */
1469 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1470 DUPLEX_HALF);
1471 gp->timer_ticks = 5;
1472 gp->lstate = link_force_try;
1473 return 0;
1474 case link_force_try:
1475 /* Downgrade from 100 to 10 Mbps if necessary.
1476 * If already at 10Mbps, warn user about the
1477 * situation every 10 ticks.
1478 */
1479 if (gp->phy_mii.speed == SPEED_100) {
1480 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1481 DUPLEX_HALF);
1482 gp->timer_ticks = 5;
1483 netif_info(gp, link, gp->dev,
1484 "switching to forced 10bt\n");
1485 return 0;
1486 } else
1487 return 1;
1488 default:
1489 return 0;
1490 }
1491 }
1492
1493 static void gem_link_timer(unsigned long data)
1494 {
1495 struct gem *gp = (struct gem *) data;
1496 struct net_device *dev = gp->dev;
1497 int restart_aneg = 0;
1498
1499 /* There's no point doing anything if we're going to be reset */
1500 if (gp->reset_task_pending)
1501 return;
1502
1503 if (gp->phy_type == phy_serialink ||
1504 gp->phy_type == phy_serdes) {
1505 u32 val = readl(gp->regs + PCS_MIISTAT);
1506
1507 if (!(val & PCS_MIISTAT_LS))
1508 val = readl(gp->regs + PCS_MIISTAT);
1509
1510 if ((val & PCS_MIISTAT_LS) != 0) {
1511 if (gp->lstate == link_up)
1512 goto restart;
1513
1514 gp->lstate = link_up;
1515 netif_carrier_on(dev);
1516 (void)gem_set_link_modes(gp);
1517 }
1518 goto restart;
1519 }
1520 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1521 /* Ok, here we got a link. If we had it due to a forced
1522 * fallback, and we were configured for autoneg, we do
1523 * retry a short autoneg pass. If you know your hub is
1524 * broken, use ethtool ;)
1525 */
1526 if (gp->lstate == link_force_try && gp->want_autoneg) {
1527 gp->lstate = link_force_ret;
1528 gp->last_forced_speed = gp->phy_mii.speed;
1529 gp->timer_ticks = 5;
1530 if (netif_msg_link(gp))
1531 netdev_info(dev,
1532 "Got link after fallback, retrying autoneg once...\n");
1533 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1534 } else if (gp->lstate != link_up) {
1535 gp->lstate = link_up;
1536 netif_carrier_on(dev);
1537 if (gem_set_link_modes(gp))
1538 restart_aneg = 1;
1539 }
1540 } else {
1541 /* If the link was previously up, we restart the
1542 * whole process
1543 */
1544 if (gp->lstate == link_up) {
1545 gp->lstate = link_down;
1546 netif_info(gp, link, dev, "Link down\n");
1547 netif_carrier_off(dev);
1548 gem_schedule_reset(gp);
1549 /* The reset task will restart the timer */
1550 return;
1551 } else if (++gp->timer_ticks > 10) {
1552 if (found_mii_phy(gp))
1553 restart_aneg = gem_mdio_link_not_up(gp);
1554 else
1555 restart_aneg = 1;
1556 }
1557 }
1558 if (restart_aneg) {
1559 gem_begin_auto_negotiation(gp, NULL);
1560 return;
1561 }
1562 restart:
1563 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1564 }
1565
1566 static void gem_clean_rings(struct gem *gp)
1567 {
1568 struct gem_init_block *gb = gp->init_block;
1569 struct sk_buff *skb;
1570 int i;
1571 dma_addr_t dma_addr;
1572
1573 for (i = 0; i < RX_RING_SIZE; i++) {
1574 struct gem_rxd *rxd;
1575
1576 rxd = &gb->rxd[i];
1577 if (gp->rx_skbs[i] != NULL) {
1578 skb = gp->rx_skbs[i];
1579 dma_addr = le64_to_cpu(rxd->buffer);
1580 pci_unmap_page(gp->pdev, dma_addr,
1581 RX_BUF_ALLOC_SIZE(gp),
1582 PCI_DMA_FROMDEVICE);
1583 dev_kfree_skb_any(skb);
1584 gp->rx_skbs[i] = NULL;
1585 }
1586 rxd->status_word = 0;
1587 dma_wmb();
1588 rxd->buffer = 0;
1589 }
1590
1591 for (i = 0; i < TX_RING_SIZE; i++) {
1592 if (gp->tx_skbs[i] != NULL) {
1593 struct gem_txd *txd;
1594 int frag;
1595
1596 skb = gp->tx_skbs[i];
1597 gp->tx_skbs[i] = NULL;
1598
1599 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1600 int ent = i & (TX_RING_SIZE - 1);
1601
1602 txd = &gb->txd[ent];
1603 dma_addr = le64_to_cpu(txd->buffer);
1604 pci_unmap_page(gp->pdev, dma_addr,
1605 le64_to_cpu(txd->control_word) &
1606 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1607
1608 if (frag != skb_shinfo(skb)->nr_frags)
1609 i++;
1610 }
1611 dev_kfree_skb_any(skb);
1612 }
1613 }
1614 }
1615
1616 static void gem_init_rings(struct gem *gp)
1617 {
1618 struct gem_init_block *gb = gp->init_block;
1619 struct net_device *dev = gp->dev;
1620 int i;
1621 dma_addr_t dma_addr;
1622
1623 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1624
1625 gem_clean_rings(gp);
1626
1627 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1628 (unsigned)VLAN_ETH_FRAME_LEN);
1629
1630 for (i = 0; i < RX_RING_SIZE; i++) {
1631 struct sk_buff *skb;
1632 struct gem_rxd *rxd = &gb->rxd[i];
1633
1634 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);
1635 if (!skb) {
1636 rxd->buffer = 0;
1637 rxd->status_word = 0;
1638 continue;
1639 }
1640
1641 gp->rx_skbs[i] = skb;
1642 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1643 dma_addr = pci_map_page(gp->pdev,
1644 virt_to_page(skb->data),
1645 offset_in_page(skb->data),
1646 RX_BUF_ALLOC_SIZE(gp),
1647 PCI_DMA_FROMDEVICE);
1648 rxd->buffer = cpu_to_le64(dma_addr);
1649 dma_wmb();
1650 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1651 skb_reserve(skb, RX_OFFSET);
1652 }
1653
1654 for (i = 0; i < TX_RING_SIZE; i++) {
1655 struct gem_txd *txd = &gb->txd[i];
1656
1657 txd->control_word = 0;
1658 dma_wmb();
1659 txd->buffer = 0;
1660 }
1661 wmb();
1662 }
1663
1664 /* Init PHY interface and start link poll state machine */
1665 static void gem_init_phy(struct gem *gp)
1666 {
1667 u32 mifcfg;
1668
1669 /* Revert MIF CFG setting done on stop_phy */
1670 mifcfg = readl(gp->regs + MIF_CFG);
1671 mifcfg &= ~MIF_CFG_BBMODE;
1672 writel(mifcfg, gp->regs + MIF_CFG);
1673
1674 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1675 int i;
1676
1677 /* Those delay sucks, the HW seem to love them though, I'll
1678 * serisouly consider breaking some locks here to be able
1679 * to schedule instead
1680 */
1681 for (i = 0; i < 3; i++) {
1682 #ifdef CONFIG_PPC_PMAC
1683 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1684 msleep(20);
1685 #endif
1686 /* Some PHYs used by apple have problem getting back to us,
1687 * we do an additional reset here
1688 */
1689 sungem_phy_write(gp, MII_BMCR, BMCR_RESET);
1690 msleep(20);
1691 if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
1692 break;
1693 if (i == 2)
1694 netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1695 }
1696 }
1697
1698 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1699 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1700 u32 val;
1701
1702 /* Init datapath mode register. */
1703 if (gp->phy_type == phy_mii_mdio0 ||
1704 gp->phy_type == phy_mii_mdio1) {
1705 val = PCS_DMODE_MGM;
1706 } else if (gp->phy_type == phy_serialink) {
1707 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1708 } else {
1709 val = PCS_DMODE_ESM;
1710 }
1711
1712 writel(val, gp->regs + PCS_DMODE);
1713 }
1714
1715 if (gp->phy_type == phy_mii_mdio0 ||
1716 gp->phy_type == phy_mii_mdio1) {
1717 /* Reset and detect MII PHY */
1718 sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1719
1720 /* Init PHY */
1721 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1722 gp->phy_mii.def->ops->init(&gp->phy_mii);
1723 } else {
1724 gem_pcs_reset(gp);
1725 gem_pcs_reinit_adv(gp);
1726 }
1727
1728 /* Default aneg parameters */
1729 gp->timer_ticks = 0;
1730 gp->lstate = link_down;
1731 netif_carrier_off(gp->dev);
1732
1733 /* Print things out */
1734 if (gp->phy_type == phy_mii_mdio0 ||
1735 gp->phy_type == phy_mii_mdio1)
1736 netdev_info(gp->dev, "Found %s PHY\n",
1737 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
1738
1739 gem_begin_auto_negotiation(gp, NULL);
1740 }
1741
1742 static void gem_init_dma(struct gem *gp)
1743 {
1744 u64 desc_dma = (u64) gp->gblock_dvma;
1745 u32 val;
1746
1747 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1748 writel(val, gp->regs + TXDMA_CFG);
1749
1750 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1751 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1752 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1753
1754 writel(0, gp->regs + TXDMA_KICK);
1755
1756 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1757 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1758 writel(val, gp->regs + RXDMA_CFG);
1759
1760 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1761 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1762
1763 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1764
1765 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1766 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1767 writel(val, gp->regs + RXDMA_PTHRESH);
1768
1769 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1770 writel(((5 & RXDMA_BLANK_IPKTS) |
1771 ((8 << 12) & RXDMA_BLANK_ITIME)),
1772 gp->regs + RXDMA_BLANK);
1773 else
1774 writel(((5 & RXDMA_BLANK_IPKTS) |
1775 ((4 << 12) & RXDMA_BLANK_ITIME)),
1776 gp->regs + RXDMA_BLANK);
1777 }
1778
1779 static u32 gem_setup_multicast(struct gem *gp)
1780 {
1781 u32 rxcfg = 0;
1782 int i;
1783
1784 if ((gp->dev->flags & IFF_ALLMULTI) ||
1785 (netdev_mc_count(gp->dev) > 256)) {
1786 for (i=0; i<16; i++)
1787 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1788 rxcfg |= MAC_RXCFG_HFE;
1789 } else if (gp->dev->flags & IFF_PROMISC) {
1790 rxcfg |= MAC_RXCFG_PROM;
1791 } else {
1792 u16 hash_table[16];
1793 u32 crc;
1794 struct netdev_hw_addr *ha;
1795 int i;
1796
1797 memset(hash_table, 0, sizeof(hash_table));
1798 netdev_for_each_mc_addr(ha, gp->dev) {
1799 crc = ether_crc_le(6, ha->addr);
1800 crc >>= 24;
1801 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1802 }
1803 for (i=0; i<16; i++)
1804 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1805 rxcfg |= MAC_RXCFG_HFE;
1806 }
1807
1808 return rxcfg;
1809 }
1810
1811 static void gem_init_mac(struct gem *gp)
1812 {
1813 unsigned char *e = &gp->dev->dev_addr[0];
1814
1815 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1816
1817 writel(0x00, gp->regs + MAC_IPG0);
1818 writel(0x08, gp->regs + MAC_IPG1);
1819 writel(0x04, gp->regs + MAC_IPG2);
1820 writel(0x40, gp->regs + MAC_STIME);
1821 writel(0x40, gp->regs + MAC_MINFSZ);
1822
1823 /* Ethernet payload + header + FCS + optional VLAN tag. */
1824 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1825
1826 writel(0x07, gp->regs + MAC_PASIZE);
1827 writel(0x04, gp->regs + MAC_JAMSIZE);
1828 writel(0x10, gp->regs + MAC_ATTLIM);
1829 writel(0x8808, gp->regs + MAC_MCTYPE);
1830
1831 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1832
1833 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1834 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1835 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1836
1837 writel(0, gp->regs + MAC_ADDR3);
1838 writel(0, gp->regs + MAC_ADDR4);
1839 writel(0, gp->regs + MAC_ADDR5);
1840
1841 writel(0x0001, gp->regs + MAC_ADDR6);
1842 writel(0xc200, gp->regs + MAC_ADDR7);
1843 writel(0x0180, gp->regs + MAC_ADDR8);
1844
1845 writel(0, gp->regs + MAC_AFILT0);
1846 writel(0, gp->regs + MAC_AFILT1);
1847 writel(0, gp->regs + MAC_AFILT2);
1848 writel(0, gp->regs + MAC_AF21MSK);
1849 writel(0, gp->regs + MAC_AF0MSK);
1850
1851 gp->mac_rx_cfg = gem_setup_multicast(gp);
1852 #ifdef STRIP_FCS
1853 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1854 #endif
1855 writel(0, gp->regs + MAC_NCOLL);
1856 writel(0, gp->regs + MAC_FASUCC);
1857 writel(0, gp->regs + MAC_ECOLL);
1858 writel(0, gp->regs + MAC_LCOLL);
1859 writel(0, gp->regs + MAC_DTIMER);
1860 writel(0, gp->regs + MAC_PATMPS);
1861 writel(0, gp->regs + MAC_RFCTR);
1862 writel(0, gp->regs + MAC_LERR);
1863 writel(0, gp->regs + MAC_AERR);
1864 writel(0, gp->regs + MAC_FCSERR);
1865 writel(0, gp->regs + MAC_RXCVERR);
1866
1867 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1868 * them once a link is established.
1869 */
1870 writel(0, gp->regs + MAC_TXCFG);
1871 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1872 writel(0, gp->regs + MAC_MCCFG);
1873 writel(0, gp->regs + MAC_XIFCFG);
1874
1875 /* Setup MAC interrupts. We want to get all of the interesting
1876 * counter expiration events, but we do not want to hear about
1877 * normal rx/tx as the DMA engine tells us that.
1878 */
1879 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1880 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1881
1882 /* Don't enable even the PAUSE interrupts for now, we
1883 * make no use of those events other than to record them.
1884 */
1885 writel(0xffffffff, gp->regs + MAC_MCMASK);
1886
1887 /* Don't enable GEM's WOL in normal operations
1888 */
1889 if (gp->has_wol)
1890 writel(0, gp->regs + WOL_WAKECSR);
1891 }
1892
1893 static void gem_init_pause_thresholds(struct gem *gp)
1894 {
1895 u32 cfg;
1896
1897 /* Calculate pause thresholds. Setting the OFF threshold to the
1898 * full RX fifo size effectively disables PAUSE generation which
1899 * is what we do for 10/100 only GEMs which have FIFOs too small
1900 * to make real gains from PAUSE.
1901 */
1902 if (gp->rx_fifo_sz <= (2 * 1024)) {
1903 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1904 } else {
1905 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1906 int off = (gp->rx_fifo_sz - (max_frame * 2));
1907 int on = off - max_frame;
1908
1909 gp->rx_pause_off = off;
1910 gp->rx_pause_on = on;
1911 }
1912
1913
1914 /* Configure the chip "burst" DMA mode & enable some
1915 * HW bug fixes on Apple version
1916 */
1917 cfg = 0;
1918 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1919 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1920 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1921 cfg |= GREG_CFG_IBURST;
1922 #endif
1923 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1924 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1925 writel(cfg, gp->regs + GREG_CFG);
1926
1927 /* If Infinite Burst didn't stick, then use different
1928 * thresholds (and Apple bug fixes don't exist)
1929 */
1930 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1931 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1932 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1933 writel(cfg, gp->regs + GREG_CFG);
1934 }
1935 }
1936
1937 static int gem_check_invariants(struct gem *gp)
1938 {
1939 struct pci_dev *pdev = gp->pdev;
1940 u32 mif_cfg;
1941
1942 /* On Apple's sungem, we can't rely on registers as the chip
1943 * was been powered down by the firmware. The PHY is looked
1944 * up later on.
1945 */
1946 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1947 gp->phy_type = phy_mii_mdio0;
1948 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1949 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1950 gp->swrst_base = 0;
1951
1952 mif_cfg = readl(gp->regs + MIF_CFG);
1953 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1954 mif_cfg |= MIF_CFG_MDI0;
1955 writel(mif_cfg, gp->regs + MIF_CFG);
1956 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1957 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1958
1959 /* We hard-code the PHY address so we can properly bring it out of
1960 * reset later on, we can't really probe it at this point, though
1961 * that isn't an issue.
1962 */
1963 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1964 gp->mii_phy_addr = 1;
1965 else
1966 gp->mii_phy_addr = 0;
1967
1968 return 0;
1969 }
1970
1971 mif_cfg = readl(gp->regs + MIF_CFG);
1972
1973 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1974 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1975 /* One of the MII PHYs _must_ be present
1976 * as this chip has no gigabit PHY.
1977 */
1978 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1979 pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1980 mif_cfg);
1981 return -1;
1982 }
1983 }
1984
1985 /* Determine initial PHY interface type guess. MDIO1 is the
1986 * external PHY and thus takes precedence over MDIO0.
1987 */
1988
1989 if (mif_cfg & MIF_CFG_MDI1) {
1990 gp->phy_type = phy_mii_mdio1;
1991 mif_cfg |= MIF_CFG_PSELECT;
1992 writel(mif_cfg, gp->regs + MIF_CFG);
1993 } else if (mif_cfg & MIF_CFG_MDI0) {
1994 gp->phy_type = phy_mii_mdio0;
1995 mif_cfg &= ~MIF_CFG_PSELECT;
1996 writel(mif_cfg, gp->regs + MIF_CFG);
1997 } else {
1998 #ifdef CONFIG_SPARC
1999 const char *p;
2000
2001 p = of_get_property(gp->of_node, "shared-pins", NULL);
2002 if (p && !strcmp(p, "serdes"))
2003 gp->phy_type = phy_serdes;
2004 else
2005 #endif
2006 gp->phy_type = phy_serialink;
2007 }
2008 if (gp->phy_type == phy_mii_mdio1 ||
2009 gp->phy_type == phy_mii_mdio0) {
2010 int i;
2011
2012 for (i = 0; i < 32; i++) {
2013 gp->mii_phy_addr = i;
2014 if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
2015 break;
2016 }
2017 if (i == 32) {
2018 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2019 pr_err("RIO MII phy will not respond\n");
2020 return -1;
2021 }
2022 gp->phy_type = phy_serdes;
2023 }
2024 }
2025
2026 /* Fetch the FIFO configurations now too. */
2027 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2028 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2029
2030 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2031 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2032 if (gp->tx_fifo_sz != (9 * 1024) ||
2033 gp->rx_fifo_sz != (20 * 1024)) {
2034 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2035 gp->tx_fifo_sz, gp->rx_fifo_sz);
2036 return -1;
2037 }
2038 gp->swrst_base = 0;
2039 } else {
2040 if (gp->tx_fifo_sz != (2 * 1024) ||
2041 gp->rx_fifo_sz != (2 * 1024)) {
2042 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2043 gp->tx_fifo_sz, gp->rx_fifo_sz);
2044 return -1;
2045 }
2046 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2047 }
2048 }
2049
2050 return 0;
2051 }
2052
2053 static void gem_reinit_chip(struct gem *gp)
2054 {
2055 /* Reset the chip */
2056 gem_reset(gp);
2057
2058 /* Make sure ints are disabled */
2059 gem_disable_ints(gp);
2060
2061 /* Allocate & setup ring buffers */
2062 gem_init_rings(gp);
2063
2064 /* Configure pause thresholds */
2065 gem_init_pause_thresholds(gp);
2066
2067 /* Init DMA & MAC engines */
2068 gem_init_dma(gp);
2069 gem_init_mac(gp);
2070 }
2071
2072
2073 static void gem_stop_phy(struct gem *gp, int wol)
2074 {
2075 u32 mifcfg;
2076
2077 /* Let the chip settle down a bit, it seems that helps
2078 * for sleep mode on some models
2079 */
2080 msleep(10);
2081
2082 /* Make sure we aren't polling PHY status change. We
2083 * don't currently use that feature though
2084 */
2085 mifcfg = readl(gp->regs + MIF_CFG);
2086 mifcfg &= ~MIF_CFG_POLL;
2087 writel(mifcfg, gp->regs + MIF_CFG);
2088
2089 if (wol && gp->has_wol) {
2090 unsigned char *e = &gp->dev->dev_addr[0];
2091 u32 csr;
2092
2093 /* Setup wake-on-lan for MAGIC packet */
2094 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2095 gp->regs + MAC_RXCFG);
2096 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2097 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2098 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2099
2100 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2101 csr = WOL_WAKECSR_ENABLE;
2102 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2103 csr |= WOL_WAKECSR_MII;
2104 writel(csr, gp->regs + WOL_WAKECSR);
2105 } else {
2106 writel(0, gp->regs + MAC_RXCFG);
2107 (void)readl(gp->regs + MAC_RXCFG);
2108 /* Machine sleep will die in strange ways if we
2109 * dont wait a bit here, looks like the chip takes
2110 * some time to really shut down
2111 */
2112 msleep(10);
2113 }
2114
2115 writel(0, gp->regs + MAC_TXCFG);
2116 writel(0, gp->regs + MAC_XIFCFG);
2117 writel(0, gp->regs + TXDMA_CFG);
2118 writel(0, gp->regs + RXDMA_CFG);
2119
2120 if (!wol) {
2121 gem_reset(gp);
2122 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2123 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2124
2125 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2126 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2127
2128 /* According to Apple, we must set the MDIO pins to this begnign
2129 * state or we may 1) eat more current, 2) damage some PHYs
2130 */
2131 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2132 writel(0, gp->regs + MIF_BBCLK);
2133 writel(0, gp->regs + MIF_BBDATA);
2134 writel(0, gp->regs + MIF_BBOENAB);
2135 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2136 (void) readl(gp->regs + MAC_XIFCFG);
2137 }
2138 }
2139
2140 static int gem_do_start(struct net_device *dev)
2141 {
2142 struct gem *gp = netdev_priv(dev);
2143 int rc;
2144
2145 /* Enable the cell */
2146 gem_get_cell(gp);
2147
2148 /* Make sure PCI access and bus master are enabled */
2149 rc = pci_enable_device(gp->pdev);
2150 if (rc) {
2151 netdev_err(dev, "Failed to enable chip on PCI bus !\n");
2152
2153 /* Put cell and forget it for now, it will be considered as
2154 * still asleep, a new sleep cycle may bring it back
2155 */
2156 gem_put_cell(gp);
2157 return -ENXIO;
2158 }
2159 pci_set_master(gp->pdev);
2160
2161 /* Init & setup chip hardware */
2162 gem_reinit_chip(gp);
2163
2164 /* An interrupt might come in handy */
2165 rc = request_irq(gp->pdev->irq, gem_interrupt,
2166 IRQF_SHARED, dev->name, (void *)dev);
2167 if (rc) {
2168 netdev_err(dev, "failed to request irq !\n");
2169
2170 gem_reset(gp);
2171 gem_clean_rings(gp);
2172 gem_put_cell(gp);
2173 return rc;
2174 }
2175
2176 /* Mark us as attached again if we come from resume(), this has
2177 * no effect if we weren't detached and needs to be done now.
2178 */
2179 netif_device_attach(dev);
2180
2181 /* Restart NAPI & queues */
2182 gem_netif_start(gp);
2183
2184 /* Detect & init PHY, start autoneg etc... this will
2185 * eventually result in starting DMA operations when
2186 * the link is up
2187 */
2188 gem_init_phy(gp);
2189
2190 return 0;
2191 }
2192
2193 static void gem_do_stop(struct net_device *dev, int wol)
2194 {
2195 struct gem *gp = netdev_priv(dev);
2196
2197 /* Stop NAPI and stop tx queue */
2198 gem_netif_stop(gp);
2199
2200 /* Make sure ints are disabled. We don't care about
2201 * synchronizing as NAPI is disabled, thus a stray
2202 * interrupt will do nothing bad (our irq handler
2203 * just schedules NAPI)
2204 */
2205 gem_disable_ints(gp);
2206
2207 /* Stop the link timer */
2208 del_timer_sync(&gp->link_timer);
2209
2210 /* We cannot cancel the reset task while holding the
2211 * rtnl lock, we'd get an A->B / B->A deadlock stituation
2212 * if we did. This is not an issue however as the reset
2213 * task is synchronized vs. us (rtnl_lock) and will do
2214 * nothing if the device is down or suspended. We do
2215 * still clear reset_task_pending to avoid a spurrious
2216 * reset later on in case we do resume before it gets
2217 * scheduled.
2218 */
2219 gp->reset_task_pending = 0;
2220
2221 /* If we are going to sleep with WOL */
2222 gem_stop_dma(gp);
2223 msleep(10);
2224 if (!wol)
2225 gem_reset(gp);
2226 msleep(10);
2227
2228 /* Get rid of rings */
2229 gem_clean_rings(gp);
2230
2231 /* No irq needed anymore */
2232 free_irq(gp->pdev->irq, (void *) dev);
2233
2234 /* Shut the PHY down eventually and setup WOL */
2235 gem_stop_phy(gp, wol);
2236
2237 /* Make sure bus master is disabled */
2238 pci_disable_device(gp->pdev);
2239
2240 /* Cell not needed neither if no WOL */
2241 if (!wol)
2242 gem_put_cell(gp);
2243 }
2244
2245 static void gem_reset_task(struct work_struct *work)
2246 {
2247 struct gem *gp = container_of(work, struct gem, reset_task);
2248
2249 /* Lock out the network stack (essentially shield ourselves
2250 * against a racing open, close, control call, or suspend
2251 */
2252 rtnl_lock();
2253
2254 /* Skip the reset task if suspended or closed, or if it's
2255 * been cancelled by gem_do_stop (see comment there)
2256 */
2257 if (!netif_device_present(gp->dev) ||
2258 !netif_running(gp->dev) ||
2259 !gp->reset_task_pending) {
2260 rtnl_unlock();
2261 return;
2262 }
2263
2264 /* Stop the link timer */
2265 del_timer_sync(&gp->link_timer);
2266
2267 /* Stop NAPI and tx */
2268 gem_netif_stop(gp);
2269
2270 /* Reset the chip & rings */
2271 gem_reinit_chip(gp);
2272 if (gp->lstate == link_up)
2273 gem_set_link_modes(gp);
2274
2275 /* Restart NAPI and Tx */
2276 gem_netif_start(gp);
2277
2278 /* We are back ! */
2279 gp->reset_task_pending = 0;
2280
2281 /* If the link is not up, restart autoneg, else restart the
2282 * polling timer
2283 */
2284 if (gp->lstate != link_up)
2285 gem_begin_auto_negotiation(gp, NULL);
2286 else
2287 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
2288
2289 rtnl_unlock();
2290 }
2291
2292 static int gem_open(struct net_device *dev)
2293 {
2294 /* We allow open while suspended, we just do nothing,
2295 * the chip will be initialized in resume()
2296 */
2297 if (netif_device_present(dev))
2298 return gem_do_start(dev);
2299 return 0;
2300 }
2301
2302 static int gem_close(struct net_device *dev)
2303 {
2304 if (netif_device_present(dev))
2305 gem_do_stop(dev, 0);
2306
2307 return 0;
2308 }
2309
2310 #ifdef CONFIG_PM
2311 static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2312 {
2313 struct net_device *dev = pci_get_drvdata(pdev);
2314 struct gem *gp = netdev_priv(dev);
2315
2316 /* Lock the network stack first to avoid racing with open/close,
2317 * reset task and setting calls
2318 */
2319 rtnl_lock();
2320
2321 /* Not running, mark ourselves non-present, no need for
2322 * a lock here
2323 */
2324 if (!netif_running(dev)) {
2325 netif_device_detach(dev);
2326 rtnl_unlock();
2327 return 0;
2328 }
2329 netdev_info(dev, "suspending, WakeOnLan %s\n",
2330 (gp->wake_on_lan && netif_running(dev)) ?
2331 "enabled" : "disabled");
2332
2333 /* Tell the network stack we're gone. gem_do_stop() below will
2334 * synchronize with TX, stop NAPI etc...
2335 */
2336 netif_device_detach(dev);
2337
2338 /* Switch off chip, remember WOL setting */
2339 gp->asleep_wol = !!gp->wake_on_lan;
2340 gem_do_stop(dev, gp->asleep_wol);
2341
2342 /* Unlock the network stack */
2343 rtnl_unlock();
2344
2345 return 0;
2346 }
2347
2348 static int gem_resume(struct pci_dev *pdev)
2349 {
2350 struct net_device *dev = pci_get_drvdata(pdev);
2351 struct gem *gp = netdev_priv(dev);
2352
2353 /* See locking comment in gem_suspend */
2354 rtnl_lock();
2355
2356 /* Not running, mark ourselves present, no need for
2357 * a lock here
2358 */
2359 if (!netif_running(dev)) {
2360 netif_device_attach(dev);
2361 rtnl_unlock();
2362 return 0;
2363 }
2364
2365 /* Restart chip. If that fails there isn't much we can do, we
2366 * leave things stopped.
2367 */
2368 gem_do_start(dev);
2369
2370 /* If we had WOL enabled, the cell clock was never turned off during
2371 * sleep, so we end up beeing unbalanced. Fix that here
2372 */
2373 if (gp->asleep_wol)
2374 gem_put_cell(gp);
2375
2376 /* Unlock the network stack */
2377 rtnl_unlock();
2378
2379 return 0;
2380 }
2381 #endif /* CONFIG_PM */
2382
2383 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2384 {
2385 struct gem *gp = netdev_priv(dev);
2386
2387 /* I have seen this being called while the PM was in progress,
2388 * so we shield against this. Let's also not poke at registers
2389 * while the reset task is going on.
2390 *
2391 * TODO: Move stats collection elsewhere (link timer ?) and
2392 * make this a nop to avoid all those synchro issues
2393 */
2394 if (!netif_device_present(dev) || !netif_running(dev))
2395 goto bail;
2396
2397 /* Better safe than sorry... */
2398 if (WARN_ON(!gp->cell_enabled))
2399 goto bail;
2400
2401 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2402 writel(0, gp->regs + MAC_FCSERR);
2403
2404 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2405 writel(0, gp->regs + MAC_AERR);
2406
2407 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2408 writel(0, gp->regs + MAC_LERR);
2409
2410 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2411 dev->stats.collisions +=
2412 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
2413 writel(0, gp->regs + MAC_ECOLL);
2414 writel(0, gp->regs + MAC_LCOLL);
2415 bail:
2416 return &dev->stats;
2417 }
2418
2419 static int gem_set_mac_address(struct net_device *dev, void *addr)
2420 {
2421 struct sockaddr *macaddr = (struct sockaddr *) addr;
2422 struct gem *gp = netdev_priv(dev);
2423 unsigned char *e = &dev->dev_addr[0];
2424
2425 if (!is_valid_ether_addr(macaddr->sa_data))
2426 return -EADDRNOTAVAIL;
2427
2428 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2429
2430 /* We'll just catch it later when the device is up'd or resumed */
2431 if (!netif_running(dev) || !netif_device_present(dev))
2432 return 0;
2433
2434 /* Better safe than sorry... */
2435 if (WARN_ON(!gp->cell_enabled))
2436 return 0;
2437
2438 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2439 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2440 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2441
2442 return 0;
2443 }
2444
2445 static void gem_set_multicast(struct net_device *dev)
2446 {
2447 struct gem *gp = netdev_priv(dev);
2448 u32 rxcfg, rxcfg_new;
2449 int limit = 10000;
2450
2451 if (!netif_running(dev) || !netif_device_present(dev))
2452 return;
2453
2454 /* Better safe than sorry... */
2455 if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))
2456 return;
2457
2458 rxcfg = readl(gp->regs + MAC_RXCFG);
2459 rxcfg_new = gem_setup_multicast(gp);
2460 #ifdef STRIP_FCS
2461 rxcfg_new |= MAC_RXCFG_SFCS;
2462 #endif
2463 gp->mac_rx_cfg = rxcfg_new;
2464
2465 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2466 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2467 if (!limit--)
2468 break;
2469 udelay(10);
2470 }
2471
2472 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2473 rxcfg |= rxcfg_new;
2474
2475 writel(rxcfg, gp->regs + MAC_RXCFG);
2476 }
2477
2478 /* Jumbo-grams don't seem to work :-( */
2479 #define GEM_MIN_MTU 68
2480 #if 1
2481 #define GEM_MAX_MTU 1500
2482 #else
2483 #define GEM_MAX_MTU 9000
2484 #endif
2485
2486 static int gem_change_mtu(struct net_device *dev, int new_mtu)
2487 {
2488 struct gem *gp = netdev_priv(dev);
2489
2490 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2491 return -EINVAL;
2492
2493 dev->mtu = new_mtu;
2494
2495 /* We'll just catch it later when the device is up'd or resumed */
2496 if (!netif_running(dev) || !netif_device_present(dev))
2497 return 0;
2498
2499 /* Better safe than sorry... */
2500 if (WARN_ON(!gp->cell_enabled))
2501 return 0;
2502
2503 gem_netif_stop(gp);
2504 gem_reinit_chip(gp);
2505 if (gp->lstate == link_up)
2506 gem_set_link_modes(gp);
2507 gem_netif_start(gp);
2508
2509 return 0;
2510 }
2511
2512 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2513 {
2514 struct gem *gp = netdev_priv(dev);
2515
2516 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2517 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2518 strlcpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info));
2519 }
2520
2521 static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2522 {
2523 struct gem *gp = netdev_priv(dev);
2524
2525 if (gp->phy_type == phy_mii_mdio0 ||
2526 gp->phy_type == phy_mii_mdio1) {
2527 if (gp->phy_mii.def)
2528 cmd->supported = gp->phy_mii.def->features;
2529 else
2530 cmd->supported = (SUPPORTED_10baseT_Half |
2531 SUPPORTED_10baseT_Full);
2532
2533 /* XXX hardcoded stuff for now */
2534 cmd->port = PORT_MII;
2535 cmd->transceiver = XCVR_EXTERNAL;
2536 cmd->phy_address = 0; /* XXX fixed PHYAD */
2537
2538 /* Return current PHY settings */
2539 cmd->autoneg = gp->want_autoneg;
2540 ethtool_cmd_speed_set(cmd, gp->phy_mii.speed);
2541 cmd->duplex = gp->phy_mii.duplex;
2542 cmd->advertising = gp->phy_mii.advertising;
2543
2544 /* If we started with a forced mode, we don't have a default
2545 * advertise set, we need to return something sensible so
2546 * userland can re-enable autoneg properly.
2547 */
2548 if (cmd->advertising == 0)
2549 cmd->advertising = cmd->supported;
2550 } else { // XXX PCS ?
2551 cmd->supported =
2552 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2553 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2554 SUPPORTED_Autoneg);
2555 cmd->advertising = cmd->supported;
2556 ethtool_cmd_speed_set(cmd, 0);
2557 cmd->duplex = cmd->port = cmd->phy_address =
2558 cmd->transceiver = cmd->autoneg = 0;
2559
2560 /* serdes means usually a Fibre connector, with most fixed */
2561 if (gp->phy_type == phy_serdes) {
2562 cmd->port = PORT_FIBRE;
2563 cmd->supported = (SUPPORTED_1000baseT_Half |
2564 SUPPORTED_1000baseT_Full |
2565 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2566 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2567 cmd->advertising = cmd->supported;
2568 cmd->transceiver = XCVR_INTERNAL;
2569 if (gp->lstate == link_up)
2570 ethtool_cmd_speed_set(cmd, SPEED_1000);
2571 cmd->duplex = DUPLEX_FULL;
2572 cmd->autoneg = 1;
2573 }
2574 }
2575 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2576
2577 return 0;
2578 }
2579
2580 static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2581 {
2582 struct gem *gp = netdev_priv(dev);
2583 u32 speed = ethtool_cmd_speed(cmd);
2584
2585 /* Verify the settings we care about. */
2586 if (cmd->autoneg != AUTONEG_ENABLE &&
2587 cmd->autoneg != AUTONEG_DISABLE)
2588 return -EINVAL;
2589
2590 if (cmd->autoneg == AUTONEG_ENABLE &&
2591 cmd->advertising == 0)
2592 return -EINVAL;
2593
2594 if (cmd->autoneg == AUTONEG_DISABLE &&
2595 ((speed != SPEED_1000 &&
2596 speed != SPEED_100 &&
2597 speed != SPEED_10) ||
2598 (cmd->duplex != DUPLEX_HALF &&
2599 cmd->duplex != DUPLEX_FULL)))
2600 return -EINVAL;
2601
2602 /* Apply settings and restart link process. */
2603 if (netif_device_present(gp->dev)) {
2604 del_timer_sync(&gp->link_timer);
2605 gem_begin_auto_negotiation(gp, cmd);
2606 }
2607
2608 return 0;
2609 }
2610
2611 static int gem_nway_reset(struct net_device *dev)
2612 {
2613 struct gem *gp = netdev_priv(dev);
2614
2615 if (!gp->want_autoneg)
2616 return -EINVAL;
2617
2618 /* Restart link process */
2619 if (netif_device_present(gp->dev)) {
2620 del_timer_sync(&gp->link_timer);
2621 gem_begin_auto_negotiation(gp, NULL);
2622 }
2623
2624 return 0;
2625 }
2626
2627 static u32 gem_get_msglevel(struct net_device *dev)
2628 {
2629 struct gem *gp = netdev_priv(dev);
2630 return gp->msg_enable;
2631 }
2632
2633 static void gem_set_msglevel(struct net_device *dev, u32 value)
2634 {
2635 struct gem *gp = netdev_priv(dev);
2636 gp->msg_enable = value;
2637 }
2638
2639
2640 /* Add more when I understand how to program the chip */
2641 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2642
2643 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2644
2645 static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2646 {
2647 struct gem *gp = netdev_priv(dev);
2648
2649 /* Add more when I understand how to program the chip */
2650 if (gp->has_wol) {
2651 wol->supported = WOL_SUPPORTED_MASK;
2652 wol->wolopts = gp->wake_on_lan;
2653 } else {
2654 wol->supported = 0;
2655 wol->wolopts = 0;
2656 }
2657 }
2658
2659 static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2660 {
2661 struct gem *gp = netdev_priv(dev);
2662
2663 if (!gp->has_wol)
2664 return -EOPNOTSUPP;
2665 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2666 return 0;
2667 }
2668
2669 static const struct ethtool_ops gem_ethtool_ops = {
2670 .get_drvinfo = gem_get_drvinfo,
2671 .get_link = ethtool_op_get_link,
2672 .get_settings = gem_get_settings,
2673 .set_settings = gem_set_settings,
2674 .nway_reset = gem_nway_reset,
2675 .get_msglevel = gem_get_msglevel,
2676 .set_msglevel = gem_set_msglevel,
2677 .get_wol = gem_get_wol,
2678 .set_wol = gem_set_wol,
2679 };
2680
2681 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2682 {
2683 struct gem *gp = netdev_priv(dev);
2684 struct mii_ioctl_data *data = if_mii(ifr);
2685 int rc = -EOPNOTSUPP;
2686
2687 /* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
2688 * netif_device_present() is true and holds rtnl_lock for us
2689 * so we have nothing to worry about
2690 */
2691
2692 switch (cmd) {
2693 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2694 data->phy_id = gp->mii_phy_addr;
2695 /* Fallthrough... */
2696
2697 case SIOCGMIIREG: /* Read MII PHY register. */
2698 data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f,
2699 data->reg_num & 0x1f);
2700 rc = 0;
2701 break;
2702
2703 case SIOCSMIIREG: /* Write MII PHY register. */
2704 __sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2705 data->val_in);
2706 rc = 0;
2707 break;
2708 }
2709 return rc;
2710 }
2711
2712 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2713 /* Fetch MAC address from vital product data of PCI ROM. */
2714 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2715 {
2716 int this_offset;
2717
2718 for (this_offset = 0x20; this_offset < len; this_offset++) {
2719 void __iomem *p = rom_base + this_offset;
2720 int i;
2721
2722 if (readb(p + 0) != 0x90 ||
2723 readb(p + 1) != 0x00 ||
2724 readb(p + 2) != 0x09 ||
2725 readb(p + 3) != 0x4e ||
2726 readb(p + 4) != 0x41 ||
2727 readb(p + 5) != 0x06)
2728 continue;
2729
2730 this_offset += 6;
2731 p += 6;
2732
2733 for (i = 0; i < 6; i++)
2734 dev_addr[i] = readb(p + i);
2735 return 1;
2736 }
2737 return 0;
2738 }
2739
2740 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2741 {
2742 size_t size;
2743 void __iomem *p = pci_map_rom(pdev, &size);
2744
2745 if (p) {
2746 int found;
2747
2748 found = readb(p) == 0x55 &&
2749 readb(p + 1) == 0xaa &&
2750 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2751 pci_unmap_rom(pdev, p);
2752 if (found)
2753 return;
2754 }
2755
2756 /* Sun MAC prefix then 3 random bytes. */
2757 dev_addr[0] = 0x08;
2758 dev_addr[1] = 0x00;
2759 dev_addr[2] = 0x20;
2760 get_random_bytes(dev_addr + 3, 3);
2761 }
2762 #endif /* not Sparc and not PPC */
2763
2764 static int gem_get_device_address(struct gem *gp)
2765 {
2766 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2767 struct net_device *dev = gp->dev;
2768 const unsigned char *addr;
2769
2770 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2771 if (addr == NULL) {
2772 #ifdef CONFIG_SPARC
2773 addr = idprom->id_ethaddr;
2774 #else
2775 printk("\n");
2776 pr_err("%s: can't get mac-address\n", dev->name);
2777 return -1;
2778 #endif
2779 }
2780 memcpy(dev->dev_addr, addr, ETH_ALEN);
2781 #else
2782 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2783 #endif
2784 return 0;
2785 }
2786
2787 static void gem_remove_one(struct pci_dev *pdev)
2788 {
2789 struct net_device *dev = pci_get_drvdata(pdev);
2790
2791 if (dev) {
2792 struct gem *gp = netdev_priv(dev);
2793
2794 unregister_netdev(dev);
2795
2796 /* Ensure reset task is truly gone */
2797 cancel_work_sync(&gp->reset_task);
2798
2799 /* Free resources */
2800 pci_free_consistent(pdev,
2801 sizeof(struct gem_init_block),
2802 gp->init_block,
2803 gp->gblock_dvma);
2804 iounmap(gp->regs);
2805 pci_release_regions(pdev);
2806 free_netdev(dev);
2807 }
2808 }
2809
2810 static const struct net_device_ops gem_netdev_ops = {
2811 .ndo_open = gem_open,
2812 .ndo_stop = gem_close,
2813 .ndo_start_xmit = gem_start_xmit,
2814 .ndo_get_stats = gem_get_stats,
2815 .ndo_set_rx_mode = gem_set_multicast,
2816 .ndo_do_ioctl = gem_ioctl,
2817 .ndo_tx_timeout = gem_tx_timeout,
2818 .ndo_change_mtu = gem_change_mtu,
2819 .ndo_validate_addr = eth_validate_addr,
2820 .ndo_set_mac_address = gem_set_mac_address,
2821 #ifdef CONFIG_NET_POLL_CONTROLLER
2822 .ndo_poll_controller = gem_poll_controller,
2823 #endif
2824 };
2825
2826 static int gem_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2827 {
2828 unsigned long gemreg_base, gemreg_len;
2829 struct net_device *dev;
2830 struct gem *gp;
2831 int err, pci_using_dac;
2832
2833 printk_once(KERN_INFO "%s", version);
2834
2835 /* Apple gmac note: during probe, the chip is powered up by
2836 * the arch code to allow the code below to work (and to let
2837 * the chip be probed on the config space. It won't stay powered
2838 * up until the interface is brought up however, so we can't rely
2839 * on register configuration done at this point.
2840 */
2841 err = pci_enable_device(pdev);
2842 if (err) {
2843 pr_err("Cannot enable MMIO operation, aborting\n");
2844 return err;
2845 }
2846 pci_set_master(pdev);
2847
2848 /* Configure DMA attributes. */
2849
2850 /* All of the GEM documentation states that 64-bit DMA addressing
2851 * is fully supported and should work just fine. However the
2852 * front end for RIO based GEMs is different and only supports
2853 * 32-bit addressing.
2854 *
2855 * For now we assume the various PPC GEMs are 32-bit only as well.
2856 */
2857 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2858 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2859 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2860 pci_using_dac = 1;
2861 } else {
2862 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2863 if (err) {
2864 pr_err("No usable DMA configuration, aborting\n");
2865 goto err_disable_device;
2866 }
2867 pci_using_dac = 0;
2868 }
2869
2870 gemreg_base = pci_resource_start(pdev, 0);
2871 gemreg_len = pci_resource_len(pdev, 0);
2872
2873 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2874 pr_err("Cannot find proper PCI device base address, aborting\n");
2875 err = -ENODEV;
2876 goto err_disable_device;
2877 }
2878
2879 dev = alloc_etherdev(sizeof(*gp));
2880 if (!dev) {
2881 err = -ENOMEM;
2882 goto err_disable_device;
2883 }
2884 SET_NETDEV_DEV(dev, &pdev->dev);
2885
2886 gp = netdev_priv(dev);
2887
2888 err = pci_request_regions(pdev, DRV_NAME);
2889 if (err) {
2890 pr_err("Cannot obtain PCI resources, aborting\n");
2891 goto err_out_free_netdev;
2892 }
2893
2894 gp->pdev = pdev;
2895 gp->dev = dev;
2896
2897 gp->msg_enable = DEFAULT_MSG;
2898
2899 init_timer(&gp->link_timer);
2900 gp->link_timer.function = gem_link_timer;
2901 gp->link_timer.data = (unsigned long) gp;
2902
2903 INIT_WORK(&gp->reset_task, gem_reset_task);
2904
2905 gp->lstate = link_down;
2906 gp->timer_ticks = 0;
2907 netif_carrier_off(dev);
2908
2909 gp->regs = ioremap(gemreg_base, gemreg_len);
2910 if (!gp->regs) {
2911 pr_err("Cannot map device registers, aborting\n");
2912 err = -EIO;
2913 goto err_out_free_res;
2914 }
2915
2916 /* On Apple, we want a reference to the Open Firmware device-tree
2917 * node. We use it for clock control.
2918 */
2919 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
2920 gp->of_node = pci_device_to_OF_node(pdev);
2921 #endif
2922
2923 /* Only Apple version supports WOL afaik */
2924 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2925 gp->has_wol = 1;
2926
2927 /* Make sure cell is enabled */
2928 gem_get_cell(gp);
2929
2930 /* Make sure everything is stopped and in init state */
2931 gem_reset(gp);
2932
2933 /* Fill up the mii_phy structure (even if we won't use it) */
2934 gp->phy_mii.dev = dev;
2935 gp->phy_mii.mdio_read = _sungem_phy_read;
2936 gp->phy_mii.mdio_write = _sungem_phy_write;
2937 #ifdef CONFIG_PPC_PMAC
2938 gp->phy_mii.platform_data = gp->of_node;
2939 #endif
2940 /* By default, we start with autoneg */
2941 gp->want_autoneg = 1;
2942
2943 /* Check fifo sizes, PHY type, etc... */
2944 if (gem_check_invariants(gp)) {
2945 err = -ENODEV;
2946 goto err_out_iounmap;
2947 }
2948
2949 /* It is guaranteed that the returned buffer will be at least
2950 * PAGE_SIZE aligned.
2951 */
2952 gp->init_block = (struct gem_init_block *)
2953 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
2954 &gp->gblock_dvma);
2955 if (!gp->init_block) {
2956 pr_err("Cannot allocate init block, aborting\n");
2957 err = -ENOMEM;
2958 goto err_out_iounmap;
2959 }
2960
2961 err = gem_get_device_address(gp);
2962 if (err)
2963 goto err_out_free_consistent;
2964
2965 dev->netdev_ops = &gem_netdev_ops;
2966 netif_napi_add(dev, &gp->napi, gem_poll, 64);
2967 dev->ethtool_ops = &gem_ethtool_ops;
2968 dev->watchdog_timeo = 5 * HZ;
2969 dev->dma = 0;
2970
2971 /* Set that now, in case PM kicks in now */
2972 pci_set_drvdata(pdev, dev);
2973
2974 /* We can do scatter/gather and HW checksum */
2975 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
2976 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
2977 if (pci_using_dac)
2978 dev->features |= NETIF_F_HIGHDMA;
2979
2980 /* Register with kernel */
2981 if (register_netdev(dev)) {
2982 pr_err("Cannot register net device, aborting\n");
2983 err = -ENOMEM;
2984 goto err_out_free_consistent;
2985 }
2986
2987 /* Undo the get_cell with appropriate locking (we could use
2988 * ndo_init/uninit but that would be even more clumsy imho)
2989 */
2990 rtnl_lock();
2991 gem_put_cell(gp);
2992 rtnl_unlock();
2993
2994 netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
2995 dev->dev_addr);
2996 return 0;
2997
2998 err_out_free_consistent:
2999 gem_remove_one(pdev);
3000 err_out_iounmap:
3001 gem_put_cell(gp);
3002 iounmap(gp->regs);
3003
3004 err_out_free_res:
3005 pci_release_regions(pdev);
3006
3007 err_out_free_netdev:
3008 free_netdev(dev);
3009 err_disable_device:
3010 pci_disable_device(pdev);
3011 return err;
3012
3013 }
3014
3015
3016 static struct pci_driver gem_driver = {
3017 .name = GEM_MODULE_NAME,
3018 .id_table = gem_pci_tbl,
3019 .probe = gem_init_one,
3020 .remove = gem_remove_one,
3021 #ifdef CONFIG_PM
3022 .suspend = gem_suspend,
3023 .resume = gem_resume,
3024 #endif /* CONFIG_PM */
3025 };
3026
3027 module_pci_driver(gem_driver);
Linux with added FPC-III support