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Linux 3.2.36
[linux/fpc-iii.git] / drivers / tty / serial / imx.c
blob8e68f792d84d6099601b196d60a9072c4a83645b
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50
51 #include <asm/io.h>
52 #include <asm/irq.h>
53 #include <mach/imx-uart.h>
54
55 /* Register definitions */
56 #define URXD0 0x0 /* Receiver Register */
57 #define URTX0 0x40 /* Transmitter Register */
58 #define UCR1 0x80 /* Control Register 1 */
59 #define UCR2 0x84 /* Control Register 2 */
60 #define UCR3 0x88 /* Control Register 3 */
61 #define UCR4 0x8c /* Control Register 4 */
62 #define UFCR 0x90 /* FIFO Control Register */
63 #define USR1 0x94 /* Status Register 1 */
64 #define USR2 0x98 /* Status Register 2 */
65 #define UESC 0x9c /* Escape Character Register */
66 #define UTIM 0xa0 /* Escape Timer Register */
67 #define UBIR 0xa4 /* BRM Incremental Register */
68 #define UBMR 0xa8 /* BRM Modulator Register */
69 #define UBRC 0xac /* Baud Rate Count Register */
70 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
71 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
72 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
73
74 /* UART Control Register Bit Fields.*/
75 #define URXD_CHARRDY (1<<15)
76 #define URXD_ERR (1<<14)
77 #define URXD_OVRRUN (1<<13)
78 #define URXD_FRMERR (1<<12)
79 #define URXD_BRK (1<<11)
80 #define URXD_PRERR (1<<10)
81 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
93 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
106 #define UCR2_RXEN (1<<1) /* Receiver enabled */
107 #define UCR2_SRST (1<<0) /* SW reset */
108 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109 #define UCR3_PARERREN (1<<12) /* Parity enable */
110 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111 #define UCR3_DSR (1<<10) /* Data set ready */
112 #define UCR3_DCD (1<<9) /* Data carrier detect */
113 #define UCR3_RI (1<<8) /* Ring indicator */
114 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
119 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
120 #define UCR3_BPEN (1<<0) /* Preset registers enable */
121 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
122 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IRSC (1<<5) /* IR special case */
128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
134 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
135 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
136 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
137 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
138 #define USR1_RTSS (1<<14) /* RTS pin status */
139 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
140 #define USR1_RTSD (1<<12) /* RTS delta */
141 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
142 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
143 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
144 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
145 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
146 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
147 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
148 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
149 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
150 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
151 #define USR2_IDLE (1<<12) /* Idle condition */
152 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
153 #define USR2_WAKE (1<<7) /* Wake */
154 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
155 #define USR2_TXDC (1<<3) /* Transmitter complete */
156 #define USR2_BRCD (1<<2) /* Break condition */
157 #define USR2_ORE (1<<1) /* Overrun error */
158 #define USR2_RDR (1<<0) /* Recv data ready */
159 #define UTS_FRCPERR (1<<13) /* Force parity error */
160 #define UTS_LOOP (1<<12) /* Loop tx and rx */
161 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
162 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
163 #define UTS_TXFULL (1<<4) /* TxFIFO full */
164 #define UTS_RXFULL (1<<3) /* RxFIFO full */
165 #define UTS_SOFTRST (1<<0) /* Software reset */
166
167 /* We've been assigned a range on the "Low-density serial ports" major */
168 #define SERIAL_IMX_MAJOR 207
169 #define MINOR_START 16
170 #define DEV_NAME "ttymxc"
171 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
172
173 /*
174 * This determines how often we check the modem status signals
175 * for any change. They generally aren't connected to an IRQ
176 * so we have to poll them. We also check immediately before
177 * filling the TX fifo incase CTS has been dropped.
178 */
179 #define MCTRL_TIMEOUT (250*HZ/1000)
180
181 #define DRIVER_NAME "IMX-uart"
182
183 #define UART_NR 8
184
185 /* i.mx21 type uart runs on all i.mx except i.mx1 */
186 enum imx_uart_type {
187 IMX1_UART,
188 IMX21_UART,
189 };
190
191 /* device type dependent stuff */
192 struct imx_uart_data {
193 unsigned uts_reg;
194 enum imx_uart_type devtype;
195 };
196
197 struct imx_port {
198 struct uart_port port;
199 struct timer_list timer;
200 unsigned int old_status;
201 int txirq,rxirq,rtsirq;
202 unsigned int have_rtscts:1;
203 unsigned int use_irda:1;
204 unsigned int irda_inv_rx:1;
205 unsigned int irda_inv_tx:1;
206 unsigned short trcv_delay; /* transceiver delay */
207 struct clk *clk;
208 struct imx_uart_data *devdata;
209 };
210
211 #ifdef CONFIG_IRDA
212 #define USE_IRDA(sport) ((sport)->use_irda)
213 #else
214 #define USE_IRDA(sport) (0)
215 #endif
216
217 static struct imx_uart_data imx_uart_devdata[] = {
218 [IMX1_UART] = {
219 .uts_reg = IMX1_UTS,
220 .devtype = IMX1_UART,
221 },
222 [IMX21_UART] = {
223 .uts_reg = IMX21_UTS,
224 .devtype = IMX21_UART,
225 },
226 };
227
228 static struct platform_device_id imx_uart_devtype[] = {
229 {
230 .name = "imx1-uart",
231 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
232 }, {
233 .name = "imx21-uart",
234 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
235 }, {
236 /* sentinel */
237 }
238 };
239 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
240
241 static struct of_device_id imx_uart_dt_ids[] = {
242 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
243 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
244 { /* sentinel */ }
245 };
246 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
247
248 static inline unsigned uts_reg(struct imx_port *sport)
249 {
250 return sport->devdata->uts_reg;
251 }
252
253 static inline int is_imx1_uart(struct imx_port *sport)
254 {
255 return sport->devdata->devtype == IMX1_UART;
256 }
257
258 static inline int is_imx21_uart(struct imx_port *sport)
259 {
260 return sport->devdata->devtype == IMX21_UART;
261 }
262
263 /*
264 * Handle any change of modem status signal since we were last called.
265 */
266 static void imx_mctrl_check(struct imx_port *sport)
267 {
268 unsigned int status, changed;
269
270 status = sport->port.ops->get_mctrl(&sport->port);
271 changed = status ^ sport->old_status;
272
273 if (changed == 0)
274 return;
275
276 sport->old_status = status;
277
278 if (changed & TIOCM_RI)
279 sport->port.icount.rng++;
280 if (changed & TIOCM_DSR)
281 sport->port.icount.dsr++;
282 if (changed & TIOCM_CAR)
283 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
284 if (changed & TIOCM_CTS)
285 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
286
287 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
288 }
289
290 /*
291 * This is our per-port timeout handler, for checking the
292 * modem status signals.
293 */
294 static void imx_timeout(unsigned long data)
295 {
296 struct imx_port *sport = (struct imx_port *)data;
297 unsigned long flags;
298
299 if (sport->port.state) {
300 spin_lock_irqsave(&sport->port.lock, flags);
301 imx_mctrl_check(sport);
302 spin_unlock_irqrestore(&sport->port.lock, flags);
303
304 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
305 }
306 }
307
308 /*
309 * interrupts disabled on entry
310 */
311 static void imx_stop_tx(struct uart_port *port)
312 {
313 struct imx_port *sport = (struct imx_port *)port;
314 unsigned long temp;
315
316 if (USE_IRDA(sport)) {
317 /* half duplex - wait for end of transmission */
318 int n = 256;
319 while ((--n > 0) &&
320 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
321 udelay(5);
322 barrier();
323 }
324 /*
325 * irda transceiver - wait a bit more to avoid
326 * cutoff, hardware dependent
327 */
328 udelay(sport->trcv_delay);
329
330 /*
331 * half duplex - reactivate receive mode,
332 * flush receive pipe echo crap
333 */
334 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
335 temp = readl(sport->port.membase + UCR1);
336 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
337 writel(temp, sport->port.membase + UCR1);
338
339 temp = readl(sport->port.membase + UCR4);
340 temp &= ~(UCR4_TCEN);
341 writel(temp, sport->port.membase + UCR4);
342
343 while (readl(sport->port.membase + URXD0) &
344 URXD_CHARRDY)
345 barrier();
346
347 temp = readl(sport->port.membase + UCR1);
348 temp |= UCR1_RRDYEN;
349 writel(temp, sport->port.membase + UCR1);
350
351 temp = readl(sport->port.membase + UCR4);
352 temp |= UCR4_DREN;
353 writel(temp, sport->port.membase + UCR4);
354 }
355 return;
356 }
357
358 temp = readl(sport->port.membase + UCR1);
359 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
360 }
361
362 /*
363 * interrupts disabled on entry
364 */
365 static void imx_stop_rx(struct uart_port *port)
366 {
367 struct imx_port *sport = (struct imx_port *)port;
368 unsigned long temp;
369
370 temp = readl(sport->port.membase + UCR2);
371 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
372 }
373
374 /*
375 * Set the modem control timer to fire immediately.
376 */
377 static void imx_enable_ms(struct uart_port *port)
378 {
379 struct imx_port *sport = (struct imx_port *)port;
380
381 mod_timer(&sport->timer, jiffies);
382 }
383
384 static inline void imx_transmit_buffer(struct imx_port *sport)
385 {
386 struct circ_buf *xmit = &sport->port.state->xmit;
387
388 while (!uart_circ_empty(xmit) &&
389 !(readl(sport->port.membase + uts_reg(sport))
390 & UTS_TXFULL)) {
391 /* send xmit->buf[xmit->tail]
392 * out the port here */
393 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
394 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
395 sport->port.icount.tx++;
396 }
397
398 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
399 uart_write_wakeup(&sport->port);
400
401 if (uart_circ_empty(xmit))
402 imx_stop_tx(&sport->port);
403 }
404
405 /*
406 * interrupts disabled on entry
407 */
408 static void imx_start_tx(struct uart_port *port)
409 {
410 struct imx_port *sport = (struct imx_port *)port;
411 unsigned long temp;
412
413 if (USE_IRDA(sport)) {
414 /* half duplex in IrDA mode; have to disable receive mode */
415 temp = readl(sport->port.membase + UCR4);
416 temp &= ~(UCR4_DREN);
417 writel(temp, sport->port.membase + UCR4);
418
419 temp = readl(sport->port.membase + UCR1);
420 temp &= ~(UCR1_RRDYEN);
421 writel(temp, sport->port.membase + UCR1);
422 }
423
424 temp = readl(sport->port.membase + UCR1);
425 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
426
427 if (USE_IRDA(sport)) {
428 temp = readl(sport->port.membase + UCR1);
429 temp |= UCR1_TRDYEN;
430 writel(temp, sport->port.membase + UCR1);
431
432 temp = readl(sport->port.membase + UCR4);
433 temp |= UCR4_TCEN;
434 writel(temp, sport->port.membase + UCR4);
435 }
436
437 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
438 imx_transmit_buffer(sport);
439 }
440
441 static irqreturn_t imx_rtsint(int irq, void *dev_id)
442 {
443 struct imx_port *sport = dev_id;
444 unsigned int val;
445 unsigned long flags;
446
447 spin_lock_irqsave(&sport->port.lock, flags);
448
449 writel(USR1_RTSD, sport->port.membase + USR1);
450 val = readl(sport->port.membase + USR1) & USR1_RTSS;
451 uart_handle_cts_change(&sport->port, !!val);
452 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
453
454 spin_unlock_irqrestore(&sport->port.lock, flags);
455 return IRQ_HANDLED;
456 }
457
458 static irqreturn_t imx_txint(int irq, void *dev_id)
459 {
460 struct imx_port *sport = dev_id;
461 struct circ_buf *xmit = &sport->port.state->xmit;
462 unsigned long flags;
463
464 spin_lock_irqsave(&sport->port.lock,flags);
465 if (sport->port.x_char)
466 {
467 /* Send next char */
468 writel(sport->port.x_char, sport->port.membase + URTX0);
469 goto out;
470 }
471
472 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
473 imx_stop_tx(&sport->port);
474 goto out;
475 }
476
477 imx_transmit_buffer(sport);
478
479 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
480 uart_write_wakeup(&sport->port);
481
482 out:
483 spin_unlock_irqrestore(&sport->port.lock,flags);
484 return IRQ_HANDLED;
485 }
486
487 static irqreturn_t imx_rxint(int irq, void *dev_id)
488 {
489 struct imx_port *sport = dev_id;
490 unsigned int rx,flg,ignored = 0;
491 struct tty_struct *tty = sport->port.state->port.tty;
492 unsigned long flags, temp;
493
494 spin_lock_irqsave(&sport->port.lock,flags);
495
496 while (readl(sport->port.membase + USR2) & USR2_RDR) {
497 flg = TTY_NORMAL;
498 sport->port.icount.rx++;
499
500 rx = readl(sport->port.membase + URXD0);
501
502 temp = readl(sport->port.membase + USR2);
503 if (temp & USR2_BRCD) {
504 writel(USR2_BRCD, sport->port.membase + USR2);
505 if (uart_handle_break(&sport->port))
506 continue;
507 }
508
509 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
510 continue;
511
512 if (unlikely(rx & URXD_ERR)) {
513 if (rx & URXD_BRK)
514 sport->port.icount.brk++;
515 else if (rx & URXD_PRERR)
516 sport->port.icount.parity++;
517 else if (rx & URXD_FRMERR)
518 sport->port.icount.frame++;
519 if (rx & URXD_OVRRUN)
520 sport->port.icount.overrun++;
521
522 if (rx & sport->port.ignore_status_mask) {
523 if (++ignored > 100)
524 goto out;
525 continue;
526 }
527
528 rx &= sport->port.read_status_mask;
529
530 if (rx & URXD_BRK)
531 flg = TTY_BREAK;
532 else if (rx & URXD_PRERR)
533 flg = TTY_PARITY;
534 else if (rx & URXD_FRMERR)
535 flg = TTY_FRAME;
536 if (rx & URXD_OVRRUN)
537 flg = TTY_OVERRUN;
538
539 #ifdef SUPPORT_SYSRQ
540 sport->port.sysrq = 0;
541 #endif
542 }
543
544 tty_insert_flip_char(tty, rx, flg);
545 }
546
547 out:
548 spin_unlock_irqrestore(&sport->port.lock,flags);
549 tty_flip_buffer_push(tty);
550 return IRQ_HANDLED;
551 }
552
553 static irqreturn_t imx_int(int irq, void *dev_id)
554 {
555 struct imx_port *sport = dev_id;
556 unsigned int sts;
557
558 sts = readl(sport->port.membase + USR1);
559
560 if (sts & USR1_RRDY)
561 imx_rxint(irq, dev_id);
562
563 if (sts & USR1_TRDY &&
564 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
565 imx_txint(irq, dev_id);
566
567 if (sts & USR1_RTSD)
568 imx_rtsint(irq, dev_id);
569
570 return IRQ_HANDLED;
571 }
572
573 /*
574 * Return TIOCSER_TEMT when transmitter is not busy.
575 */
576 static unsigned int imx_tx_empty(struct uart_port *port)
577 {
578 struct imx_port *sport = (struct imx_port *)port;
579
580 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
581 }
582
583 /*
584 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
585 */
586 static unsigned int imx_get_mctrl(struct uart_port *port)
587 {
588 struct imx_port *sport = (struct imx_port *)port;
589 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
590
591 if (readl(sport->port.membase + USR1) & USR1_RTSS)
592 tmp |= TIOCM_CTS;
593
594 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
595 tmp |= TIOCM_RTS;
596
597 return tmp;
598 }
599
600 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
601 {
602 struct imx_port *sport = (struct imx_port *)port;
603 unsigned long temp;
604
605 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
606
607 if (mctrl & TIOCM_RTS)
608 temp |= UCR2_CTS;
609
610 writel(temp, sport->port.membase + UCR2);
611 }
612
613 /*
614 * Interrupts always disabled.
615 */
616 static void imx_break_ctl(struct uart_port *port, int break_state)
617 {
618 struct imx_port *sport = (struct imx_port *)port;
619 unsigned long flags, temp;
620
621 spin_lock_irqsave(&sport->port.lock, flags);
622
623 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
624
625 if ( break_state != 0 )
626 temp |= UCR1_SNDBRK;
627
628 writel(temp, sport->port.membase + UCR1);
629
630 spin_unlock_irqrestore(&sport->port.lock, flags);
631 }
632
633 #define TXTL 2 /* reset default */
634 #define RXTL 1 /* reset default */
635
636 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
637 {
638 unsigned int val;
639
640 /* set receiver / transmitter trigger level */
641 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
642 val |= TXTL << UFCR_TXTL_SHF | RXTL;
643 writel(val, sport->port.membase + UFCR);
644 return 0;
645 }
646
647 /* half the RX buffer size */
648 #define CTSTL 16
649
650 static int imx_startup(struct uart_port *port)
651 {
652 struct imx_port *sport = (struct imx_port *)port;
653 int retval;
654 unsigned long flags, temp;
655
656 imx_setup_ufcr(sport, 0);
657
658 /* disable the DREN bit (Data Ready interrupt enable) before
659 * requesting IRQs
660 */
661 temp = readl(sport->port.membase + UCR4);
662
663 if (USE_IRDA(sport))
664 temp |= UCR4_IRSC;
665
666 /* set the trigger level for CTS */
667 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
668 temp |= CTSTL<< UCR4_CTSTL_SHF;
669
670 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
671
672 if (USE_IRDA(sport)) {
673 /* reset fifo's and state machines */
674 int i = 100;
675 temp = readl(sport->port.membase + UCR2);
676 temp &= ~UCR2_SRST;
677 writel(temp, sport->port.membase + UCR2);
678 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
679 (--i > 0)) {
680 udelay(1);
681 }
682 }
683
684 /*
685 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
686 * chips only have one interrupt.
687 */
688 if (sport->txirq > 0) {
689 retval = request_irq(sport->rxirq, imx_rxint, 0,
690 DRIVER_NAME, sport);
691 if (retval)
692 goto error_out1;
693
694 retval = request_irq(sport->txirq, imx_txint, 0,
695 DRIVER_NAME, sport);
696 if (retval)
697 goto error_out2;
698
699 /* do not use RTS IRQ on IrDA */
700 if (!USE_IRDA(sport)) {
701 retval = request_irq(sport->rtsirq, imx_rtsint,
702 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
703 IRQF_TRIGGER_FALLING |
704 IRQF_TRIGGER_RISING,
705 DRIVER_NAME, sport);
706 if (retval)
707 goto error_out3;
708 }
709 } else {
710 retval = request_irq(sport->port.irq, imx_int, 0,
711 DRIVER_NAME, sport);
712 if (retval) {
713 free_irq(sport->port.irq, sport);
714 goto error_out1;
715 }
716 }
717
718 spin_lock_irqsave(&sport->port.lock, flags);
719 /*
720 * Finally, clear and enable interrupts
721 */
722 writel(USR1_RTSD, sport->port.membase + USR1);
723
724 temp = readl(sport->port.membase + UCR1);
725 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
726
727 if (USE_IRDA(sport)) {
728 temp |= UCR1_IREN;
729 temp &= ~(UCR1_RTSDEN);
730 }
731
732 writel(temp, sport->port.membase + UCR1);
733
734 temp = readl(sport->port.membase + UCR2);
735 temp |= (UCR2_RXEN | UCR2_TXEN);
736 writel(temp, sport->port.membase + UCR2);
737
738 if (USE_IRDA(sport)) {
739 /* clear RX-FIFO */
740 int i = 64;
741 while ((--i > 0) &&
742 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
743 barrier();
744 }
745 }
746
747 if (is_imx21_uart(sport)) {
748 temp = readl(sport->port.membase + UCR3);
749 temp |= IMX21_UCR3_RXDMUXSEL;
750 writel(temp, sport->port.membase + UCR3);
751 }
752
753 if (USE_IRDA(sport)) {
754 temp = readl(sport->port.membase + UCR4);
755 if (sport->irda_inv_rx)
756 temp |= UCR4_INVR;
757 else
758 temp &= ~(UCR4_INVR);
759 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
760
761 temp = readl(sport->port.membase + UCR3);
762 if (sport->irda_inv_tx)
763 temp |= UCR3_INVT;
764 else
765 temp &= ~(UCR3_INVT);
766 writel(temp, sport->port.membase + UCR3);
767 }
768
769 /*
770 * Enable modem status interrupts
771 */
772 imx_enable_ms(&sport->port);
773 spin_unlock_irqrestore(&sport->port.lock,flags);
774
775 if (USE_IRDA(sport)) {
776 struct imxuart_platform_data *pdata;
777 pdata = sport->port.dev->platform_data;
778 sport->irda_inv_rx = pdata->irda_inv_rx;
779 sport->irda_inv_tx = pdata->irda_inv_tx;
780 sport->trcv_delay = pdata->transceiver_delay;
781 if (pdata->irda_enable)
782 pdata->irda_enable(1);
783 }
784
785 return 0;
786
787 error_out3:
788 if (sport->txirq)
789 free_irq(sport->txirq, sport);
790 error_out2:
791 if (sport->rxirq)
792 free_irq(sport->rxirq, sport);
793 error_out1:
794 return retval;
795 }
796
797 static void imx_shutdown(struct uart_port *port)
798 {
799 struct imx_port *sport = (struct imx_port *)port;
800 unsigned long temp;
801 unsigned long flags;
802
803 spin_lock_irqsave(&sport->port.lock, flags);
804 temp = readl(sport->port.membase + UCR2);
805 temp &= ~(UCR2_TXEN);
806 writel(temp, sport->port.membase + UCR2);
807 spin_unlock_irqrestore(&sport->port.lock, flags);
808
809 if (USE_IRDA(sport)) {
810 struct imxuart_platform_data *pdata;
811 pdata = sport->port.dev->platform_data;
812 if (pdata->irda_enable)
813 pdata->irda_enable(0);
814 }
815
816 /*
817 * Stop our timer.
818 */
819 del_timer_sync(&sport->timer);
820
821 /*
822 * Free the interrupts
823 */
824 if (sport->txirq > 0) {
825 if (!USE_IRDA(sport))
826 free_irq(sport->rtsirq, sport);
827 free_irq(sport->txirq, sport);
828 free_irq(sport->rxirq, sport);
829 } else
830 free_irq(sport->port.irq, sport);
831
832 /*
833 * Disable all interrupts, port and break condition.
834 */
835
836 spin_lock_irqsave(&sport->port.lock, flags);
837 temp = readl(sport->port.membase + UCR1);
838 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
839 if (USE_IRDA(sport))
840 temp &= ~(UCR1_IREN);
841
842 writel(temp, sport->port.membase + UCR1);
843 spin_unlock_irqrestore(&sport->port.lock, flags);
844 }
845
846 static void
847 imx_set_termios(struct uart_port *port, struct ktermios *termios,
848 struct ktermios *old)
849 {
850 struct imx_port *sport = (struct imx_port *)port;
851 unsigned long flags;
852 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
853 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
854 unsigned int div, ufcr;
855 unsigned long num, denom;
856 uint64_t tdiv64;
857
858 /*
859 * If we don't support modem control lines, don't allow
860 * these to be set.
861 */
862 if (0) {
863 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
864 termios->c_cflag |= CLOCAL;
865 }
866
867 /*
868 * We only support CS7 and CS8.
869 */
870 while ((termios->c_cflag & CSIZE) != CS7 &&
871 (termios->c_cflag & CSIZE) != CS8) {
872 termios->c_cflag &= ~CSIZE;
873 termios->c_cflag |= old_csize;
874 old_csize = CS8;
875 }
876
877 if ((termios->c_cflag & CSIZE) == CS8)
878 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
879 else
880 ucr2 = UCR2_SRST | UCR2_IRTS;
881
882 if (termios->c_cflag & CRTSCTS) {
883 if( sport->have_rtscts ) {
884 ucr2 &= ~UCR2_IRTS;
885 ucr2 |= UCR2_CTSC;
886 } else {
887 termios->c_cflag &= ~CRTSCTS;
888 }
889 }
890
891 if (termios->c_cflag & CSTOPB)
892 ucr2 |= UCR2_STPB;
893 if (termios->c_cflag & PARENB) {
894 ucr2 |= UCR2_PREN;
895 if (termios->c_cflag & PARODD)
896 ucr2 |= UCR2_PROE;
897 }
898
899 /*
900 * Ask the core to calculate the divisor for us.
901 */
902 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
903 quot = uart_get_divisor(port, baud);
904
905 spin_lock_irqsave(&sport->port.lock, flags);
906
907 sport->port.read_status_mask = 0;
908 if (termios->c_iflag & INPCK)
909 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
910 if (termios->c_iflag & (BRKINT | PARMRK))
911 sport->port.read_status_mask |= URXD_BRK;
912
913 /*
914 * Characters to ignore
915 */
916 sport->port.ignore_status_mask = 0;
917 if (termios->c_iflag & IGNPAR)
918 sport->port.ignore_status_mask |= URXD_PRERR;
919 if (termios->c_iflag & IGNBRK) {
920 sport->port.ignore_status_mask |= URXD_BRK;
921 /*
922 * If we're ignoring parity and break indicators,
923 * ignore overruns too (for real raw support).
924 */
925 if (termios->c_iflag & IGNPAR)
926 sport->port.ignore_status_mask |= URXD_OVRRUN;
927 }
928
929 del_timer_sync(&sport->timer);
930
931 /*
932 * Update the per-port timeout.
933 */
934 uart_update_timeout(port, termios->c_cflag, baud);
935
936 /*
937 * disable interrupts and drain transmitter
938 */
939 old_ucr1 = readl(sport->port.membase + UCR1);
940 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
941 sport->port.membase + UCR1);
942
943 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
944 barrier();
945
946 /* then, disable everything */
947 old_txrxen = readl(sport->port.membase + UCR2);
948 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
949 sport->port.membase + UCR2);
950 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
951
952 if (USE_IRDA(sport)) {
953 /*
954 * use maximum available submodule frequency to
955 * avoid missing short pulses due to low sampling rate
956 */
957 div = 1;
958 } else {
959 div = sport->port.uartclk / (baud * 16);
960 if (div > 7)
961 div = 7;
962 if (!div)
963 div = 1;
964 }
965
966 rational_best_approximation(16 * div * baud, sport->port.uartclk,
967 1 << 16, 1 << 16, &num, &denom);
968
969 tdiv64 = sport->port.uartclk;
970 tdiv64 *= num;
971 do_div(tdiv64, denom * 16 * div);
972 tty_termios_encode_baud_rate(termios,
973 (speed_t)tdiv64, (speed_t)tdiv64);
974
975 num -= 1;
976 denom -= 1;
977
978 ufcr = readl(sport->port.membase + UFCR);
979 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
980 writel(ufcr, sport->port.membase + UFCR);
981
982 writel(num, sport->port.membase + UBIR);
983 writel(denom, sport->port.membase + UBMR);
984
985 if (is_imx21_uart(sport))
986 writel(sport->port.uartclk / div / 1000,
987 sport->port.membase + IMX21_ONEMS);
988
989 writel(old_ucr1, sport->port.membase + UCR1);
990
991 /* set the parity, stop bits and data size */
992 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
993
994 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
995 imx_enable_ms(&sport->port);
996
997 spin_unlock_irqrestore(&sport->port.lock, flags);
998 }
999
1000 static const char *imx_type(struct uart_port *port)
1001 {
1002 struct imx_port *sport = (struct imx_port *)port;
1003
1004 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1005 }
1006
1007 /*
1008 * Release the memory region(s) being used by 'port'.
1009 */
1010 static void imx_release_port(struct uart_port *port)
1011 {
1012 struct platform_device *pdev = to_platform_device(port->dev);
1013 struct resource *mmres;
1014
1015 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1016 release_mem_region(mmres->start, resource_size(mmres));
1017 }
1018
1019 /*
1020 * Request the memory region(s) being used by 'port'.
1021 */
1022 static int imx_request_port(struct uart_port *port)
1023 {
1024 struct platform_device *pdev = to_platform_device(port->dev);
1025 struct resource *mmres;
1026 void *ret;
1027
1028 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1029 if (!mmres)
1030 return -ENODEV;
1031
1032 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1033
1034 return ret ? 0 : -EBUSY;
1035 }
1036
1037 /*
1038 * Configure/autoconfigure the port.
1039 */
1040 static void imx_config_port(struct uart_port *port, int flags)
1041 {
1042 struct imx_port *sport = (struct imx_port *)port;
1043
1044 if (flags & UART_CONFIG_TYPE &&
1045 imx_request_port(&sport->port) == 0)
1046 sport->port.type = PORT_IMX;
1047 }
1048
1049 /*
1050 * Verify the new serial_struct (for TIOCSSERIAL).
1051 * The only change we allow are to the flags and type, and
1052 * even then only between PORT_IMX and PORT_UNKNOWN
1053 */
1054 static int
1055 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1056 {
1057 struct imx_port *sport = (struct imx_port *)port;
1058 int ret = 0;
1059
1060 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1061 ret = -EINVAL;
1062 if (sport->port.irq != ser->irq)
1063 ret = -EINVAL;
1064 if (ser->io_type != UPIO_MEM)
1065 ret = -EINVAL;
1066 if (sport->port.uartclk / 16 != ser->baud_base)
1067 ret = -EINVAL;
1068 if ((void *)sport->port.mapbase != ser->iomem_base)
1069 ret = -EINVAL;
1070 if (sport->port.iobase != ser->port)
1071 ret = -EINVAL;
1072 if (ser->hub6 != 0)
1073 ret = -EINVAL;
1074 return ret;
1075 }
1076
1077 static struct uart_ops imx_pops = {
1078 .tx_empty = imx_tx_empty,
1079 .set_mctrl = imx_set_mctrl,
1080 .get_mctrl = imx_get_mctrl,
1081 .stop_tx = imx_stop_tx,
1082 .start_tx = imx_start_tx,
1083 .stop_rx = imx_stop_rx,
1084 .enable_ms = imx_enable_ms,
1085 .break_ctl = imx_break_ctl,
1086 .startup = imx_startup,
1087 .shutdown = imx_shutdown,
1088 .set_termios = imx_set_termios,
1089 .type = imx_type,
1090 .release_port = imx_release_port,
1091 .request_port = imx_request_port,
1092 .config_port = imx_config_port,
1093 .verify_port = imx_verify_port,
1094 };
1095
1096 static struct imx_port *imx_ports[UART_NR];
1097
1098 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1099 static void imx_console_putchar(struct uart_port *port, int ch)
1100 {
1101 struct imx_port *sport = (struct imx_port *)port;
1102
1103 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1104 barrier();
1105
1106 writel(ch, sport->port.membase + URTX0);
1107 }
1108
1109 /*
1110 * Interrupts are disabled on entering
1111 */
1112 static void
1113 imx_console_write(struct console *co, const char *s, unsigned int count)
1114 {
1115 struct imx_port *sport = imx_ports[co->index];
1116 unsigned int old_ucr1, old_ucr2, ucr1;
1117 unsigned long flags;
1118
1119 spin_lock_irqsave(&sport->port.lock, flags);
1120
1121 /*
1122 * First, save UCR1/2 and then disable interrupts
1123 */
1124 ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);
1125 old_ucr2 = readl(sport->port.membase + UCR2);
1126
1127 if (is_imx1_uart(sport))
1128 ucr1 |= IMX1_UCR1_UARTCLKEN;
1129 ucr1 |= UCR1_UARTEN;
1130 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1131
1132 writel(ucr1, sport->port.membase + UCR1);
1133
1134 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1135
1136 uart_console_write(&sport->port, s, count, imx_console_putchar);
1137
1138 /*
1139 * Finally, wait for transmitter to become empty
1140 * and restore UCR1/2
1141 */
1142 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1143
1144 writel(old_ucr1, sport->port.membase + UCR1);
1145 writel(old_ucr2, sport->port.membase + UCR2);
1146
1147 spin_unlock_irqrestore(&sport->port.lock, flags);
1148 }
1149
1150 /*
1151 * If the port was already initialised (eg, by a boot loader),
1152 * try to determine the current setup.
1153 */
1154 static void __init
1155 imx_console_get_options(struct imx_port *sport, int *baud,
1156 int *parity, int *bits)
1157 {
1158
1159 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1160 /* ok, the port was enabled */
1161 unsigned int ucr2, ubir,ubmr, uartclk;
1162 unsigned int baud_raw;
1163 unsigned int ucfr_rfdiv;
1164
1165 ucr2 = readl(sport->port.membase + UCR2);
1166
1167 *parity = 'n';
1168 if (ucr2 & UCR2_PREN) {
1169 if (ucr2 & UCR2_PROE)
1170 *parity = 'o';
1171 else
1172 *parity = 'e';
1173 }
1174
1175 if (ucr2 & UCR2_WS)
1176 *bits = 8;
1177 else
1178 *bits = 7;
1179
1180 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1181 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1182
1183 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1184 if (ucfr_rfdiv == 6)
1185 ucfr_rfdiv = 7;
1186 else
1187 ucfr_rfdiv = 6 - ucfr_rfdiv;
1188
1189 uartclk = clk_get_rate(sport->clk);
1190 uartclk /= ucfr_rfdiv;
1191
1192 { /*
1193 * The next code provides exact computation of
1194 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1195 * without need of float support or long long division,
1196 * which would be required to prevent 32bit arithmetic overflow
1197 */
1198 unsigned int mul = ubir + 1;
1199 unsigned int div = 16 * (ubmr + 1);
1200 unsigned int rem = uartclk % div;
1201
1202 baud_raw = (uartclk / div) * mul;
1203 baud_raw += (rem * mul + div / 2) / div;
1204 *baud = (baud_raw + 50) / 100 * 100;
1205 }
1206
1207 if(*baud != baud_raw)
1208 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1209 baud_raw, *baud);
1210 }
1211 }
1212
1213 static int __init
1214 imx_console_setup(struct console *co, char *options)
1215 {
1216 struct imx_port *sport;
1217 int baud = 9600;
1218 int bits = 8;
1219 int parity = 'n';
1220 int flow = 'n';
1221
1222 /*
1223 * Check whether an invalid uart number has been specified, and
1224 * if so, search for the first available port that does have
1225 * console support.
1226 */
1227 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1228 co->index = 0;
1229 sport = imx_ports[co->index];
1230 if(sport == NULL)
1231 return -ENODEV;
1232
1233 if (options)
1234 uart_parse_options(options, &baud, &parity, &bits, &flow);
1235 else
1236 imx_console_get_options(sport, &baud, &parity, &bits);
1237
1238 imx_setup_ufcr(sport, 0);
1239
1240 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1241 }
1242
1243 static struct uart_driver imx_reg;
1244 static struct console imx_console = {
1245 .name = DEV_NAME,
1246 .write = imx_console_write,
1247 .device = uart_console_device,
1248 .setup = imx_console_setup,
1249 .flags = CON_PRINTBUFFER,
1250 .index = -1,
1251 .data = &imx_reg,
1252 };
1253
1254 #define IMX_CONSOLE &imx_console
1255 #else
1256 #define IMX_CONSOLE NULL
1257 #endif
1258
1259 static struct uart_driver imx_reg = {
1260 .owner = THIS_MODULE,
1261 .driver_name = DRIVER_NAME,
1262 .dev_name = DEV_NAME,
1263 .major = SERIAL_IMX_MAJOR,
1264 .minor = MINOR_START,
1265 .nr = ARRAY_SIZE(imx_ports),
1266 .cons = IMX_CONSOLE,
1267 };
1268
1269 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1270 {
1271 struct imx_port *sport = platform_get_drvdata(dev);
1272
1273 if (sport)
1274 uart_suspend_port(&imx_reg, &sport->port);
1275
1276 return 0;
1277 }
1278
1279 static int serial_imx_resume(struct platform_device *dev)
1280 {
1281 struct imx_port *sport = platform_get_drvdata(dev);
1282
1283 if (sport)
1284 uart_resume_port(&imx_reg, &sport->port);
1285
1286 return 0;
1287 }
1288
1289 #ifdef CONFIG_OF
1290 static int serial_imx_probe_dt(struct imx_port *sport,
1291 struct platform_device *pdev)
1292 {
1293 struct device_node *np = pdev->dev.of_node;
1294 const struct of_device_id *of_id =
1295 of_match_device(imx_uart_dt_ids, &pdev->dev);
1296 int ret;
1297
1298 if (!np)
1299 return -ENODEV;
1300
1301 ret = of_alias_get_id(np, "serial");
1302 if (ret < 0) {
1303 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1304 return -ENODEV;
1305 }
1306 sport->port.line = ret;
1307
1308 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1309 sport->have_rtscts = 1;
1310
1311 if (of_get_property(np, "fsl,irda-mode", NULL))
1312 sport->use_irda = 1;
1313
1314 sport->devdata = of_id->data;
1315
1316 return 0;
1317 }
1318 #else
1319 static inline int serial_imx_probe_dt(struct imx_port *sport,
1320 struct platform_device *pdev)
1321 {
1322 return -ENODEV;
1323 }
1324 #endif
1325
1326 static void serial_imx_probe_pdata(struct imx_port *sport,
1327 struct platform_device *pdev)
1328 {
1329 struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1330
1331 sport->port.line = pdev->id;
1332 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1333
1334 if (!pdata)
1335 return;
1336
1337 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1338 sport->have_rtscts = 1;
1339
1340 if (pdata->flags & IMXUART_IRDA)
1341 sport->use_irda = 1;
1342 }
1343
1344 static int serial_imx_probe(struct platform_device *pdev)
1345 {
1346 struct imx_port *sport;
1347 struct imxuart_platform_data *pdata;
1348 void __iomem *base;
1349 int ret = 0;
1350 struct resource *res;
1351
1352 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1353 if (!sport)
1354 return -ENOMEM;
1355
1356 ret = serial_imx_probe_dt(sport, pdev);
1357 if (ret == -ENODEV)
1358 serial_imx_probe_pdata(sport, pdev);
1359
1360 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1361 if (!res) {
1362 ret = -ENODEV;
1363 goto free;
1364 }
1365
1366 base = ioremap(res->start, PAGE_SIZE);
1367 if (!base) {
1368 ret = -ENOMEM;
1369 goto free;
1370 }
1371
1372 sport->port.dev = &pdev->dev;
1373 sport->port.mapbase = res->start;
1374 sport->port.membase = base;
1375 sport->port.type = PORT_IMX,
1376 sport->port.iotype = UPIO_MEM;
1377 sport->port.irq = platform_get_irq(pdev, 0);
1378 sport->rxirq = platform_get_irq(pdev, 0);
1379 sport->txirq = platform_get_irq(pdev, 1);
1380 sport->rtsirq = platform_get_irq(pdev, 2);
1381 sport->port.fifosize = 32;
1382 sport->port.ops = &imx_pops;
1383 sport->port.flags = UPF_BOOT_AUTOCONF;
1384 init_timer(&sport->timer);
1385 sport->timer.function = imx_timeout;
1386 sport->timer.data = (unsigned long)sport;
1387
1388 sport->clk = clk_get(&pdev->dev, "uart");
1389 if (IS_ERR(sport->clk)) {
1390 ret = PTR_ERR(sport->clk);
1391 goto unmap;
1392 }
1393 clk_enable(sport->clk);
1394
1395 sport->port.uartclk = clk_get_rate(sport->clk);
1396
1397 imx_ports[sport->port.line] = sport;
1398
1399 pdata = pdev->dev.platform_data;
1400 if (pdata && pdata->init) {
1401 ret = pdata->init(pdev);
1402 if (ret)
1403 goto clkput;
1404 }
1405
1406 ret = uart_add_one_port(&imx_reg, &sport->port);
1407 if (ret)
1408 goto deinit;
1409 platform_set_drvdata(pdev, &sport->port);
1410
1411 return 0;
1412 deinit:
1413 if (pdata && pdata->exit)
1414 pdata->exit(pdev);
1415 clkput:
1416 clk_put(sport->clk);
1417 clk_disable(sport->clk);
1418 unmap:
1419 iounmap(sport->port.membase);
1420 free:
1421 kfree(sport);
1422
1423 return ret;
1424 }
1425
1426 static int serial_imx_remove(struct platform_device *pdev)
1427 {
1428 struct imxuart_platform_data *pdata;
1429 struct imx_port *sport = platform_get_drvdata(pdev);
1430
1431 pdata = pdev->dev.platform_data;
1432
1433 platform_set_drvdata(pdev, NULL);
1434
1435 if (sport) {
1436 uart_remove_one_port(&imx_reg, &sport->port);
1437 clk_put(sport->clk);
1438 }
1439
1440 clk_disable(sport->clk);
1441
1442 if (pdata && pdata->exit)
1443 pdata->exit(pdev);
1444
1445 iounmap(sport->port.membase);
1446 kfree(sport);
1447
1448 return 0;
1449 }
1450
1451 static struct platform_driver serial_imx_driver = {
1452 .probe = serial_imx_probe,
1453 .remove = serial_imx_remove,
1454
1455 .suspend = serial_imx_suspend,
1456 .resume = serial_imx_resume,
1457 .id_table = imx_uart_devtype,
1458 .driver = {
1459 .name = "imx-uart",
1460 .owner = THIS_MODULE,
1461 .of_match_table = imx_uart_dt_ids,
1462 },
1463 };
1464
1465 static int __init imx_serial_init(void)
1466 {
1467 int ret;
1468
1469 printk(KERN_INFO "Serial: IMX driver\n");
1470
1471 ret = uart_register_driver(&imx_reg);
1472 if (ret)
1473 return ret;
1474
1475 ret = platform_driver_register(&serial_imx_driver);
1476 if (ret != 0)
1477 uart_unregister_driver(&imx_reg);
1478
1479 return 0;
1480 }
1481
1482 static void __exit imx_serial_exit(void)
1483 {
1484 platform_driver_unregister(&serial_imx_driver);
1485 uart_unregister_driver(&imx_reg);
1486 }
1487
1488 module_init(imx_serial_init);
1489 module_exit(imx_serial_exit);
1490
1491 MODULE_AUTHOR("Sascha Hauer");
1492 MODULE_DESCRIPTION("IMX generic serial port driver");
1493 MODULE_LICENSE("GPL");
1494 MODULE_ALIAS("platform:imx-uart");
Linux with added FPC-III support