drivers/acpi/pci_mcfg.c

   1 /*
   2  * Copyright (C) 2016 Broadcom
   3  *      Author: Jayachandran C <jchandra@broadcom.com>
   4  * Copyright (C) 2016 Semihalf
   5  *      Author: Tomasz Nowicki <tn@semihalf.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License, version 2, as
   9  * published by the Free Software Foundation (the "GPL").
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License version 2 (GPLv2) for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * version 2 (GPLv2) along with this source code.
  18  */
  19
  20 #define pr_fmt(fmt) "ACPI: " fmt
  21
  22 #include <linux/kernel.h>
  23 #include <linux/pci.h>
  24 #include <linux/pci-acpi.h>
  25 #include <linux/pci-ecam.h>
  26
  27 /* Structure to hold entries from the MCFG table */
  28 struct mcfg_entry {
  29         struct list_head        list;
  30         phys_addr_t             addr;
  31         u16                     segment;
  32         u8                      bus_start;
  33         u8                      bus_end;
  34 };
  35
  36 #ifdef CONFIG_PCI_QUIRKS
  37 struct mcfg_fixup {
  38         char oem_id[ACPI_OEM_ID_SIZE + 1];
  39         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
  40         u32 oem_revision;
  41         u16 segment;
  42         struct resource bus_range;
  43         struct pci_ecam_ops *ops;
  44         struct resource cfgres;
  45 };
  46
  47 #define MCFG_BUS_RANGE(start, end)      DEFINE_RES_NAMED((start),       \
  48                                                 ((end) - (start) + 1),  \
  49                                                 NULL, IORESOURCE_BUS)
  50 #define MCFG_BUS_ANY                    MCFG_BUS_RANGE(0x0, 0xff)
  51
  52 static struct mcfg_fixup mcfg_quirks[] = {
  53 /*      { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
  54
  55 #define QCOM_ECAM32(seg) \
  56         { "QCOM  ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
  57
  58         QCOM_ECAM32(0),
  59         QCOM_ECAM32(1),
  60         QCOM_ECAM32(2),
  61         QCOM_ECAM32(3),
  62         QCOM_ECAM32(4),
  63         QCOM_ECAM32(5),
  64         QCOM_ECAM32(6),
  65         QCOM_ECAM32(7),
  66
  67 #define HISI_QUAD_DOM(table_id, seg, ops) \
  68         { "HISI  ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
  69         { "HISI  ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
  70         { "HISI  ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
  71         { "HISI  ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
  72
  73         HISI_QUAD_DOM("HIP05   ",  0, &hisi_pcie_ops),
  74         HISI_QUAD_DOM("HIP06   ",  0, &hisi_pcie_ops),
  75         HISI_QUAD_DOM("HIP07   ",  0, &hisi_pcie_ops),
  76         HISI_QUAD_DOM("HIP07   ",  4, &hisi_pcie_ops),
  77         HISI_QUAD_DOM("HIP07   ",  8, &hisi_pcie_ops),
  78         HISI_QUAD_DOM("HIP07   ", 12, &hisi_pcie_ops),
  79
  80 #define THUNDER_PEM_RES(addr, node) \
  81         DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
  82
  83 #define THUNDER_PEM_QUIRK(rev, node) \
  84         { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY,       \
  85           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) },  \
  86         { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY,       \
  87           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) },  \
  88         { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY,       \
  89           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) },  \
  90         { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY,       \
  91           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) },  \
  92         { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY,       \
  93           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) },  \
  94         { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY,       \
  95           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
  96
  97 #define THUNDER_ECAM_QUIRK(rev, seg)                                    \
  98         { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY,                 \
  99         &pci_thunder_ecam_ops }
 100
 101         /* SoC pass2.x */
 102         THUNDER_PEM_QUIRK(1, 0),
 103         THUNDER_PEM_QUIRK(1, 1),
 104         THUNDER_ECAM_QUIRK(1, 10),
 105
 106         /* SoC pass1.x */
 107         THUNDER_PEM_QUIRK(2, 0),        /* off-chip devices */
 108         THUNDER_PEM_QUIRK(2, 1),        /* off-chip devices */
 109         THUNDER_ECAM_QUIRK(2,  0),
 110         THUNDER_ECAM_QUIRK(2,  1),
 111         THUNDER_ECAM_QUIRK(2,  2),
 112         THUNDER_ECAM_QUIRK(2,  3),
 113         THUNDER_ECAM_QUIRK(2, 10),
 114         THUNDER_ECAM_QUIRK(2, 11),
 115         THUNDER_ECAM_QUIRK(2, 12),
 116         THUNDER_ECAM_QUIRK(2, 13),
 117
 118 #define XGENE_V1_ECAM_MCFG(rev, seg) \
 119         {"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \
 120                 &xgene_v1_pcie_ecam_ops }
 121
 122 #define XGENE_V2_ECAM_MCFG(rev, seg) \
 123         {"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \
 124                 &xgene_v2_pcie_ecam_ops }
 125
 126         /* X-Gene SoC with v1 PCIe controller */
 127         XGENE_V1_ECAM_MCFG(1, 0),
 128         XGENE_V1_ECAM_MCFG(1, 1),
 129         XGENE_V1_ECAM_MCFG(1, 2),
 130         XGENE_V1_ECAM_MCFG(1, 3),
 131         XGENE_V1_ECAM_MCFG(1, 4),
 132         XGENE_V1_ECAM_MCFG(2, 0),
 133         XGENE_V1_ECAM_MCFG(2, 1),
 134         XGENE_V1_ECAM_MCFG(2, 2),
 135         XGENE_V1_ECAM_MCFG(2, 3),
 136         XGENE_V1_ECAM_MCFG(2, 4),
 137         /* X-Gene SoC with v2.1 PCIe controller */
 138         XGENE_V2_ECAM_MCFG(3, 0),
 139         XGENE_V2_ECAM_MCFG(3, 1),
 140         /* X-Gene SoC with v2.2 PCIe controller */
 141         XGENE_V2_ECAM_MCFG(4, 0),
 142         XGENE_V2_ECAM_MCFG(4, 1),
 143         XGENE_V2_ECAM_MCFG(4, 2),
 144 };
 145
 146 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
 147 static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
 148 static u32 mcfg_oem_revision;
 149
 150 static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
 151                                   struct resource *bus_range)
 152 {
 153         if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
 154             !memcmp(f->oem_table_id, mcfg_oem_table_id,
 155                     ACPI_OEM_TABLE_ID_SIZE) &&
 156             f->oem_revision == mcfg_oem_revision &&
 157             f->segment == segment &&
 158             resource_contains(&f->bus_range, bus_range))
 159                 return 1;
 160
 161         return 0;
 162 }
 163 #endif
 164
 165 static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
 166                                   struct resource *cfgres,
 167                                   struct pci_ecam_ops **ecam_ops)
 168 {
 169 #ifdef CONFIG_PCI_QUIRKS
 170         u16 segment = root->segment;
 171         struct resource *bus_range = &root->secondary;
 172         struct mcfg_fixup *f;
 173         int i;
 174
 175         for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
 176                 if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
 177                         if (f->cfgres.start)
 178                                 *cfgres = f->cfgres;
 179                         if (f->ops)
 180                                 *ecam_ops =  f->ops;
 181                         dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
 182                                  cfgres, bus_range, *ecam_ops);
 183                         return;
 184                 }
 185         }
 186 #endif
 187 }
 188
 189 /* List to save MCFG entries */
 190 static LIST_HEAD(pci_mcfg_list);
 191
 192 int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
 193                     struct pci_ecam_ops **ecam_ops)
 194 {
 195         struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
 196         struct resource *bus_res = &root->secondary;
 197         u16 seg = root->segment;
 198         struct mcfg_entry *e;
 199         struct resource res;
 200
 201         /* Use address from _CBA if present, otherwise lookup MCFG */
 202         if (root->mcfg_addr)
 203                 goto skip_lookup;
 204
 205         /*
 206          * We expect the range in bus_res in the coverage of MCFG bus range.
 207          */
 208         list_for_each_entry(e, &pci_mcfg_list, list) {
 209                 if (e->segment == seg && e->bus_start <= bus_res->start &&
 210                     e->bus_end >= bus_res->end) {
 211                         root->mcfg_addr = e->addr;
 212                 }
 213
 214         }
 215
 216 skip_lookup:
 217         memset(&res, 0, sizeof(res));
 218         if (root->mcfg_addr) {
 219                 res.start = root->mcfg_addr + (bus_res->start << 20);
 220                 res.end = res.start + (resource_size(bus_res) << 20) - 1;
 221                 res.flags = IORESOURCE_MEM;
 222         }
 223
 224         /*
 225          * Allow quirks to override default ECAM ops and CFG resource
 226          * range.  This may even fabricate a CFG resource range in case
 227          * MCFG does not have it.  Invalid CFG start address means MCFG
 228          * firmware bug or we need another quirk in array.
 229          */
 230         pci_mcfg_apply_quirks(root, &res, &ops);
 231         if (!res.start)
 232                 return -ENXIO;
 233
 234         *cfgres = res;
 235         *ecam_ops = ops;
 236         return 0;
 237 }
 238
 239 static __init int pci_mcfg_parse(struct acpi_table_header *header)
 240 {
 241         struct acpi_table_mcfg *mcfg;
 242         struct acpi_mcfg_allocation *mptr;
 243         struct mcfg_entry *e, *arr;
 244         int i, n;
 245
 246         if (header->length < sizeof(struct acpi_table_mcfg))
 247                 return -EINVAL;
 248
 249         n = (header->length - sizeof(struct acpi_table_mcfg)) /
 250                                         sizeof(struct acpi_mcfg_allocation);
 251         mcfg = (struct acpi_table_mcfg *)header;
 252         mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
 253
 254         arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
 255         if (!arr)
 256                 return -ENOMEM;
 257
 258         for (i = 0, e = arr; i < n; i++, mptr++, e++) {
 259                 e->segment = mptr->pci_segment;
 260                 e->addr =  mptr->address;
 261                 e->bus_start = mptr->start_bus_number;
 262                 e->bus_end = mptr->end_bus_number;
 263                 list_add(&e->list, &pci_mcfg_list);
 264         }
 265
 266 #ifdef CONFIG_PCI_QUIRKS
 267         /* Save MCFG IDs and revision for quirks matching */
 268         memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
 269         memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
 270         mcfg_oem_revision = header->oem_revision;
 271 #endif
 272
 273         pr_info("MCFG table detected, %d entries\n", n);
 274         return 0;
 275 }
 276
 277 /* Interface called by ACPI - parse and save MCFG table */
 278 void __init pci_mmcfg_late_init(void)
 279 {
 280         int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
 281         if (err)
 282                 pr_err("Failed to parse MCFG (%d)\n", err);
 283 }