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Linux 4.19.133
[linux/fpc-iii.git] / drivers / ata / ata_piix.c
blob7ecb1322a5142f53c5d0e6e9fa1c9d26984ae6e3
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/driver-api/libata.rst
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publicly available from Intel web site. Errata documentation
42 * is also publicly available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independent device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independent timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
97
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
100
101 enum {
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* address map register */
104 ICH5_PCS = 0x92, /* port control and status */
105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
109
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
112
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
115
116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* constants for mapping table */
122 P0 = 0, /* port 0 */
123 P1 = 1, /* port 1 */
124 P2 = 2, /* port 2 */
125 P3 = 3, /* port 3 */
126 IDE = -1, /* IDE */
127 NA = -2, /* not available */
128 RV = -3, /* reserved */
129
130 PIIX_AHCI_DEVICE = 6,
131
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
134 };
135
136 enum piix_controller_ids {
137 /* controller IDs */
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
144 ich5_sata,
145 ich6_sata,
146 ich6m_sata,
147 ich8_sata,
148 ich8_2port_sata,
149 ich8m_apple_sata, /* locks up on second port enable */
150 tolapai_sata,
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
152 ich8_sata_snb,
153 ich8_2port_sata_snb,
154 ich8_2port_sata_byt,
155 };
156
157 struct piix_map_db {
158 const u32 mask;
159 const u16 port_enable;
160 const int map[][4];
161 };
162
163 struct piix_host_priv {
164 const int *map;
165 u32 saved_iocfg;
166 void __iomem *sidpr;
167 };
168
169 static unsigned int in_module_init = 1;
170
171 static const struct pci_device_id piix_pci_tbl[] = {
172 /* Intel PIIX3 for the 430HX etc */
173 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
174 /* VMware ICH4 */
175 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
176 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
177 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
178 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
179 /* Intel PIIX4 */
180 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
181 /* Intel PIIX4 */
182 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
183 /* Intel PIIX */
184 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
185 /* Intel ICH (i810, i815, i840) UDMA 66*/
186 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
187 /* Intel ICH0 : UDMA 33*/
188 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
189 /* Intel ICH2M */
190 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
192 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH3M */
194 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH3 (E7500/1) UDMA 100 */
196 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 /* Intel ICH4-L */
198 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
200 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 /* Intel ICH5 */
203 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204 /* C-ICH (i810E2) */
205 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
207 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* ICH6 (and 6) (i915) UDMA 100 */
209 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* ICH7/7-R (i945, i975) UDMA 100*/
211 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
212 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
213 /* ICH8 Mobile PATA Controller */
214 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
215
216 /* SATA ports */
217
218 /* 82801EB (ICH5) */
219 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
220 /* 82801EB (ICH5) */
221 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
222 /* 6300ESB (ICH5 variant with broken PCS present bits) */
223 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
224 /* 6300ESB pretending RAID */
225 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
226 /* 82801FB/FW (ICH6/ICH6W) */
227 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
228 /* 82801FR/FRW (ICH6R/ICH6RW) */
229 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
230 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
231 * Attach iff the controller is in IDE mode. */
232 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
233 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
234 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
235 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
236 /* 82801GBM/GHM (ICH7M, identical to ICH6M) */
237 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
238 /* Enterprise Southbridge 2 (631xESB/632xESB) */
239 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
240 /* SATA Controller 1 IDE (ICH8) */
241 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
242 /* SATA Controller 2 IDE (ICH8) */
243 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
244 /* Mobile SATA Controller IDE (ICH8M), Apple */
245 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
246 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
247 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
248 /* Mobile SATA Controller IDE (ICH8M) */
249 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
250 /* SATA Controller IDE (ICH9) */
251 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
252 /* SATA Controller IDE (ICH9) */
253 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
254 /* SATA Controller IDE (ICH9) */
255 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
256 /* SATA Controller IDE (ICH9M) */
257 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
258 /* SATA Controller IDE (ICH9M) */
259 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
260 /* SATA Controller IDE (ICH9M) */
261 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
262 /* SATA Controller IDE (Tolapai) */
263 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
264 /* SATA Controller IDE (ICH10) */
265 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
266 /* SATA Controller IDE (ICH10) */
267 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
268 /* SATA Controller IDE (ICH10) */
269 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
270 /* SATA Controller IDE (ICH10) */
271 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
272 /* SATA Controller IDE (PCH) */
273 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
274 /* SATA Controller IDE (PCH) */
275 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (PCH) */
277 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
278 /* SATA Controller IDE (PCH) */
279 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
280 /* SATA Controller IDE (PCH) */
281 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
282 /* SATA Controller IDE (PCH) */
283 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
284 /* SATA Controller IDE (CPT) */
285 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
286 /* SATA Controller IDE (CPT) */
287 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
288 /* SATA Controller IDE (CPT) */
289 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
290 /* SATA Controller IDE (CPT) */
291 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
292 /* SATA Controller IDE (PBG) */
293 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
294 /* SATA Controller IDE (PBG) */
295 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
296 /* SATA Controller IDE (Panther Point) */
297 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
298 /* SATA Controller IDE (Panther Point) */
299 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
300 /* SATA Controller IDE (Panther Point) */
301 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
302 /* SATA Controller IDE (Panther Point) */
303 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
304 /* SATA Controller IDE (Lynx Point) */
305 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
306 /* SATA Controller IDE (Lynx Point) */
307 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
308 /* SATA Controller IDE (Lynx Point) */
309 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
310 /* SATA Controller IDE (Lynx Point) */
311 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
312 /* SATA Controller IDE (Lynx Point-LP) */
313 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
314 /* SATA Controller IDE (Lynx Point-LP) */
315 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
316 /* SATA Controller IDE (Lynx Point-LP) */
317 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
318 /* SATA Controller IDE (Lynx Point-LP) */
319 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
320 /* SATA Controller IDE (DH89xxCC) */
321 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
322 /* SATA Controller IDE (Avoton) */
323 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
324 /* SATA Controller IDE (Avoton) */
325 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
326 /* SATA Controller IDE (Avoton) */
327 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
328 /* SATA Controller IDE (Avoton) */
329 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
330 /* SATA Controller IDE (Wellsburg) */
331 { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
332 /* SATA Controller IDE (Wellsburg) */
333 { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
334 /* SATA Controller IDE (Wellsburg) */
335 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
336 /* SATA Controller IDE (Wellsburg) */
337 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
338 /* SATA Controller IDE (BayTrail) */
339 { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
340 { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
341 /* SATA Controller IDE (Coleto Creek) */
342 { 0x8086, 0x23a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
343 /* SATA Controller IDE (9 Series) */
344 { 0x8086, 0x8c88, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
345 /* SATA Controller IDE (9 Series) */
346 { 0x8086, 0x8c89, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
347 /* SATA Controller IDE (9 Series) */
348 { 0x8086, 0x8c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
349 /* SATA Controller IDE (9 Series) */
350 { 0x8086, 0x8c81, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
351
352 { } /* terminate list */
353 };
354
355 static const struct piix_map_db ich5_map_db = {
356 .mask = 0x7,
357 .port_enable = 0x3,
358 .map = {
359 /* PM PS SM SS MAP */
360 { P0, NA, P1, NA }, /* 000b */
361 { P1, NA, P0, NA }, /* 001b */
362 { RV, RV, RV, RV },
363 { RV, RV, RV, RV },
364 { P0, P1, IDE, IDE }, /* 100b */
365 { P1, P0, IDE, IDE }, /* 101b */
366 { IDE, IDE, P0, P1 }, /* 110b */
367 { IDE, IDE, P1, P0 }, /* 111b */
368 },
369 };
370
371 static const struct piix_map_db ich6_map_db = {
372 .mask = 0x3,
373 .port_enable = 0xf,
374 .map = {
375 /* PM PS SM SS MAP */
376 { P0, P2, P1, P3 }, /* 00b */
377 { IDE, IDE, P1, P3 }, /* 01b */
378 { P0, P2, IDE, IDE }, /* 10b */
379 { RV, RV, RV, RV },
380 },
381 };
382
383 static const struct piix_map_db ich6m_map_db = {
384 .mask = 0x3,
385 .port_enable = 0x5,
386
387 /* Map 01b isn't specified in the doc but some notebooks use
388 * it anyway. MAP 01b have been spotted on both ICH6M and
389 * ICH7M.
390 */
391 .map = {
392 /* PM PS SM SS MAP */
393 { P0, P2, NA, NA }, /* 00b */
394 { IDE, IDE, P1, P3 }, /* 01b */
395 { P0, P2, IDE, IDE }, /* 10b */
396 { RV, RV, RV, RV },
397 },
398 };
399
400 static const struct piix_map_db ich8_map_db = {
401 .mask = 0x3,
402 .port_enable = 0xf,
403 .map = {
404 /* PM PS SM SS MAP */
405 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
406 { RV, RV, RV, RV },
407 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
408 { RV, RV, RV, RV },
409 },
410 };
411
412 static const struct piix_map_db ich8_2port_map_db = {
413 .mask = 0x3,
414 .port_enable = 0x3,
415 .map = {
416 /* PM PS SM SS MAP */
417 { P0, NA, P1, NA }, /* 00b */
418 { RV, RV, RV, RV }, /* 01b */
419 { RV, RV, RV, RV }, /* 10b */
420 { RV, RV, RV, RV },
421 },
422 };
423
424 static const struct piix_map_db ich8m_apple_map_db = {
425 .mask = 0x3,
426 .port_enable = 0x1,
427 .map = {
428 /* PM PS SM SS MAP */
429 { P0, NA, NA, NA }, /* 00b */
430 { RV, RV, RV, RV },
431 { P0, P2, IDE, IDE }, /* 10b */
432 { RV, RV, RV, RV },
433 },
434 };
435
436 static const struct piix_map_db tolapai_map_db = {
437 .mask = 0x3,
438 .port_enable = 0x3,
439 .map = {
440 /* PM PS SM SS MAP */
441 { P0, NA, P1, NA }, /* 00b */
442 { RV, RV, RV, RV }, /* 01b */
443 { RV, RV, RV, RV }, /* 10b */
444 { RV, RV, RV, RV },
445 },
446 };
447
448 static const struct piix_map_db *piix_map_db_table[] = {
449 [ich5_sata] = &ich5_map_db,
450 [ich6_sata] = &ich6_map_db,
451 [ich6m_sata] = &ich6m_map_db,
452 [ich8_sata] = &ich8_map_db,
453 [ich8_2port_sata] = &ich8_2port_map_db,
454 [ich8m_apple_sata] = &ich8m_apple_map_db,
455 [tolapai_sata] = &tolapai_map_db,
456 [ich8_sata_snb] = &ich8_map_db,
457 [ich8_2port_sata_snb] = &ich8_2port_map_db,
458 [ich8_2port_sata_byt] = &ich8_2port_map_db,
459 };
460
461 static const struct pci_bits piix_enable_bits[] = {
462 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
463 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
464 };
465
466 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
467 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
468 MODULE_LICENSE("GPL");
469 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
470 MODULE_VERSION(DRV_VERSION);
471
472 struct ich_laptop {
473 u16 device;
474 u16 subvendor;
475 u16 subdevice;
476 };
477
478 /*
479 * List of laptops that use short cables rather than 80 wire
480 */
481
482 static const struct ich_laptop ich_laptop[] = {
483 /* devid, subvendor, subdev */
484 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
485 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
486 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
487 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
488 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
489 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
490 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
491 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
492 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
493 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
494 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
495 { 0x24CA, 0x10CF, 0x11AB }, /* ICH4M on Fujitsu-Siemens Lifebook S6120 */
496 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
497 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
498 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
499 /* end marker */
500 { 0, }
501 };
502
503 static int piix_port_start(struct ata_port *ap)
504 {
505 if (!(ap->flags & PIIX_FLAG_PIO16))
506 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
507
508 return ata_bmdma_port_start(ap);
509 }
510
511 /**
512 * ich_pata_cable_detect - Probe host controller cable detect info
513 * @ap: Port for which cable detect info is desired
514 *
515 * Read 80c cable indicator from ATA PCI device's PCI config
516 * register. This register is normally set by firmware (BIOS).
517 *
518 * LOCKING:
519 * None (inherited from caller).
520 */
521
522 static int ich_pata_cable_detect(struct ata_port *ap)
523 {
524 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
525 struct piix_host_priv *hpriv = ap->host->private_data;
526 const struct ich_laptop *lap = &ich_laptop[0];
527 u8 mask;
528
529 /* Check for specials */
530 while (lap->device) {
531 if (lap->device == pdev->device &&
532 lap->subvendor == pdev->subsystem_vendor &&
533 lap->subdevice == pdev->subsystem_device)
534 return ATA_CBL_PATA40_SHORT;
535
536 lap++;
537 }
538
539 /* check BIOS cable detect results */
540 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
541 if ((hpriv->saved_iocfg & mask) == 0)
542 return ATA_CBL_PATA40;
543 return ATA_CBL_PATA80;
544 }
545
546 /**
547 * piix_pata_prereset - prereset for PATA host controller
548 * @link: Target link
549 * @deadline: deadline jiffies for the operation
550 *
551 * LOCKING:
552 * None (inherited from caller).
553 */
554 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
555 {
556 struct ata_port *ap = link->ap;
557 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
558
559 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
560 return -ENOENT;
561 return ata_sff_prereset(link, deadline);
562 }
563
564 static DEFINE_SPINLOCK(piix_lock);
565
566 static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
567 u8 pio)
568 {
569 struct pci_dev *dev = to_pci_dev(ap->host->dev);
570 unsigned long flags;
571 unsigned int is_slave = (adev->devno != 0);
572 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
573 unsigned int slave_port = 0x44;
574 u16 master_data;
575 u8 slave_data;
576 u8 udma_enable;
577 int control = 0;
578
579 /*
580 * See Intel Document 298600-004 for the timing programing rules
581 * for ICH controllers.
582 */
583
584 static const /* ISP RTC */
585 u8 timings[][2] = { { 0, 0 },
586 { 0, 0 },
587 { 1, 0 },
588 { 2, 1 },
589 { 2, 3 }, };
590
591 if (pio >= 2)
592 control |= 1; /* TIME1 enable */
593 if (ata_pio_need_iordy(adev))
594 control |= 2; /* IE enable */
595 /* Intel specifies that the PPE functionality is for disk only */
596 if (adev->class == ATA_DEV_ATA)
597 control |= 4; /* PPE enable */
598 /*
599 * If the drive MWDMA is faster than it can do PIO then
600 * we must force PIO into PIO0
601 */
602 if (adev->pio_mode < XFER_PIO_0 + pio)
603 /* Enable DMA timing only */
604 control |= 8; /* PIO cycles in PIO0 */
605
606 spin_lock_irqsave(&piix_lock, flags);
607
608 /* PIO configuration clears DTE unconditionally. It will be
609 * programmed in set_dmamode which is guaranteed to be called
610 * after set_piomode if any DMA mode is available.
611 */
612 pci_read_config_word(dev, master_port, &master_data);
613 if (is_slave) {
614 /* clear TIME1|IE1|PPE1|DTE1 */
615 master_data &= 0xff0f;
616 /* enable PPE1, IE1 and TIME1 as needed */
617 master_data |= (control << 4);
618 pci_read_config_byte(dev, slave_port, &slave_data);
619 slave_data &= (ap->port_no ? 0x0f : 0xf0);
620 /* Load the timing nibble for this slave */
621 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
622 << (ap->port_no ? 4 : 0);
623 } else {
624 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
625 master_data &= 0xccf0;
626 /* Enable PPE, IE and TIME as appropriate */
627 master_data |= control;
628 /* load ISP and RCT */
629 master_data |=
630 (timings[pio][0] << 12) |
631 (timings[pio][1] << 8);
632 }
633
634 /* Enable SITRE (separate slave timing register) */
635 master_data |= 0x4000;
636 pci_write_config_word(dev, master_port, master_data);
637 if (is_slave)
638 pci_write_config_byte(dev, slave_port, slave_data);
639
640 /* Ensure the UDMA bit is off - it will be turned back on if
641 UDMA is selected */
642
643 if (ap->udma_mask) {
644 pci_read_config_byte(dev, 0x48, &udma_enable);
645 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
646 pci_write_config_byte(dev, 0x48, udma_enable);
647 }
648
649 spin_unlock_irqrestore(&piix_lock, flags);
650 }
651
652 /**
653 * piix_set_piomode - Initialize host controller PATA PIO timings
654 * @ap: Port whose timings we are configuring
655 * @adev: Drive in question
656 *
657 * Set PIO mode for device, in host controller PCI config space.
658 *
659 * LOCKING:
660 * None (inherited from caller).
661 */
662
663 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
664 {
665 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
666 }
667
668 /**
669 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
670 * @ap: Port whose timings we are configuring
671 * @adev: Drive in question
672 * @isich: set if the chip is an ICH device
673 *
674 * Set UDMA mode for device, in host controller PCI config space.
675 *
676 * LOCKING:
677 * None (inherited from caller).
678 */
679
680 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
681 {
682 struct pci_dev *dev = to_pci_dev(ap->host->dev);
683 unsigned long flags;
684 u8 speed = adev->dma_mode;
685 int devid = adev->devno + 2 * ap->port_no;
686 u8 udma_enable = 0;
687
688 if (speed >= XFER_UDMA_0) {
689 unsigned int udma = speed - XFER_UDMA_0;
690 u16 udma_timing;
691 u16 ideconf;
692 int u_clock, u_speed;
693
694 spin_lock_irqsave(&piix_lock, flags);
695
696 pci_read_config_byte(dev, 0x48, &udma_enable);
697
698 /*
699 * UDMA is handled by a combination of clock switching and
700 * selection of dividers
701 *
702 * Handy rule: Odd modes are UDMATIMx 01, even are 02
703 * except UDMA0 which is 00
704 */
705 u_speed = min(2 - (udma & 1), udma);
706 if (udma == 5)
707 u_clock = 0x1000; /* 100Mhz */
708 else if (udma > 2)
709 u_clock = 1; /* 66Mhz */
710 else
711 u_clock = 0; /* 33Mhz */
712
713 udma_enable |= (1 << devid);
714
715 /* Load the CT/RP selection */
716 pci_read_config_word(dev, 0x4A, &udma_timing);
717 udma_timing &= ~(3 << (4 * devid));
718 udma_timing |= u_speed << (4 * devid);
719 pci_write_config_word(dev, 0x4A, udma_timing);
720
721 if (isich) {
722 /* Select a 33/66/100Mhz clock */
723 pci_read_config_word(dev, 0x54, &ideconf);
724 ideconf &= ~(0x1001 << devid);
725 ideconf |= u_clock << devid;
726 /* For ICH or later we should set bit 10 for better
727 performance (WR_PingPong_En) */
728 pci_write_config_word(dev, 0x54, ideconf);
729 }
730
731 pci_write_config_byte(dev, 0x48, udma_enable);
732
733 spin_unlock_irqrestore(&piix_lock, flags);
734 } else {
735 /* MWDMA is driven by the PIO timings. */
736 unsigned int mwdma = speed - XFER_MW_DMA_0;
737 const unsigned int needed_pio[3] = {
738 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
739 };
740 int pio = needed_pio[mwdma] - XFER_PIO_0;
741
742 /* XFER_PIO_0 is never used currently */
743 piix_set_timings(ap, adev, pio);
744 }
745 }
746
747 /**
748 * piix_set_dmamode - Initialize host controller PATA DMA timings
749 * @ap: Port whose timings we are configuring
750 * @adev: um
751 *
752 * Set MW/UDMA mode for device, in host controller PCI config space.
753 *
754 * LOCKING:
755 * None (inherited from caller).
756 */
757
758 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
759 {
760 do_pata_set_dmamode(ap, adev, 0);
761 }
762
763 /**
764 * ich_set_dmamode - Initialize host controller PATA DMA timings
765 * @ap: Port whose timings we are configuring
766 * @adev: um
767 *
768 * Set MW/UDMA mode for device, in host controller PCI config space.
769 *
770 * LOCKING:
771 * None (inherited from caller).
772 */
773
774 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
775 {
776 do_pata_set_dmamode(ap, adev, 1);
777 }
778
779 /*
780 * Serial ATA Index/Data Pair Superset Registers access
781 *
782 * Beginning from ICH8, there's a sane way to access SCRs using index
783 * and data register pair located at BAR5 which means that we have
784 * separate SCRs for master and slave. This is handled using libata
785 * slave_link facility.
786 */
787 static const int piix_sidx_map[] = {
788 [SCR_STATUS] = 0,
789 [SCR_ERROR] = 2,
790 [SCR_CONTROL] = 1,
791 };
792
793 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
794 {
795 struct ata_port *ap = link->ap;
796 struct piix_host_priv *hpriv = ap->host->private_data;
797
798 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
799 hpriv->sidpr + PIIX_SIDPR_IDX);
800 }
801
802 static int piix_sidpr_scr_read(struct ata_link *link,
803 unsigned int reg, u32 *val)
804 {
805 struct piix_host_priv *hpriv = link->ap->host->private_data;
806
807 if (reg >= ARRAY_SIZE(piix_sidx_map))
808 return -EINVAL;
809
810 piix_sidpr_sel(link, reg);
811 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
812 return 0;
813 }
814
815 static int piix_sidpr_scr_write(struct ata_link *link,
816 unsigned int reg, u32 val)
817 {
818 struct piix_host_priv *hpriv = link->ap->host->private_data;
819
820 if (reg >= ARRAY_SIZE(piix_sidx_map))
821 return -EINVAL;
822
823 piix_sidpr_sel(link, reg);
824 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
825 return 0;
826 }
827
828 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
829 unsigned hints)
830 {
831 return sata_link_scr_lpm(link, policy, false);
832 }
833
834 static bool piix_irq_check(struct ata_port *ap)
835 {
836 if (unlikely(!ap->ioaddr.bmdma_addr))
837 return false;
838
839 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
840 }
841
842 #ifdef CONFIG_PM_SLEEP
843 static int piix_broken_suspend(void)
844 {
845 static const struct dmi_system_id sysids[] = {
846 {
847 .ident = "TECRA M3",
848 .matches = {
849 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
850 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
851 },
852 },
853 {
854 .ident = "TECRA M3",
855 .matches = {
856 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
857 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
858 },
859 },
860 {
861 .ident = "TECRA M4",
862 .matches = {
863 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
864 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
865 },
866 },
867 {
868 .ident = "TECRA M4",
869 .matches = {
870 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
871 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
872 },
873 },
874 {
875 .ident = "TECRA M5",
876 .matches = {
877 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
878 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
879 },
880 },
881 {
882 .ident = "TECRA M6",
883 .matches = {
884 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
885 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
886 },
887 },
888 {
889 .ident = "TECRA M7",
890 .matches = {
891 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
892 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
893 },
894 },
895 {
896 .ident = "TECRA A8",
897 .matches = {
898 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
899 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
900 },
901 },
902 {
903 .ident = "Satellite R20",
904 .matches = {
905 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
906 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
907 },
908 },
909 {
910 .ident = "Satellite R25",
911 .matches = {
912 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
913 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
914 },
915 },
916 {
917 .ident = "Satellite U200",
918 .matches = {
919 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
920 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
921 },
922 },
923 {
924 .ident = "Satellite U200",
925 .matches = {
926 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
927 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
928 },
929 },
930 {
931 .ident = "Satellite Pro U200",
932 .matches = {
933 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
934 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
935 },
936 },
937 {
938 .ident = "Satellite U205",
939 .matches = {
940 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
941 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
942 },
943 },
944 {
945 .ident = "SATELLITE U205",
946 .matches = {
947 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
948 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
949 },
950 },
951 {
952 .ident = "Satellite Pro A120",
953 .matches = {
954 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
955 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
956 },
957 },
958 {
959 .ident = "Portege M500",
960 .matches = {
961 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
962 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
963 },
964 },
965 {
966 .ident = "VGN-BX297XP",
967 .matches = {
968 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
969 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
970 },
971 },
972
973 { } /* terminate list */
974 };
975 static const char *oemstrs[] = {
976 "Tecra M3,",
977 };
978 int i;
979
980 if (dmi_check_system(sysids))
981 return 1;
982
983 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
984 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
985 return 1;
986
987 /* TECRA M4 sometimes forgets its identify and reports bogus
988 * DMI information. As the bogus information is a bit
989 * generic, match as many entries as possible. This manual
990 * matching is necessary because dmi_system_id.matches is
991 * limited to four entries.
992 */
993 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
994 dmi_match(DMI_PRODUCT_NAME, "000000") &&
995 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
996 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
997 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
998 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
999 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1000 return 1;
1001
1002 return 0;
1003 }
1004
1005 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1006 {
1007 struct ata_host *host = pci_get_drvdata(pdev);
1008 unsigned long flags;
1009 int rc = 0;
1010
1011 rc = ata_host_suspend(host, mesg);
1012 if (rc)
1013 return rc;
1014
1015 /* Some braindamaged ACPI suspend implementations expect the
1016 * controller to be awake on entry; otherwise, it burns cpu
1017 * cycles and power trying to do something to the sleeping
1018 * beauty.
1019 */
1020 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1021 pci_save_state(pdev);
1022
1023 /* mark its power state as "unknown", since we don't
1024 * know if e.g. the BIOS will change its device state
1025 * when we suspend.
1026 */
1027 if (pdev->current_state == PCI_D0)
1028 pdev->current_state = PCI_UNKNOWN;
1029
1030 /* tell resume that it's waking up from broken suspend */
1031 spin_lock_irqsave(&host->lock, flags);
1032 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1033 spin_unlock_irqrestore(&host->lock, flags);
1034 } else
1035 ata_pci_device_do_suspend(pdev, mesg);
1036
1037 return 0;
1038 }
1039
1040 static int piix_pci_device_resume(struct pci_dev *pdev)
1041 {
1042 struct ata_host *host = pci_get_drvdata(pdev);
1043 unsigned long flags;
1044 int rc;
1045
1046 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1047 spin_lock_irqsave(&host->lock, flags);
1048 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1049 spin_unlock_irqrestore(&host->lock, flags);
1050
1051 pci_set_power_state(pdev, PCI_D0);
1052 pci_restore_state(pdev);
1053
1054 /* PCI device wasn't disabled during suspend. Use
1055 * pci_reenable_device() to avoid affecting the enable
1056 * count.
1057 */
1058 rc = pci_reenable_device(pdev);
1059 if (rc)
1060 dev_err(&pdev->dev,
1061 "failed to enable device after resume (%d)\n",
1062 rc);
1063 } else
1064 rc = ata_pci_device_do_resume(pdev);
1065
1066 if (rc == 0)
1067 ata_host_resume(host);
1068
1069 return rc;
1070 }
1071 #endif
1072
1073 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1074 {
1075 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1076 }
1077
1078 static struct scsi_host_template piix_sht = {
1079 ATA_BMDMA_SHT(DRV_NAME),
1080 };
1081
1082 static struct ata_port_operations piix_sata_ops = {
1083 .inherits = &ata_bmdma32_port_ops,
1084 .sff_irq_check = piix_irq_check,
1085 .port_start = piix_port_start,
1086 };
1087
1088 static struct ata_port_operations piix_pata_ops = {
1089 .inherits = &piix_sata_ops,
1090 .cable_detect = ata_cable_40wire,
1091 .set_piomode = piix_set_piomode,
1092 .set_dmamode = piix_set_dmamode,
1093 .prereset = piix_pata_prereset,
1094 };
1095
1096 static struct ata_port_operations piix_vmw_ops = {
1097 .inherits = &piix_pata_ops,
1098 .bmdma_status = piix_vmw_bmdma_status,
1099 };
1100
1101 static struct ata_port_operations ich_pata_ops = {
1102 .inherits = &piix_pata_ops,
1103 .cable_detect = ich_pata_cable_detect,
1104 .set_dmamode = ich_set_dmamode,
1105 };
1106
1107 static struct device_attribute *piix_sidpr_shost_attrs[] = {
1108 &dev_attr_link_power_management_policy,
1109 NULL
1110 };
1111
1112 static struct scsi_host_template piix_sidpr_sht = {
1113 ATA_BMDMA_SHT(DRV_NAME),
1114 .shost_attrs = piix_sidpr_shost_attrs,
1115 };
1116
1117 static struct ata_port_operations piix_sidpr_sata_ops = {
1118 .inherits = &piix_sata_ops,
1119 .hardreset = sata_std_hardreset,
1120 .scr_read = piix_sidpr_scr_read,
1121 .scr_write = piix_sidpr_scr_write,
1122 .set_lpm = piix_sidpr_set_lpm,
1123 };
1124
1125 static struct ata_port_info piix_port_info[] = {
1126 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
1127 {
1128 .flags = PIIX_PATA_FLAGS,
1129 .pio_mask = ATA_PIO4,
1130 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1131 .port_ops = &piix_pata_ops,
1132 },
1133
1134 [piix_pata_33] = /* PIIX4 at 33MHz */
1135 {
1136 .flags = PIIX_PATA_FLAGS,
1137 .pio_mask = ATA_PIO4,
1138 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1139 .udma_mask = ATA_UDMA2,
1140 .port_ops = &piix_pata_ops,
1141 },
1142
1143 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
1144 {
1145 .flags = PIIX_PATA_FLAGS,
1146 .pio_mask = ATA_PIO4,
1147 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
1148 .udma_mask = ATA_UDMA2,
1149 .port_ops = &ich_pata_ops,
1150 },
1151
1152 [ich_pata_66] = /* ICH controllers up to 66MHz */
1153 {
1154 .flags = PIIX_PATA_FLAGS,
1155 .pio_mask = ATA_PIO4,
1156 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
1157 .udma_mask = ATA_UDMA4,
1158 .port_ops = &ich_pata_ops,
1159 },
1160
1161 [ich_pata_100] =
1162 {
1163 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1164 .pio_mask = ATA_PIO4,
1165 .mwdma_mask = ATA_MWDMA12_ONLY,
1166 .udma_mask = ATA_UDMA5,
1167 .port_ops = &ich_pata_ops,
1168 },
1169
1170 [ich_pata_100_nomwdma1] =
1171 {
1172 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1173 .pio_mask = ATA_PIO4,
1174 .mwdma_mask = ATA_MWDMA2_ONLY,
1175 .udma_mask = ATA_UDMA5,
1176 .port_ops = &ich_pata_ops,
1177 },
1178
1179 [ich5_sata] =
1180 {
1181 .flags = PIIX_SATA_FLAGS,
1182 .pio_mask = ATA_PIO4,
1183 .mwdma_mask = ATA_MWDMA2,
1184 .udma_mask = ATA_UDMA6,
1185 .port_ops = &piix_sata_ops,
1186 },
1187
1188 [ich6_sata] =
1189 {
1190 .flags = PIIX_SATA_FLAGS,
1191 .pio_mask = ATA_PIO4,
1192 .mwdma_mask = ATA_MWDMA2,
1193 .udma_mask = ATA_UDMA6,
1194 .port_ops = &piix_sata_ops,
1195 },
1196
1197 [ich6m_sata] =
1198 {
1199 .flags = PIIX_SATA_FLAGS,
1200 .pio_mask = ATA_PIO4,
1201 .mwdma_mask = ATA_MWDMA2,
1202 .udma_mask = ATA_UDMA6,
1203 .port_ops = &piix_sata_ops,
1204 },
1205
1206 [ich8_sata] =
1207 {
1208 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1209 .pio_mask = ATA_PIO4,
1210 .mwdma_mask = ATA_MWDMA2,
1211 .udma_mask = ATA_UDMA6,
1212 .port_ops = &piix_sata_ops,
1213 },
1214
1215 [ich8_2port_sata] =
1216 {
1217 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1218 .pio_mask = ATA_PIO4,
1219 .mwdma_mask = ATA_MWDMA2,
1220 .udma_mask = ATA_UDMA6,
1221 .port_ops = &piix_sata_ops,
1222 },
1223
1224 [tolapai_sata] =
1225 {
1226 .flags = PIIX_SATA_FLAGS,
1227 .pio_mask = ATA_PIO4,
1228 .mwdma_mask = ATA_MWDMA2,
1229 .udma_mask = ATA_UDMA6,
1230 .port_ops = &piix_sata_ops,
1231 },
1232
1233 [ich8m_apple_sata] =
1234 {
1235 .flags = PIIX_SATA_FLAGS,
1236 .pio_mask = ATA_PIO4,
1237 .mwdma_mask = ATA_MWDMA2,
1238 .udma_mask = ATA_UDMA6,
1239 .port_ops = &piix_sata_ops,
1240 },
1241
1242 [piix_pata_vmw] =
1243 {
1244 .flags = PIIX_PATA_FLAGS,
1245 .pio_mask = ATA_PIO4,
1246 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1247 .udma_mask = ATA_UDMA2,
1248 .port_ops = &piix_vmw_ops,
1249 },
1250
1251 /*
1252 * some Sandybridge chipsets have broken 32 mode up to now,
1253 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
1254 */
1255 [ich8_sata_snb] =
1256 {
1257 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1258 .pio_mask = ATA_PIO4,
1259 .mwdma_mask = ATA_MWDMA2,
1260 .udma_mask = ATA_UDMA6,
1261 .port_ops = &piix_sata_ops,
1262 },
1263
1264 [ich8_2port_sata_snb] =
1265 {
1266 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR
1267 | PIIX_FLAG_PIO16,
1268 .pio_mask = ATA_PIO4,
1269 .mwdma_mask = ATA_MWDMA2,
1270 .udma_mask = ATA_UDMA6,
1271 .port_ops = &piix_sata_ops,
1272 },
1273
1274 [ich8_2port_sata_byt] =
1275 {
1276 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1277 .pio_mask = ATA_PIO4,
1278 .mwdma_mask = ATA_MWDMA2,
1279 .udma_mask = ATA_UDMA6,
1280 .port_ops = &piix_sata_ops,
1281 },
1282
1283 };
1284
1285 #define AHCI_PCI_BAR 5
1286 #define AHCI_GLOBAL_CTL 0x04
1287 #define AHCI_ENABLE (1 << 31)
1288 static int piix_disable_ahci(struct pci_dev *pdev)
1289 {
1290 void __iomem *mmio;
1291 u32 tmp;
1292 int rc = 0;
1293
1294 /* BUG: pci_enable_device has not yet been called. This
1295 * works because this device is usually set up by BIOS.
1296 */
1297
1298 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1299 !pci_resource_len(pdev, AHCI_PCI_BAR))
1300 return 0;
1301
1302 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1303 if (!mmio)
1304 return -ENOMEM;
1305
1306 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1307 if (tmp & AHCI_ENABLE) {
1308 tmp &= ~AHCI_ENABLE;
1309 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1310
1311 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1312 if (tmp & AHCI_ENABLE)
1313 rc = -EIO;
1314 }
1315
1316 pci_iounmap(pdev, mmio);
1317 return rc;
1318 }
1319
1320 /**
1321 * piix_check_450nx_errata - Check for problem 450NX setup
1322 * @ata_dev: the PCI device to check
1323 *
1324 * Check for the present of 450NX errata #19 and errata #25. If
1325 * they are found return an error code so we can turn off DMA
1326 */
1327
1328 static int piix_check_450nx_errata(struct pci_dev *ata_dev)
1329 {
1330 struct pci_dev *pdev = NULL;
1331 u16 cfg;
1332 int no_piix_dma = 0;
1333
1334 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1335 /* Look for 450NX PXB. Check for problem configurations
1336 A PCI quirk checks bit 6 already */
1337 pci_read_config_word(pdev, 0x41, &cfg);
1338 /* Only on the original revision: IDE DMA can hang */
1339 if (pdev->revision == 0x00)
1340 no_piix_dma = 1;
1341 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1342 else if (cfg & (1<<14) && pdev->revision < 5)
1343 no_piix_dma = 2;
1344 }
1345 if (no_piix_dma)
1346 dev_warn(&ata_dev->dev,
1347 "450NX errata present, disabling IDE DMA%s\n",
1348 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1349 : "");
1350
1351 return no_piix_dma;
1352 }
1353
1354 static void piix_init_pcs(struct ata_host *host,
1355 const struct piix_map_db *map_db)
1356 {
1357 struct pci_dev *pdev = to_pci_dev(host->dev);
1358 u16 pcs, new_pcs;
1359
1360 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1361
1362 new_pcs = pcs | map_db->port_enable;
1363
1364 if (new_pcs != pcs) {
1365 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1366 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1367 msleep(150);
1368 }
1369 }
1370
1371 static const int *piix_init_sata_map(struct pci_dev *pdev,
1372 struct ata_port_info *pinfo,
1373 const struct piix_map_db *map_db)
1374 {
1375 const int *map;
1376 int i, invalid_map = 0;
1377 u8 map_value;
1378 char buf[32];
1379 char *p = buf, *end = buf + sizeof(buf);
1380
1381 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1382
1383 map = map_db->map[map_value & map_db->mask];
1384
1385 for (i = 0; i < 4; i++) {
1386 switch (map[i]) {
1387 case RV:
1388 invalid_map = 1;
1389 p += scnprintf(p, end - p, " XX");
1390 break;
1391
1392 case NA:
1393 p += scnprintf(p, end - p, " --");
1394 break;
1395
1396 case IDE:
1397 WARN_ON((i & 1) || map[i + 1] != IDE);
1398 pinfo[i / 2] = piix_port_info[ich_pata_100];
1399 i++;
1400 p += scnprintf(p, end - p, " IDE IDE");
1401 break;
1402
1403 default:
1404 p += scnprintf(p, end - p, " P%d", map[i]);
1405 if (i & 1)
1406 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1407 break;
1408 }
1409 }
1410 dev_info(&pdev->dev, "MAP [%s ]\n", buf);
1411
1412 if (invalid_map)
1413 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1414
1415 return map;
1416 }
1417
1418 static bool piix_no_sidpr(struct ata_host *host)
1419 {
1420 struct pci_dev *pdev = to_pci_dev(host->dev);
1421
1422 /*
1423 * Samsung DB-P70 only has three ATA ports exposed and
1424 * curiously the unconnected first port reports link online
1425 * while not responding to SRST protocol causing excessive
1426 * detection delay.
1427 *
1428 * Unfortunately, the system doesn't carry enough DMI
1429 * information to identify the machine but does have subsystem
1430 * vendor and device set. As it's unclear whether the
1431 * subsystem vendor/device is used only for this specific
1432 * board, the port can't be disabled solely with the
1433 * information; however, turning off SIDPR access works around
1434 * the problem. Turn it off.
1435 *
1436 * This problem is reported in bnc#441240.
1437 *
1438 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1439 */
1440 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1441 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1442 pdev->subsystem_device == 0xb049) {
1443 dev_warn(host->dev,
1444 "Samsung DB-P70 detected, disabling SIDPR\n");
1445 return true;
1446 }
1447
1448 return false;
1449 }
1450
1451 static int piix_init_sidpr(struct ata_host *host)
1452 {
1453 struct pci_dev *pdev = to_pci_dev(host->dev);
1454 struct piix_host_priv *hpriv = host->private_data;
1455 struct ata_link *link0 = &host->ports[0]->link;
1456 u32 scontrol;
1457 int i, rc;
1458
1459 /* check for availability */
1460 for (i = 0; i < 4; i++)
1461 if (hpriv->map[i] == IDE)
1462 return 0;
1463
1464 /* is it blacklisted? */
1465 if (piix_no_sidpr(host))
1466 return 0;
1467
1468 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1469 return 0;
1470
1471 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1472 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1473 return 0;
1474
1475 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1476 return 0;
1477
1478 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1479
1480 /* SCR access via SIDPR doesn't work on some configurations.
1481 * Give it a test drive by inhibiting power save modes which
1482 * we'll do anyway.
1483 */
1484 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1485
1486 /* if IPM is already 3, SCR access is probably working. Don't
1487 * un-inhibit power save modes as BIOS might have inhibited
1488 * them for a reason.
1489 */
1490 if ((scontrol & 0xf00) != 0x300) {
1491 scontrol |= 0x300;
1492 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1493 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1494
1495 if ((scontrol & 0xf00) != 0x300) {
1496 dev_info(host->dev,
1497 "SCR access via SIDPR is available but doesn't work\n");
1498 return 0;
1499 }
1500 }
1501
1502 /* okay, SCRs available, set ops and ask libata for slave_link */
1503 for (i = 0; i < 2; i++) {
1504 struct ata_port *ap = host->ports[i];
1505
1506 ap->ops = &piix_sidpr_sata_ops;
1507
1508 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1509 rc = ata_slave_link_init(ap);
1510 if (rc)
1511 return rc;
1512 }
1513 }
1514
1515 return 0;
1516 }
1517
1518 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1519 {
1520 static const struct dmi_system_id sysids[] = {
1521 {
1522 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1523 * isn't used to boot the system which
1524 * disables the channel.
1525 */
1526 .ident = "M570U",
1527 .matches = {
1528 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1529 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1530 },
1531 },
1532
1533 { } /* terminate list */
1534 };
1535 struct pci_dev *pdev = to_pci_dev(host->dev);
1536 struct piix_host_priv *hpriv = host->private_data;
1537
1538 if (!dmi_check_system(sysids))
1539 return;
1540
1541 /* The datasheet says that bit 18 is NOOP but certain systems
1542 * seem to use it to disable a channel. Clear the bit on the
1543 * affected systems.
1544 */
1545 if (hpriv->saved_iocfg & (1 << 18)) {
1546 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1547 pci_write_config_dword(pdev, PIIX_IOCFG,
1548 hpriv->saved_iocfg & ~(1 << 18));
1549 }
1550 }
1551
1552 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1553 {
1554 static const struct dmi_system_id broken_systems[] = {
1555 {
1556 .ident = "HP Compaq 2510p",
1557 .matches = {
1558 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1559 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1560 },
1561 /* PCI slot number of the controller */
1562 .driver_data = (void *)0x1FUL,
1563 },
1564 {
1565 .ident = "HP Compaq nc6000",
1566 .matches = {
1567 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1568 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1569 },
1570 /* PCI slot number of the controller */
1571 .driver_data = (void *)0x1FUL,
1572 },
1573
1574 { } /* terminate list */
1575 };
1576 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1577
1578 if (dmi) {
1579 unsigned long slot = (unsigned long)dmi->driver_data;
1580 /* apply the quirk only to on-board controllers */
1581 return slot == PCI_SLOT(pdev->devfn);
1582 }
1583
1584 return false;
1585 }
1586
1587 static int prefer_ms_hyperv = 1;
1588 module_param(prefer_ms_hyperv, int, 0);
1589 MODULE_PARM_DESC(prefer_ms_hyperv,
1590 "Prefer Hyper-V paravirtualization drivers instead of ATA, "
1591 "0 - Use ATA drivers, "
1592 "1 (Default) - Use the paravirtualization drivers.");
1593
1594 static void piix_ignore_devices_quirk(struct ata_host *host)
1595 {
1596 #if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1597 static const struct dmi_system_id ignore_hyperv[] = {
1598 {
1599 /* On Hyper-V hypervisors the disks are exposed on
1600 * both the emulated SATA controller and on the
1601 * paravirtualised drivers. The CD/DVD devices
1602 * are only exposed on the emulated controller.
1603 * Request we ignore ATA devices on this host.
1604 */
1605 .ident = "Hyper-V Virtual Machine",
1606 .matches = {
1607 DMI_MATCH(DMI_SYS_VENDOR,
1608 "Microsoft Corporation"),
1609 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1610 },
1611 },
1612 { } /* terminate list */
1613 };
1614 static const struct dmi_system_id allow_virtual_pc[] = {
1615 {
1616 /* In MS Virtual PC guests the DMI ident is nearly
1617 * identical to a Hyper-V guest. One difference is the
1618 * product version which is used here to identify
1619 * a Virtual PC guest. This entry allows ata_piix to
1620 * drive the emulated hardware.
1621 */
1622 .ident = "MS Virtual PC 2007",
1623 .matches = {
1624 DMI_MATCH(DMI_SYS_VENDOR,
1625 "Microsoft Corporation"),
1626 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1627 DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
1628 },
1629 },
1630 { } /* terminate list */
1631 };
1632 const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
1633 const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
1634
1635 if (ignore && !allow && prefer_ms_hyperv) {
1636 host->flags |= ATA_HOST_IGNORE_ATA;
1637 dev_info(host->dev, "%s detected, ATA device ignore set\n",
1638 ignore->ident);
1639 }
1640 #endif
1641 }
1642
1643 /**
1644 * piix_init_one - Register PIIX ATA PCI device with kernel services
1645 * @pdev: PCI device to register
1646 * @ent: Entry in piix_pci_tbl matching with @pdev
1647 *
1648 * Called from kernel PCI layer. We probe for combined mode (sigh),
1649 * and then hand over control to libata, for it to do the rest.
1650 *
1651 * LOCKING:
1652 * Inherited from PCI layer (may sleep).
1653 *
1654 * RETURNS:
1655 * Zero on success, or -ERRNO value.
1656 */
1657
1658 static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1659 {
1660 struct device *dev = &pdev->dev;
1661 struct ata_port_info port_info[2];
1662 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1663 struct scsi_host_template *sht = &piix_sht;
1664 unsigned long port_flags;
1665 struct ata_host *host;
1666 struct piix_host_priv *hpriv;
1667 int rc;
1668
1669 ata_print_version_once(&pdev->dev, DRV_VERSION);
1670
1671 /* no hotplugging support for later devices (FIXME) */
1672 if (!in_module_init && ent->driver_data >= ich5_sata)
1673 return -ENODEV;
1674
1675 if (piix_broken_system_poweroff(pdev)) {
1676 piix_port_info[ent->driver_data].flags |=
1677 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1678 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1679 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1680 "on poweroff and hibernation\n");
1681 }
1682
1683 port_info[0] = piix_port_info[ent->driver_data];
1684 port_info[1] = piix_port_info[ent->driver_data];
1685
1686 port_flags = port_info[0].flags;
1687
1688 /* enable device and prepare host */
1689 rc = pcim_enable_device(pdev);
1690 if (rc)
1691 return rc;
1692
1693 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1694 if (!hpriv)
1695 return -ENOMEM;
1696
1697 /* Save IOCFG, this will be used for cable detection, quirk
1698 * detection and restoration on detach. This is necessary
1699 * because some ACPI implementations mess up cable related
1700 * bits on _STM. Reported on kernel bz#11879.
1701 */
1702 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1703
1704 /* ICH6R may be driven by either ata_piix or ahci driver
1705 * regardless of BIOS configuration. Make sure AHCI mode is
1706 * off.
1707 */
1708 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1709 rc = piix_disable_ahci(pdev);
1710 if (rc)
1711 return rc;
1712 }
1713
1714 /* SATA map init can change port_info, do it before prepping host */
1715 if (port_flags & ATA_FLAG_SATA)
1716 hpriv->map = piix_init_sata_map(pdev, port_info,
1717 piix_map_db_table[ent->driver_data]);
1718
1719 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1720 if (rc)
1721 return rc;
1722 host->private_data = hpriv;
1723
1724 /* initialize controller */
1725 if (port_flags & ATA_FLAG_SATA) {
1726 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1727 rc = piix_init_sidpr(host);
1728 if (rc)
1729 return rc;
1730 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1731 sht = &piix_sidpr_sht;
1732 }
1733
1734 /* apply IOCFG bit18 quirk */
1735 piix_iocfg_bit18_quirk(host);
1736
1737 /* On ICH5, some BIOSen disable the interrupt using the
1738 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1739 * On ICH6, this bit has the same effect, but only when
1740 * MSI is disabled (and it is disabled, as we don't use
1741 * message-signalled interrupts currently).
1742 */
1743 if (port_flags & PIIX_FLAG_CHECKINTR)
1744 pci_intx(pdev, 1);
1745
1746 if (piix_check_450nx_errata(pdev)) {
1747 /* This writes into the master table but it does not
1748 really matter for this errata as we will apply it to
1749 all the PIIX devices on the board */
1750 host->ports[0]->mwdma_mask = 0;
1751 host->ports[0]->udma_mask = 0;
1752 host->ports[1]->mwdma_mask = 0;
1753 host->ports[1]->udma_mask = 0;
1754 }
1755 host->flags |= ATA_HOST_PARALLEL_SCAN;
1756
1757 /* Allow hosts to specify device types to ignore when scanning. */
1758 piix_ignore_devices_quirk(host);
1759
1760 pci_set_master(pdev);
1761 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1762 }
1763
1764 static void piix_remove_one(struct pci_dev *pdev)
1765 {
1766 struct ata_host *host = pci_get_drvdata(pdev);
1767 struct piix_host_priv *hpriv = host->private_data;
1768
1769 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1770
1771 ata_pci_remove_one(pdev);
1772 }
1773
1774 static struct pci_driver piix_pci_driver = {
1775 .name = DRV_NAME,
1776 .id_table = piix_pci_tbl,
1777 .probe = piix_init_one,
1778 .remove = piix_remove_one,
1779 #ifdef CONFIG_PM_SLEEP
1780 .suspend = piix_pci_device_suspend,
1781 .resume = piix_pci_device_resume,
1782 #endif
1783 };
1784
1785 static int __init piix_init(void)
1786 {
1787 int rc;
1788
1789 DPRINTK("pci_register_driver\n");
1790 rc = pci_register_driver(&piix_pci_driver);
1791 if (rc)
1792 return rc;
1793
1794 in_module_init = 0;
1795
1796 DPRINTK("done\n");
1797 return 0;
1798 }
1799
1800 static void __exit piix_exit(void)
1801 {
1802 pci_unregister_driver(&piix_pci_driver);
1803 }
1804
1805 module_init(piix_init);
1806 module_exit(piix_exit);
Linux with added FPC-III support