drivers/ata/sata_svw.c

   1 /*
   2  *  sata_svw.c - ServerWorks / Apple K2 SATA
   3  *
   4  *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
   5  *                 Jeff Garzik <jgarzik@pobox.com>
   6  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   7  *                  on emails.
   8  *
   9  *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
  10  *
  11  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
  12  *
  13  *  This driver probably works with non-Apple versions of the
  14  *  Broadcom chipset...
  15  *
  16  *
  17  *  This program is free software; you can redistribute it and/or modify
  18  *  it under the terms of the GNU General Public License as published by
  19  *  the Free Software Foundation; either version 2, or (at your option)
  20  *  any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful,
  23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  *  GNU General Public License for more details.
  26  *
  27  *  You should have received a copy of the GNU General Public License
  28  *  along with this program; see the file COPYING.  If not, write to
  29  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  30  *
  31  *
  32  *  libata documentation is available via 'make {ps|pdf}docs',
  33  *  as Documentation/driver-api/libata.rst
  34  *
  35  *  Hardware documentation available under NDA.
  36  *
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/pci.h>
  42 #include <linux/blkdev.h>
  43 #include <linux/delay.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/device.h>
  46 #include <scsi/scsi_host.h>
  47 #include <scsi/scsi_cmnd.h>
  48 #include <scsi/scsi.h>
  49 #include <linux/libata.h>
  50 #include <linux/of.h>
  51
  52 #define DRV_NAME        "sata_svw"
  53 #define DRV_VERSION     "2.3"
  54
  55 enum {
  56         /* ap->flags bits */
  57         K2_FLAG_SATA_8_PORTS            = (1 << 24),
  58         K2_FLAG_NO_ATAPI_DMA            = (1 << 25),
  59         K2_FLAG_BAR_POS_3                       = (1 << 26),
  60
  61         /* Taskfile registers offsets */
  62         K2_SATA_TF_CMD_OFFSET           = 0x00,
  63         K2_SATA_TF_DATA_OFFSET          = 0x00,
  64         K2_SATA_TF_ERROR_OFFSET         = 0x04,
  65         K2_SATA_TF_NSECT_OFFSET         = 0x08,
  66         K2_SATA_TF_LBAL_OFFSET          = 0x0c,
  67         K2_SATA_TF_LBAM_OFFSET          = 0x10,
  68         K2_SATA_TF_LBAH_OFFSET          = 0x14,
  69         K2_SATA_TF_DEVICE_OFFSET        = 0x18,
  70         K2_SATA_TF_CMDSTAT_OFFSET       = 0x1c,
  71         K2_SATA_TF_CTL_OFFSET           = 0x20,
  72
  73         /* DMA base */
  74         K2_SATA_DMA_CMD_OFFSET          = 0x30,
  75
  76         /* SCRs base */
  77         K2_SATA_SCR_STATUS_OFFSET       = 0x40,
  78         K2_SATA_SCR_ERROR_OFFSET        = 0x44,
  79         K2_SATA_SCR_CONTROL_OFFSET      = 0x48,
  80
  81         /* Others */
  82         K2_SATA_SICR1_OFFSET            = 0x80,
  83         K2_SATA_SICR2_OFFSET            = 0x84,
  84         K2_SATA_SIM_OFFSET              = 0x88,
  85
  86         /* Port stride */
  87         K2_SATA_PORT_OFFSET             = 0x100,
  88
  89         chip_svw4                       = 0,
  90         chip_svw8                       = 1,
  91         chip_svw42                      = 2,    /* bar 3 */
  92         chip_svw43                      = 3,    /* bar 5 */
  93 };
  94
  95 static u8 k2_stat_check_status(struct ata_port *ap);
  96
  97
  98 static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
  99 {
 100         u8 cmnd = qc->scsicmd->cmnd[0];
 101
 102         if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
 103                 return -1;      /* ATAPI DMA not supported */
 104         else {
 105                 switch (cmnd) {
 106                 case READ_10:
 107                 case READ_12:
 108                 case READ_16:
 109                 case WRITE_10:
 110                 case WRITE_12:
 111                 case WRITE_16:
 112                         return 0;
 113
 114                 default:
 115                         return -1;
 116                 }
 117
 118         }
 119 }
 120
 121 static int k2_sata_scr_read(struct ata_link *link,
 122                             unsigned int sc_reg, u32 *val)
 123 {
 124         if (sc_reg > SCR_CONTROL)
 125                 return -EINVAL;
 126         *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
 127         return 0;
 128 }
 129
 130
 131 static int k2_sata_scr_write(struct ata_link *link,
 132                              unsigned int sc_reg, u32 val)
 133 {
 134         if (sc_reg > SCR_CONTROL)
 135                 return -EINVAL;
 136         writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
 137         return 0;
 138 }
 139
 140 static int k2_sata_softreset(struct ata_link *link,
 141                              unsigned int *class, unsigned long deadline)
 142 {
 143         u8 dmactl;
 144         void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
 145
 146         dmactl = readb(mmio + ATA_DMA_CMD);
 147
 148         /* Clear the start bit */
 149         if (dmactl & ATA_DMA_START) {
 150                 dmactl &= ~ATA_DMA_START;
 151                 writeb(dmactl, mmio + ATA_DMA_CMD);
 152         }
 153
 154         return ata_sff_softreset(link, class, deadline);
 155 }
 156
 157 static int k2_sata_hardreset(struct ata_link *link,
 158                              unsigned int *class, unsigned long deadline)
 159 {
 160         u8 dmactl;
 161         void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
 162
 163         dmactl = readb(mmio + ATA_DMA_CMD);
 164
 165         /* Clear the start bit */
 166         if (dmactl & ATA_DMA_START) {
 167                 dmactl &= ~ATA_DMA_START;
 168                 writeb(dmactl, mmio + ATA_DMA_CMD);
 169         }
 170
 171         return sata_sff_hardreset(link, class, deadline);
 172 }
 173
 174 static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 175 {
 176         struct ata_ioports *ioaddr = &ap->ioaddr;
 177         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 178
 179         if (tf->ctl != ap->last_ctl) {
 180                 writeb(tf->ctl, ioaddr->ctl_addr);
 181                 ap->last_ctl = tf->ctl;
 182                 ata_wait_idle(ap);
 183         }
 184         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 185                 writew(tf->feature | (((u16)tf->hob_feature) << 8),
 186                        ioaddr->feature_addr);
 187                 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
 188                        ioaddr->nsect_addr);
 189                 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
 190                        ioaddr->lbal_addr);
 191                 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
 192                        ioaddr->lbam_addr);
 193                 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
 194                        ioaddr->lbah_addr);
 195         } else if (is_addr) {
 196                 writew(tf->feature, ioaddr->feature_addr);
 197                 writew(tf->nsect, ioaddr->nsect_addr);
 198                 writew(tf->lbal, ioaddr->lbal_addr);
 199                 writew(tf->lbam, ioaddr->lbam_addr);
 200                 writew(tf->lbah, ioaddr->lbah_addr);
 201         }
 202
 203         if (tf->flags & ATA_TFLAG_DEVICE)
 204                 writeb(tf->device, ioaddr->device_addr);
 205
 206         ata_wait_idle(ap);
 207 }
 208
 209
 210 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 211 {
 212         struct ata_ioports *ioaddr = &ap->ioaddr;
 213         u16 nsect, lbal, lbam, lbah, feature;
 214
 215         tf->command = k2_stat_check_status(ap);
 216         tf->device = readw(ioaddr->device_addr);
 217         feature = readw(ioaddr->error_addr);
 218         nsect = readw(ioaddr->nsect_addr);
 219         lbal = readw(ioaddr->lbal_addr);
 220         lbam = readw(ioaddr->lbam_addr);
 221         lbah = readw(ioaddr->lbah_addr);
 222
 223         tf->feature = feature;
 224         tf->nsect = nsect;
 225         tf->lbal = lbal;
 226         tf->lbam = lbam;
 227         tf->lbah = lbah;
 228
 229         if (tf->flags & ATA_TFLAG_LBA48) {
 230                 tf->hob_feature = feature >> 8;
 231                 tf->hob_nsect = nsect >> 8;
 232                 tf->hob_lbal = lbal >> 8;
 233                 tf->hob_lbam = lbam >> 8;
 234                 tf->hob_lbah = lbah >> 8;
 235         }
 236 }
 237
 238 /**
 239  *      k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 240  *      @qc: Info associated with this ATA transaction.
 241  *
 242  *      LOCKING:
 243  *      spin_lock_irqsave(host lock)
 244  */
 245
 246 static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
 247 {
 248         struct ata_port *ap = qc->ap;
 249         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 250         u8 dmactl;
 251         void __iomem *mmio = ap->ioaddr.bmdma_addr;
 252
 253         /* load PRD table addr. */
 254         mb();   /* make sure PRD table writes are visible to controller */
 255         writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
 256
 257         /* specify data direction, triple-check start bit is clear */
 258         dmactl = readb(mmio + ATA_DMA_CMD);
 259         dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
 260         if (!rw)
 261                 dmactl |= ATA_DMA_WR;
 262         writeb(dmactl, mmio + ATA_DMA_CMD);
 263
 264         /* issue r/w command if this is not a ATA DMA command*/
 265         if (qc->tf.protocol != ATA_PROT_DMA)
 266                 ap->ops->sff_exec_command(ap, &qc->tf);
 267 }
 268
 269 /**
 270  *      k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 271  *      @qc: Info associated with this ATA transaction.
 272  *
 273  *      LOCKING:
 274  *      spin_lock_irqsave(host lock)
 275  */
 276
 277 static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
 278 {
 279         struct ata_port *ap = qc->ap;
 280         void __iomem *mmio = ap->ioaddr.bmdma_addr;
 281         u8 dmactl;
 282
 283         /* start host DMA transaction */
 284         dmactl = readb(mmio + ATA_DMA_CMD);
 285         writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
 286         /* This works around possible data corruption.
 287
 288            On certain SATA controllers that can be seen when the r/w
 289            command is given to the controller before the host DMA is
 290            started.
 291
 292            On a Read command, the controller would initiate the
 293            command to the drive even before it sees the DMA
 294            start. When there are very fast drives connected to the
 295            controller, or when the data request hits in the drive
 296            cache, there is the possibility that the drive returns a
 297            part or all of the requested data to the controller before
 298            the DMA start is issued.  In this case, the controller
 299            would become confused as to what to do with the data.  In
 300            the worst case when all the data is returned back to the
 301            controller, the controller could hang. In other cases it
 302            could return partial data returning in data
 303            corruption. This problem has been seen in PPC systems and
 304            can also appear on an system with very fast disks, where
 305            the SATA controller is sitting behind a number of bridges,
 306            and hence there is significant latency between the r/w
 307            command and the start command. */
 308         /* issue r/w command if the access is to ATA */
 309         if (qc->tf.protocol == ATA_PROT_DMA)
 310                 ap->ops->sff_exec_command(ap, &qc->tf);
 311 }
 312
 313
 314 static u8 k2_stat_check_status(struct ata_port *ap)
 315 {
 316         return readl(ap->ioaddr.status_addr);
 317 }
 318
 319 static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
 320 {
 321         struct ata_port *ap;
 322         struct device_node *np;
 323         int index;
 324
 325         /* Find  the ata_port */
 326         ap = ata_shost_to_port(shost);
 327         if (ap == NULL)
 328                 return 0;
 329
 330         /* Find the OF node for the PCI device proper */
 331         np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
 332         if (np == NULL)
 333                 return 0;
 334
 335         /* Match it to a port node */
 336         index = (ap == ap->host->ports[0]) ? 0 : 1;
 337         for (np = np->child; np != NULL; np = np->sibling) {
 338                 const u32 *reg = of_get_property(np, "reg", NULL);
 339                 if (!reg)
 340                         continue;
 341                 if (index == *reg) {
 342                         seq_printf(m, "devspec: %pOF\n", np);
 343                         break;
 344                 }
 345         }
 346         return 0;
 347 }
 348
 349 static struct scsi_host_template k2_sata_sht = {
 350         ATA_BMDMA_SHT(DRV_NAME),
 351         .show_info              = k2_sata_show_info,
 352 };
 353
 354
 355 static struct ata_port_operations k2_sata_ops = {
 356         .inherits               = &ata_bmdma_port_ops,
 357         .softreset              = k2_sata_softreset,
 358         .hardreset              = k2_sata_hardreset,
 359         .sff_tf_load            = k2_sata_tf_load,
 360         .sff_tf_read            = k2_sata_tf_read,
 361         .sff_check_status       = k2_stat_check_status,
 362         .check_atapi_dma        = k2_sata_check_atapi_dma,
 363         .bmdma_setup            = k2_bmdma_setup_mmio,
 364         .bmdma_start            = k2_bmdma_start_mmio,
 365         .scr_read               = k2_sata_scr_read,
 366         .scr_write              = k2_sata_scr_write,
 367 };
 368
 369 static const struct ata_port_info k2_port_info[] = {
 370         /* chip_svw4 */
 371         {
 372                 .flags          = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,
 373                 .pio_mask       = ATA_PIO4,
 374                 .mwdma_mask     = ATA_MWDMA2,
 375                 .udma_mask      = ATA_UDMA6,
 376                 .port_ops       = &k2_sata_ops,
 377         },
 378         /* chip_svw8 */
 379         {
 380                 .flags          = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |
 381                                   K2_FLAG_SATA_8_PORTS,
 382                 .pio_mask       = ATA_PIO4,
 383                 .mwdma_mask     = ATA_MWDMA2,
 384                 .udma_mask      = ATA_UDMA6,
 385                 .port_ops       = &k2_sata_ops,
 386         },
 387         /* chip_svw42 */
 388         {
 389                 .flags          = ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,
 390                 .pio_mask       = ATA_PIO4,
 391                 .mwdma_mask     = ATA_MWDMA2,
 392                 .udma_mask      = ATA_UDMA6,
 393                 .port_ops       = &k2_sata_ops,
 394         },
 395         /* chip_svw43 */
 396         {
 397                 .flags          = ATA_FLAG_SATA,
 398                 .pio_mask       = ATA_PIO4,
 399                 .mwdma_mask     = ATA_MWDMA2,
 400                 .udma_mask      = ATA_UDMA6,
 401                 .port_ops       = &k2_sata_ops,
 402         },
 403 };
 404
 405 static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
 406 {
 407         port->cmd_addr          = base + K2_SATA_TF_CMD_OFFSET;
 408         port->data_addr         = base + K2_SATA_TF_DATA_OFFSET;
 409         port->feature_addr      =
 410         port->error_addr        = base + K2_SATA_TF_ERROR_OFFSET;
 411         port->nsect_addr        = base + K2_SATA_TF_NSECT_OFFSET;
 412         port->lbal_addr         = base + K2_SATA_TF_LBAL_OFFSET;
 413         port->lbam_addr         = base + K2_SATA_TF_LBAM_OFFSET;
 414         port->lbah_addr         = base + K2_SATA_TF_LBAH_OFFSET;
 415         port->device_addr       = base + K2_SATA_TF_DEVICE_OFFSET;
 416         port->command_addr      =
 417         port->status_addr       = base + K2_SATA_TF_CMDSTAT_OFFSET;
 418         port->altstatus_addr    =
 419         port->ctl_addr          = base + K2_SATA_TF_CTL_OFFSET;
 420         port->bmdma_addr        = base + K2_SATA_DMA_CMD_OFFSET;
 421         port->scr_addr          = base + K2_SATA_SCR_STATUS_OFFSET;
 422 }
 423
 424
 425 static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 426 {
 427         const struct ata_port_info *ppi[] =
 428                 { &k2_port_info[ent->driver_data], NULL };
 429         struct ata_host *host;
 430         void __iomem *mmio_base;
 431         int n_ports, i, rc, bar_pos;
 432
 433         ata_print_version_once(&pdev->dev, DRV_VERSION);
 434
 435         /* allocate host */
 436         n_ports = 4;
 437         if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
 438                 n_ports = 8;
 439
 440         host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
 441         if (!host)
 442                 return -ENOMEM;
 443
 444         bar_pos = 5;
 445         if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
 446                 bar_pos = 3;
 447         /*
 448          * If this driver happens to only be useful on Apple's K2, then
 449          * we should check that here as it has a normal Serverworks ID
 450          */
 451         rc = pcim_enable_device(pdev);
 452         if (rc)
 453                 return rc;
 454
 455         /*
 456          * Check if we have resources mapped at all (second function may
 457          * have been disabled by firmware)
 458          */
 459         if (pci_resource_len(pdev, bar_pos) == 0) {
 460                 /* In IDE mode we need to pin the device to ensure that
 461                         pcim_release does not clear the busmaster bit in config
 462                         space, clearing causes busmaster DMA to fail on
 463                         ports 3 & 4 */
 464                 pcim_pin_device(pdev);
 465                 return -ENODEV;
 466         }
 467
 468         /* Request and iomap PCI regions */
 469         rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
 470         if (rc == -EBUSY)
 471                 pcim_pin_device(pdev);
 472         if (rc)
 473                 return rc;
 474         host->iomap = pcim_iomap_table(pdev);
 475         mmio_base = host->iomap[bar_pos];
 476
 477         /* different controllers have different number of ports - currently 4 or 8 */
 478         /* All ports are on the same function. Multi-function device is no
 479          * longer available. This should not be seen in any system. */
 480         for (i = 0; i < host->n_ports; i++) {
 481                 struct ata_port *ap = host->ports[i];
 482                 unsigned int offset = i * K2_SATA_PORT_OFFSET;
 483
 484                 k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
 485
 486                 ata_port_pbar_desc(ap, 5, -1, "mmio");
 487                 ata_port_pbar_desc(ap, 5, offset, "port");
 488         }
 489
 490         rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
 491         if (rc)
 492                 return rc;
 493         rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
 494         if (rc)
 495                 return rc;
 496
 497         /* Clear a magic bit in SCR1 according to Darwin, those help
 498          * some funky seagate drives (though so far, those were already
 499          * set by the firmware on the machines I had access to)
 500          */
 501         writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
 502                mmio_base + K2_SATA_SICR1_OFFSET);
 503
 504         /* Clear SATA error & interrupts we don't use */
 505         writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
 506         writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
 507
 508         pci_set_master(pdev);
 509         return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
 510                                  IRQF_SHARED, &k2_sata_sht);
 511 }
 512
 513 /* 0x240 is device ID for Apple K2 device
 514  * 0x241 is device ID for Serverworks Frodo4
 515  * 0x242 is device ID for Serverworks Frodo8
 516  * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 517  * controller
 518  * */
 519 static const struct pci_device_id k2_sata_pci_tbl[] = {
 520         { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
 521         { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
 522         { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
 523         { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
 524         { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
 525         { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
 526         { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
 527
 528         { }
 529 };
 530
 531 static struct pci_driver k2_sata_pci_driver = {
 532         .name                   = DRV_NAME,
 533         .id_table               = k2_sata_pci_tbl,
 534         .probe                  = k2_sata_init_one,
 535         .remove                 = ata_pci_remove_one,
 536 };
 537
 538 module_pci_driver(k2_sata_pci_driver);
 539
 540 MODULE_AUTHOR("Benjamin Herrenschmidt");
 541 MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
 542 MODULE_LICENSE("GPL");
 543 MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
 544 MODULE_VERSION(DRV_VERSION);