drivers/bus/tegra-gmi.c

   1 /*
   2  * Driver for NVIDIA Generic Memory Interface
   3  *
   4  * Copyright (C) 2016 Host Mobility AB. All rights reserved.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2. This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/of_device.h>
  16 #include <linux/reset.h>
  17
  18 #define TEGRA_GMI_CONFIG                0x00
  19 #define TEGRA_GMI_CONFIG_GO             BIT(31)
  20 #define TEGRA_GMI_BUS_WIDTH_32BIT       BIT(30)
  21 #define TEGRA_GMI_MUX_MODE              BIT(28)
  22 #define TEGRA_GMI_RDY_BEFORE_DATA       BIT(24)
  23 #define TEGRA_GMI_RDY_ACTIVE_HIGH       BIT(23)
  24 #define TEGRA_GMI_ADV_ACTIVE_HIGH       BIT(22)
  25 #define TEGRA_GMI_OE_ACTIVE_HIGH        BIT(21)
  26 #define TEGRA_GMI_CS_ACTIVE_HIGH        BIT(20)
  27 #define TEGRA_GMI_CS_SELECT(x)          ((x & 0x7) << 4)
  28
  29 #define TEGRA_GMI_TIMING0               0x10
  30 #define TEGRA_GMI_MUXED_WIDTH(x)        ((x & 0xf) << 12)
  31 #define TEGRA_GMI_HOLD_WIDTH(x)         ((x & 0xf) << 8)
  32 #define TEGRA_GMI_ADV_WIDTH(x)          ((x & 0xf) << 4)
  33 #define TEGRA_GMI_CE_WIDTH(x)           (x & 0xf)
  34
  35 #define TEGRA_GMI_TIMING1               0x14
  36 #define TEGRA_GMI_WE_WIDTH(x)           ((x & 0xff) << 16)
  37 #define TEGRA_GMI_OE_WIDTH(x)           ((x & 0xff) << 8)
  38 #define TEGRA_GMI_WAIT_WIDTH(x)         (x & 0xff)
  39
  40 #define TEGRA_GMI_MAX_CHIP_SELECT       8
  41
  42 struct tegra_gmi {
  43         struct device *dev;
  44         void __iomem *base;
  45         struct clk *clk;
  46         struct reset_control *rst;
  47
  48         u32 snor_config;
  49         u32 snor_timing0;
  50         u32 snor_timing1;
  51 };
  52
  53 static int tegra_gmi_enable(struct tegra_gmi *gmi)
  54 {
  55         int err;
  56
  57         err = clk_prepare_enable(gmi->clk);
  58         if (err < 0) {
  59                 dev_err(gmi->dev, "failed to enable clock: %d\n", err);
  60                 return err;
  61         }
  62
  63         reset_control_assert(gmi->rst);
  64         usleep_range(2000, 4000);
  65         reset_control_deassert(gmi->rst);
  66
  67         writel(gmi->snor_timing0, gmi->base + TEGRA_GMI_TIMING0);
  68         writel(gmi->snor_timing1, gmi->base + TEGRA_GMI_TIMING1);
  69
  70         gmi->snor_config |= TEGRA_GMI_CONFIG_GO;
  71         writel(gmi->snor_config, gmi->base + TEGRA_GMI_CONFIG);
  72
  73         return 0;
  74 }
  75
  76 static void tegra_gmi_disable(struct tegra_gmi *gmi)
  77 {
  78         u32 config;
  79
  80         /* stop GMI operation */
  81         config = readl(gmi->base + TEGRA_GMI_CONFIG);
  82         config &= ~TEGRA_GMI_CONFIG_GO;
  83         writel(config, gmi->base + TEGRA_GMI_CONFIG);
  84
  85         reset_control_assert(gmi->rst);
  86         clk_disable_unprepare(gmi->clk);
  87 }
  88
  89 static int tegra_gmi_parse_dt(struct tegra_gmi *gmi)
  90 {
  91         struct device_node *child;
  92         u32 property, ranges[4];
  93         int err;
  94
  95         child = of_get_next_available_child(gmi->dev->of_node, NULL);
  96         if (!child) {
  97                 dev_err(gmi->dev, "no child nodes found\n");
  98                 return -ENODEV;
  99         }
 100
 101         /*
 102          * We currently only support one child device due to lack of
 103          * chip-select address decoding. Which means that we only have one
 104          * chip-select line from the GMI controller.
 105          */
 106         if (of_get_child_count(gmi->dev->of_node) > 1)
 107                 dev_warn(gmi->dev, "only one child device is supported.");
 108
 109         if (of_property_read_bool(child, "nvidia,snor-data-width-32bit"))
 110                 gmi->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT;
 111
 112         if (of_property_read_bool(child, "nvidia,snor-mux-mode"))
 113                 gmi->snor_config |= TEGRA_GMI_MUX_MODE;
 114
 115         if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data"))
 116                 gmi->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA;
 117
 118         if (of_property_read_bool(child, "nvidia,snor-rdy-active-high"))
 119                 gmi->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH;
 120
 121         if (of_property_read_bool(child, "nvidia,snor-adv-active-high"))
 122                 gmi->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH;
 123
 124         if (of_property_read_bool(child, "nvidia,snor-oe-active-high"))
 125                 gmi->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH;
 126
 127         if (of_property_read_bool(child, "nvidia,snor-cs-active-high"))
 128                 gmi->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH;
 129
 130         /* Decode the CS# */
 131         err = of_property_read_u32_array(child, "ranges", ranges, 4);
 132         if (err < 0) {
 133                 /* Invalid binding */
 134                 if (err == -EOVERFLOW) {
 135                         dev_err(gmi->dev,
 136                                 "failed to decode CS: invalid ranges length\n");
 137                         goto error_cs;
 138                 }
 139
 140                 /*
 141                  * If we reach here it means that the child node has an empty
 142                  * ranges or it does not exist at all. Attempt to decode the
 143                  * CS# from the reg property instead.
 144                  */
 145                 err = of_property_read_u32(child, "reg", &property);
 146                 if (err < 0) {
 147                         dev_err(gmi->dev,
 148                                 "failed to decode CS: no reg property found\n");
 149                         goto error_cs;
 150                 }
 151         } else {
 152                 property = ranges[1];
 153         }
 154
 155         /* Valid chip selects are CS0-CS7 */
 156         if (property >= TEGRA_GMI_MAX_CHIP_SELECT) {
 157                 dev_err(gmi->dev, "invalid chip select: %d", property);
 158                 err = -EINVAL;
 159                 goto error_cs;
 160         }
 161
 162         gmi->snor_config |= TEGRA_GMI_CS_SELECT(property);
 163
 164         /* The default values that are provided below are reset values */
 165         if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))
 166                 gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
 167         else
 168                 gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1);
 169
 170         if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))
 171                 gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
 172         else
 173                 gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1);
 174
 175         if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))
 176                 gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
 177         else
 178                 gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1);
 179
 180         if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))
 181                 gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
 182         else
 183                 gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4);
 184
 185         if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))
 186                 gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
 187         else
 188                 gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1);
 189
 190         if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))
 191                 gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
 192         else
 193                 gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1);
 194
 195         if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))
 196                 gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);
 197         else
 198                 gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3);
 199
 200 error_cs:
 201         of_node_put(child);
 202         return err;
 203 }
 204
 205 static int tegra_gmi_probe(struct platform_device *pdev)
 206 {
 207         struct device *dev = &pdev->dev;
 208         struct tegra_gmi *gmi;
 209         struct resource *res;
 210         int err;
 211
 212         gmi = devm_kzalloc(dev, sizeof(*gmi), GFP_KERNEL);
 213         if (!gmi)
 214                 return -ENOMEM;
 215
 216         gmi->dev = dev;
 217
 218         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 219         gmi->base = devm_ioremap_resource(dev, res);
 220         if (IS_ERR(gmi->base))
 221                 return PTR_ERR(gmi->base);
 222
 223         gmi->clk = devm_clk_get(dev, "gmi");
 224         if (IS_ERR(gmi->clk)) {
 225                 dev_err(dev, "can not get clock\n");
 226                 return PTR_ERR(gmi->clk);
 227         }
 228
 229         gmi->rst = devm_reset_control_get(dev, "gmi");
 230         if (IS_ERR(gmi->rst)) {
 231                 dev_err(dev, "can not get reset\n");
 232                 return PTR_ERR(gmi->rst);
 233         }
 234
 235         err = tegra_gmi_parse_dt(gmi);
 236         if (err)
 237                 return err;
 238
 239         err = tegra_gmi_enable(gmi);
 240         if (err < 0)
 241                 return err;
 242
 243         err = of_platform_default_populate(dev->of_node, NULL, dev);
 244         if (err < 0) {
 245                 dev_err(dev, "fail to create devices.\n");
 246                 tegra_gmi_disable(gmi);
 247                 return err;
 248         }
 249
 250         platform_set_drvdata(pdev, gmi);
 251
 252         return 0;
 253 }
 254
 255 static int tegra_gmi_remove(struct platform_device *pdev)
 256 {
 257         struct tegra_gmi *gmi = platform_get_drvdata(pdev);
 258
 259         of_platform_depopulate(gmi->dev);
 260         tegra_gmi_disable(gmi);
 261
 262         return 0;
 263 }
 264
 265 static const struct of_device_id tegra_gmi_id_table[] = {
 266         { .compatible = "nvidia,tegra20-gmi", },
 267         { .compatible = "nvidia,tegra30-gmi", },
 268         { }
 269 };
 270 MODULE_DEVICE_TABLE(of, tegra_gmi_id_table);
 271
 272 static struct platform_driver tegra_gmi_driver = {
 273         .probe = tegra_gmi_probe,
 274         .remove = tegra_gmi_remove,
 275         .driver = {
 276                 .name           = "tegra-gmi",
 277                 .of_match_table = tegra_gmi_id_table,
 278         },
 279 };
 280 module_platform_driver(tegra_gmi_driver);
 281
 282 MODULE_AUTHOR("Mirza Krak <mirza.krak@gmail.com");
 283 MODULE_DESCRIPTION("NVIDIA Tegra GMI Bus Driver");
 284 MODULE_LICENSE("GPL v2");