drivers/clk/bcm/clk-sr.c

   1 /*
   2  * Copyright 2017 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License, version 2, as
   6  * published by the Free Software Foundation (the "GPL").
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License version 2 (GPLv2) for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * version 2 (GPLv2) along with this source code.
  15  */
  16
  17 #include <linux/err.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21
  22 #include <dt-bindings/clock/bcm-sr.h>
  23 #include "clk-iproc.h"
  24
  25 #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
  26
  27 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
  28         .pwr_shift = ps, .iso_shift = is }
  29
  30 #define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
  31
  32 #define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
  33         .p_reset_shift = prs }
  34
  35 #define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
  36         .ki_shift = kis, .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, \
  37         .ka_shift = kas, .ka_width = kaw }
  38
  39 #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
  40
  41 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
  42         .hold_shift = hs, .bypass_shift = bs }
  43
  44
  45 static const struct iproc_pll_ctrl sr_genpll0 = {
  46         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
  47                 IPROC_CLK_PLL_NEEDS_SW_CFG,
  48         .aon = AON_VAL(0x0, 5, 1, 0),
  49         .reset = RESET_VAL(0x0, 12, 11),
  50         .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
  51         .sw_ctrl = SW_CTRL_VAL(0x10, 31),
  52         .ndiv_int = REG_VAL(0x10, 20, 10),
  53         .ndiv_frac = REG_VAL(0x10, 0, 20),
  54         .pdiv = REG_VAL(0x14, 0, 4),
  55         .status = REG_VAL(0x30, 12, 1),
  56 };
  57
  58 static const struct iproc_clk_ctrl sr_genpll0_clk[] = {
  59         [BCM_SR_GENPLL0_125M_CLK] = {
  60                 .channel = BCM_SR_GENPLL0_125M_CLK,
  61                 .flags = IPROC_CLK_AON,
  62                 .enable = ENABLE_VAL(0x4, 6, 0, 12),
  63                 .mdiv = REG_VAL(0x18, 0, 9),
  64         },
  65         [BCM_SR_GENPLL0_SCR_CLK] = {
  66                 .channel = BCM_SR_GENPLL0_SCR_CLK,
  67                 .flags = IPROC_CLK_AON,
  68                 .enable = ENABLE_VAL(0x4, 7, 1, 13),
  69                 .mdiv = REG_VAL(0x18, 10, 9),
  70         },
  71         [BCM_SR_GENPLL0_250M_CLK] = {
  72                 .channel = BCM_SR_GENPLL0_250M_CLK,
  73                 .flags = IPROC_CLK_AON,
  74                 .enable = ENABLE_VAL(0x4, 8, 2, 14),
  75                 .mdiv = REG_VAL(0x18, 20, 9),
  76         },
  77         [BCM_SR_GENPLL0_PCIE_AXI_CLK] = {
  78                 .channel = BCM_SR_GENPLL0_PCIE_AXI_CLK,
  79                 .flags = IPROC_CLK_AON,
  80                 .enable = ENABLE_VAL(0x4, 9, 3, 15),
  81                 .mdiv = REG_VAL(0x1c, 0, 9),
  82         },
  83         [BCM_SR_GENPLL0_PAXC_AXI_X2_CLK] = {
  84                 .channel = BCM_SR_GENPLL0_PAXC_AXI_X2_CLK,
  85                 .flags = IPROC_CLK_AON,
  86                 .enable = ENABLE_VAL(0x4, 10, 4, 16),
  87                 .mdiv = REG_VAL(0x1c, 10, 9),
  88         },
  89         [BCM_SR_GENPLL0_PAXC_AXI_CLK] = {
  90                 .channel = BCM_SR_GENPLL0_PAXC_AXI_CLK,
  91                 .flags = IPROC_CLK_AON,
  92                 .enable = ENABLE_VAL(0x4, 11, 5, 17),
  93                 .mdiv = REG_VAL(0x1c, 20, 9),
  94         },
  95 };
  96
  97 static int sr_genpll0_clk_init(struct platform_device *pdev)
  98 {
  99         iproc_pll_clk_setup(pdev->dev.of_node,
 100                             &sr_genpll0, NULL, 0, sr_genpll0_clk,
 101                             ARRAY_SIZE(sr_genpll0_clk));
 102         return 0;
 103 }
 104
 105 static const struct iproc_pll_ctrl sr_genpll2 = {
 106         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
 107                 IPROC_CLK_PLL_NEEDS_SW_CFG,
 108         .aon = AON_VAL(0x0, 1, 13, 12),
 109         .reset = RESET_VAL(0x0, 12, 11),
 110         .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
 111         .sw_ctrl = SW_CTRL_VAL(0x10, 31),
 112         .ndiv_int = REG_VAL(0x10, 20, 10),
 113         .ndiv_frac = REG_VAL(0x10, 0, 20),
 114         .pdiv = REG_VAL(0x14, 0, 4),
 115         .status = REG_VAL(0x30, 12, 1),
 116 };
 117
 118 static const struct iproc_clk_ctrl sr_genpll2_clk[] = {
 119         [BCM_SR_GENPLL2_NIC_CLK] = {
 120                 .channel = BCM_SR_GENPLL2_NIC_CLK,
 121                 .flags = IPROC_CLK_AON,
 122                 .enable = ENABLE_VAL(0x4, 6, 0, 12),
 123                 .mdiv = REG_VAL(0x18, 0, 9),
 124         },
 125         [BCM_SR_GENPLL2_TS_500_CLK] = {
 126                 .channel = BCM_SR_GENPLL2_TS_500_CLK,
 127                 .flags = IPROC_CLK_AON,
 128                 .enable = ENABLE_VAL(0x4, 7, 1, 13),
 129                 .mdiv = REG_VAL(0x18, 10, 9),
 130         },
 131         [BCM_SR_GENPLL2_125_NITRO_CLK] = {
 132                 .channel = BCM_SR_GENPLL2_125_NITRO_CLK,
 133                 .flags = IPROC_CLK_AON,
 134                 .enable = ENABLE_VAL(0x4, 8, 2, 14),
 135                 .mdiv = REG_VAL(0x18, 20, 9),
 136         },
 137         [BCM_SR_GENPLL2_CHIMP_CLK] = {
 138                 .channel = BCM_SR_GENPLL2_CHIMP_CLK,
 139                 .flags = IPROC_CLK_AON,
 140                 .enable = ENABLE_VAL(0x4, 9, 3, 15),
 141                 .mdiv = REG_VAL(0x1c, 0, 9),
 142         },
 143         [BCM_SR_GENPLL2_NIC_FLASH_CLK] = {
 144                 .channel = BCM_SR_GENPLL2_NIC_FLASH_CLK,
 145                 .flags = IPROC_CLK_AON,
 146                 .enable = ENABLE_VAL(0x4, 10, 4, 16),
 147                 .mdiv = REG_VAL(0x1c, 10, 9),
 148         },
 149         [BCM_SR_GENPLL2_FS4_CLK] = {
 150                 .channel = BCM_SR_GENPLL2_FS4_CLK,
 151                 .enable = ENABLE_VAL(0x4, 11, 5, 17),
 152                 .mdiv = REG_VAL(0x1c, 20, 9),
 153         },
 154 };
 155
 156 static int sr_genpll2_clk_init(struct platform_device *pdev)
 157 {
 158         iproc_pll_clk_setup(pdev->dev.of_node,
 159                             &sr_genpll2, NULL, 0, sr_genpll2_clk,
 160                             ARRAY_SIZE(sr_genpll2_clk));
 161         return 0;
 162 }
 163
 164 static const struct iproc_pll_ctrl sr_genpll3 = {
 165         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
 166                 IPROC_CLK_PLL_NEEDS_SW_CFG,
 167         .aon = AON_VAL(0x0, 1, 19, 18),
 168         .reset = RESET_VAL(0x0, 12, 11),
 169         .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
 170         .sw_ctrl = SW_CTRL_VAL(0x10, 31),
 171         .ndiv_int = REG_VAL(0x10, 20, 10),
 172         .ndiv_frac = REG_VAL(0x10, 0, 20),
 173         .pdiv = REG_VAL(0x14, 0, 4),
 174         .status = REG_VAL(0x30, 12, 1),
 175 };
 176
 177 static const struct iproc_clk_ctrl sr_genpll3_clk[] = {
 178         [BCM_SR_GENPLL3_HSLS_CLK] = {
 179                 .channel = BCM_SR_GENPLL3_HSLS_CLK,
 180                 .flags = IPROC_CLK_AON,
 181                 .enable = ENABLE_VAL(0x4, 6, 0, 12),
 182                 .mdiv = REG_VAL(0x18, 0, 9),
 183         },
 184         [BCM_SR_GENPLL3_SDIO_CLK] = {
 185                 .channel = BCM_SR_GENPLL3_SDIO_CLK,
 186                 .flags = IPROC_CLK_AON,
 187                 .enable = ENABLE_VAL(0x4, 7, 1, 13),
 188                 .mdiv = REG_VAL(0x18, 10, 9),
 189         },
 190 };
 191
 192 static void sr_genpll3_clk_init(struct device_node *node)
 193 {
 194         iproc_pll_clk_setup(node, &sr_genpll3, NULL, 0, sr_genpll3_clk,
 195                             ARRAY_SIZE(sr_genpll3_clk));
 196 }
 197 CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3", sr_genpll3_clk_init);
 198
 199 static const struct iproc_pll_ctrl sr_genpll4 = {
 200         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
 201                 IPROC_CLK_PLL_NEEDS_SW_CFG,
 202         .aon = AON_VAL(0x0, 1, 25, 24),
 203         .reset = RESET_VAL(0x0, 12, 11),
 204         .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
 205         .sw_ctrl = SW_CTRL_VAL(0x10, 31),
 206         .ndiv_int = REG_VAL(0x10, 20, 10),
 207         .ndiv_frac = REG_VAL(0x10, 0, 20),
 208         .pdiv = REG_VAL(0x14, 0, 4),
 209         .status = REG_VAL(0x30, 12, 1),
 210 };
 211
 212 static const struct iproc_clk_ctrl sr_genpll4_clk[] = {
 213         [BCM_SR_GENPLL4_CCN_CLK] = {
 214                 .channel = BCM_SR_GENPLL4_CCN_CLK,
 215                 .flags = IPROC_CLK_AON,
 216                 .enable = ENABLE_VAL(0x4, 6, 0, 12),
 217                 .mdiv = REG_VAL(0x18, 0, 9),
 218         },
 219         [BCM_SR_GENPLL4_TPIU_PLL_CLK] = {
 220                 .channel = BCM_SR_GENPLL4_TPIU_PLL_CLK,
 221                 .flags = IPROC_CLK_AON,
 222                 .enable = ENABLE_VAL(0x4, 7, 1, 13),
 223                 .mdiv = REG_VAL(0x18, 10, 9),
 224         },
 225         [BCM_SR_GENPLL4_NOC_CLK] = {
 226                 .channel = BCM_SR_GENPLL4_NOC_CLK,
 227                 .flags = IPROC_CLK_AON,
 228                 .enable = ENABLE_VAL(0x4, 8, 2, 14),
 229                 .mdiv = REG_VAL(0x18, 20, 9),
 230         },
 231         [BCM_SR_GENPLL4_CHCLK_FS4_CLK] = {
 232                 .channel = BCM_SR_GENPLL4_CHCLK_FS4_CLK,
 233                 .flags = IPROC_CLK_AON,
 234                 .enable = ENABLE_VAL(0x4, 9, 3, 15),
 235                 .mdiv = REG_VAL(0x1c, 0, 9),
 236         },
 237         [BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK] = {
 238                 .channel = BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK,
 239                 .flags = IPROC_CLK_AON,
 240                 .enable = ENABLE_VAL(0x4, 10, 4, 16),
 241                 .mdiv = REG_VAL(0x1c, 10, 9),
 242         },
 243 };
 244
 245 static int sr_genpll4_clk_init(struct platform_device *pdev)
 246 {
 247         iproc_pll_clk_setup(pdev->dev.of_node,
 248                             &sr_genpll4, NULL, 0, sr_genpll4_clk,
 249                             ARRAY_SIZE(sr_genpll4_clk));
 250         return 0;
 251 }
 252
 253 static const struct iproc_pll_ctrl sr_genpll5 = {
 254         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
 255                 IPROC_CLK_PLL_NEEDS_SW_CFG,
 256         .aon = AON_VAL(0x0, 1, 1, 0),
 257         .reset = RESET_VAL(0x0, 12, 11),
 258         .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
 259         .sw_ctrl = SW_CTRL_VAL(0x10, 31),
 260         .ndiv_int = REG_VAL(0x10, 20, 10),
 261         .ndiv_frac = REG_VAL(0x10, 0, 20),
 262         .pdiv = REG_VAL(0x14, 0, 4),
 263         .status = REG_VAL(0x30, 12, 1),
 264 };
 265
 266 static const struct iproc_clk_ctrl sr_genpll5_clk[] = {
 267         [BCM_SR_GENPLL5_FS4_HF_CLK] = {
 268                 .channel = BCM_SR_GENPLL5_FS4_HF_CLK,
 269                 .enable = ENABLE_VAL(0x4, 6, 0, 12),
 270                 .mdiv = REG_VAL(0x18, 0, 9),
 271         },
 272         [BCM_SR_GENPLL5_CRYPTO_AE_CLK] = {
 273                 .channel = BCM_SR_GENPLL5_CRYPTO_AE_CLK,
 274                 .enable = ENABLE_VAL(0x4, 7, 1, 12),
 275                 .mdiv = REG_VAL(0x18, 10, 9),
 276         },
 277         [BCM_SR_GENPLL5_RAID_AE_CLK] = {
 278                 .channel = BCM_SR_GENPLL5_RAID_AE_CLK,
 279                 .enable = ENABLE_VAL(0x4, 8, 2, 14),
 280                 .mdiv = REG_VAL(0x18, 20, 9),
 281         },
 282 };
 283
 284 static int sr_genpll5_clk_init(struct platform_device *pdev)
 285 {
 286         iproc_pll_clk_setup(pdev->dev.of_node,
 287                             &sr_genpll5, NULL, 0, sr_genpll5_clk,
 288                             ARRAY_SIZE(sr_genpll5_clk));
 289         return 0;
 290 }
 291
 292 static const struct iproc_pll_ctrl sr_lcpll0 = {
 293         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
 294         .aon = AON_VAL(0x0, 2, 19, 18),
 295         .reset = RESET_VAL(0x0, 31, 30),
 296         .sw_ctrl = SW_CTRL_VAL(0x4, 31),
 297         .ndiv_int = REG_VAL(0x4, 16, 10),
 298         .pdiv = REG_VAL(0x4, 26, 4),
 299         .status = REG_VAL(0x38, 12, 1),
 300 };
 301
 302 static const struct iproc_clk_ctrl sr_lcpll0_clk[] = {
 303         [BCM_SR_LCPLL0_SATA_REFP_CLK] = {
 304                 .channel = BCM_SR_LCPLL0_SATA_REFP_CLK,
 305                 .flags = IPROC_CLK_AON,
 306                 .enable = ENABLE_VAL(0x0, 7, 1, 13),
 307                 .mdiv = REG_VAL(0x14, 0, 9),
 308         },
 309         [BCM_SR_LCPLL0_SATA_REFN_CLK] = {
 310                 .channel = BCM_SR_LCPLL0_SATA_REFN_CLK,
 311                 .flags = IPROC_CLK_AON,
 312                 .enable = ENABLE_VAL(0x0, 8, 2, 14),
 313                 .mdiv = REG_VAL(0x14, 10, 9),
 314         },
 315         [BCM_SR_LCPLL0_SATA_350_CLK] = {
 316                 .channel = BCM_SR_LCPLL0_SATA_350_CLK,
 317                 .flags = IPROC_CLK_AON,
 318                 .enable = ENABLE_VAL(0x0, 9, 3, 15),
 319                 .mdiv = REG_VAL(0x14, 20, 9),
 320         },
 321         [BCM_SR_LCPLL0_SATA_500_CLK] = {
 322                 .channel = BCM_SR_LCPLL0_SATA_500_CLK,
 323                 .flags = IPROC_CLK_AON,
 324                 .enable = ENABLE_VAL(0x0, 10, 4, 16),
 325                 .mdiv = REG_VAL(0x18, 0, 9),
 326         },
 327 };
 328
 329 static int sr_lcpll0_clk_init(struct platform_device *pdev)
 330 {
 331         iproc_pll_clk_setup(pdev->dev.of_node,
 332                             &sr_lcpll0, NULL, 0, sr_lcpll0_clk,
 333                             ARRAY_SIZE(sr_lcpll0_clk));
 334         return 0;
 335 }
 336
 337 static const struct iproc_pll_ctrl sr_lcpll1 = {
 338         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
 339         .aon = AON_VAL(0x0, 2, 22, 21),
 340         .reset = RESET_VAL(0x0, 31, 30),
 341         .sw_ctrl = SW_CTRL_VAL(0x4, 31),
 342         .ndiv_int = REG_VAL(0x4, 16, 10),
 343         .pdiv = REG_VAL(0x4, 26, 4),
 344         .status = REG_VAL(0x38, 12, 1),
 345 };
 346
 347 static const struct iproc_clk_ctrl sr_lcpll1_clk[] = {
 348         [BCM_SR_LCPLL1_WAN_CLK] = {
 349                 .channel = BCM_SR_LCPLL1_WAN_CLK,
 350                 .flags = IPROC_CLK_AON,
 351                 .enable = ENABLE_VAL(0x0, 7, 1, 13),
 352                 .mdiv = REG_VAL(0x14, 0, 9),
 353         },
 354         [BCM_SR_LCPLL1_USB_REF_CLK] = {
 355                 .channel = BCM_SR_LCPLL1_USB_REF_CLK,
 356                 .flags = IPROC_CLK_AON,
 357                 .enable = ENABLE_VAL(0x0, 8, 2, 14),
 358                 .mdiv = REG_VAL(0x14, 10, 9),
 359         },
 360         [BCM_SR_LCPLL1_CRMU_TS_CLK] = {
 361                 .channel = BCM_SR_LCPLL1_CRMU_TS_CLK,
 362                 .flags = IPROC_CLK_AON,
 363                 .enable = ENABLE_VAL(0x0, 9, 3, 15),
 364                 .mdiv = REG_VAL(0x14, 20, 9),
 365         },
 366 };
 367
 368 static int sr_lcpll1_clk_init(struct platform_device *pdev)
 369 {
 370         iproc_pll_clk_setup(pdev->dev.of_node,
 371                             &sr_lcpll1, NULL, 0, sr_lcpll1_clk,
 372                             ARRAY_SIZE(sr_lcpll1_clk));
 373         return 0;
 374 }
 375
 376 static const struct iproc_pll_ctrl sr_lcpll_pcie = {
 377         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
 378         .aon = AON_VAL(0x0, 2, 25, 24),
 379         .reset = RESET_VAL(0x0, 31, 30),
 380         .sw_ctrl = SW_CTRL_VAL(0x4, 31),
 381         .ndiv_int = REG_VAL(0x4, 16, 10),
 382         .pdiv = REG_VAL(0x4, 26, 4),
 383         .status = REG_VAL(0x38, 12, 1),
 384 };
 385
 386 static const struct iproc_clk_ctrl sr_lcpll_pcie_clk[] = {
 387         [BCM_SR_LCPLL_PCIE_PHY_REF_CLK] = {
 388                 .channel = BCM_SR_LCPLL_PCIE_PHY_REF_CLK,
 389                 .flags = IPROC_CLK_AON,
 390                 .enable = ENABLE_VAL(0x0, 7, 1, 13),
 391                 .mdiv = REG_VAL(0x14, 0, 9),
 392         },
 393 };
 394
 395 static int sr_lcpll_pcie_clk_init(struct platform_device *pdev)
 396 {
 397         iproc_pll_clk_setup(pdev->dev.of_node,
 398                             &sr_lcpll_pcie, NULL, 0, sr_lcpll_pcie_clk,
 399                             ARRAY_SIZE(sr_lcpll_pcie_clk));
 400         return 0;
 401 }
 402
 403 static const struct of_device_id sr_clk_dt_ids[] = {
 404         { .compatible = "brcm,sr-genpll0", .data = sr_genpll0_clk_init },
 405         { .compatible = "brcm,sr-genpll2", .data = sr_genpll2_clk_init },
 406         { .compatible = "brcm,sr-genpll4", .data = sr_genpll4_clk_init },
 407         { .compatible = "brcm,sr-genpll5", .data = sr_genpll5_clk_init },
 408         { .compatible = "brcm,sr-lcpll0", .data = sr_lcpll0_clk_init },
 409         { .compatible = "brcm,sr-lcpll1", .data = sr_lcpll1_clk_init },
 410         { .compatible = "brcm,sr-lcpll-pcie", .data = sr_lcpll_pcie_clk_init },
 411         { /* sentinel */ }
 412 };
 413
 414 static int sr_clk_probe(struct platform_device *pdev)
 415 {
 416         int (*probe_func)(struct platform_device *);
 417
 418         probe_func = of_device_get_match_data(&pdev->dev);
 419         if (!probe_func)
 420                 return -ENODEV;
 421
 422         return probe_func(pdev);
 423 }
 424
 425 static struct platform_driver sr_clk_driver = {
 426         .driver = {
 427                 .name = "sr-clk",
 428                 .of_match_table = sr_clk_dt_ids,
 429         },
 430         .probe = sr_clk_probe,
 431 };
 432 builtin_platform_driver(sr_clk_driver);