1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
8 #include <linux/clk-provider.h>
10 #include <linux/device.h>
11 #include <linux/of_address.h>
12 #include <linux/slab.h>
14 static DEFINE_SPINLOCK(clklock
);
16 #define MAX_FREQ 33333333
17 #define MIN_FREQ 8000000
25 #define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
27 static unsigned long pll_recalc_rate(struct clk_hw
*hw
,
28 unsigned long parent_rate
)
30 struct pll_clock
*pll_clock
= to_pll_clock(hw
);
31 int mul
= 1 << (readb(pll_clock
->pllcr
) & 3);
33 return parent_rate
* mul
;
36 static long pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
47 for (i
= 0; i
< 3; i
++)
48 offset
[i
] = abs(rate
- (*prate
* (1 << i
)));
49 for (i
= 0; i
< 3; i
++)
53 m
= (offset
[i
] < offset
[m
])?i
:m
;
55 return *prate
* (1 << m
);
58 static int pll_set_rate(struct clk_hw
*hw
, unsigned long rate
,
59 unsigned long parent_rate
)
64 struct pll_clock
*pll_clock
= to_pll_clock(hw
);
66 pll
= ((rate
/ parent_rate
) / 2) & 0x03;
67 spin_lock_irqsave(&clklock
, flags
);
68 val
= readb(pll_clock
->sckcr
);
70 writeb(val
, pll_clock
->sckcr
);
71 val
= readb(pll_clock
->pllcr
);
74 writeb(val
, pll_clock
->pllcr
);
75 spin_unlock_irqrestore(&clklock
, flags
);
79 static const struct clk_ops pll_ops
= {
80 .recalc_rate
= pll_recalc_rate
,
81 .round_rate
= pll_round_rate
,
82 .set_rate
= pll_set_rate
,
85 static void __init
h8s2678_pll_clk_setup(struct device_node
*node
)
87 unsigned int num_parents
;
88 const char *clk_name
= node
->name
;
89 const char *parent_name
;
90 struct pll_clock
*pll_clock
;
91 struct clk_init_data init
;
94 num_parents
= of_clk_get_parent_count(node
);
96 pr_err("%s: no parent found\n", clk_name
);
101 pll_clock
= kzalloc(sizeof(*pll_clock
), GFP_KERNEL
);
105 pll_clock
->sckcr
= of_iomap(node
, 0);
106 if (pll_clock
->sckcr
== NULL
) {
107 pr_err("%s: failed to map divide register\n", clk_name
);
111 pll_clock
->pllcr
= of_iomap(node
, 1);
112 if (pll_clock
->pllcr
== NULL
) {
113 pr_err("%s: failed to map multiply register\n", clk_name
);
117 parent_name
= of_clk_get_parent_name(node
, 0);
118 init
.name
= clk_name
;
120 init
.flags
= CLK_IS_BASIC
;
121 init
.parent_names
= &parent_name
;
122 init
.num_parents
= 1;
123 pll_clock
->hw
.init
= &init
;
125 ret
= clk_hw_register(NULL
, &pll_clock
->hw
);
127 pr_err("%s: failed to register %s div clock (%d)\n",
128 __func__
, clk_name
, ret
);
132 of_clk_add_hw_provider(node
, of_clk_hw_simple_get
, &pll_clock
->hw
);
136 iounmap(pll_clock
->pllcr
);
138 iounmap(pll_clock
->sckcr
);
143 CLK_OF_DECLARE(h8s2678_div_clk
, "renesas,h8s2678-pll-clock",
144 h8s2678_pll_clk_setup
);