2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/clock/imx6ul-clock.h>
13 #include <linux/clk.h>
14 #include <linux/clkdev.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/types.h>
25 #define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16)
28 static const char *pll_bypass_src_sels
[] = { "osc", "dummy", };
29 static const char *pll1_bypass_sels
[] = { "pll1", "pll1_bypass_src", };
30 static const char *pll2_bypass_sels
[] = { "pll2", "pll2_bypass_src", };
31 static const char *pll3_bypass_sels
[] = { "pll3", "pll3_bypass_src", };
32 static const char *pll4_bypass_sels
[] = { "pll4", "pll4_bypass_src", };
33 static const char *pll5_bypass_sels
[] = { "pll5", "pll5_bypass_src", };
34 static const char *pll6_bypass_sels
[] = { "pll6", "pll6_bypass_src", };
35 static const char *pll7_bypass_sels
[] = { "pll7", "pll7_bypass_src", };
36 static const char *ca7_secondary_sels
[] = { "pll2_pfd2_396m", "pll2_bus", };
37 static const char *step_sels
[] = { "osc", "ca7_secondary_sel", };
38 static const char *pll1_sw_sels
[] = { "pll1_sys", "step", };
39 static const char *axi_alt_sels
[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
40 static const char *axi_sels
[] = {"periph", "axi_alt_sel", };
41 static const char *periph_pre_sels
[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
42 static const char *periph2_pre_sels
[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
43 static const char *periph_clk2_sels
[] = { "pll3_usb_otg", "osc", "pll2_bypass_src", };
44 static const char *periph2_clk2_sels
[] = { "pll3_usb_otg", "osc", };
45 static const char *periph_sels
[] = { "periph_pre", "periph_clk2", };
46 static const char *periph2_sels
[] = { "periph2_pre", "periph2_clk2", };
47 static const char *usdhc_sels
[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
48 static const char *bch_sels
[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
49 static const char *gpmi_sels
[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
50 static const char *eim_slow_sels
[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd0_720m", };
51 static const char *spdif_sels
[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
52 static const char *sai_sels
[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", };
53 static const char *lcdif_pre_sels
[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
54 static const char *sim_pre_sels
[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
55 static const char *ldb_di0_sels
[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
56 static const char *ldb_di0_div_sels
[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
57 static const char *ldb_di1_div_sels
[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
58 static const char *qspi1_sels
[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
59 static const char *enfc_sels
[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
60 static const char *can_sels
[] = { "pll3_60m", "osc", "pll3_80m", "dummy", };
61 static const char *ecspi_sels
[] = { "pll3_60m", "osc", };
62 static const char *uart_sels
[] = { "pll3_80m", "osc", };
63 static const char *perclk_sels
[] = { "ipg", "osc", };
64 static const char *lcdif_sels
[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
65 static const char *csi_sels
[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
66 static const char *sim_sels
[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
67 /* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */
68 static const char *epdc_pre_sels
[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
69 static const char *esai_sels
[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
70 static const char *epdc_sels
[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
71 static const char *cko1_sels
[] = { "dummy", "dummy", "dummy", "dummy", "dummy", "axi", "enfc", "dummy", "dummy",
72 "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
73 static const char *cko2_sels
[] = { "dummy", "dummy", "dummy", "usdhc1", "dummy", "dummy", "ecspi_root", "dummy",
74 "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "osc", "dummy",
75 "dummy", "usdhc2", "sai1", "sai2", "sai3", "dummy", "dummy", "can_root",
76 "dummy", "dummy", "dummy", "dummy", "uart_serial", "spdif", "dummy", "dummy", };
77 static const char *cko_sels
[] = { "cko1", "cko2", };
79 static struct clk
*clks
[IMX6UL_CLK_END
];
80 static struct clk_onecell_data clk_data
;
82 static const struct clk_div_table clk_enet_ref_table
[] = {
83 { .val
= 0, .div
= 20, },
84 { .val
= 1, .div
= 10, },
85 { .val
= 2, .div
= 5, },
86 { .val
= 3, .div
= 4, },
90 static const struct clk_div_table post_div_table
[] = {
91 { .val
= 2, .div
= 1, },
92 { .val
= 1, .div
= 2, },
93 { .val
= 0, .div
= 4, },
97 static const struct clk_div_table video_div_table
[] = {
98 { .val
= 0, .div
= 1, },
99 { .val
= 1, .div
= 2, },
100 { .val
= 2, .div
= 1, },
101 { .val
= 3, .div
= 4, },
105 static u32 share_count_asrc
;
106 static u32 share_count_audio
;
107 static u32 share_count_sai1
;
108 static u32 share_count_sai2
;
109 static u32 share_count_sai3
;
110 static u32 share_count_esai
;
112 static inline int clk_on_imx6ul(void)
114 return of_machine_is_compatible("fsl,imx6ul");
117 static inline int clk_on_imx6ull(void)
119 return of_machine_is_compatible("fsl,imx6ull");
122 static void __init
imx6ul_clocks_init(struct device_node
*ccm_node
)
124 struct device_node
*np
;
127 clks
[IMX6UL_CLK_DUMMY
] = imx_clk_fixed("dummy", 0);
129 clks
[IMX6UL_CLK_CKIL
] = of_clk_get_by_name(ccm_node
, "ckil");
130 clks
[IMX6UL_CLK_OSC
] = of_clk_get_by_name(ccm_node
, "osc");
132 /* ipp_di clock is external input */
133 clks
[IMX6UL_CLK_IPP_DI0
] = of_clk_get_by_name(ccm_node
, "ipp_di0");
134 clks
[IMX6UL_CLK_IPP_DI1
] = of_clk_get_by_name(ccm_node
, "ipp_di1");
136 np
= of_find_compatible_node(NULL
, NULL
, "fsl,imx6ul-anatop");
137 base
= of_iomap(np
, 0);
141 clks
[IMX6UL_PLL1_BYPASS_SRC
] = imx_clk_mux("pll1_bypass_src", base
+ 0x00, 14, 1, pll_bypass_src_sels
, ARRAY_SIZE(pll_bypass_src_sels
));
142 clks
[IMX6UL_PLL2_BYPASS_SRC
] = imx_clk_mux("pll2_bypass_src", base
+ 0x30, 14, 1, pll_bypass_src_sels
, ARRAY_SIZE(pll_bypass_src_sels
));
143 clks
[IMX6UL_PLL3_BYPASS_SRC
] = imx_clk_mux("pll3_bypass_src", base
+ 0x10, 14, 1, pll_bypass_src_sels
, ARRAY_SIZE(pll_bypass_src_sels
));
144 clks
[IMX6UL_PLL4_BYPASS_SRC
] = imx_clk_mux("pll4_bypass_src", base
+ 0x70, 14, 1, pll_bypass_src_sels
, ARRAY_SIZE(pll_bypass_src_sels
));
145 clks
[IMX6UL_PLL5_BYPASS_SRC
] = imx_clk_mux("pll5_bypass_src", base
+ 0xa0, 14, 1, pll_bypass_src_sels
, ARRAY_SIZE(pll_bypass_src_sels
));
146 clks
[IMX6UL_PLL6_BYPASS_SRC
] = imx_clk_mux("pll6_bypass_src", base
+ 0xe0, 14, 1, pll_bypass_src_sels
, ARRAY_SIZE(pll_bypass_src_sels
));
147 clks
[IMX6UL_PLL7_BYPASS_SRC
] = imx_clk_mux("pll7_bypass_src", base
+ 0x20, 14, 1, pll_bypass_src_sels
, ARRAY_SIZE(pll_bypass_src_sels
));
149 clks
[IMX6UL_CLK_PLL1
] = imx_clk_pllv3(IMX_PLLV3_SYS
, "pll1", "osc", base
+ 0x00, 0x7f);
150 clks
[IMX6UL_CLK_PLL2
] = imx_clk_pllv3(IMX_PLLV3_GENERIC
, "pll2", "osc", base
+ 0x30, 0x1);
151 clks
[IMX6UL_CLK_PLL3
] = imx_clk_pllv3(IMX_PLLV3_USB
, "pll3", "osc", base
+ 0x10, 0x3);
152 clks
[IMX6UL_CLK_PLL4
] = imx_clk_pllv3(IMX_PLLV3_AV
, "pll4", "osc", base
+ 0x70, 0x7f);
153 clks
[IMX6UL_CLK_PLL5
] = imx_clk_pllv3(IMX_PLLV3_AV
, "pll5", "osc", base
+ 0xa0, 0x7f);
154 clks
[IMX6UL_CLK_PLL6
] = imx_clk_pllv3(IMX_PLLV3_ENET
, "pll6", "osc", base
+ 0xe0, 0x3);
155 clks
[IMX6UL_CLK_PLL7
] = imx_clk_pllv3(IMX_PLLV3_USB
, "pll7", "osc", base
+ 0x20, 0x3);
157 clks
[IMX6UL_PLL1_BYPASS
] = imx_clk_mux_flags("pll1_bypass", base
+ 0x00, 16, 1, pll1_bypass_sels
, ARRAY_SIZE(pll1_bypass_sels
), CLK_SET_RATE_PARENT
);
158 clks
[IMX6UL_PLL2_BYPASS
] = imx_clk_mux_flags("pll2_bypass", base
+ 0x30, 16, 1, pll2_bypass_sels
, ARRAY_SIZE(pll2_bypass_sels
), CLK_SET_RATE_PARENT
);
159 clks
[IMX6UL_PLL3_BYPASS
] = imx_clk_mux_flags("pll3_bypass", base
+ 0x10, 16, 1, pll3_bypass_sels
, ARRAY_SIZE(pll3_bypass_sels
), CLK_SET_RATE_PARENT
);
160 clks
[IMX6UL_PLL4_BYPASS
] = imx_clk_mux_flags("pll4_bypass", base
+ 0x70, 16, 1, pll4_bypass_sels
, ARRAY_SIZE(pll4_bypass_sels
), CLK_SET_RATE_PARENT
);
161 clks
[IMX6UL_PLL5_BYPASS
] = imx_clk_mux_flags("pll5_bypass", base
+ 0xa0, 16, 1, pll5_bypass_sels
, ARRAY_SIZE(pll5_bypass_sels
), CLK_SET_RATE_PARENT
);
162 clks
[IMX6UL_PLL6_BYPASS
] = imx_clk_mux_flags("pll6_bypass", base
+ 0xe0, 16, 1, pll6_bypass_sels
, ARRAY_SIZE(pll6_bypass_sels
), CLK_SET_RATE_PARENT
);
163 clks
[IMX6UL_PLL7_BYPASS
] = imx_clk_mux_flags("pll7_bypass", base
+ 0x20, 16, 1, pll7_bypass_sels
, ARRAY_SIZE(pll7_bypass_sels
), CLK_SET_RATE_PARENT
);
164 clks
[IMX6UL_CLK_CSI_SEL
] = imx_clk_mux_flags("csi_sel", base
+ 0x3c, 9, 2, csi_sels
, ARRAY_SIZE(csi_sels
), CLK_SET_RATE_PARENT
);
166 /* Do not bypass PLLs initially */
167 clk_set_parent(clks
[IMX6UL_PLL1_BYPASS
], clks
[IMX6UL_CLK_PLL1
]);
168 clk_set_parent(clks
[IMX6UL_PLL2_BYPASS
], clks
[IMX6UL_CLK_PLL2
]);
169 clk_set_parent(clks
[IMX6UL_PLL3_BYPASS
], clks
[IMX6UL_CLK_PLL3
]);
170 clk_set_parent(clks
[IMX6UL_PLL4_BYPASS
], clks
[IMX6UL_CLK_PLL4
]);
171 clk_set_parent(clks
[IMX6UL_PLL5_BYPASS
], clks
[IMX6UL_CLK_PLL5
]);
172 clk_set_parent(clks
[IMX6UL_PLL6_BYPASS
], clks
[IMX6UL_CLK_PLL6
]);
173 clk_set_parent(clks
[IMX6UL_PLL7_BYPASS
], clks
[IMX6UL_CLK_PLL7
]);
175 clks
[IMX6UL_CLK_PLL1_SYS
] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
176 clks
[IMX6UL_CLK_PLL2_BUS
] = imx_clk_gate("pll2_bus", "pll2_bypass", base
+ 0x30, 13);
177 clks
[IMX6UL_CLK_PLL3_USB_OTG
] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base
+ 0x10, 13);
178 clks
[IMX6UL_CLK_PLL4_AUDIO
] = imx_clk_gate("pll4_audio", "pll4_bypass", base
+ 0x70, 13);
179 clks
[IMX6UL_CLK_PLL5_VIDEO
] = imx_clk_gate("pll5_video", "pll5_bypass", base
+ 0xa0, 13);
180 clks
[IMX6UL_CLK_PLL6_ENET
] = imx_clk_gate("pll6_enet", "pll6_bypass", base
+ 0xe0, 13);
181 clks
[IMX6UL_CLK_PLL7_USB_HOST
] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base
+ 0x20, 13);
184 * Bit 20 is the reserved and read-only bit, we do this only for:
185 * - Do nothing for usbphy clk_enable/disable
186 * - Keep refcount when do usbphy clk_enable/disable, in that case,
187 * the clk framework many need to enable/disable usbphy's parent
189 clks
[IMX6UL_CLK_USBPHY1
] = imx_clk_gate("usbphy1", "pll3_usb_otg", base
+ 0x10, 20);
190 clks
[IMX6UL_CLK_USBPHY2
] = imx_clk_gate("usbphy2", "pll7_usb_host", base
+ 0x20, 20);
193 * usbphy*_gate needs to be on after system boots up, and software
194 * never needs to control it anymore.
196 clks
[IMX6UL_CLK_USBPHY1_GATE
] = imx_clk_gate("usbphy1_gate", "dummy", base
+ 0x10, 6);
197 clks
[IMX6UL_CLK_USBPHY2_GATE
] = imx_clk_gate("usbphy2_gate", "dummy", base
+ 0x20, 6);
199 /* name parent_name reg idx */
200 clks
[IMX6UL_CLK_PLL2_PFD0
] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base
+ 0x100, 0);
201 clks
[IMX6UL_CLK_PLL2_PFD1
] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base
+ 0x100, 1);
202 clks
[IMX6UL_CLK_PLL2_PFD2
] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base
+ 0x100, 2);
203 clks
[IMX6UL_CLK_PLL2_PFD3
] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base
+ 0x100, 3);
204 clks
[IMX6UL_CLK_PLL3_PFD0
] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base
+ 0xf0, 0);
205 clks
[IMX6UL_CLK_PLL3_PFD1
] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base
+ 0xf0, 1);
206 clks
[IMX6UL_CLK_PLL3_PFD2
] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base
+ 0xf0, 2);
207 clks
[IMX6UL_CLK_PLL3_PFD3
] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base
+ 0xf0, 3);
209 clks
[IMX6UL_CLK_ENET_REF
] = clk_register_divider_table(NULL
, "enet_ref", "pll6_enet", 0,
210 base
+ 0xe0, 0, 2, 0, clk_enet_ref_table
, &imx_ccm_lock
);
211 clks
[IMX6UL_CLK_ENET2_REF
] = clk_register_divider_table(NULL
, "enet2_ref", "pll6_enet", 0,
212 base
+ 0xe0, 2, 2, 0, clk_enet_ref_table
, &imx_ccm_lock
);
214 clks
[IMX6UL_CLK_ENET2_REF_125M
] = imx_clk_gate("enet_ref_125m", "enet2_ref", base
+ 0xe0, 20);
215 clks
[IMX6UL_CLK_ENET_PTP_REF
] = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
216 clks
[IMX6UL_CLK_ENET_PTP
] = imx_clk_gate("enet_ptp", "enet_ptp_ref", base
+ 0xe0, 21);
218 clks
[IMX6UL_CLK_PLL4_POST_DIV
] = clk_register_divider_table(NULL
, "pll4_post_div", "pll4_audio",
219 CLK_SET_RATE_PARENT
| CLK_SET_RATE_GATE
, base
+ 0x70, 19, 2, 0, post_div_table
, &imx_ccm_lock
);
220 clks
[IMX6UL_CLK_PLL4_AUDIO_DIV
] = clk_register_divider(NULL
, "pll4_audio_div", "pll4_post_div",
221 CLK_SET_RATE_PARENT
| CLK_SET_RATE_GATE
, base
+ 0x170, 15, 1, 0, &imx_ccm_lock
);
222 clks
[IMX6UL_CLK_PLL5_POST_DIV
] = clk_register_divider_table(NULL
, "pll5_post_div", "pll5_video",
223 CLK_SET_RATE_PARENT
| CLK_SET_RATE_GATE
, base
+ 0xa0, 19, 2, 0, post_div_table
, &imx_ccm_lock
);
224 clks
[IMX6UL_CLK_PLL5_VIDEO_DIV
] = clk_register_divider_table(NULL
, "pll5_video_div", "pll5_post_div",
225 CLK_SET_RATE_PARENT
| CLK_SET_RATE_GATE
, base
+ 0x170, 30, 2, 0, video_div_table
, &imx_ccm_lock
);
227 /* name parent_name mult div */
228 clks
[IMX6UL_CLK_PLL2_198M
] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
229 clks
[IMX6UL_CLK_PLL3_80M
] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
230 clks
[IMX6UL_CLK_PLL3_60M
] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
231 clks
[IMX6UL_CLK_GPT_3M
] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
234 base
= of_iomap(np
, 0);
237 clks
[IMX6UL_CA7_SECONDARY_SEL
] = imx_clk_mux("ca7_secondary_sel", base
+ 0xc, 3, 1, ca7_secondary_sels
, ARRAY_SIZE(ca7_secondary_sels
));
238 clks
[IMX6UL_CLK_STEP
] = imx_clk_mux("step", base
+ 0x0c, 8, 1, step_sels
, ARRAY_SIZE(step_sels
));
239 clks
[IMX6UL_CLK_PLL1_SW
] = imx_clk_mux_flags("pll1_sw", base
+ 0x0c, 2, 1, pll1_sw_sels
, ARRAY_SIZE(pll1_sw_sels
), 0);
240 clks
[IMX6UL_CLK_AXI_ALT_SEL
] = imx_clk_mux("axi_alt_sel", base
+ 0x14, 7, 1, axi_alt_sels
, ARRAY_SIZE(axi_alt_sels
));
241 clks
[IMX6UL_CLK_AXI_SEL
] = imx_clk_mux_flags("axi_sel", base
+ 0x14, 6, 1, axi_sels
, ARRAY_SIZE(axi_sels
), 0);
242 clks
[IMX6UL_CLK_PERIPH_PRE
] = imx_clk_mux("periph_pre", base
+ 0x18, 18, 2, periph_pre_sels
, ARRAY_SIZE(periph_pre_sels
));
243 clks
[IMX6UL_CLK_PERIPH2_PRE
] = imx_clk_mux("periph2_pre", base
+ 0x18, 21, 2, periph2_pre_sels
, ARRAY_SIZE(periph2_pre_sels
));
244 clks
[IMX6UL_CLK_PERIPH_CLK2_SEL
] = imx_clk_mux("periph_clk2_sel", base
+ 0x18, 12, 2, periph_clk2_sels
, ARRAY_SIZE(periph_clk2_sels
));
245 clks
[IMX6UL_CLK_PERIPH2_CLK2_SEL
] = imx_clk_mux("periph2_clk2_sel", base
+ 0x18, 20, 1, periph2_clk2_sels
, ARRAY_SIZE(periph2_clk2_sels
));
246 clks
[IMX6UL_CLK_EIM_SLOW_SEL
] = imx_clk_mux("eim_slow_sel", base
+ 0x1c, 29, 2, eim_slow_sels
, ARRAY_SIZE(eim_slow_sels
));
247 clks
[IMX6UL_CLK_GPMI_SEL
] = imx_clk_mux("gpmi_sel", base
+ 0x1c, 19, 1, gpmi_sels
, ARRAY_SIZE(gpmi_sels
));
248 clks
[IMX6UL_CLK_BCH_SEL
] = imx_clk_mux("bch_sel", base
+ 0x1c, 18, 1, bch_sels
, ARRAY_SIZE(bch_sels
));
249 clks
[IMX6UL_CLK_USDHC2_SEL
] = imx_clk_mux("usdhc2_sel", base
+ 0x1c, 17, 1, usdhc_sels
, ARRAY_SIZE(usdhc_sels
));
250 clks
[IMX6UL_CLK_USDHC1_SEL
] = imx_clk_mux("usdhc1_sel", base
+ 0x1c, 16, 1, usdhc_sels
, ARRAY_SIZE(usdhc_sels
));
251 clks
[IMX6UL_CLK_SAI3_SEL
] = imx_clk_mux("sai3_sel", base
+ 0x1c, 14, 2, sai_sels
, ARRAY_SIZE(sai_sels
));
252 clks
[IMX6UL_CLK_SAI2_SEL
] = imx_clk_mux("sai2_sel", base
+ 0x1c, 12, 2, sai_sels
, ARRAY_SIZE(sai_sels
));
253 clks
[IMX6UL_CLK_SAI1_SEL
] = imx_clk_mux("sai1_sel", base
+ 0x1c, 10, 2, sai_sels
, ARRAY_SIZE(sai_sels
));
254 clks
[IMX6UL_CLK_QSPI1_SEL
] = imx_clk_mux("qspi1_sel", base
+ 0x1c, 7, 3, qspi1_sels
, ARRAY_SIZE(qspi1_sels
));
255 clks
[IMX6UL_CLK_PERCLK_SEL
] = imx_clk_mux("perclk_sel", base
+ 0x1c, 6, 1, perclk_sels
, ARRAY_SIZE(perclk_sels
));
256 clks
[IMX6UL_CLK_CAN_SEL
] = imx_clk_mux("can_sel", base
+ 0x20, 8, 2, can_sels
, ARRAY_SIZE(can_sels
));
257 if (clk_on_imx6ull())
258 clks
[IMX6ULL_CLK_ESAI_SEL
] = imx_clk_mux("esai_sel", base
+ 0x20, 19, 2, esai_sels
, ARRAY_SIZE(esai_sels
));
259 clks
[IMX6UL_CLK_UART_SEL
] = imx_clk_mux("uart_sel", base
+ 0x24, 6, 1, uart_sels
, ARRAY_SIZE(uart_sels
));
260 clks
[IMX6UL_CLK_ENFC_SEL
] = imx_clk_mux("enfc_sel", base
+ 0x2c, 15, 3, enfc_sels
, ARRAY_SIZE(enfc_sels
));
261 clks
[IMX6UL_CLK_LDB_DI0_SEL
] = imx_clk_mux("ldb_di0_sel", base
+ 0x2c, 9, 3, ldb_di0_sels
, ARRAY_SIZE(ldb_di0_sels
));
262 clks
[IMX6UL_CLK_SPDIF_SEL
] = imx_clk_mux("spdif_sel", base
+ 0x30, 20, 2, spdif_sels
, ARRAY_SIZE(spdif_sels
));
263 if (clk_on_imx6ul()) {
264 clks
[IMX6UL_CLK_SIM_PRE_SEL
] = imx_clk_mux("sim_pre_sel", base
+ 0x34, 15, 3, sim_pre_sels
, ARRAY_SIZE(sim_pre_sels
));
265 clks
[IMX6UL_CLK_SIM_SEL
] = imx_clk_mux("sim_sel", base
+ 0x34, 9, 3, sim_sels
, ARRAY_SIZE(sim_sels
));
266 } else if (clk_on_imx6ull()) {
267 clks
[IMX6ULL_CLK_EPDC_PRE_SEL
] = imx_clk_mux("epdc_pre_sel", base
+ 0x34, 15, 3, epdc_pre_sels
, ARRAY_SIZE(epdc_pre_sels
));
268 clks
[IMX6ULL_CLK_EPDC_SEL
] = imx_clk_mux("epdc_sel", base
+ 0x34, 9, 3, epdc_sels
, ARRAY_SIZE(epdc_sels
));
270 clks
[IMX6UL_CLK_ECSPI_SEL
] = imx_clk_mux("ecspi_sel", base
+ 0x38, 18, 1, ecspi_sels
, ARRAY_SIZE(ecspi_sels
));
271 clks
[IMX6UL_CLK_LCDIF_PRE_SEL
] = imx_clk_mux_flags("lcdif_pre_sel", base
+ 0x38, 15, 3, lcdif_pre_sels
, ARRAY_SIZE(lcdif_pre_sels
), CLK_SET_RATE_PARENT
);
272 clks
[IMX6UL_CLK_LCDIF_SEL
] = imx_clk_mux("lcdif_sel", base
+ 0x38, 9, 3, lcdif_sels
, ARRAY_SIZE(lcdif_sels
));
274 clks
[IMX6UL_CLK_LDB_DI0_DIV_SEL
] = imx_clk_mux("ldb_di0", base
+ 0x20, 10, 1, ldb_di0_div_sels
, ARRAY_SIZE(ldb_di0_div_sels
));
275 clks
[IMX6UL_CLK_LDB_DI1_DIV_SEL
] = imx_clk_mux("ldb_di1", base
+ 0x20, 11, 1, ldb_di1_div_sels
, ARRAY_SIZE(ldb_di1_div_sels
));
277 clks
[IMX6UL_CLK_CKO1_SEL
] = imx_clk_mux("cko1_sel", base
+ 0x60, 0, 4, cko1_sels
, ARRAY_SIZE(cko1_sels
));
278 clks
[IMX6UL_CLK_CKO2_SEL
] = imx_clk_mux("cko2_sel", base
+ 0x60, 16, 5, cko2_sels
, ARRAY_SIZE(cko2_sels
));
279 clks
[IMX6UL_CLK_CKO
] = imx_clk_mux("cko", base
+ 0x60, 8, 1, cko_sels
, ARRAY_SIZE(cko_sels
));
281 clks
[IMX6UL_CLK_LDB_DI0_DIV_3_5
] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
282 clks
[IMX6UL_CLK_LDB_DI0_DIV_7
] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
283 clks
[IMX6UL_CLK_LDB_DI1_DIV_3_5
] = imx_clk_fixed_factor("ldb_di1_div_3_5", "qspi1_sel", 2, 7);
284 clks
[IMX6UL_CLK_LDB_DI1_DIV_7
] = imx_clk_fixed_factor("ldb_di1_div_7", "qspi1_sel", 1, 7);
286 clks
[IMX6UL_CLK_PERIPH
] = imx_clk_busy_mux("periph", base
+ 0x14, 25, 1, base
+ 0x48, 5, periph_sels
, ARRAY_SIZE(periph_sels
));
287 clks
[IMX6UL_CLK_PERIPH2
] = imx_clk_busy_mux("periph2", base
+ 0x14, 26, 1, base
+ 0x48, 3, periph2_sels
, ARRAY_SIZE(periph2_sels
));
289 clks
[IMX6UL_CLK_PERIPH_CLK2
] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base
+ 0x14, 27, 3);
290 clks
[IMX6UL_CLK_PERIPH2_CLK2
] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base
+ 0x14, 0, 3);
291 clks
[IMX6UL_CLK_IPG
] = imx_clk_divider("ipg", "ahb", base
+ 0x14, 8, 2);
292 clks
[IMX6UL_CLK_LCDIF_PODF
] = imx_clk_divider("lcdif_podf", "lcdif_pred", base
+ 0x18, 23, 3);
293 clks
[IMX6UL_CLK_QSPI1_PDOF
] = imx_clk_divider("qspi1_podf", "qspi1_sel", base
+ 0x1c, 26, 3);
294 clks
[IMX6UL_CLK_EIM_SLOW_PODF
] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base
+ 0x1c, 23, 3);
295 clks
[IMX6UL_CLK_PERCLK
] = imx_clk_divider("perclk", "perclk_sel", base
+ 0x1c, 0, 6);
296 clks
[IMX6UL_CLK_CAN_PODF
] = imx_clk_divider("can_podf", "can_sel", base
+ 0x20, 2, 6);
297 clks
[IMX6UL_CLK_GPMI_PODF
] = imx_clk_divider("gpmi_podf", "gpmi_sel", base
+ 0x24, 22, 3);
298 clks
[IMX6UL_CLK_BCH_PODF
] = imx_clk_divider("bch_podf", "bch_sel", base
+ 0x24, 19, 3);
299 clks
[IMX6UL_CLK_USDHC2_PODF
] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base
+ 0x24, 16, 3);
300 clks
[IMX6UL_CLK_USDHC1_PODF
] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base
+ 0x24, 11, 3);
301 clks
[IMX6UL_CLK_UART_PODF
] = imx_clk_divider("uart_podf", "uart_sel", base
+ 0x24, 0, 6);
302 clks
[IMX6UL_CLK_SAI3_PRED
] = imx_clk_divider("sai3_pred", "sai3_sel", base
+ 0x28, 22, 3);
303 clks
[IMX6UL_CLK_SAI3_PODF
] = imx_clk_divider("sai3_podf", "sai3_pred", base
+ 0x28, 16, 6);
304 clks
[IMX6UL_CLK_SAI1_PRED
] = imx_clk_divider("sai1_pred", "sai1_sel", base
+ 0x28, 6, 3);
305 clks
[IMX6UL_CLK_SAI1_PODF
] = imx_clk_divider("sai1_podf", "sai1_pred", base
+ 0x28, 0, 6);
306 if (clk_on_imx6ull()) {
307 clks
[IMX6ULL_CLK_ESAI_PRED
] = imx_clk_divider("esai_pred", "esai_sel", base
+ 0x28, 9, 3);
308 clks
[IMX6ULL_CLK_ESAI_PODF
] = imx_clk_divider("esai_podf", "esai_pred", base
+ 0x28, 25, 3);
310 clks
[IMX6UL_CLK_ENFC_PRED
] = imx_clk_divider("enfc_pred", "enfc_sel", base
+ 0x2c, 18, 3);
311 clks
[IMX6UL_CLK_ENFC_PODF
] = imx_clk_divider("enfc_podf", "enfc_pred", base
+ 0x2c, 21, 6);
312 clks
[IMX6UL_CLK_SAI2_PRED
] = imx_clk_divider("sai2_pred", "sai2_sel", base
+ 0x2c, 6, 3);
313 clks
[IMX6UL_CLK_SAI2_PODF
] = imx_clk_divider("sai2_podf", "sai2_pred", base
+ 0x2c, 0, 6);
314 clks
[IMX6UL_CLK_SPDIF_PRED
] = imx_clk_divider("spdif_pred", "spdif_sel", base
+ 0x30, 25, 3);
315 clks
[IMX6UL_CLK_SPDIF_PODF
] = imx_clk_divider("spdif_podf", "spdif_pred", base
+ 0x30, 22, 3);
317 clks
[IMX6UL_CLK_SIM_PODF
] = imx_clk_divider("sim_podf", "sim_pre_sel", base
+ 0x34, 12, 3);
318 else if (clk_on_imx6ull())
319 clks
[IMX6ULL_CLK_EPDC_PODF
] = imx_clk_divider("epdc_podf", "epdc_pre_sel", base
+ 0x34, 12, 3);
320 clks
[IMX6UL_CLK_ECSPI_PODF
] = imx_clk_divider("ecspi_podf", "ecspi_sel", base
+ 0x38, 19, 6);
321 clks
[IMX6UL_CLK_LCDIF_PRED
] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base
+ 0x38, 12, 3);
322 clks
[IMX6UL_CLK_CSI_PODF
] = imx_clk_divider("csi_podf", "csi_sel", base
+ 0x3c, 11, 3);
324 clks
[IMX6UL_CLK_CKO1_PODF
] = imx_clk_divider("cko1_podf", "cko1_sel", base
+ 0x60, 4, 3);
325 clks
[IMX6UL_CLK_CKO2_PODF
] = imx_clk_divider("cko2_podf", "cko2_sel", base
+ 0x60, 21, 3);
327 clks
[IMX6UL_CLK_ARM
] = imx_clk_busy_divider("arm", "pll1_sw", base
+ 0x10, 0, 3, base
+ 0x48, 16);
328 clks
[IMX6UL_CLK_MMDC_PODF
] = imx_clk_busy_divider("mmdc_podf", "periph2", base
+ 0x14, 3, 3, base
+ 0x48, 2);
329 clks
[IMX6UL_CLK_AXI_PODF
] = imx_clk_busy_divider("axi_podf", "axi_sel", base
+ 0x14, 16, 3, base
+ 0x48, 0);
330 clks
[IMX6UL_CLK_AHB
] = imx_clk_busy_divider("ahb", "periph", base
+ 0x14, 10, 3, base
+ 0x48, 1);
333 clks
[IMX6UL_CLK_AIPSTZ1
] = imx_clk_gate2_flags("aips_tz1", "ahb", base
+ 0x68, 0, CLK_IS_CRITICAL
);
334 clks
[IMX6UL_CLK_AIPSTZ2
] = imx_clk_gate2_flags("aips_tz2", "ahb", base
+ 0x68, 2, CLK_IS_CRITICAL
);
335 clks
[IMX6UL_CLK_APBHDMA
] = imx_clk_gate2("apbh_dma", "bch_podf", base
+ 0x68, 4);
336 clks
[IMX6UL_CLK_ASRC_IPG
] = imx_clk_gate2_shared("asrc_ipg", "ahb", base
+ 0x68, 6, &share_count_asrc
);
337 clks
[IMX6UL_CLK_ASRC_MEM
] = imx_clk_gate2_shared("asrc_mem", "ahb", base
+ 0x68, 6, &share_count_asrc
);
338 if (clk_on_imx6ul()) {
339 clks
[IMX6UL_CLK_CAAM_MEM
] = imx_clk_gate2("caam_mem", "ahb", base
+ 0x68, 8);
340 clks
[IMX6UL_CLK_CAAM_ACLK
] = imx_clk_gate2("caam_aclk", "ahb", base
+ 0x68, 10);
341 clks
[IMX6UL_CLK_CAAM_IPG
] = imx_clk_gate2("caam_ipg", "ipg", base
+ 0x68, 12);
342 } else if (clk_on_imx6ull()) {
343 clks
[IMX6ULL_CLK_DCP_CLK
] = imx_clk_gate2("dcp", "ahb", base
+ 0x68, 10);
344 clks
[IMX6UL_CLK_ENET
] = imx_clk_gate2("enet", "ipg", base
+ 0x68, 12);
345 clks
[IMX6UL_CLK_ENET_AHB
] = imx_clk_gate2("enet_ahb", "ahb", base
+ 0x68, 12);
347 clks
[IMX6UL_CLK_CAN1_IPG
] = imx_clk_gate2("can1_ipg", "ipg", base
+ 0x68, 14);
348 clks
[IMX6UL_CLK_CAN1_SERIAL
] = imx_clk_gate2("can1_serial", "can_podf", base
+ 0x68, 16);
349 clks
[IMX6UL_CLK_CAN2_IPG
] = imx_clk_gate2("can2_ipg", "ipg", base
+ 0x68, 18);
350 clks
[IMX6UL_CLK_CAN2_SERIAL
] = imx_clk_gate2("can2_serial", "can_podf", base
+ 0x68, 20);
351 clks
[IMX6UL_CLK_GPT2_BUS
] = imx_clk_gate2("gpt2_bus", "perclk", base
+ 0x68, 24);
352 clks
[IMX6UL_CLK_GPT2_SERIAL
] = imx_clk_gate2("gpt2_serial", "perclk", base
+ 0x68, 26);
353 clks
[IMX6UL_CLK_UART2_IPG
] = imx_clk_gate2("uart2_ipg", "ipg", base
+ 0x68, 28);
354 clks
[IMX6UL_CLK_UART2_SERIAL
] = imx_clk_gate2("uart2_serial", "uart_podf", base
+ 0x68, 28);
355 if (clk_on_imx6ull())
356 clks
[IMX6UL_CLK_AIPSTZ3
] = imx_clk_gate2("aips_tz3", "ahb", base
+ 0x80, 18);
357 clks
[IMX6UL_CLK_GPIO2
] = imx_clk_gate2("gpio2", "ipg", base
+ 0x68, 30);
360 clks
[IMX6UL_CLK_ECSPI1
] = imx_clk_gate2("ecspi1", "ecspi_podf", base
+ 0x6c, 0);
361 clks
[IMX6UL_CLK_ECSPI2
] = imx_clk_gate2("ecspi2", "ecspi_podf", base
+ 0x6c, 2);
362 clks
[IMX6UL_CLK_ECSPI3
] = imx_clk_gate2("ecspi3", "ecspi_podf", base
+ 0x6c, 4);
363 clks
[IMX6UL_CLK_ECSPI4
] = imx_clk_gate2("ecspi4", "ecspi_podf", base
+ 0x6c, 6);
364 clks
[IMX6UL_CLK_ADC2
] = imx_clk_gate2("adc2", "ipg", base
+ 0x6c, 8);
365 clks
[IMX6UL_CLK_UART3_IPG
] = imx_clk_gate2("uart3_ipg", "ipg", base
+ 0x6c, 10);
366 clks
[IMX6UL_CLK_UART3_SERIAL
] = imx_clk_gate2("uart3_serial", "uart_podf", base
+ 0x6c, 10);
367 clks
[IMX6UL_CLK_EPIT1
] = imx_clk_gate2("epit1", "perclk", base
+ 0x6c, 12);
368 clks
[IMX6UL_CLK_EPIT2
] = imx_clk_gate2("epit2", "perclk", base
+ 0x6c, 14);
369 clks
[IMX6UL_CLK_ADC1
] = imx_clk_gate2("adc1", "ipg", base
+ 0x6c, 16);
370 clks
[IMX6UL_CLK_GPT1_BUS
] = imx_clk_gate2("gpt1_bus", "perclk", base
+ 0x6c, 20);
371 clks
[IMX6UL_CLK_GPT1_SERIAL
] = imx_clk_gate2("gpt1_serial", "perclk", base
+ 0x6c, 22);
372 clks
[IMX6UL_CLK_UART4_IPG
] = imx_clk_gate2("uart4_ipg", "ipg", base
+ 0x6c, 24);
373 clks
[IMX6UL_CLK_UART4_SERIAL
] = imx_clk_gate2("uart4_serial", "uart_podf", base
+ 0x6c, 24);
374 clks
[IMX6UL_CLK_GPIO1
] = imx_clk_gate2("gpio1", "ipg", base
+ 0x6c, 26);
375 clks
[IMX6UL_CLK_GPIO5
] = imx_clk_gate2("gpio5", "ipg", base
+ 0x6c, 30);
378 if (clk_on_imx6ull()) {
379 clks
[IMX6ULL_CLK_ESAI_EXTAL
] = imx_clk_gate2_shared("esai_extal", "esai_podf", base
+ 0x70, 0, &share_count_esai
);
380 clks
[IMX6ULL_CLK_ESAI_IPG
] = imx_clk_gate2_shared("esai_ipg", "ahb", base
+ 0x70, 0, &share_count_esai
);
381 clks
[IMX6ULL_CLK_ESAI_MEM
] = imx_clk_gate2_shared("esai_mem", "ahb", base
+ 0x70, 0, &share_count_esai
);
383 clks
[IMX6UL_CLK_CSI
] = imx_clk_gate2("csi", "csi_podf", base
+ 0x70, 2);
384 clks
[IMX6UL_CLK_I2C1
] = imx_clk_gate2("i2c1", "perclk", base
+ 0x70, 6);
385 clks
[IMX6UL_CLK_I2C2
] = imx_clk_gate2("i2c2", "perclk", base
+ 0x70, 8);
386 clks
[IMX6UL_CLK_I2C3
] = imx_clk_gate2("i2c3", "perclk", base
+ 0x70, 10);
387 clks
[IMX6UL_CLK_OCOTP
] = imx_clk_gate2("ocotp", "ipg", base
+ 0x70, 12);
388 clks
[IMX6UL_CLK_IOMUXC
] = imx_clk_gate2("iomuxc", "lcdif_podf", base
+ 0x70, 14);
389 clks
[IMX6UL_CLK_GPIO3
] = imx_clk_gate2("gpio3", "ipg", base
+ 0x70, 26);
390 clks
[IMX6UL_CLK_LCDIF_APB
] = imx_clk_gate2("lcdif_apb", "axi", base
+ 0x70, 28);
391 clks
[IMX6UL_CLK_PXP
] = imx_clk_gate2("pxp", "axi", base
+ 0x70, 30);
394 clks
[IMX6UL_CLK_UART5_IPG
] = imx_clk_gate2("uart5_ipg", "ipg", base
+ 0x74, 2);
395 clks
[IMX6UL_CLK_UART5_SERIAL
] = imx_clk_gate2("uart5_serial", "uart_podf", base
+ 0x74, 2);
396 if (clk_on_imx6ul()) {
397 clks
[IMX6UL_CLK_ENET
] = imx_clk_gate2("enet", "ipg", base
+ 0x74, 4);
398 clks
[IMX6UL_CLK_ENET_AHB
] = imx_clk_gate2("enet_ahb", "ahb", base
+ 0x74, 4);
399 } else if (clk_on_imx6ull()) {
400 clks
[IMX6ULL_CLK_EPDC_ACLK
] = imx_clk_gate2("epdc_aclk", "axi", base
+ 0x74, 4);
401 clks
[IMX6ULL_CLK_EPDC_PIX
] = imx_clk_gate2("epdc_pix", "epdc_podf", base
+ 0x74, 4);
403 clks
[IMX6UL_CLK_UART6_IPG
] = imx_clk_gate2("uart6_ipg", "ipg", base
+ 0x74, 6);
404 clks
[IMX6UL_CLK_UART6_SERIAL
] = imx_clk_gate2("uart6_serial", "uart_podf", base
+ 0x74, 6);
405 clks
[IMX6UL_CLK_LCDIF_PIX
] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base
+ 0x74, 10);
406 clks
[IMX6UL_CLK_GPIO4
] = imx_clk_gate2("gpio4", "ipg", base
+ 0x74, 12);
407 clks
[IMX6UL_CLK_QSPI
] = imx_clk_gate2("qspi1", "qspi1_podf", base
+ 0x74, 14);
408 clks
[IMX6UL_CLK_WDOG1
] = imx_clk_gate2("wdog1", "ipg", base
+ 0x74, 16);
409 clks
[IMX6UL_CLK_MMDC_P0_FAST
] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base
+ 0x74, 20, CLK_IS_CRITICAL
);
410 clks
[IMX6UL_CLK_MMDC_P0_IPG
] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base
+ 0x74, 24, CLK_IS_CRITICAL
);
411 clks
[IMX6UL_CLK_AXI
] = imx_clk_gate_flags("axi", "axi_podf", base
+ 0x74, 28, CLK_IS_CRITICAL
);
414 clks
[IMX6UL_CLK_PER_BCH
] = imx_clk_gate2("per_bch", "bch_podf", base
+ 0x78, 12);
415 clks
[IMX6UL_CLK_PWM1
] = imx_clk_gate2("pwm1", "perclk", base
+ 0x78, 16);
416 clks
[IMX6UL_CLK_PWM2
] = imx_clk_gate2("pwm2", "perclk", base
+ 0x78, 18);
417 clks
[IMX6UL_CLK_PWM3
] = imx_clk_gate2("pwm3", "perclk", base
+ 0x78, 20);
418 clks
[IMX6UL_CLK_PWM4
] = imx_clk_gate2("pwm4", "perclk", base
+ 0x78, 22);
419 clks
[IMX6UL_CLK_GPMI_BCH_APB
] = imx_clk_gate2("gpmi_bch_apb", "bch_podf", base
+ 0x78, 24);
420 clks
[IMX6UL_CLK_GPMI_BCH
] = imx_clk_gate2("gpmi_bch", "gpmi_podf", base
+ 0x78, 26);
421 clks
[IMX6UL_CLK_GPMI_IO
] = imx_clk_gate2("gpmi_io", "enfc_podf", base
+ 0x78, 28);
422 clks
[IMX6UL_CLK_GPMI_APB
] = imx_clk_gate2("gpmi_apb", "bch_podf", base
+ 0x78, 30);
425 clks
[IMX6UL_CLK_ROM
] = imx_clk_gate2_flags("rom", "ahb", base
+ 0x7c, 0, CLK_IS_CRITICAL
);
426 clks
[IMX6UL_CLK_SDMA
] = imx_clk_gate2("sdma", "ahb", base
+ 0x7c, 6);
427 clks
[IMX6UL_CLK_KPP
] = imx_clk_gate2("kpp", "ipg", base
+ 0x7c, 8);
428 clks
[IMX6UL_CLK_WDOG2
] = imx_clk_gate2("wdog2", "ipg", base
+ 0x7c, 10);
429 clks
[IMX6UL_CLK_SPBA
] = imx_clk_gate2("spba", "ipg", base
+ 0x7c, 12);
430 clks
[IMX6UL_CLK_SPDIF
] = imx_clk_gate2_shared("spdif", "spdif_podf", base
+ 0x7c, 14, &share_count_audio
);
431 clks
[IMX6UL_CLK_SPDIF_GCLK
] = imx_clk_gate2_shared("spdif_gclk", "ipg", base
+ 0x7c, 14, &share_count_audio
);
432 clks
[IMX6UL_CLK_SAI3
] = imx_clk_gate2_shared("sai3", "sai3_podf", base
+ 0x7c, 22, &share_count_sai3
);
433 clks
[IMX6UL_CLK_SAI3_IPG
] = imx_clk_gate2_shared("sai3_ipg", "ipg", base
+ 0x7c, 22, &share_count_sai3
);
434 clks
[IMX6UL_CLK_UART1_IPG
] = imx_clk_gate2("uart1_ipg", "ipg", base
+ 0x7c, 24);
435 clks
[IMX6UL_CLK_UART1_SERIAL
] = imx_clk_gate2("uart1_serial", "uart_podf", base
+ 0x7c, 24);
436 clks
[IMX6UL_CLK_UART7_IPG
] = imx_clk_gate2("uart7_ipg", "ipg", base
+ 0x7c, 26);
437 clks
[IMX6UL_CLK_UART7_SERIAL
] = imx_clk_gate2("uart7_serial", "uart_podf", base
+ 0x7c, 26);
438 clks
[IMX6UL_CLK_SAI1
] = imx_clk_gate2_shared("sai1", "sai1_podf", base
+ 0x7c, 28, &share_count_sai1
);
439 clks
[IMX6UL_CLK_SAI1_IPG
] = imx_clk_gate2_shared("sai1_ipg", "ipg", base
+ 0x7c, 28, &share_count_sai1
);
440 clks
[IMX6UL_CLK_SAI2
] = imx_clk_gate2_shared("sai2", "sai2_podf", base
+ 0x7c, 30, &share_count_sai2
);
441 clks
[IMX6UL_CLK_SAI2_IPG
] = imx_clk_gate2_shared("sai2_ipg", "ipg", base
+ 0x7c, 30, &share_count_sai2
);
444 clks
[IMX6UL_CLK_USBOH3
] = imx_clk_gate2("usboh3", "ipg", base
+ 0x80, 0);
445 clks
[IMX6UL_CLK_USDHC1
] = imx_clk_gate2("usdhc1", "usdhc1_podf", base
+ 0x80, 2);
446 clks
[IMX6UL_CLK_USDHC2
] = imx_clk_gate2("usdhc2", "usdhc2_podf", base
+ 0x80, 4);
447 if (clk_on_imx6ul()) {
448 clks
[IMX6UL_CLK_SIM1
] = imx_clk_gate2("sim1", "sim_sel", base
+ 0x80, 6);
449 clks
[IMX6UL_CLK_SIM2
] = imx_clk_gate2("sim2", "sim_sel", base
+ 0x80, 8);
451 clks
[IMX6UL_CLK_EIM
] = imx_clk_gate2("eim", "eim_slow_podf", base
+ 0x80, 10);
452 clks
[IMX6UL_CLK_PWM8
] = imx_clk_gate2("pwm8", "perclk", base
+ 0x80, 16);
453 clks
[IMX6UL_CLK_UART8_IPG
] = imx_clk_gate2("uart8_ipg", "ipg", base
+ 0x80, 14);
454 clks
[IMX6UL_CLK_UART8_SERIAL
] = imx_clk_gate2("uart8_serial", "uart_podf", base
+ 0x80, 14);
455 clks
[IMX6UL_CLK_WDOG3
] = imx_clk_gate2("wdog3", "ipg", base
+ 0x80, 20);
456 clks
[IMX6UL_CLK_I2C4
] = imx_clk_gate2("i2c4", "perclk", base
+ 0x80, 24);
457 clks
[IMX6UL_CLK_PWM5
] = imx_clk_gate2("pwm5", "perclk", base
+ 0x80, 26);
458 clks
[IMX6UL_CLK_PWM6
] = imx_clk_gate2("pwm6", "perclk", base
+ 0x80, 28);
459 clks
[IMX6UL_CLK_PWM7
] = imx_clk_gate2("pwm7", "perclk", base
+ 0x80, 30);
462 clks
[IMX6UL_CLK_CKO1
] = imx_clk_gate("cko1", "cko1_podf", base
+ 0x60, 7);
463 clks
[IMX6UL_CLK_CKO2
] = imx_clk_gate("cko2", "cko2_podf", base
+ 0x60, 24);
465 /* mask handshake of mmdc */
466 writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK
, base
+ CCDR
);
468 imx_check_clocks(clks
, ARRAY_SIZE(clks
));
470 clk_data
.clks
= clks
;
471 clk_data
.clk_num
= ARRAY_SIZE(clks
);
472 of_clk_add_provider(np
, of_clk_src_onecell_get
, &clk_data
);
475 * Lower the AHB clock rate before changing the parent clock source,
476 * as AHB clock rate can NOT be higher than 133MHz, but its parent
477 * will be switched from 396MHz PFD to 528MHz PLL in order to increase
478 * AXI clock rate, so we need to lower AHB rate first to make sure at
479 * any time, AHB rate is <= 133MHz.
481 clk_set_rate(clks
[IMX6UL_CLK_AHB
], 99000000);
483 /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
484 clk_set_parent(clks
[IMX6UL_CLK_PERIPH_CLK2_SEL
], clks
[IMX6UL_CLK_OSC
]);
485 clk_set_parent(clks
[IMX6UL_CLK_PERIPH
], clks
[IMX6UL_CLK_PERIPH_CLK2
]);
486 clk_set_parent(clks
[IMX6UL_CLK_PERIPH_PRE
], clks
[IMX6UL_CLK_PLL2_BUS
]);
487 clk_set_parent(clks
[IMX6UL_CLK_PERIPH
], clks
[IMX6UL_CLK_PERIPH_PRE
]);
489 /* Make sure AHB rate is 132MHz */
490 clk_set_rate(clks
[IMX6UL_CLK_AHB
], 132000000);
492 /* set perclk to from OSC */
493 clk_set_parent(clks
[IMX6UL_CLK_PERCLK_SEL
], clks
[IMX6UL_CLK_OSC
]);
495 clk_set_rate(clks
[IMX6UL_CLK_ENET_REF
], 50000000);
496 clk_set_rate(clks
[IMX6UL_CLK_ENET2_REF
], 50000000);
497 clk_set_rate(clks
[IMX6UL_CLK_CSI
], 24000000);
499 if (clk_on_imx6ull())
500 clk_prepare_enable(clks
[IMX6UL_CLK_AIPSTZ3
]);
502 if (IS_ENABLED(CONFIG_USB_MXS_PHY
)) {
503 clk_prepare_enable(clks
[IMX6UL_CLK_USBPHY1_GATE
]);
504 clk_prepare_enable(clks
[IMX6UL_CLK_USBPHY2_GATE
]);
507 clk_set_parent(clks
[IMX6UL_CLK_CAN_SEL
], clks
[IMX6UL_CLK_PLL3_60M
]);
509 clk_set_parent(clks
[IMX6UL_CLK_SIM_PRE_SEL
], clks
[IMX6UL_CLK_PLL3_USB_OTG
]);
510 else if (clk_on_imx6ull())
511 clk_set_parent(clks
[IMX6ULL_CLK_EPDC_PRE_SEL
], clks
[IMX6UL_CLK_PLL3_PFD2
]);
513 clk_set_parent(clks
[IMX6UL_CLK_ENFC_SEL
], clks
[IMX6UL_CLK_PLL2_PFD2
]);
516 CLK_OF_DECLARE(imx6ul
, "fsl,imx6ul-ccm", imx6ul_clocks_init
);
