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Linux 4.19.133
[linux/fpc-iii.git] / drivers / clk / mediatek / clk-mt2712.c
blob991d4093726e5c1a191af47895a2dd247a53f9dc
1 /*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23
24 #include "clk-mtk.h"
25 #include "clk-gate.h"
26
27 #include <dt-bindings/clock/mt2712-clk.h>
28
29 static DEFINE_SPINLOCK(mt2712_clk_lock);
30
31 static const struct mtk_fixed_clk top_fixed_clks[] = {
32 FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
33 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
34 FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
35 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
36 FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
37 FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
38 FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
39 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
40 FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
41 FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
42 FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
43 FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
44 };
45
46 static const struct mtk_fixed_factor top_early_divs[] = {
47 FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
48 1),
49 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
50 2),
51 };
52
53 static const struct mtk_fixed_factor top_divs[] = {
54 FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
55 1),
56 FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
57 2),
58 FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
59 3),
60 FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
61 1),
62 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
63 1),
64 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
65 2),
66 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
67 2),
68 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
69 4),
70 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
71 8),
72 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
73 16),
74 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
75 3),
76 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
77 2),
78 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
79 4),
80 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
81 5),
82 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
83 2),
84 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
85 4),
86 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
87 7),
88 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
89 2),
90 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
91 4),
92 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
93 1),
94 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
95 7),
96 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
97 26),
98 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
99 52),
100 FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
101 104),
102 FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
103 208),
104 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
105 2),
106 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
107 2),
108 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
109 4),
110 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
111 8),
112 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
113 3),
114 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
115 2),
116 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
117 4),
118 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
119 8),
120 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
121 5),
122 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
123 2),
124 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
125 4),
126 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
127 8),
128 FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
129 1),
130 FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
131 1),
132 FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
133 1),
134 FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
135 1),
136 FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
137 1),
138 FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
139 1),
140 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
141 1),
142 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
143 2),
144 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
145 4),
146 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
147 8),
148 FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
149 16),
150 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
151 1),
152 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
153 2),
154 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
155 4),
156 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
157 8),
158 FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
159 16),
160 FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
161 1),
162 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
163 2),
164 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
165 4),
166 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
167 8),
168 FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
169 1),
170 FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
171 2),
172 FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
173 4),
174 FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
175 8),
176 FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
177 1),
178 FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
179 1),
180 FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
181 1),
182 FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
183 2),
184 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
185 1),
186 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
187 2),
188 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
189 1),
190 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
191 2),
192 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
193 1),
194 FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
195 2),
196 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
197 1),
198 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
199 2),
200 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
201 4),
202 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
203 8),
204 FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
205 1),
206 FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
207 2),
208 FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
209 4),
210 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
211 1),
212 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
213 2),
214 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
215 4),
216 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
217 1),
218 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
219 2),
220 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
221 4),
222 FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
223 4),
224 FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
225 3),
226 };
227
228 static const char * const axi_parents[] = {
229 "clk26m",
230 "syspll1_d2",
231 "syspll_d5",
232 "syspll1_d4",
233 "univpll_d5",
234 "univpll2_d2",
235 "msdcpll2_ck"
236 };
237
238 static const char * const mem_parents[] = {
239 "clk26m",
240 "dmpll_ck"
241 };
242
243 static const char * const mm_parents[] = {
244 "clk26m",
245 "vencpll_ck",
246 "syspll_d3",
247 "syspll1_d2",
248 "syspll_d5",
249 "syspll1_d4",
250 "univpll1_d2",
251 "univpll2_d2"
252 };
253
254 static const char * const pwm_parents[] = {
255 "clk26m",
256 "univpll2_d4",
257 "univpll3_d2",
258 "univpll1_d4"
259 };
260
261 static const char * const vdec_parents[] = {
262 "clk26m",
263 "vcodecpll_ck",
264 "tvdpll_429m",
265 "univpll_d3",
266 "vencpll_ck",
267 "syspll_d3",
268 "univpll1_d2",
269 "mmpll_d2",
270 "syspll3_d2",
271 "tvdpll_ck"
272 };
273
274 static const char * const venc_parents[] = {
275 "clk26m",
276 "univpll1_d2",
277 "mmpll_d2",
278 "tvdpll_d2",
279 "syspll1_d2",
280 "univpll_d5",
281 "vcodecpll_d2",
282 "univpll2_d2",
283 "syspll3_d2"
284 };
285
286 static const char * const mfg_parents[] = {
287 "clk26m",
288 "mmpll_ck",
289 "univpll_d3",
290 "clk26m",
291 "clk26m",
292 "clk26m",
293 "clk26m",
294 "clk26m",
295 "clk26m",
296 "syspll_d3",
297 "syspll1_d2",
298 "syspll_d5",
299 "univpll_d3",
300 "univpll1_d2",
301 "univpll_d5",
302 "univpll2_d2"
303 };
304
305 static const char * const camtg_parents[] = {
306 "clk26m",
307 "univpll_d52",
308 "univpll_d208",
309 "univpll_d104",
310 "clk26m_d2",
311 "univpll_d26",
312 "univpll2_d8",
313 "syspll3_d4",
314 "syspll3_d2",
315 "univpll1_d4",
316 "univpll2_d2"
317 };
318
319 static const char * const uart_parents[] = {
320 "clk26m",
321 "univpll2_d8"
322 };
323
324 static const char * const spi_parents[] = {
325 "clk26m",
326 "univpll2_d4",
327 "univpll1_d4",
328 "univpll2_d2",
329 "univpll3_d2",
330 "univpll1_d8"
331 };
332
333 static const char * const usb20_parents[] = {
334 "clk26m",
335 "univpll1_d8",
336 "univpll3_d4"
337 };
338
339 static const char * const usb30_parents[] = {
340 "clk26m",
341 "univpll3_d2",
342 "univpll3_d4",
343 "univpll2_d4"
344 };
345
346 static const char * const msdc50_0_h_parents[] = {
347 "clk26m",
348 "syspll1_d2",
349 "syspll2_d2",
350 "syspll4_d2",
351 "univpll_d5",
352 "univpll1_d4"
353 };
354
355 static const char * const msdc50_0_parents[] = {
356 "clk26m",
357 "msdcpll_ck",
358 "msdcpll_d2",
359 "univpll1_d4",
360 "syspll2_d2",
361 "msdcpll_d4",
362 "vencpll_d2",
363 "univpll1_d2",
364 "msdcpll2_ck",
365 "msdcpll2_d2",
366 "msdcpll2_d4"
367 };
368
369 static const char * const msdc30_1_parents[] = {
370 "clk26m",
371 "univpll2_d2",
372 "msdcpll_d2",
373 "univpll1_d4",
374 "syspll2_d2",
375 "univpll_d7",
376 "vencpll_d2"
377 };
378
379 static const char * const msdc30_3_parents[] = {
380 "clk26m",
381 "msdcpll2_ck",
382 "msdcpll2_d2",
383 "univpll2_d2",
384 "msdcpll2_d4",
385 "univpll1_d4",
386 "syspll2_d2",
387 "syspll_d7",
388 "univpll_d7",
389 "vencpll_d2",
390 "msdcpll_ck",
391 "msdcpll_d2",
392 "msdcpll_d4"
393 };
394
395 static const char * const audio_parents[] = {
396 "clk26m",
397 "syspll3_d4",
398 "syspll4_d4",
399 "syspll1_d16"
400 };
401
402 static const char * const aud_intbus_parents[] = {
403 "clk26m",
404 "syspll1_d4",
405 "syspll4_d2",
406 "univpll3_d2",
407 "univpll2_d8",
408 "syspll3_d2",
409 "syspll3_d4"
410 };
411
412 static const char * const pmicspi_parents[] = {
413 "clk26m",
414 "syspll1_d8",
415 "syspll3_d4",
416 "syspll1_d16",
417 "univpll3_d4",
418 "univpll_d26",
419 "syspll3_d4"
420 };
421
422 static const char * const dpilvds1_parents[] = {
423 "clk26m",
424 "lvdspll2_ck",
425 "lvdspll2_d2",
426 "lvdspll2_d4",
427 "lvdspll2_d8",
428 "clkfpc"
429 };
430
431 static const char * const atb_parents[] = {
432 "clk26m",
433 "syspll1_d2",
434 "univpll_d5",
435 "syspll_d5"
436 };
437
438 static const char * const nr_parents[] = {
439 "clk26m",
440 "univpll1_d4",
441 "syspll2_d2",
442 "syspll1_d4",
443 "univpll1_d8",
444 "univpll3_d2",
445 "univpll2_d2",
446 "syspll_d5"
447 };
448
449 static const char * const nfi2x_parents[] = {
450 "clk26m",
451 "syspll4_d4",
452 "univpll3_d4",
453 "univpll1_d8",
454 "syspll2_d4",
455 "univpll3_d2",
456 "syspll_d7",
457 "syspll2_d2",
458 "univpll2_d2",
459 "syspll_d5",
460 "syspll1_d2"
461 };
462
463 static const char * const irda_parents[] = {
464 "clk26m",
465 "univpll2_d4",
466 "syspll2_d4",
467 "univpll2_d8"
468 };
469
470 static const char * const cci400_parents[] = {
471 "clk26m",
472 "vencpll_ck",
473 "armca35pll_600m",
474 "armca35pll_400m",
475 "univpll_d2",
476 "syspll_d2",
477 "msdcpll_ck",
478 "univpll_d3"
479 };
480
481 static const char * const aud_1_parents[] = {
482 "clk26m",
483 "apll1_ck",
484 "univpll2_d4",
485 "univpll2_d8"
486 };
487
488 static const char * const aud_2_parents[] = {
489 "clk26m",
490 "apll2_ck",
491 "univpll2_d4",
492 "univpll2_d8"
493 };
494
495 static const char * const mem_mfg_parents[] = {
496 "clk26m",
497 "mmpll_ck",
498 "univpll_d3"
499 };
500
501 static const char * const axi_mfg_parents[] = {
502 "clk26m",
503 "axi_sel",
504 "univpll_d5"
505 };
506
507 static const char * const scam_parents[] = {
508 "clk26m",
509 "syspll3_d2",
510 "univpll2_d4",
511 "syspll2_d4"
512 };
513
514 static const char * const nfiecc_parents[] = {
515 "clk26m",
516 "nfi2x_sel",
517 "syspll_d7",
518 "syspll2_d2",
519 "univpll2_d2",
520 "univpll_d5",
521 "syspll1_d2"
522 };
523
524 static const char * const pe2_mac_p0_parents[] = {
525 "clk26m",
526 "syspll1_d8",
527 "syspll4_d2",
528 "syspll2_d4",
529 "univpll2_d4",
530 "syspll3_d2"
531 };
532
533 static const char * const dpilvds_parents[] = {
534 "clk26m",
535 "lvdspll_ck",
536 "lvdspll_d2",
537 "lvdspll_d4",
538 "lvdspll_d8",
539 "clkfpc"
540 };
541
542 static const char * const hdcp_parents[] = {
543 "clk26m",
544 "syspll4_d2",
545 "syspll3_d4",
546 "univpll2_d4"
547 };
548
549 static const char * const hdcp_24m_parents[] = {
550 "clk26m",
551 "univpll_d26",
552 "univpll_d52",
553 "univpll2_d8"
554 };
555
556 static const char * const rtc_parents[] = {
557 "clkrtc_int",
558 "clkrtc_ext",
559 "clk26m",
560 "univpll3_d8"
561 };
562
563 static const char * const spinor_parents[] = {
564 "clk26m",
565 "clk26m_d2",
566 "syspll4_d4",
567 "univpll2_d8",
568 "univpll3_d4",
569 "syspll4_d2",
570 "syspll2_d4",
571 "univpll2_d4",
572 "etherpll_125m",
573 "syspll1_d4"
574 };
575
576 static const char * const apll_parents[] = {
577 "clk26m",
578 "apll1_ck",
579 "apll1_d2",
580 "apll1_d4",
581 "apll1_d8",
582 "apll1_d16",
583 "apll2_ck",
584 "apll2_d2",
585 "apll2_d4",
586 "apll2_d8",
587 "apll2_d16",
588 "clk26m",
589 "clk26m"
590 };
591
592 static const char * const a1sys_hp_parents[] = {
593 "clk26m",
594 "apll1_ck",
595 "apll1_d2",
596 "apll1_d4",
597 "apll1_d8"
598 };
599
600 static const char * const a2sys_hp_parents[] = {
601 "clk26m",
602 "apll2_ck",
603 "apll2_d2",
604 "apll2_d4",
605 "apll2_d8"
606 };
607
608 static const char * const asm_l_parents[] = {
609 "clk26m",
610 "univpll2_d4",
611 "univpll2_d2",
612 "syspll_d5"
613 };
614
615 static const char * const i2so1_parents[] = {
616 "clk26m",
617 "apll1_ck",
618 "apll2_ck"
619 };
620
621 static const char * const ether_125m_parents[] = {
622 "clk26m",
623 "etherpll_125m",
624 "univpll3_d2"
625 };
626
627 static const char * const ether_50m_parents[] = {
628 "clk26m",
629 "etherpll_50m",
630 "apll1_d3",
631 "univpll3_d4"
632 };
633
634 static const char * const jpgdec_parents[] = {
635 "clk26m",
636 "univpll_d3",
637 "tvdpll_429m",
638 "vencpll_ck",
639 "syspll_d3",
640 "vcodecpll_ck",
641 "univpll1_d2",
642 "armca35pll_400m",
643 "tvdpll_429m_d2",
644 "tvdpll_429m_d4"
645 };
646
647 static const char * const spislv_parents[] = {
648 "clk26m",
649 "univpll2_d4",
650 "univpll1_d4",
651 "univpll2_d2",
652 "univpll3_d2",
653 "univpll1_d8",
654 "univpll1_d2",
655 "univpll_d5"
656 };
657
658 static const char * const ether_parents[] = {
659 "clk26m",
660 "etherpll_50m",
661 "univpll_d26"
662 };
663
664 static const char * const di_parents[] = {
665 "clk26m",
666 "tvdpll_d2",
667 "tvdpll_d4",
668 "tvdpll_d8",
669 "vencpll_ck",
670 "vencpll_d2",
671 "cvbs",
672 "cvbs_d2"
673 };
674
675 static const char * const tvd_parents[] = {
676 "clk26m",
677 "cvbs_d2",
678 "univpll2_d8"
679 };
680
681 static const char * const i2c_parents[] = {
682 "clk26m",
683 "univpll_d26",
684 "univpll2_d4",
685 "univpll3_d2",
686 "univpll1_d4"
687 };
688
689 static const char * const msdc0p_aes_parents[] = {
690 "clk26m",
691 "syspll_d2",
692 "univpll_d3",
693 "vcodecpll_ck"
694 };
695
696 static const char * const cmsys_parents[] = {
697 "clk26m",
698 "univpll_d3",
699 "syspll_d3",
700 "syspll1_d2",
701 "syspll2_d2"
702 };
703
704 static const char * const gcpu_parents[] = {
705 "clk26m",
706 "syspll_d3",
707 "syspll1_d2",
708 "univpll1_d2",
709 "univpll_d5",
710 "univpll3_d2",
711 "univpll_d3"
712 };
713
714 static const char * const aud_apll1_parents[] = {
715 "apll1",
716 "clkaud_ext_i_1"
717 };
718
719 static const char * const aud_apll2_parents[] = {
720 "apll2",
721 "clkaud_ext_i_2"
722 };
723
724 static const char * const apll1_ref_parents[] = {
725 "clkaud_ext_i_2",
726 "clkaud_ext_i_1",
727 "clki2si0_mck_i",
728 "clki2si1_mck_i",
729 "clki2si2_mck_i",
730 "clktdmin_mclk_i",
731 "clki2si2_mck_i",
732 "clktdmin_mclk_i"
733 };
734
735 static const char * const audull_vtx_parents[] = {
736 "d2a_ulclk_6p5m",
737 "clkaud_ext_i_0"
738 };
739
740 static struct mtk_composite top_muxes[] = {
741 /* CLK_CFG_0 */
742 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
743 7, CLK_IS_CRITICAL),
744 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
745 15, CLK_IS_CRITICAL),
746 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
747 mm_parents, 0x040, 24, 3, 31),
748 /* CLK_CFG_1 */
749 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
750 pwm_parents, 0x050, 0, 2, 7),
751 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
752 vdec_parents, 0x050, 8, 4, 15),
753 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
754 venc_parents, 0x050, 16, 4, 23),
755 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
756 mfg_parents, 0x050, 24, 4, 31),
757 /* CLK_CFG_2 */
758 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
759 camtg_parents, 0x060, 0, 4, 7),
760 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
761 uart_parents, 0x060, 8, 1, 15),
762 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
763 spi_parents, 0x060, 16, 3, 23),
764 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
765 usb20_parents, 0x060, 24, 2, 31),
766 /* CLK_CFG_3 */
767 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
768 usb30_parents, 0x070, 0, 2, 7),
769 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
770 msdc50_0_h_parents, 0x070, 8, 3, 15),
771 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
772 msdc50_0_parents, 0x070, 16, 4, 23),
773 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
774 msdc30_1_parents, 0x070, 24, 3, 31),
775 /* CLK_CFG_4 */
776 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
777 msdc30_1_parents, 0x080, 0, 3, 7),
778 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
779 msdc30_3_parents, 0x080, 8, 4, 15),
780 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
781 audio_parents, 0x080, 16, 2, 23),
782 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
783 aud_intbus_parents, 0x080, 24, 3, 31),
784 /* CLK_CFG_5 */
785 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
786 pmicspi_parents, 0x090, 0, 3, 7),
787 MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
788 dpilvds1_parents, 0x090, 8, 3, 15),
789 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
790 atb_parents, 0x090, 16, 2, 23),
791 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
792 nr_parents, 0x090, 24, 3, 31),
793 /* CLK_CFG_6 */
794 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
795 nfi2x_parents, 0x0a0, 0, 4, 7),
796 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
797 irda_parents, 0x0a0, 8, 2, 15),
798 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
799 cci400_parents, 0x0a0, 16, 3, 23),
800 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
801 aud_1_parents, 0x0a0, 24, 2, 31),
802 /* CLK_CFG_7 */
803 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
804 aud_2_parents, 0x0b0, 0, 2, 7),
805 MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
806 mem_mfg_parents, 0x0b0, 8, 2, 15),
807 MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
808 axi_mfg_parents, 0x0b0, 16, 2, 23),
809 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
810 scam_parents, 0x0b0, 24, 2, 31),
811 /* CLK_CFG_8 */
812 MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
813 nfiecc_parents, 0x0c0, 0, 3, 7),
814 MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
815 pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
816 MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
817 pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
818 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
819 dpilvds_parents, 0x0c0, 24, 3, 31),
820 /* CLK_CFG_9 */
821 MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
822 msdc50_0_h_parents, 0x0d0, 0, 3, 7),
823 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
824 hdcp_parents, 0x0d0, 8, 2, 15),
825 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
826 hdcp_24m_parents, 0x0d0, 16, 2, 23),
827 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
828 31, CLK_IS_CRITICAL),
829 /* CLK_CFG_10 */
830 MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
831 spinor_parents, 0x500, 0, 4, 7),
832 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
833 apll_parents, 0x500, 8, 4, 15),
834 MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
835 apll_parents, 0x500, 16, 4, 23),
836 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
837 a1sys_hp_parents, 0x500, 24, 3, 31),
838 /* CLK_CFG_11 */
839 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
840 a2sys_hp_parents, 0x510, 0, 3, 7),
841 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
842 asm_l_parents, 0x510, 8, 2, 15),
843 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
844 asm_l_parents, 0x510, 16, 2, 23),
845 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
846 asm_l_parents, 0x510, 24, 2, 31),
847 /* CLK_CFG_12 */
848 MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
849 i2so1_parents, 0x520, 0, 2, 7),
850 MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
851 i2so1_parents, 0x520, 8, 2, 15),
852 MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
853 i2so1_parents, 0x520, 16, 2, 23),
854 MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
855 i2so1_parents, 0x520, 24, 2, 31),
856 /* CLK_CFG_13 */
857 MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
858 i2so1_parents, 0x530, 0, 2, 7),
859 MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
860 i2so1_parents, 0x530, 8, 2, 15),
861 MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
862 i2so1_parents, 0x530, 16, 2, 23),
863 MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
864 i2so1_parents, 0x530, 24, 2, 31),
865 /* CLK_CFG_14 */
866 MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
867 ether_125m_parents, 0x540, 0, 2, 7),
868 MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
869 ether_50m_parents, 0x540, 8, 2, 15),
870 MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
871 jpgdec_parents, 0x540, 16, 4, 23),
872 MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
873 spislv_parents, 0x540, 24, 3, 31),
874 /* CLK_CFG_15 */
875 MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
876 ether_parents, 0x550, 0, 2, 7),
877 MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
878 camtg_parents, 0x550, 8, 4, 15),
879 MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
880 di_parents, 0x550, 16, 3, 23),
881 MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
882 tvd_parents, 0x550, 24, 2, 31),
883 /* CLK_CFG_16 */
884 MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
885 i2c_parents, 0x560, 0, 3, 7),
886 MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
887 pwm_parents, 0x560, 8, 2, 15),
888 MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
889 msdc0p_aes_parents, 0x560, 16, 2, 23),
890 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
891 cmsys_parents, 0x560, 24, 3, 31),
892 /* CLK_CFG_17 */
893 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
894 gcpu_parents, 0x570, 0, 3, 7),
895 /* CLK_AUDDIV_4 */
896 MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
897 aud_apll1_parents, 0x134, 0, 1),
898 MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
899 aud_apll2_parents, 0x134, 1, 1),
900 MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
901 audull_vtx_parents, 0x134, 31, 1),
902 MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel",
903 apll1_ref_parents, 0x134, 4, 3),
904 MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel",
905 apll1_ref_parents, 0x134, 7, 3),
906 };
907
908 static const char * const mcu_mp0_parents[] = {
909 "clk26m",
910 "armca35pll_ck",
911 "f_mp0_pll1_ck",
912 "f_mp0_pll2_ck"
913 };
914
915 static const char * const mcu_mp2_parents[] = {
916 "clk26m",
917 "armca72pll_ck",
918 "f_big_pll1_ck",
919 "f_big_pll2_ck"
920 };
921
922 static const char * const mcu_bus_parents[] = {
923 "clk26m",
924 "cci400_sel",
925 "f_bus_pll1_ck",
926 "f_bus_pll2_ck"
927 };
928
929 static struct mtk_composite mcu_muxes[] = {
930 /* mp0_pll_divider_cfg */
931 MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
932 9, 2, -1, CLK_IS_CRITICAL),
933 /* mp2_pll_divider_cfg */
934 MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
935 9, 2, -1, CLK_IS_CRITICAL),
936 /* bus_pll_divider_cfg */
937 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
938 9, 2, -1, CLK_IS_CRITICAL),
939 };
940
941 static const struct mtk_clk_divider top_adj_divs[] = {
942 DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
943 DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
944 DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
945 DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
946 DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
947 DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
948 DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
949 DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
950 };
951
952 static const struct mtk_gate_regs top0_cg_regs = {
953 .set_ofs = 0x120,
954 .clr_ofs = 0x120,
955 .sta_ofs = 0x120,
956 };
957
958 static const struct mtk_gate_regs top1_cg_regs = {
959 .set_ofs = 0x424,
960 .clr_ofs = 0x424,
961 .sta_ofs = 0x424,
962 };
963
964 #define GATE_TOP0(_id, _name, _parent, _shift) { \
965 .id = _id, \
966 .name = _name, \
967 .parent_name = _parent, \
968 .regs = &top0_cg_regs, \
969 .shift = _shift, \
970 .ops = &mtk_clk_gate_ops_no_setclr, \
971 }
972
973 #define GATE_TOP1(_id, _name, _parent, _shift) { \
974 .id = _id, \
975 .name = _name, \
976 .parent_name = _parent, \
977 .regs = &top1_cg_regs, \
978 .shift = _shift, \
979 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
980 }
981
982 static const struct mtk_gate top_clks[] = {
983 /* TOP0 */
984 GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
985 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
986 GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
987 GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
988 GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
989 GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
990 GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
991 GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
992 /* TOP1 */
993 GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0),
994 GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1),
995 GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2),
996 };
997
998 static const struct mtk_gate_regs infra_cg_regs = {
999 .set_ofs = 0x40,
1000 .clr_ofs = 0x44,
1001 .sta_ofs = 0x48,
1002 };
1003
1004 #define GATE_INFRA(_id, _name, _parent, _shift) { \
1005 .id = _id, \
1006 .name = _name, \
1007 .parent_name = _parent, \
1008 .regs = &infra_cg_regs, \
1009 .shift = _shift, \
1010 .ops = &mtk_clk_gate_ops_setclr, \
1011 }
1012
1013 static const struct mtk_gate infra_clks[] = {
1014 GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
1015 GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
1016 GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
1017 GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
1018 GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
1019 GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
1020 GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
1021 };
1022
1023 static const struct mtk_gate_regs peri0_cg_regs = {
1024 .set_ofs = 0x8,
1025 .clr_ofs = 0x10,
1026 .sta_ofs = 0x18,
1027 };
1028
1029 static const struct mtk_gate_regs peri1_cg_regs = {
1030 .set_ofs = 0xc,
1031 .clr_ofs = 0x14,
1032 .sta_ofs = 0x1c,
1033 };
1034
1035 static const struct mtk_gate_regs peri2_cg_regs = {
1036 .set_ofs = 0x42c,
1037 .clr_ofs = 0x42c,
1038 .sta_ofs = 0x42c,
1039 };
1040
1041 #define GATE_PERI0(_id, _name, _parent, _shift) { \
1042 .id = _id, \
1043 .name = _name, \
1044 .parent_name = _parent, \
1045 .regs = &peri0_cg_regs, \
1046 .shift = _shift, \
1047 .ops = &mtk_clk_gate_ops_setclr, \
1048 }
1049
1050 #define GATE_PERI1(_id, _name, _parent, _shift) { \
1051 .id = _id, \
1052 .name = _name, \
1053 .parent_name = _parent, \
1054 .regs = &peri1_cg_regs, \
1055 .shift = _shift, \
1056 .ops = &mtk_clk_gate_ops_setclr, \
1057 }
1058
1059 #define GATE_PERI2(_id, _name, _parent, _shift) { \
1060 .id = _id, \
1061 .name = _name, \
1062 .parent_name = _parent, \
1063 .regs = &peri2_cg_regs, \
1064 .shift = _shift, \
1065 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
1066 }
1067
1068 static const struct mtk_gate peri_clks[] = {
1069 /* PERI0 */
1070 GATE_PERI0(CLK_PERI_NFI, "per_nfi",
1071 "axi_sel", 0),
1072 GATE_PERI0(CLK_PERI_THERM, "per_therm",
1073 "axi_sel", 1),
1074 GATE_PERI0(CLK_PERI_PWM0, "per_pwm0",
1075 "pwm_sel", 2),
1076 GATE_PERI0(CLK_PERI_PWM1, "per_pwm1",
1077 "pwm_sel", 3),
1078 GATE_PERI0(CLK_PERI_PWM2, "per_pwm2",
1079 "pwm_sel", 4),
1080 GATE_PERI0(CLK_PERI_PWM3, "per_pwm3",
1081 "pwm_sel", 5),
1082 GATE_PERI0(CLK_PERI_PWM4, "per_pwm4",
1083 "pwm_sel", 6),
1084 GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
1085 "pwm_sel", 7),
1086 GATE_PERI0(CLK_PERI_PWM6, "per_pwm6",
1087 "pwm_sel", 8),
1088 GATE_PERI0(CLK_PERI_PWM7, "per_pwm7",
1089 "pwm_sel", 9),
1090 GATE_PERI0(CLK_PERI_PWM, "per_pwm",
1091 "pwm_sel", 10),
1092 GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma",
1093 "axi_sel", 13),
1094 GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0",
1095 "msdc50_0_sel", 14),
1096 GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1",
1097 "msdc30_1_sel", 15),
1098 GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2",
1099 "msdc30_2_sel", 16),
1100 GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3",
1101 "msdc30_3_sel", 17),
1102 GATE_PERI0(CLK_PERI_UART0, "per_uart0",
1103 "uart_sel", 20),
1104 GATE_PERI0(CLK_PERI_UART1, "per_uart1",
1105 "uart_sel", 21),
1106 GATE_PERI0(CLK_PERI_UART2, "per_uart2",
1107 "uart_sel", 22),
1108 GATE_PERI0(CLK_PERI_UART3, "per_uart3",
1109 "uart_sel", 23),
1110 GATE_PERI0(CLK_PERI_I2C0, "per_i2c0",
1111 "axi_sel", 24),
1112 GATE_PERI0(CLK_PERI_I2C1, "per_i2c1",
1113 "axi_sel", 25),
1114 GATE_PERI0(CLK_PERI_I2C2, "per_i2c2",
1115 "axi_sel", 26),
1116 GATE_PERI0(CLK_PERI_I2C3, "per_i2c3",
1117 "axi_sel", 27),
1118 GATE_PERI0(CLK_PERI_I2C4, "per_i2c4",
1119 "axi_sel", 28),
1120 GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc",
1121 "ltepll_fs26m", 29),
1122 GATE_PERI0(CLK_PERI_SPI0, "per_spi0",
1123 "spi_sel", 30),
1124 /* PERI1 */
1125 GATE_PERI1(CLK_PERI_SPI, "per_spi",
1126 "spinor_sel", 1),
1127 GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
1128 "axi_sel", 3),
1129 GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
1130 "spi_sel", 5),
1131 GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
1132 "spi_sel", 6),
1133 GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
1134 "spi_sel", 8),
1135 GATE_PERI1(CLK_PERI_UART4, "per_uart4",
1136 "uart_sel", 9),
1137 GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
1138 "uart_sel", 11),
1139 GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
1140 "uart_sel", 12),
1141 GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
1142 "uart_sel", 14),
1143 GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1",
1144 "uart_sel", 15),
1145 GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk",
1146 "uart_sel", 16),
1147 /* PERI2 */
1148 GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en",
1149 "msdc50_0_sel", 0),
1150 GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en",
1151 "msdc30_1_sel", 1),
1152 GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en",
1153 "msdc30_2_sel", 2),
1154 GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en",
1155 "msdc30_3_sel", 3),
1156 GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h",
1157 "msdc50_0_h_sel", 4),
1158 GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
1159 "msdc50_3_h_sel", 5),
1160 GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q",
1161 "axi_sel", 6),
1162 GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q",
1163 "mem_sel", 7),
1164 };
1165
1166 #define MT2712_PLL_FMAX (3000UL * MHZ)
1167
1168 #define CON0_MT2712_RST_BAR BIT(24)
1169
1170 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1171 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
1172 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1173 _div_table) { \
1174 .id = _id, \
1175 .name = _name, \
1176 .reg = _reg, \
1177 .pwr_reg = _pwr_reg, \
1178 .en_mask = _en_mask, \
1179 .flags = _flags, \
1180 .rst_bar_mask = CON0_MT2712_RST_BAR, \
1181 .fmax = MT2712_PLL_FMAX, \
1182 .pcwbits = _pcwbits, \
1183 .pd_reg = _pd_reg, \
1184 .pd_shift = _pd_shift, \
1185 .tuner_reg = _tuner_reg, \
1186 .tuner_en_reg = _tuner_en_reg, \
1187 .tuner_en_bit = _tuner_en_bit, \
1188 .pcw_reg = _pcw_reg, \
1189 .pcw_shift = _pcw_shift, \
1190 .div_table = _div_table, \
1191 }
1192
1193 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1194 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
1195 _tuner_en_bit, _pcw_reg, _pcw_shift) \
1196 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1197 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
1198 _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
1199 _pcw_shift, NULL)
1200
1201 static const struct mtk_pll_div_table armca35pll_div_table[] = {
1202 { .div = 0, .freq = MT2712_PLL_FMAX },
1203 { .div = 1, .freq = 1202500000 },
1204 { .div = 2, .freq = 500500000 },
1205 { .div = 3, .freq = 315250000 },
1206 { .div = 4, .freq = 157625000 },
1207 { } /* sentinel */
1208 };
1209
1210 static const struct mtk_pll_div_table armca72pll_div_table[] = {
1211 { .div = 0, .freq = MT2712_PLL_FMAX },
1212 { .div = 1, .freq = 994500000 },
1213 { .div = 2, .freq = 520000000 },
1214 { .div = 3, .freq = 315250000 },
1215 { .div = 4, .freq = 157625000 },
1216 { } /* sentinel */
1217 };
1218
1219 static const struct mtk_pll_div_table mmpll_div_table[] = {
1220 { .div = 0, .freq = MT2712_PLL_FMAX },
1221 { .div = 1, .freq = 1001000000 },
1222 { .div = 2, .freq = 601250000 },
1223 { .div = 3, .freq = 250250000 },
1224 { .div = 4, .freq = 125125000 },
1225 { } /* sentinel */
1226 };
1227
1228 static const struct mtk_pll_data plls[] = {
1229 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
1230 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
1231 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
1232 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
1233 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
1234 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
1235 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
1236 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
1237 PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
1238 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
1239 PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
1240 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
1241 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
1242 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
1243 PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
1244 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
1245 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
1246 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
1247 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
1248 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
1249 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
1250 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
1251 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
1252 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
1253 mmpll_div_table),
1254 PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
1255 HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
1256 armca35pll_div_table),
1257 PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
1258 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
1259 armca72pll_div_table),
1260 PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
1261 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
1262 };
1263
1264 static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
1265 {
1266 struct clk_onecell_data *clk_data;
1267 int r;
1268 struct device_node *node = pdev->dev.of_node;
1269
1270 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1271
1272 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1273
1274 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1275
1276 if (r != 0)
1277 pr_err("%s(): could not register clock provider: %d\n",
1278 __func__, r);
1279
1280 return r;
1281 }
1282
1283 static struct clk_onecell_data *top_clk_data;
1284
1285 static void clk_mt2712_top_init_early(struct device_node *node)
1286 {
1287 int r, i;
1288
1289 if (!top_clk_data) {
1290 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1291
1292 for (i = 0; i < CLK_TOP_NR_CLK; i++)
1293 top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
1294 }
1295
1296 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1297 top_clk_data);
1298
1299 r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1300 if (r)
1301 pr_err("%s(): could not register clock provider: %d\n",
1302 __func__, r);
1303 }
1304
1305 CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
1306 clk_mt2712_top_init_early);
1307
1308 static int clk_mt2712_top_probe(struct platform_device *pdev)
1309 {
1310 int r, i;
1311 struct device_node *node = pdev->dev.of_node;
1312 void __iomem *base;
1313 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1314
1315 base = devm_ioremap_resource(&pdev->dev, res);
1316 if (IS_ERR(base)) {
1317 pr_err("%s(): ioremap failed\n", __func__);
1318 return PTR_ERR(base);
1319 }
1320
1321 if (!top_clk_data) {
1322 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1323 } else {
1324 for (i = 0; i < CLK_TOP_NR_CLK; i++) {
1325 if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
1326 top_clk_data->clks[i] = ERR_PTR(-ENOENT);
1327 }
1328 }
1329
1330 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1331 top_clk_data);
1332 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1333 top_clk_data);
1334 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1335 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
1336 &mt2712_clk_lock, top_clk_data);
1337 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
1338 &mt2712_clk_lock, top_clk_data);
1339 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
1340 top_clk_data);
1341
1342 r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1343
1344 if (r != 0)
1345 pr_err("%s(): could not register clock provider: %d\n",
1346 __func__, r);
1347
1348 return r;
1349 }
1350
1351 static int clk_mt2712_infra_probe(struct platform_device *pdev)
1352 {
1353 struct clk_onecell_data *clk_data;
1354 int r;
1355 struct device_node *node = pdev->dev.of_node;
1356
1357 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1358
1359 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1360 clk_data);
1361
1362 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1363
1364 if (r != 0)
1365 pr_err("%s(): could not register clock provider: %d\n",
1366 __func__, r);
1367
1368 mtk_register_reset_controller(node, 2, 0x30);
1369
1370 return r;
1371 }
1372
1373 static int clk_mt2712_peri_probe(struct platform_device *pdev)
1374 {
1375 struct clk_onecell_data *clk_data;
1376 int r;
1377 struct device_node *node = pdev->dev.of_node;
1378
1379 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1380
1381 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1382 clk_data);
1383
1384 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1385
1386 if (r != 0)
1387 pr_err("%s(): could not register clock provider: %d\n",
1388 __func__, r);
1389
1390 mtk_register_reset_controller(node, 2, 0);
1391
1392 return r;
1393 }
1394
1395 static int clk_mt2712_mcu_probe(struct platform_device *pdev)
1396 {
1397 struct clk_onecell_data *clk_data;
1398 int r;
1399 struct device_node *node = pdev->dev.of_node;
1400 void __iomem *base;
1401 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1402
1403 base = devm_ioremap_resource(&pdev->dev, res);
1404 if (IS_ERR(base)) {
1405 pr_err("%s(): ioremap failed\n", __func__);
1406 return PTR_ERR(base);
1407 }
1408
1409 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
1410
1411 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
1412 &mt2712_clk_lock, clk_data);
1413
1414 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1415
1416 if (r != 0)
1417 pr_err("%s(): could not register clock provider: %d\n",
1418 __func__, r);
1419
1420 return r;
1421 }
1422
1423 static const struct of_device_id of_match_clk_mt2712[] = {
1424 {
1425 .compatible = "mediatek,mt2712-apmixedsys",
1426 .data = clk_mt2712_apmixed_probe,
1427 }, {
1428 .compatible = "mediatek,mt2712-topckgen",
1429 .data = clk_mt2712_top_probe,
1430 }, {
1431 .compatible = "mediatek,mt2712-infracfg",
1432 .data = clk_mt2712_infra_probe,
1433 }, {
1434 .compatible = "mediatek,mt2712-pericfg",
1435 .data = clk_mt2712_peri_probe,
1436 }, {
1437 .compatible = "mediatek,mt2712-mcucfg",
1438 .data = clk_mt2712_mcu_probe,
1439 }, {
1440 /* sentinel */
1441 }
1442 };
1443
1444 static int clk_mt2712_probe(struct platform_device *pdev)
1445 {
1446 int (*clk_probe)(struct platform_device *);
1447 int r;
1448
1449 clk_probe = of_device_get_match_data(&pdev->dev);
1450 if (!clk_probe)
1451 return -EINVAL;
1452
1453 r = clk_probe(pdev);
1454 if (r != 0)
1455 dev_err(&pdev->dev,
1456 "could not register clock provider: %s: %d\n",
1457 pdev->name, r);
1458
1459 return r;
1460 }
1461
1462 static struct platform_driver clk_mt2712_drv = {
1463 .probe = clk_mt2712_probe,
1464 .driver = {
1465 .name = "clk-mt2712",
1466 .owner = THIS_MODULE,
1467 .of_match_table = of_match_clk_mt2712,
1468 },
1469 };
1470
1471 static int __init clk_mt2712_init(void)
1472 {
1473 return platform_driver_register(&clk_mt2712_drv);
1474 }
1475
1476 arch_initcall(clk_mt2712_init);
Linux with added FPC-III support