drivers/clk/mvebu/armada-xp.c

   1 /*
   2  * Marvell Armada XP SoC clocks
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   8  * Andrew Lunn <andrew@lunn.ch>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/io.h>
  18 #include <linux/of.h>
  19 #include "common.h"
  20
  21 /*
  22  * Core Clocks
  23  *
  24  * Armada XP Sample At Reset is a 64 bit bitfiled split in two
  25  * register of 32 bits
  26  */
  27
  28 #define SARL                            0       /* Low part [0:31] */
  29 #define  SARL_AXP_PCLK_FREQ_OPT         21
  30 #define  SARL_AXP_PCLK_FREQ_OPT_MASK    0x7
  31 #define  SARL_AXP_FAB_FREQ_OPT          24
  32 #define  SARL_AXP_FAB_FREQ_OPT_MASK     0xF
  33 #define SARH                            4       /* High part [32:63] */
  34 #define  SARH_AXP_PCLK_FREQ_OPT         (52-32)
  35 #define  SARH_AXP_PCLK_FREQ_OPT_MASK    0x1
  36 #define  SARH_AXP_PCLK_FREQ_OPT_SHIFT   3
  37 #define  SARH_AXP_FAB_FREQ_OPT          (51-32)
  38 #define  SARH_AXP_FAB_FREQ_OPT_MASK     0x1
  39 #define  SARH_AXP_FAB_FREQ_OPT_SHIFT    4
  40
  41 enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
  42
  43 static const struct coreclk_ratio axp_coreclk_ratios[] __initconst = {
  44         { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
  45         { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
  46         { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
  47 };
  48
  49 /* Armada XP TCLK frequency is fixed to 250MHz */
  50 static u32 __init axp_get_tclk_freq(void __iomem *sar)
  51 {
  52         return 250000000;
  53 }
  54
  55 /* MV98DX3236 TCLK frequency is fixed to 200MHz */
  56 static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
  57 {
  58         return 200000000;
  59 }
  60
  61 static const u32 axp_cpu_freqs[] __initconst = {
  62         1000000000,
  63         1066000000,
  64         1200000000,
  65         1333000000,
  66         1500000000,
  67         1666000000,
  68         1800000000,
  69         2000000000,
  70         667000000,
  71         0,
  72         800000000,
  73         1600000000,
  74 };
  75
  76 static u32 __init axp_get_cpu_freq(void __iomem *sar)
  77 {
  78         u32 cpu_freq;
  79         u8 cpu_freq_select = 0;
  80
  81         cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
  82                            SARL_AXP_PCLK_FREQ_OPT_MASK);
  83         /*
  84          * The upper bit is not contiguous to the other ones and
  85          * located in the high part of the SAR registers
  86          */
  87         cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
  88              SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
  89         if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
  90                 pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
  91                 cpu_freq = 0;
  92         } else
  93                 cpu_freq = axp_cpu_freqs[cpu_freq_select];
  94
  95         return cpu_freq;
  96 }
  97
  98 /* MV98DX3236 CLK frequency is fixed to 800MHz */
  99 static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
 100 {
 101         return 800000000;
 102 }
 103
 104 static const int axp_nbclk_ratios[32][2] __initconst = {
 105         {0, 1}, {1, 2}, {2, 2}, {2, 2},
 106         {1, 2}, {1, 2}, {1, 1}, {2, 3},
 107         {0, 1}, {1, 2}, {2, 4}, {0, 1},
 108         {1, 2}, {0, 1}, {0, 1}, {2, 2},
 109         {0, 1}, {0, 1}, {0, 1}, {1, 1},
 110         {2, 3}, {0, 1}, {0, 1}, {0, 1},
 111         {0, 1}, {0, 1}, {0, 1}, {1, 1},
 112         {0, 1}, {0, 1}, {0, 1}, {0, 1},
 113 };
 114
 115 static const int axp_hclk_ratios[32][2] __initconst = {
 116         {0, 1}, {1, 2}, {2, 6}, {2, 3},
 117         {1, 3}, {1, 4}, {1, 2}, {2, 6},
 118         {0, 1}, {1, 6}, {2, 10}, {0, 1},
 119         {1, 4}, {0, 1}, {0, 1}, {2, 5},
 120         {0, 1}, {0, 1}, {0, 1}, {1, 2},
 121         {2, 6}, {0, 1}, {0, 1}, {0, 1},
 122         {0, 1}, {0, 1}, {0, 1}, {1, 1},
 123         {0, 1}, {0, 1}, {0, 1}, {0, 1},
 124 };
 125
 126 static const int axp_dramclk_ratios[32][2] __initconst = {
 127         {0, 1}, {1, 2}, {2, 3}, {2, 3},
 128         {1, 3}, {1, 2}, {1, 2}, {2, 6},
 129         {0, 1}, {1, 3}, {2, 5}, {0, 1},
 130         {1, 4}, {0, 1}, {0, 1}, {2, 5},
 131         {0, 1}, {0, 1}, {0, 1}, {1, 1},
 132         {2, 3}, {0, 1}, {0, 1}, {0, 1},
 133         {0, 1}, {0, 1}, {0, 1}, {1, 1},
 134         {0, 1}, {0, 1}, {0, 1}, {0, 1},
 135 };
 136
 137 static void __init axp_get_clk_ratio(
 138         void __iomem *sar, int id, int *mult, int *div)
 139 {
 140         u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
 141               SARL_AXP_FAB_FREQ_OPT_MASK);
 142         /*
 143          * The upper bit is not contiguous to the other ones and
 144          * located in the high part of the SAR registers
 145          */
 146         opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
 147                  SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
 148
 149         switch (id) {
 150         case AXP_CPU_TO_NBCLK:
 151                 *mult = axp_nbclk_ratios[opt][0];
 152                 *div = axp_nbclk_ratios[opt][1];
 153                 break;
 154         case AXP_CPU_TO_HCLK:
 155                 *mult = axp_hclk_ratios[opt][0];
 156                 *div = axp_hclk_ratios[opt][1];
 157                 break;
 158         case AXP_CPU_TO_DRAMCLK:
 159                 *mult = axp_dramclk_ratios[opt][0];
 160                 *div = axp_dramclk_ratios[opt][1];
 161                 break;
 162         }
 163 }
 164
 165 static const struct coreclk_soc_desc axp_coreclks = {
 166         .get_tclk_freq = axp_get_tclk_freq,
 167         .get_cpu_freq = axp_get_cpu_freq,
 168         .get_clk_ratio = axp_get_clk_ratio,
 169         .ratios = axp_coreclk_ratios,
 170         .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
 171 };
 172
 173 static const struct coreclk_soc_desc mv98dx3236_coreclks = {
 174         .get_tclk_freq = mv98dx3236_get_tclk_freq,
 175         .get_cpu_freq = mv98dx3236_get_cpu_freq,
 176 };
 177
 178 /*
 179  * Clock Gating Control
 180  */
 181
 182 static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
 183         { "audio", NULL, 0, 0 },
 184         { "ge3", NULL, 1, 0 },
 185         { "ge2", NULL,  2, 0 },
 186         { "ge1", NULL, 3, 0 },
 187         { "ge0", NULL, 4, 0 },
 188         { "pex00", NULL, 5, 0 },
 189         { "pex01", NULL, 6, 0 },
 190         { "pex02", NULL, 7, 0 },
 191         { "pex03", NULL, 8, 0 },
 192         { "pex10", NULL, 9, 0 },
 193         { "pex11", NULL, 10, 0 },
 194         { "pex12", NULL, 11, 0 },
 195         { "pex13", NULL, 12, 0 },
 196         { "bp", NULL, 13, 0 },
 197         { "sata0lnk", NULL, 14, 0 },
 198         { "sata0", "sata0lnk", 15, 0 },
 199         { "lcd", NULL, 16, 0 },
 200         { "sdio", NULL, 17, 0 },
 201         { "usb0", NULL, 18, 0 },
 202         { "usb1", NULL, 19, 0 },
 203         { "usb2", NULL, 20, 0 },
 204         { "xor0", NULL, 22, 0 },
 205         { "crypto", NULL, 23, 0 },
 206         { "tdm", NULL, 25, 0 },
 207         { "pex20", NULL, 26, 0 },
 208         { "pex30", NULL, 27, 0 },
 209         { "xor1", NULL, 28, 0 },
 210         { "sata1lnk", NULL, 29, 0 },
 211         { "sata1", "sata1lnk", 30, 0 },
 212         { }
 213 };
 214
 215 static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
 216         { "ge1", NULL, 3, 0 },
 217         { "ge0", NULL, 4, 0 },
 218         { "pex00", NULL, 5, 0 },
 219         { "sdio", NULL, 17, 0 },
 220         { "xor0", NULL, 22, 0 },
 221         { }
 222 };
 223
 224 static void __init axp_clk_init(struct device_node *np)
 225 {
 226         struct device_node *cgnp =
 227                 of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
 228
 229         mvebu_coreclk_setup(np, &axp_coreclks);
 230
 231         if (cgnp) {
 232                 mvebu_clk_gating_setup(cgnp, axp_gating_desc);
 233                 of_node_put(cgnp);
 234         }
 235 }
 236 CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);