drivers/clk/renesas/r8a77980-cpg-mssr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  * Copyright (C) 2018 Cogent Embedded, Inc.
   7  *
   8  * Based on r8a7795-cpg-mssr.c
   9  *
  10  * Copyright (C) 2015 Glider bvba
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/soc/renesas/rcar-rst.h>
  17 #include <linux/sys_soc.h>
  18
  19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
  20
  21 #include "renesas-cpg-mssr.h"
  22 #include "rcar-gen3-cpg.h"
  23
  24 enum clk_ids {
  25         /* Core Clock Outputs exported to DT */
  26         LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
  27
  28         /* External Input Clocks */
  29         CLK_EXTAL,
  30         CLK_EXTALR,
  31
  32         /* Internal Core Clocks */
  33         CLK_MAIN,
  34         CLK_PLL1,
  35         CLK_PLL2,
  36         CLK_PLL3,
  37         CLK_PLL1_DIV2,
  38         CLK_PLL1_DIV4,
  39         CLK_S0,
  40         CLK_S1,
  41         CLK_S2,
  42         CLK_S3,
  43         CLK_SDSRC,
  44
  45         /* Module Clocks */
  46         MOD_CLK_BASE
  47 };
  48
  49 static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
  50         /* External Clock Inputs */
  51         DEF_INPUT("extal",  CLK_EXTAL),
  52         DEF_INPUT("extalr", CLK_EXTALR),
  53
  54         /* Internal Core Clocks */
  55         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  56         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  57         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
  58         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  59
  60         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
  61         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
  62         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
  63         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
  64         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
  65         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
  66         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
  67
  68         /* Core Clock Outputs */
  69         DEF_FIXED("ztr",        R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
  70         DEF_FIXED("ztrd2",      R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
  71         DEF_FIXED("zt",         R8A77980_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
  72         DEF_FIXED("zx",         R8A77980_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
  73         DEF_FIXED("s0d1",       R8A77980_CLK_S0D1,  CLK_S0,         1, 1),
  74         DEF_FIXED("s0d2",       R8A77980_CLK_S0D2,  CLK_S0,         2, 1),
  75         DEF_FIXED("s0d3",       R8A77980_CLK_S0D3,  CLK_S0,         3, 1),
  76         DEF_FIXED("s0d4",       R8A77980_CLK_S0D4,  CLK_S0,         4, 1),
  77         DEF_FIXED("s0d6",       R8A77980_CLK_S0D6,  CLK_S0,         6, 1),
  78         DEF_FIXED("s0d12",      R8A77980_CLK_S0D12, CLK_S0,        12, 1),
  79         DEF_FIXED("s0d24",      R8A77980_CLK_S0D24, CLK_S0,        24, 1),
  80         DEF_FIXED("s1d1",       R8A77980_CLK_S1D1,  CLK_S1,         1, 1),
  81         DEF_FIXED("s1d2",       R8A77980_CLK_S1D2,  CLK_S1,         2, 1),
  82         DEF_FIXED("s1d4",       R8A77980_CLK_S1D4,  CLK_S1,         4, 1),
  83         DEF_FIXED("s2d1",       R8A77980_CLK_S2D1,  CLK_S2,         1, 1),
  84         DEF_FIXED("s2d2",       R8A77980_CLK_S2D2,  CLK_S2,         2, 1),
  85         DEF_FIXED("s2d4",       R8A77980_CLK_S2D4,  CLK_S2,         4, 1),
  86         DEF_FIXED("s3d1",       R8A77980_CLK_S3D1,  CLK_S3,         1, 1),
  87         DEF_FIXED("s3d2",       R8A77980_CLK_S3D2,  CLK_S3,         2, 1),
  88         DEF_FIXED("s3d4",       R8A77980_CLK_S3D4,  CLK_S3,         4, 1),
  89
  90         DEF_GEN3_SD("sd0",      R8A77980_CLK_SD0,   CLK_SDSRC,    0x0074),
  91
  92         DEF_FIXED("cl",         R8A77980_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
  93         DEF_FIXED("cp",         R8A77980_CLK_CP,    CLK_EXTAL,      2, 1),
  94         DEF_FIXED("cpex",       R8A77980_CLK_CPEX,  CLK_EXTAL,      2, 1),
  95
  96         DEF_DIV6P1("canfd",     R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
  97         DEF_DIV6P1("csi0",      R8A77980_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
  98         DEF_DIV6P1("mso",       R8A77980_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
  99 };
 100
 101 static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
 102         DEF_MOD("tmu4",                  121,   R8A77980_CLK_S0D6),
 103         DEF_MOD("tmu3",                  122,   R8A77980_CLK_S0D6),
 104         DEF_MOD("tmu2",                  123,   R8A77980_CLK_S0D6),
 105         DEF_MOD("tmu1",                  124,   R8A77980_CLK_S0D6),
 106         DEF_MOD("tmu0",                  125,   R8A77980_CLK_CP),
 107         DEF_MOD("scif4",                 203,   R8A77980_CLK_S3D4),
 108         DEF_MOD("scif3",                 204,   R8A77980_CLK_S3D4),
 109         DEF_MOD("scif1",                 206,   R8A77980_CLK_S3D4),
 110         DEF_MOD("scif0",                 207,   R8A77980_CLK_S3D4),
 111         DEF_MOD("msiof3",                208,   R8A77980_CLK_MSO),
 112         DEF_MOD("msiof2",                209,   R8A77980_CLK_MSO),
 113         DEF_MOD("msiof1",                210,   R8A77980_CLK_MSO),
 114         DEF_MOD("msiof0",                211,   R8A77980_CLK_MSO),
 115         DEF_MOD("sys-dmac2",             217,   R8A77980_CLK_S0D3),
 116         DEF_MOD("sys-dmac1",             218,   R8A77980_CLK_S0D3),
 117         DEF_MOD("tpu0",                  304,   R8A77980_CLK_S3D4),
 118         DEF_MOD("sdif",                  314,   R8A77980_CLK_SD0),
 119         DEF_MOD("pciec0",                319,   R8A77980_CLK_S2D2),
 120         DEF_MOD("intc-ex",               407,   R8A77980_CLK_CP),
 121         DEF_MOD("intc-ap",               408,   R8A77980_CLK_S0D3),
 122         DEF_MOD("hscif3",                517,   R8A77980_CLK_S3D1),
 123         DEF_MOD("hscif2",                518,   R8A77980_CLK_S3D1),
 124         DEF_MOD("hscif1",                519,   R8A77980_CLK_S3D1),
 125         DEF_MOD("hscif0",                520,   R8A77980_CLK_S3D1),
 126         DEF_MOD("imp4",                  521,   R8A77980_CLK_S1D1),
 127         DEF_MOD("thermal",               522,   R8A77980_CLK_CP),
 128         DEF_MOD("pwm",                   523,   R8A77980_CLK_S0D12),
 129         DEF_MOD("impdma1",               526,   R8A77980_CLK_S1D1),
 130         DEF_MOD("impdma0",               527,   R8A77980_CLK_S1D1),
 131         DEF_MOD("imp-ocv4",              528,   R8A77980_CLK_S1D1),
 132         DEF_MOD("imp-ocv3",              529,   R8A77980_CLK_S1D1),
 133         DEF_MOD("imp-ocv2",              531,   R8A77980_CLK_S1D1),
 134         DEF_MOD("fcpvd0",                603,   R8A77980_CLK_S3D1),
 135         DEF_MOD("vspd0",                 623,   R8A77980_CLK_S3D1),
 136         DEF_MOD("csi41",                 715,   R8A77980_CLK_CSI0),
 137         DEF_MOD("csi40",                 716,   R8A77980_CLK_CSI0),
 138         DEF_MOD("du0",                   724,   R8A77980_CLK_S2D1),
 139         DEF_MOD("lvds",                  727,   R8A77980_CLK_S2D1),
 140         DEF_MOD("etheravb",              812,   R8A77980_CLK_S3D2),
 141         DEF_MOD("gether",                813,   R8A77980_CLK_S3D2),
 142         DEF_MOD("imp3",                  824,   R8A77980_CLK_S1D1),
 143         DEF_MOD("imp2",                  825,   R8A77980_CLK_S1D1),
 144         DEF_MOD("imp1",                  826,   R8A77980_CLK_S1D1),
 145         DEF_MOD("imp0",                  827,   R8A77980_CLK_S1D1),
 146         DEF_MOD("imp-ocv1",              828,   R8A77980_CLK_S1D1),
 147         DEF_MOD("imp-ocv0",              829,   R8A77980_CLK_S1D1),
 148         DEF_MOD("impram",                830,   R8A77980_CLK_S1D1),
 149         DEF_MOD("impcnn",                831,   R8A77980_CLK_S1D1),
 150         DEF_MOD("gpio5",                 907,   R8A77980_CLK_CP),
 151         DEF_MOD("gpio4",                 908,   R8A77980_CLK_CP),
 152         DEF_MOD("gpio3",                 909,   R8A77980_CLK_CP),
 153         DEF_MOD("gpio2",                 910,   R8A77980_CLK_CP),
 154         DEF_MOD("gpio1",                 911,   R8A77980_CLK_CP),
 155         DEF_MOD("gpio0",                 912,   R8A77980_CLK_CP),
 156         DEF_MOD("can-fd",                914,   R8A77980_CLK_S3D2),
 157         DEF_MOD("i2c4",                  927,   R8A77980_CLK_S0D6),
 158         DEF_MOD("i2c3",                  928,   R8A77980_CLK_S0D6),
 159         DEF_MOD("i2c2",                  929,   R8A77980_CLK_S3D2),
 160         DEF_MOD("i2c1",                  930,   R8A77980_CLK_S3D2),
 161         DEF_MOD("i2c0",                  931,   R8A77980_CLK_S3D2),
 162 };
 163
 164 static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
 165         MOD_CLK_ID(408),        /* INTC-AP (GIC) */
 166 };
 167
 168
 169 /*
 170  * CPG Clock Data
 171  */
 172
 173 /*
 174  *   MD         EXTAL           PLL2    PLL1    PLL3
 175  * 14 13        (MHz)
 176  * --------------------------------------------------
 177  * 0  0         16.66 x 1       x240    x192    x192
 178  * 0  1         20    x 1       x200    x160    x160
 179  * 1  0         27    x 1       x148    x118    x118
 180  * 1  1         33.33 / 2       x240    x192    x192
 181  */
 182 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 13) | \
 183                                          (((md) & BIT(13)) >> 13))
 184
 185 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
 186         /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
 187         { 1,            192,    1,      192,    1,      },
 188         { 1,            160,    1,      160,    1,      },
 189         { 1,            118,    1,      118,    1,      },
 190         { 2,            192,    1,      192,    1,      },
 191 };
 192
 193 static int __init r8a77980_cpg_mssr_init(struct device *dev)
 194 {
 195         const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
 196         u32 cpg_mode;
 197         int error;
 198
 199         error = rcar_rst_read_mode_pins(&cpg_mode);
 200         if (error)
 201                 return error;
 202
 203         cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 204
 205         return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
 206 }
 207
 208 const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = {
 209         /* Core Clocks */
 210         .core_clks = r8a77980_core_clks,
 211         .num_core_clks = ARRAY_SIZE(r8a77980_core_clks),
 212         .last_dt_core_clk = LAST_DT_CORE_CLK,
 213         .num_total_core_clks = MOD_CLK_BASE,
 214
 215         /* Module Clocks */
 216         .mod_clks = r8a77980_mod_clks,
 217         .num_mod_clks = ARRAY_SIZE(r8a77980_mod_clks),
 218         .num_hw_mod_clks = 12 * 32,
 219
 220         /* Critical Module Clocks */
 221         .crit_mod_clks = r8a77980_crit_mod_clks,
 222         .num_crit_mod_clks = ARRAY_SIZE(r8a77980_crit_mod_clks),
 223
 224         /* Callbacks */
 225         .init = r8a77980_cpg_mssr_init,
 226         .cpg_clk_register = rcar_gen3_cpg_clk_register,
 227 };